Storage devices and their operation methods

Abstract

This disclosure relates to a storage device and a method of operating the same. The storage device has improved performance and includes: a plurality of memory devices, each including a plurality of memory blocks, the plurality of memory devices coupled to a channel; and a memory controller coupled to the channel to communicate with the plurality of memory devices, thereby providing read commands for instructing read operations on the plurality of memory blocks to read data, and providing read enable signals to the memory devices during at least a portion of idle time of the channel occurring while the read operations are being performed. In response to the read enable signals, the plurality of memory devices output first data to the memory controller via the channel, wherein the first data is different from data previously read by a read operation that provided the read enable signals in response to the read commands.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority and benefit to Korean Patent Application No. 10-2021-0064881, filed on May 20, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The disclosed technology generally relates to an electronic device, and more specifically, to a data storage device and a method of operating the same. Background Technology

[0004] Data storage devices are used to store data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are classified as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices retain their data only while the device is powered on, and lose their data when power is turned off. Examples of volatile memory devices can include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Even without power, non-volatile memory devices can retain stored data, so their data is not lost when power is off. Examples of non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), and flash memory. Summary of the Invention

[0007] Embodiments of the disclosed technology relate to a data storage device that can reduce the time spent transitioning from an idle state to an active state by activating channels that are in an idle state if certain criteria are met.

[0008] According to one aspect of the disclosed technology, a storage device is provided, comprising: a plurality of memory devices, each memory device including a plurality of memory blocks for storing data, the plurality of memory devices being coupled to a channel; and a memory controller, coupled to the channel to communicate with the plurality of memory devices, thereby providing a read command for instructing a read operation on the plurality of memory blocks to read data, and providing a read enable signal to the memory devices during at least a portion of an idle time of the channel occurring while the read operation is being performed, and wherein the plurality of memory devices output first data to the memory controller via the channel in response to the read enable signal, wherein the first data is different from data previously read by a read operation in response to providing the read enable signal in response to the read command.

[0009] Based on another aspect of the disclosed technology, a method for operating a storage device is provided, the storage device including a plurality of memory devices coupled to a channel and a memory controller for controlling the plurality of memory devices via the channel, the method comprising: providing a read command corresponding to a read request to the plurality of memory devices in response to a read request from a host; detecting an idle time of the channel occurring while a read operation corresponding to the read command is being executed; providing a read enable signal to the plurality of memory devices during the idle time; and outputting first data via the channel in response to the read enable signal. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a storage device based on an embodiment of the disclosed technology.

[0011] Figure 2 It is shown Figure 1 A block diagram showing an example configuration of a memory controller and a memory device, as well as a channel (or bus) connecting the memory controller to the memory device.

[0012] Figure 3 It is shown in Figure 1 The diagram shows the transmission and reception of signals between the memory controller and the memory device.

[0013] Figure 4 This is a diagram illustrating idle time based on an embodiment of the disclosed technology.

[0014] Figure 5 This is a diagram illustrating the configuration and operation of a storage device based on an embodiment of the disclosed technology.

[0015] Figure 6 This is a diagram illustrating the operation of outputting dummy data based on an embodiment of the disclosed technology.

[0016] Figure 7 This is a diagram illustrating another example of the operation of outputting dummy data based on an embodiment of the disclosed technology.

[0017] Figure 8 This is a flowchart illustrating an operation method of a storage device based on an embodiment of the disclosed technology.

[0018] Figure 9 This is a flowchart illustrating an operation method of a storage device based on an additional embodiment of the disclosed technology.

[0019] Figure 10 It shows the memory controller (such as Figure 1 A diagram of the memory controller shown.

[0020] Figure 11 It shows a memory device (such as...) Figure 1 A diagram of the memory device shown.

[0021] Figure 12 It is shown Figure 11 A diagram illustrating the structure of any one of the storage blocks shown.

[0022] Figure 13 This is a diagram illustrating a memory card system that applies an embodiment of a storage device based on the disclosed technology.

[0023] Figure 14 This is a block diagram illustrating a solid-state drive (SSD) system that applies an embodiment of a storage device based on the disclosed technology.

[0024] Figure 15 This is a block diagram illustrating a user system using a storage device based on an embodiment of the disclosed technology. Detailed Implementation

[0025] Embodiments of the disclosed technology relate to a data storage device that can more efficiently perform transitions from an idle state to an active state.

[0026] Figure 1 This is a diagram illustrating a storage device based on an embodiment of the disclosed technology.

[0027] Reference Figure 1 The storage device (e.g., a data storage device) 50 may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device 100. The storage device 50 may be a device for storing data under the control of a host 300 such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television, tablet PC, or in-vehicle infotainment system.

[0028] Depending on the host interface, which serves as the communication scheme with the host 300, the storage device 50 can be manufactured as any of various types of storage devices. For example, the storage device 50 can be implemented using any of the following types of storage devices: solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), size-reduced MMC (RS-MMC), micro MMC (micro-MMC), secure digital card (SD), mini SD card, micro SD card, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card (SMC), memory stick, etc.

[0029] The storage device 50 can be manufactured in any of a variety of package types. For example, the storage device 50 can be manufactured in any of the following package types: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0030] The memory device 100 can store data. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown), which includes a plurality of memory cells for storing data.

[0031] Each memory cell can be configured as any of the following: a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, and a four-level cell (QLC) storing four data bits.

[0032] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0033] In embodiments, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), or other memory. In this specification, for ease of description, it is assumed that the memory device 100 is NAND Flash Memory and described accordingly.

[0034] Memory device 100 can receive a command CMD and an address ADDR from memory controller 200, and access the region in the memory cell array selected by the address ADDR. Memory device 100 can perform the operation indicated by command CMD on the region selected by address ADDR. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. In a programming operation, memory device 100 can program data into the region selected by address ADDR. In a read operation, memory device 100 can read data from the region selected by address ADDR. In an erase operation, memory device 100 can erase the data stored in the region selected by address ADDR.

[0035] As an example, Figure 1 The storage device 50 shown has one memory device 100, but the storage device 50 may include more than one memory device. (Refer to...) Figure 2 Describe the connection relationships between multiple memory devices and memory controller 200.

[0036] The memory controller 200 can control all operations of the storage device 50.

[0037] When power is applied to storage device 50, memory controller 200 can run firmware (FW). When storage device 100 is a flash memory device, FW may include a host interface layer (HIL) for controlling communication with host 300, a flash translation layer (FTL) for controlling communication between host and storage device 100, and a flash interface layer (FIL) for controlling communication with storage device 100.

[0038] In this embodiment, the memory controller 200 may receive data and logical block addresses (LBAs) from the host 300 and translate the LBAs into physical block addresses (PBAs), where each PBA represents the address of a memory cell containing data to be stored in the memory device 100. In this specification, an LBA may include any logical or virtual address that does not physically exist but is mapped to a physical address. Additionally, a PBA may include the physical address of a physically existing memory cell, page, or block.

[0039] The memory controller 200 can control the memory device 100 to perform programming, reading, and erasing operations in response to requests from the host 300. During a programming operation, the memory controller 200 can provide programming commands, a Programming Interface (PBA), and data to the memory device 100. During a reading operation, the memory controller 200 can provide reading commands and a PBA to the memory device 100. During an erasing operation, the memory controller 200 can provide erasing commands and a PBA to the memory device 100.

[0040] In this embodiment, the memory controller 200 can be connected to the memory device 100 via a channel. For example, the memory controller 200 can provide commands and addresses to the memory device 100 via the channel to control the memory device 100 to perform programming operations, read operations, erase operations, etc.

[0041] In this embodiment, the memory controller 200 can autonomously generate commands, addresses, and data regardless of any requests from the host 300, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 for performing read operations and programming operations that accompany processes such as wear leveling, read recycling, and garbage collection.

[0042] In this embodiment, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices according to an interleaving scheme, thereby improving operational performance. The interleaving scheme can be a scheme for controlling the overlapping of operations on at least two memory devices 100.

[0043] In an embodiment, the memory controller 200 may include a read operation controller 210, an idle time detector 220, a dummy trigger determiner 230, and an enable signal controller 240.

[0044] The read operation controller 210 can control the memory device 100 to perform a read operation in response to a read request from the host. For example, the read operation controller 210 can generate a read command instructing the read operation and provide the read command to the memory device 100. The memory device 100 can read data corresponding to the read command from multiple memory blocks. The data can be stored in a page buffer within the memory device 100. Furthermore, the read operation controller 210 can generate a data output command instructing the memory device 100 to output the read command and provide the data output command to the memory device 100. For example, the read operation controller 210 can provide a read command based on the operating state of the memory device 100, and then provide a data output command to the memory device 100. The memory device 100 can output the data stored in the page buffer according to the data output command.

[0045] The idle time detector 220 can detect the idle time of the channel, which occurs while a read operation is being performed in the memory device 100. In an embodiment, the idle time can represent the time from when a read command is provided through the channel to when data is output through the channel. Alternatively, the idle time can include the time from when a data output command is provided through the channel to when data is output through the channel.

[0046] The dummy trigger determiner 230 can determine whether to output a read enable signal based on a result obtained by comparing idle time with a predetermined threshold. The value of the threshold can vary depending on the setting. In some embodiments, the read enable signal generated based on the determination of the dummy trigger determiner 230 can be a read enable signal generated to generate "dummy" data, which is benign information that does not contain any useful data. In some embodiments, such a read enable signal can be referred to as a "dummy" read enable signal, which generates "dummy" read data even during the idle state.

[0047] In an embodiment, when the idle time exceeds a predetermined threshold, the dummy trigger determiner 230 can control the signal controller 240 to provide a read enable signal.

[0048] The enable signal controller 240 can provide a read enable signal to the memory device 100 during idle time.

[0049] For example, enable signal controller 240 may generate a read enable signal during idle time and provide the read enable signal to memory device 100. In an embodiment, enable signal controller 240 may periodically provide the read enable signal to memory device 100 during idle time.

[0050] In an embodiment, when the idle time exceeds a predetermined threshold, the enable signal controller 240 may provide a read enable signal to the memory device 100. For example, under the control of the dummy trigger determiner 230, the enable signal controller 240 may provide a read enable signal to the memory device 100 during the idle time.

[0051] In an embodiment, the memory device 100 may include a dummy data output circuit 101.

[0052] The dummy data output circuit 101 can output dummy data to the memory controller 200 via a channel in response to a read enable signal. For example, the dummy data output circuit 101 can generate dummy data based on the read enable signal and output the dummy data via a channel. Here, the read enable signal for generating dummy data is a read enable signal generated based on the determination of the dummy trigger determiner 230. For example, the read enable signal for generating dummy data is a "dummy" read enable signal that generates "dummy" read data even during idle states.

[0053] In an embodiment, the dummy data output circuit 101 can periodically output dummy data in response to a periodically provided read enable signal.

[0054] The host 300 can communicate with the storage device 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Reduced Load DIMM (LRDIMM).

[0055] Figure 2 It is shown Figure 1 A block diagram showing a memory controller and memory device, and an example configuration of a channel (e.g., a bus) connecting the memory controller to the memory device.

[0056] Reference Figure 2 The memory controller 200 can be connected to multiple memory devices (memory devices_11 to memory devices_24) via multiple channels CH1 and CH2. The number of channels and / or the number of memory devices connected to each channel can vary depending on the implementation. This is only an example. Figure 2 The memory controller 200 is shown to be connected to the memory devices via two channels, and four memory devices are connected to each channel.

[0057] For ease of description, the operation of memory devices_11,_12,_13, and_14 connected to the first channel CH1 will be described below. The operation characteristics of memory devices (memory devices_21 to_24) connected to the other channel CH2 are similar to or the same as those of memory devices_11,_12,_13, and_14.

[0058] Memory devices 11 through 14 can be connected to the first channel CH1. Memory devices 11 through 14 can communicate with the memory controller 200 via the first channel CH1. Because memory devices 11 through 14 are connected via the first channel CH1, only one memory device can communicate with the memory controller 200 at a time. However, operations performed internally by memory devices 11 through 14 can be performed simultaneously.

[0059] A storage device using multiple memory devices can be referenced. Figure 1The described interleaving scheme improves performance. To use the interleaving scheme, memory devices can be managed on a channel and path basis. To maximize the parallelism of memory devices connected to each channel, the memory controller 200 can distribute and allocate contiguous logical memory regions based on channels and paths.

[0060] For example, memory controller 200 can send commands, control signals including addresses, and data to memory device 11 via the first channel CH1. When memory device 11 is writing received data into its memory cells, memory controller 200 can send commands, control signals including addresses, and data to memory device 12.

[0061] exist Figure 2 In this configuration, multiple memory devices can form four pathways WAY1 to WAY4. The first pathway WAY1 may include memory devices_11 and_21. The second pathway WAY2 may include memory devices_12 and_22. The third pathway WAY3 may include memory devices_13 and_23. The fourth pathway WAY4 may include memory devices_14 and_24.

[0062] Each of channels CH1 and CH2 can be a bus for transmitting data and / or other signals, which are shared and used by memory devices connected to the respective channel.

[0063] although Figure 2 The 2-channel / 4-path interleaving is illustrated by way of example, but in some embodiments, the disclosed technique can be implemented to increase the number of channels and paths to improve the efficiency of interleaving.

[0064] Figure 3 It is shown in Figure 1 The diagram shows the transmission and reception of signals between the memory controller and the memory device.

[0065] Reference Figure 3 The memory device 100 can communicate with the memory controller 200 via the input / output (DQ) line, chip enable (CE) line, write enable (WE_N) line, read enable (RE_N) line, address latch enable (ALE) line, command latch enable (CLE) line, write protect (WP_N) line, and ready / busy (RB) line.

[0066] exist Figure 3The diagram illustrates, by way of example only, a connection structure between a single memory device 100 and a memory controller 200. In some embodiments, the disclosed technology can be implemented to provide a connection structure between the memory controller 200 and multiple memory devices. For example, the memory controller 200 can be coupled via the connection structure to, for example, a... Figure 2 The memory devices _11 to _14 and _21 to _24 are shown. For example, input / output (DQ) lines, chip enable (CE) lines, write enable (WE_N) lines, read enable (RE_N) lines, address latch enable (ALE) lines, command latch enable (CLE) lines, write protect (WP_N) lines, and ready / busy (RB) lines can be included in a single channel, and the memory controller 200 and multiple memory devices (memory devices _11 to _14 or memory devices _21 to _24) can be interconnected through corresponding channels. Therefore, when the memory controller 200 transmits a signal through a line included in a channel, the memory device selected by the memory controller 200 among all memory devices (memory devices_11 to memory devices_14 or memory devices_21 to memory devices_24) connected to the corresponding channel, or among the memory devices (memory devices_11 to memory devices_14 or memory devices_21 to memory devices_24) connected to the corresponding channel, can receive the signal.

[0067] Input / output (DQ) lines can input commands, addresses, and data to memory device 100, or output data from memory device 100 to memory controller 200. The input / output (DQ) lines can be configured with eight lines to send / receive eight bits of data, with each line capable of sending / receiving one bit of data. However, the number of input / output (DQ) lines is not limited to eight and can be extended to 16 or 32 lines in various embodiments.

[0068] The chip enable (CE) line can transmit a chip enable (CE) signal to indicate that the memory device 100 can be operated. The chip enable (CE) signal can be selectively applied to memory devices connected to the same channel. When the chip enable (CE) signal falls to a low level, the chip enable (CE) signal can indicate that all operations can be performed in the corresponding memory device 100. When the chip enable (CE) signal is high, the chip enable (CE) signal can indicate that the corresponding memory device 100 is in a standby state.

[0069] Memory device 100 can receive a read enable (RE_N) signal via a read enable (RE_N) line and a write enable (WE_N) signal via a write enable (WE_N) line. The read enable (RE_N) signal can be triggered when data is loaded into memory controller 200, and the write enable (WE_N) signal can be triggered when commands and addresses are loaded into memory device 100. Commands and addresses can be input to the selected memory device 100 when the write enable (WE_N) signal changes from low to high, i.e., on the rising edge of the write enable (WE_N) signal. In another embodiment, commands and addresses can be input to the selected memory device 100 when the write enable (WE_N) signal changes from high to low, i.e., on the falling edge of the write enable (WE_N) signal.

[0070] The memory device 100 can receive a command latch enable (CLE) signal via a command latch enable (CLE) line. When a command CMD is input to the memory device 100, the command latch enable (CLE) signal can go high. Alternatively, the memory device 100 can receive an address latch enable (ALE) signal via an address latch enable (ALE) line. When an address is input to the memory device 100, the address latch enable (ALE) signal can go high.

[0071] The memory device 100 can receive a write protection (WP_N) signal via a write protection (WP_N) line. The write protection (WP_N) signal can be a signal used to invalidate programming and erasing operations on the memory cell array.

[0072] When an operation is performed in memory device 100, the ready / busy (RB) signal transmitted to the ready / busy (RB) line can be in a logic low or low voltage state. When the ready / busy (RB) signal is in a logic low state, memory device 100 does not exchange any signals with the outside. When the ready / busy (RB) signal is at a high level, memory device 100 is in a ready state. When memory device 100 is in the ready state, memory device 100 can exchange signals with the outside.

[0073] Figure 4 This is a diagram illustrating idle time based on an embodiment of the disclosed technology.

[0074] In an embodiment, it can be based on Figure 4 The timing diagram shown is used for execution. Figure 2The read operations of the memory devices shown are described. For ease of description, the operations of memory devices_11,_12,_13, and_14 connected to the first channel CH1 are described. The operating characteristics of the memory devices (memory devices_21 to_24) connected to the other channel CH2 are similar to or the same as those of memory devices_11,_12,_13, and_14.

[0075] During the time period from T0 to T1, memory device_11 can receive a read command RCMD via the channel. Subsequently, memory device_11 can read data in response to the read command.

[0076] Because the memory devices (memory devices_11 to memory devices_14) share a channel, memory devices_12,_13 and_14 cannot communicate with memory controller 200 during the time period from T0 to T1.

[0077] During the time period from T1 to T2, memory device_12 can receive the read command RCMD through the channel. Subsequently, memory device_12 can read data according to the read command. Since the memory devices (memory devices_11 to memory devices_14) share the channel, memory devices_11,_13, and_14 cannot communicate with memory controller 200 during the time period from T1 to T2.

[0078] During the time period from T2 to T3, memory device_13 can receive the read command RCMD through the channel. Subsequently, memory device_13 can read data according to the read command. Since the memory devices (memory devices_11 to memory devices_14) share the channel, memory devices_11, memory devices_12, and memory devices_14 cannot communicate with memory controller 200 during the time period from T2 to T3.

[0079] During the time period from T3 to T4, memory device_14 can receive the read command RCMD through the channel. Subsequently, memory device_14 can read data according to the read command. Since the memory devices (memory devices_11 to memory devices_14) share the channel, memory devices_11,_12, and_13 cannot communicate with memory controller 200 during the time period from T3 to T4.

[0080] During the time period from T1 to T5, memory device_11 can read data from multiple memory blocks. Subsequently, during the time period from T5 to T6, memory device_11 can output data through a channel. For example, memory device_11 can receive a data output command through the channel and output data according to the data output command. Since the memory devices (memory devices_11 to memory devices_14) share the channel, memory devices_12,_13, and_14 cannot communicate with the memory controller during the time period from T5 to T6. In this embodiment, the time required to perform a read operation may include the time tR spent by memory device_11 reading data from multiple memory blocks and the time tDout spent by memory device_11 outputting data through the channel.

[0081] During the time period from T2 to T6, memory device_12 can read data from multiple memory blocks. Subsequently, during the time period from T6 to T7, memory device_12 can output data through a channel. For example, memory device_12 can receive a data output command through the channel and output data in response to the data output command. Because memory devices (memory devices_11 to memory devices_14) share a channel, memory devices_11,_13, and_14 cannot communicate with memory controller 200 during the time period from T6 to T7.

[0082] During the time period from T3 to T7, memory device_13 can read data from multiple memory blocks. Subsequently, during the time period from T7 to T8, memory device_13 can output data through a channel. For example, memory device_13 can receive a data output command through the channel and output data according to the data output command. Since memory devices (memory devices_11 to memory devices_14) share a channel, memory devices_11,_12, and_14 cannot communicate with memory controller 200 during the time period from T7 to T8.

[0083] During the time period from T4 to T8, memory device_14 can read data from multiple memory blocks. Subsequently, during the time period from T8 to T9, memory device_14 can output data through a channel. For example, memory device_14 can receive a data output command through the channel and output data according to the data output command. Because the memory devices (memory devices_11 to memory device_14) share a channel, memory devices_11,_12, and_13 cannot communicate with memory controller 200 during the time period from T8 to T9.

[0084] During the period from T4 to T5, the memory devices (memory devices_11 to memory devices_14) are performing read operations, and the channel is idle. Therefore, the time period from T4 to T5 is the idle time of the channel.

[0085] When a channel suddenly transitions from an idle state to an active state, switching noise can affect subsequent normal operation controlled by the memory controller 200. The impact of switching noise can be minimized by increasing the trigger period of the read enable signal in the initial data output operation performed after the idle state. However, increasing the trigger period of the read enable signal leads to an undesirable decrease in read operation speed.

[0086] In some embodiments of the disclosed technology, the memory device is controlled to output "dummy" data through the channel by activating the channel during idle time. As described above, a read enable signal (e.g., a "dummy" read enable signal) can be generated during idle time to activate the channel and output dummy data through the channel. In this way, the memory device 50 based on some embodiments of the disclosed technology can avoid such a reduction in read operation speed, thereby improving the performance of the memory device 50.

[0087] Figure 5 This is a diagram illustrating the configuration and operation of a storage device based on an embodiment of the disclosed technology.

[0088] Reference Figure 5 The storage device 50 may include a plurality of storage devices 100 and a storage controller 200. Each of the plurality of storage devices 100 may include Figure 1 The virtual data output circuit 101 shown is shown.

[0089] The memory controller 200 may include a read operation controller 210, an idle time detector 220, a dummy trigger determiner 230, and an enable signal controller 240.

[0090] The read operation controller 210 can provide read commands RCMD to multiple memory devices 100 based on read requests from the host 300.

[0091] In this embodiment, the read operation controller 210 can control the enable signal controller 240 to generate a chip enable (CE_N) signal to select a plurality of memory devices 100 corresponding to a read request. The enable signal controller 240 can generate a chip enable (CE_N) signal (e.g., a logic low state) to activate a specific memory device or a specific region of a memory device. The read operation controller 210 can provide a read command RCMD to the plurality of memory devices 100 activated in response to the chip enable (CE_N) signal. The plurality of memory devices 100 can read data RDATA in response to the read command RCMD. Furthermore, after the read operation controller 210 provides the read command RCMD, the read operation controller 210 can provide a data output command to the memory device 100 via a channel. The memory device 100 can provide read data to the memory controller 200 according to the data output command.

[0092] The idle time detector 220 can detect the idle time T_IDLE of the channel, which occurs when a read operation is being performed in one of the multiple memory devices 100.

[0093] In this embodiment, the idle time T_IDLE can include the time period from the point in time when the read command RCMD is provided through the channel to the point in time when the data RDATA is output through the channel. Furthermore, the idle time T_IDLE can also include the time period from the point in time when the data output command is provided through the channel to the point in time when the data RDATA is output through the channel.

[0094] In an embodiment, the idle time detector 220 can detect the idle time T_IDLE based on the time required for the host device or memory controller to read data from the plurality of memory devices 100 in response to a read command and the time required for the host device or memory controller to write data to the plurality of memory devices 100 in response to a programming command.

[0095] For example, the idle time detector 220 can provide status read commands to multiple memory devices 100 to perform read operations or programming operations. The idle time detector 220 can obtain status information from the multiple memory devices 100 through status read responses. The idle time detector 220 can check the operating status of the multiple memory devices 100 based on the status information, and calculate the idle time T_IDLE based on the operating status, the time point of providing the status read command, and the time point of receiving the status information.

[0096] In an embodiment, status information may be stored in a status register included in the memory device 100. The status information may include information about whether an operation performed on the memory device 100 was successful. The status information may also include information about whether the memory device 100 is in a "ready" state or a "busy" state. For example, the status information may be used to indicate the start or end time of a read operation. Therefore, the idle time detector 220 may detect an idle time T_IDLE based on the status information.

[0097] In some embodiments, the disclosed technique can be implemented to generate a read enable signal during "idle" time, thereby minimizing the impact of switching errors. In some embodiments, the dummy trigger determiner 230 can determine whether to generate a read enable (RE_N) signal by comparing the idle time T_IDLE with a predetermined threshold. The threshold can be varied according to settings. The dummy trigger determiner 230 can receive the idle time T_IDLE from the idle time detector 220 and compare the idle time T_IDLE with the threshold.

[0098] In this embodiment, when the idle time T_IDLE exceeds a predetermined threshold, the dummy trigger determiner 230 can control the enable signal controller 240 to provide a read enable (RE_N) signal to the memory device 100. When the idle time T_IDLE does not exceed the predetermined threshold, multiple read operations of the memory device 100 can be performed without outputting dummy data.

[0099] The enable signal controller 240 can provide a read enable (RE_N) signal to multiple memory devices 100 during the idle time T_IDLE. The read enable (RE_N) signal provided during the idle time T_IDLE can be used to control the multiple memory devices 100 to output dummy data DUMMY.

[0100] In one embodiment, when the idle time T_IDLE exceeds a predetermined threshold, the enable signal controller 240 can generate a read enable (RE_N) signal. Subsequently, the enable signal controller 240 can provide the generated read enable (RE_N) signal to the memory device 100.

[0101] In this embodiment, the enable signal controller 240 may periodically provide a read enable (RE_N) signal to a plurality of memory devices 100 during the idle time T_IDLE. That is, the enable signal controller 240 may periodically trigger the read enable (RE_N) signal during the idle time T_IDLE.

[0102] In an embodiment, the enable signal controller 240 may reduce the period at which the read enable (RE_N) signal is triggered as the idle time T_IDLE elapses. For example, the enable signal controller 240 may reduce the triggering period of the read enable (RE_N). Therefore, the enable signal controller 240 can provide the read enable (RE_N) signal more quickly.

[0103] In an embodiment, multiple memory devices 100 may output dummy data DUMMY to memory controller 200 via a channel in response to a read enable (RE_N) signal.

[0104] For example, multiple memory devices 100 may periodically output dummy data DUMMY in response to a periodically provided read enable (RE_N).

[0105] In an embodiment, the dummy data DUMMY may include state information with a logical value that is inverted each time the state information is output. For example, multiple memory devices 100 may output state information with a logical value as dummy data DUMMY, which is inverted each time the state information is periodically output. For example, multiple memory devices 100 may output state information with a first logical value as dummy data DUMMY. In the next cycle, multiple memory devices 100 may output state information with a second logical value opposite to the first logical value as dummy data DUMMY. In the next cycle, multiple memory devices 100 may output state information with a first logical value opposite to the second logical value as dummy data DUMMY. In one example, the read operation controller 210 does not provide the received dummy data DUMMY to the host device or memory controller. As described above, the multiple memory devices 100 periodically trigger the logical value of the state information during the idle time T_IDLE to warm up the channel.

[0106] When the status information is output as dummy data DUMMY, the read operation controller 210 may need to check the operating status of multiple memory devices 100. While periodically providing a read enable (RE_N) signal, the read operation controller 210 can also provide a status read command. The multiple memory devices 100 can provide a status read response to the read operation controller 210 in response to the status read command. The read operation controller 210 can check the operating status of the multiple memory devices 100 based on the status information included in the status read response.

[0107] Although in the above example the dummy data DUMMY is status information with a logical value that toggles whenever status information is output, the disclosed techniques are not necessarily limited to this. In some embodiments, the dummy data DUMMY may have different formats.

[0108] In an embodiment, the enable signal controller 240 can provide a read enable RE_N signal to any one of the plurality of memory devices 100. Additionally, a memory device can output dummy data DUMMY via a channel in response to the read enable (RE_N) signal. In other words, only one of the plurality of memory devices 100 connected to a channel can output dummy data DUMMY. In some embodiments, the number of memory devices outputting dummy data DUMMY can vary.

[0109] Subsequently, when reading data RDATA from multiple memory blocks, the multiple memory devices 100 can pause the output of dummy data DUMMY and output data RDATA through the channel. The memory controller 200 can also pause the output of the read enable (RE_N) signal and receive data RDATA through the channel.

[0110] Figure 6 This is a diagram illustrating the operation of outputting dummy data based on an embodiment of the disclosed technology.

[0111] Figure 6 It shows Figure 5 The operation of the dummy data in the output memory device is shown. For ease of description, the operation of one of the multiple memory devices will be described. It should be understood that the other memory devices operate in the same manner.

[0112] During the time period from T0' to T1', the memory device can receive the read command RCMD via the channel. During the time period from T1' to T5', the memory device can perform a read operation. The time period from T2' to T4' can be an idle period. During the time period from T2' to T3', the memory device can receive the read enable (RE_N) signal. During the time period from T3' to T4', the memory device can output dummy data DUMMY via the channel in response to the read enable (RE_N) signal. Subsequently, when read data is read, the memory device can output data during the time period from T4' to T5'.

[0113] Figure 7 This is a diagram illustrating another example of the operation of outputting dummy data based on an embodiment of the disclosed technology.

[0114] In an embodiment, Figure 7 It can represent Figure 5The diagram shows the timing of the operation of the dummy data in the output memory device. For ease of description, the operation of any one of the multiple memory devices will be described. It should be understood that the other memory devices operate in the same way as this one memory device.

[0115] During the time period from T0” to T1”, the memory device can receive the read command RCMD through the channel. During the time period from T1” to T4”, the memory device can perform a read operation. The time period from T2” to T3” can be an idle time. During the time period from T2” to T3”, the memory device can periodically receive a read enable (RE_N) signal and, in response to the periodically received read enable (RE_N) signal, periodically output dummy data DUMMY through the channel. Subsequently, when read data is read, the memory device can output data during the time period from T3” to T4”.

[0116] Figure 8 This is a flowchart illustrating an operation method of a storage device based on an embodiment of the disclosed technology.

[0117] Figure 8 The operation method shown can be, for example, by Figure 5 The storage device 50 shown is executed.

[0118] Reference Figure 8 In S801, storage device 50 can provide read commands corresponding to the host's read request to multiple storage devices in response to a read request.

[0119] In S803, the storage device 50 can detect the idle time of the channel, which occurs while a read operation corresponding to a read command is being executed.

[0120] In S805, storage device 50 can provide read enable signals to multiple memory devices during idle time.

[0121] Storage device 50 can periodically provide read enable signals to multiple memory devices during idle time.

[0122] Furthermore, as idle time passes, the storage device 50 can reduce the cycle of providing the read enable signal.

[0123] In S807, storage device 50 can output dummy data through the channel in response to a read enable signal.

[0124] The storage device 50 can periodically output dummy data in response to a periodically provided read enable signal.

[0125] In addition, the storage device 50 can output state information with a logical value as dummy data, which is inverted whenever the state information is periodically output.

[0126] Figure 9 This is a flowchart illustrating an operation method of a storage device based on an additional embodiment of the disclosed technology.

[0127] Figure 9 The operation method shown can be, for example, by Figure 5 The storage device 50 shown is executed.

[0128] Reference Figure 9 In S901, the storage device 50 can activate a chip enable signal to select multiple memory devices based on the host's read request.

[0129] In S903, storage device 50 can provide read commands corresponding to read requests to multiple memory devices.

[0130] Storage device 50 can provide read commands to multiple memory devices whose chip enable signals are activated.

[0131] In S905, the storage device 50 can detect the idle time of the channel, which occurs while a read operation corresponding to a read command is being executed.

[0132] In S907, the storage device 50 can determine whether to output a read enable signal based on the result obtained by comparing the idle time with a predetermined threshold. For example, the storage device 50 can determine whether the idle time exceeds the threshold. When the idle time exceeds the threshold, the storage device 50 can execute step S909. Optionally, when the idle time does not exceed the threshold, the storage device 50 does not output any dummy data, but can continue to perform the read operation.

[0133] In step S909, storage device 50 may provide read enable signals to multiple memory devices during idle time.

[0134] Storage device 50 can periodically provide read enable signals to multiple memory devices during idle time.

[0135] Furthermore, as idle time passes, the storage device 50 can reduce the cycle of providing the read enable signal.

[0136] In S911, the storage device 50 can output dummy data through the channel in response to a read enable signal.

[0137] The storage device 50 can periodically output dummy data in response to a periodically provided read enable signal.

[0138] In addition, the storage device 50 can output state information with a logical value as dummy data, which is inverted whenever the state information is periodically output.

[0139] Figure 10 It shows things like Figure 1 The diagram shows a memory controller.

[0140] The memory controller 1000 can be compared with a reference. Figure 1 The memory controller 200 described is implemented in the same way.

[0141] Reference Figure 1 and Figure 10 The memory controller 1000 may include a processor 1010, RAM 1020, error correction circuitry 1030, ROM 1040, host interface 1050, and flash memory interface 1060.

[0142] The processor 1010 can control all operations of the memory controller 1000. The RAM 1020 can be used as a buffer memory, cache memory, working memory, etc. of the memory controller 1000.

[0143] Error correction circuit 1030 can perform error correction. Error correction circuit 1030 can perform error correction code (ECC) encoding on data to be written to the memory device via flash interface 1060. ECC-encoded data can be transmitted to the memory device via flash interface 1060. Error correction circuit 1030 can perform ECC decoding on data received from the memory device via flash interface 1060. In one example, error correction circuit 1030 can be included as a component of flash interface 1060.

[0144] ROM 1040 can store various information required for the operation of memory controller 1000 in the form of firmware. In an embodiment, refer to... Figure 1 The described read operation controller 210, idle time detector 220, dummy trigger determiner 230, and enable signal controller 240 may be firmware stored in ROM 1040.

[0145] The memory controller 1000 can communicate with external devices (e.g., host 300, application processor, etc.) via host interface 1050.

[0146] The memory controller 1000 can communicate with the memory device 100 via the flash interface 1060. The memory controller 1000 can send commands, addresses, control signals, etc., to the memory device 1000 and receive data DATA via the flash interface 1060. In one example, the flash interface 1060 may include a NAND interface.

[0147] Figure 11 It is shown Figure 1 A diagram of the memory device shown.

[0148] Reference Figure 11 The memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input / output circuit 140, and control logic 150.

[0149] The memory cell array 110 may include multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi can be connected to the address decoder 130 via row lines RL. The multiple memory blocks BLK1 to BLKi can be connected to the input / output circuitry 140 via column lines CL. In an embodiment, the row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, the column lines CL may include bit lines.

[0150] Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the plurality of memory cells may be defined as a physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each of the memory cells in the memory device 100 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0151] In this embodiment, the voltage generator 120, address decoder 130, and input / output circuitry 140 can be collectively referred to as peripheral circuitry. The peripheral circuitry can drive the memory cell array 110 under the control of control logic 150. The peripheral circuitry can drive the memory cell array 110 to perform programming, reading, and erasing operations.

[0152] Voltage generator 120 can generate multiple operating voltages using an external power supply voltage supplied to memory device 100. Voltage generator 120 can operate under the control of control logic 150.

[0153] In this embodiment, the voltage generator 120 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 120 can be used as the operating voltage of the memory device 100.

[0154] In this embodiment, voltage generator 120 can generate multiple operating voltages using either an external power supply voltage or an internal power supply voltage. Voltage generator 120 can generate various voltages required in the memory device 100. For example, voltage generator 120 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0155] To generate multiple operating voltages with various voltage levels, voltage generator 120 may include multiple pump capacitors that receive an internal power supply voltage. Under the control of control logic 150, voltage generator 120 can generate multiple operating voltages by selectively activating the multiple pump capacitors.

[0156] The multiple operating voltages generated by voltage generator 120 can be supplied to memory cell array 110 by address decoder 130.

[0157] Address decoder 130 can be connected to memory cell array 110 via row line RL. Address decoder 130 operates under the control of control logic 150. Address decoder 130 can receive address ADDR from control logic 150. Address decoder 130 can decode the block address in the received address ADDR. Address decoder 130 can select at least one memory block among memory blocks BLK1 to BLKi based on the decoded block address. Address decoder 130 can decode the row address in the received address ADDR. Address decoder 130 can select at least one word line among the word lines of the selected memory block based on the decoded row address. In an embodiment, address decoder 130 can decode the column address in the received address ADDR. Address decoder 130 can connect input / output circuit 140 and memory cell array 110 to each other based on the decoded column address.

[0158] In embodiments of the disclosed technology, during a read operation, the address decoder 130 can apply a read voltage to the selected word line and apply a read pass voltage at a level higher than the read voltage to the unselected word line.

[0159] In one example, address decoder 130 may include components such as row decoder, column decoder, and address decoder.

[0160] Input / output circuitry 140 may include multiple page buffers. These page buffers can be connected to memory cell array 110 via bit lines. During programming operations, data stored in the multiple page buffers can be provided to a selected physical page via the bit lines, and the provided data can be stored in the memory cells included in the selected physical page. During read operations, data stored in the memory cells included in the selected physical page can be sensed via the bit lines, and the sensed data can be stored in the page buffer.

[0161] Control logic 150 can control address decoder 130, voltage generator 120, and input / output circuitry 140. Control logic 150 can operate in response to a command CMD transmitted from an external device. Control logic 150 can control peripheral circuitry by generating control signals in response to the command CMD and address ADDR.

[0162] In the embodiments, reference is made to Figure 1 The described dummy data output circuit 101 can be logic stored in control logic 150.

[0163] Figure 12 It is shown Figure 11 A diagram illustrating the structure of any one of the storage blocks shown.

[0164] Storage block BLKi representation Figure 11 The storage block BLKi shown is any one of the storage blocks BLKl to BLKi.

[0165] Reference Figure 12 In a storage block BLKi, multiple word lines arranged parallel to each other can be connected between a first select line and a second select line. The first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, a storage block BLKi can include multiple string STs connected between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be connected to string STs individually, and the source line SL can be connected to string STs collectively. String STs can be configured identically to each other; therefore, a string ST connected to the first bit line BL1 will be described in detail as an example.

[0166] A string ST may include a source select transistor (SST), multiple memory cells MC1 to MC16, and a drain select transistor (DST), which are connected in series between the source line SL and the first bit line BL1. A string ST may include at least one drain select transistor (DST), and the number of source select transistors included in a string ST may be greater than the number of source select transistors (SST) shown in the figure, and the number of memory cells included in a string ST may be greater than the number of memory cells MC1 to MC16 shown in the figure.

[0167] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistors SST and the drain select transistors DST. The gates of the source select transistors SST included in different strings of ST can be connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings of ST can be connected to the drain select line DSL. The gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells in different strings of ST that are connected to the same word line can be referred to as a physical page PG. Therefore, the memory block BLKi can include physical pages PG corresponding to the number of word lines WL1 to WL16.

[0168] A memory cell can store one bit of data. A memory cell is usually called a single-level cell (SLC). A physical page (PG) can store one logical page (LPG) of data. An LPG of data can include data bits corresponding to the number of cells included in a physical page (PG).

[0169] A memory cell can store two or more bits of data. A physical page (PG) can store two or more physical pages (LPGs).

[0170] Figure 13 This is a diagram illustrating a memory card system that applies an embodiment of a storage device based on the disclosed technology.

[0171] Reference Figure 13 The memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0172] Memory controller 2100 is connected to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 provides an interface between memory device 2200 and the host computer. Memory controller 2100 drives firmware for controlling memory device 2200. Memory controller 2100 can be used with reference to... Figure 1 The memory controller 200 described is implemented identically. The memory device 2200 can be implemented with reference to... Figure 1 The memory device 100 described is implemented in the same way.

[0173] In one example, the memory controller 2100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0174] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) according to a specific communication protocol. In one example, the memory controller 2100 can communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. In one example, connector 2300 can be defined using at least one of the aforementioned communication protocols.

[0175] In one example, memory device 2200 may be implemented using various non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0176] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and memory device 2200 can form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory (CF) cards, smart media cards (SM and SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC and eMMC), SD cards (SD, mini SD, micro SD and SDHC) and universal flash memory (UFS).

[0177] Figure 14 This is a block diagram illustrating a solid-state drive (SSD) system that applies an embodiment of a storage device based on the disclosed technology.

[0178] Reference Figure 14The SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0179] In this embodiment, the SSD controller 3210 can be used as a reference. Figure 1 The memory controller 200 is described.

[0180] SSD controller 3210 can control multiple flash storage devices 3221 to 322n in response to signals received from host 3100. In one example, the signal can be based on the interface between host 3100 and SSD 3200. For example, the signal can be a signal defined through at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0181] Auxiliary power supply 3230 is connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can receive power PWR from host 3100 and use the power PWR for charging. When the power supply from host 3100 is unstable, auxiliary power supply 3230 can provide power to SSD 3200. In one example, auxiliary power supply 3230 can be located inside SSD 3200 or externally to SSD 3200. For example, auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to SSD 3200.

[0182] Buffer memory 3240 operates as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or from multiple flash memories 3221 to 322n, or temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0183] Figure 15 This is a block diagram illustrating a user system using a storage device based on an embodiment of the disclosed technology.

[0184] Reference Figure 15 The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0185] Application processor 4100 can drive components, operating system (OS), user programs, etc., included in user system 4000. In one example, application processor 4100 may include a controller for controlling components, interfaces, graphics engine, etc., included in user system 4000. Application processor 4100 may be configured as a system-on-a-chip (SoC).

[0186] Memory module 4200 can operate as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. In one example, application processor 4100 and memory module 4200 may be configured as a single semiconductor package using a PoP-based package.

[0187] Network module 4300 can communicate with external devices. In one example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. In one example, network module 4300 may be included in application processor 4100.

[0188] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Optionally, storage module 4400 can transfer the data stored therein to application processor 4100. In one example, storage module 4400 can be implemented using non-volatile semiconductor memory devices such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional structure. In one example, storage module 4400 can be configured as a removable drive for user system 4000, such as a memory card or external drive.

[0189] In one example, storage module 4400 may include multiple non-volatile memory devices, and the multiple non-volatile memory devices may be referenced. Figure 1 The memory device 100 described operates in the same manner. The memory module 4400 can be compared with the referenced... Figure 1 The storage device 50 described operates in the same manner.

[0190] User interface 4500 may include interfaces for inputting data or commands to application processor 4100 or outputting data to external devices. In one example, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0191] In some embodiments of the disclosed technology, a storage device and a method of operating the storage device that can reduce switching noise through a preheating channel can be provided.

[0192] Although specific embodiments of the disclosed technology have been described in this patent application, various changes and modifications can be made to the disclosed embodiments and other embodiments based on the disclosure in this patent application.

Claims

1. A storage device, comprising: Multiple memory devices, each memory device including multiple memory blocks for storing data, the multiple memory devices being coupled to a channel; as well as A memory controller, coupled to the channel to communicate with the plurality of memory devices, provides read commands instructing read operations on the plurality of memory blocks to read data, and provides a read enable signal to the memory devices during at least a portion of the channel's idle time, the idle time of the channel occurring while the read operation is being performed. The plurality of memory devices, in response to the read enable signal, output first data to the memory controller via the channel, wherein the first data is different from the data previously read by a read operation that provides the read enable signal in response to the read command. The plurality of memory devices output state information with logical values ​​as the first data, and the logical values ​​are inverted whenever the state information is periodically output.

2. The storage device of claim 1, wherein the memory controller is configured such that the idle time includes a time period from the time point at which the read command is provided through the channel to the time point at which data is output through the channel, and such that the idle time includes a time period from the time point at which a data output command instructing the plurality of memory devices to output data is provided to the plurality of memory devices to the time point at which data is output.

3. The storage device according to claim 1, wherein the memory controller comprises: A read operation controller, in response to a read request from the host, controls the plurality of memory devices to perform the read operation; An idle time detector detects the idle time. as well as An enable signal controller generates the read enable signal during the idle time and provides the read enable signal to the plurality of memory devices.

4. The storage device of claim 3, wherein the enable signal controller selects the plurality of memory devices by activating a chip enable signal according to the read request, and The read operation controller provides the read command to the plurality of memory devices selected by the chip enable signal.

5. The storage device of claim 3, wherein the enable signal controller periodically provides the read enable signal to the plurality of memory devices during the idle time.

6. The storage device of claim 5, wherein as the idle time elapses, the enable signal controller reduces the trigger period of the read enable signal.

7. The storage device of claim 5, wherein the plurality of memory devices periodically output the first data in response to a periodically provided read enable signal.

8. The storage device of claim 3, wherein the memory controller further includes a dummy trigger determiner that determines whether to generate the read enable signal by comparing the idle time with a predetermined threshold.

9. The storage device of claim 8, wherein when the idle time exceeds the predetermined threshold, the dummy trigger determiner controls the enable signal controller to provide the read enable signal to the plurality of memory devices.

10. A method of operating a storage device, the storage device comprising a plurality of memory devices coupled to a channel and a memory controller controlling the plurality of memory devices via the channel, the method comprising: In response to a read request from the host, a read command corresponding to the read request is provided to the plurality of memory devices; Detect the idle time of the channel that occurs while a read operation corresponding to the read command is being executed; During the idle time, a read enable signal is provided to the plurality of memory devices; and In response to the read enable signal, first data is output through the channel. The output of the first data includes outputting state information with a logical value as the first data, wherein the logical value is inverted whenever the state information is periodically output.

11. The method of claim 10, wherein the idle time represents the time from after the read command is provided through the channel to the time when read data is output through the channel, and includes the time from after a data output command instructing the memory device to output data is provided to the plurality of memory devices to the time when the data is output.

12. The method of claim 10, further comprising: Based on the read request, the chip enable signal is activated to select the plurality of memory devices.

13. The method of claim 12, wherein providing the read command comprises providing the read command to the plurality of memory devices selected by the chip enable signal.

14. The method of claim 10, wherein providing the read enable signal comprises periodically providing the read enable signal to the plurality of memory devices during the idle time.

15. The method of claim 14, wherein providing the read enable signal includes reducing the trigger period of the read enable signal as the idle time elapses.

16. The method of claim 14, wherein outputting the first data comprises periodically outputting the first data in response to a periodically provided read enable signal.

17. The method of claim 10, further comprising: Whether to generate the read enable signal is determined by comparing the idle time with a predetermined threshold.

18. The method of claim 17, wherein providing the read enable signal includes providing the read enable signal when the idle time exceeds the predetermined threshold.

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