Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a first semiconductor structure; wherein the first semiconductor structure comprises a stress structure, the stress structure extends along a first direction, the first direction is parallel to a plane in which the first semiconductor structure is located; providing a second semiconductor structure; forming a first stress adjusting structure on the second semiconductor structure; wherein the first stress adjusting structure extends along a second direction, the second direction intersects the first direction and is parallel to the plane in which the first semiconductor structure is located; and bonding the first semiconductor structure and the second semiconductor structure comprising the first stress adjusting structure; wherein the first stress adjusting structure is used to adjust a warping degree of the first semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] With the development of the semiconductor field, the feature size of planar memory cells is approaching its lower limit and the storage density is approaching its upper limit, leading to a gradual shift towards three-dimensional (3D) memory architectures. In 3D memory manufacturing, wafer bonding is a crucial technological step. However, existing wafer bonding processes still have some issues that may affect subsequent process steps. Summary of the Invention

[0003] This disclosure presents a semiconductor device and a method for fabricating the same.

[0004] According to a first aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising:

[0005] A first semiconductor structure is provided; wherein the first semiconductor structure includes a stress structure extending along a first direction, the first direction being parallel to the plane in which the first semiconductor structure is located;

[0006] Provide a second semiconductor structure;

[0007] A first stress-adjusting structure is formed on the second semiconductor structure; wherein the first stress-adjusting structure extends along a second direction, the second direction intersects the first direction and is parallel to the plane in which the first semiconductor structure is located;

[0008] The first semiconductor structure and the second semiconductor structure including the first stress-adjusting structure are bonded together; wherein the first stress-adjusting structure is used to adjust the warpage of the first semiconductor structure.

[0009] According to a second aspect of this disclosure, a semiconductor device is provided, comprising:

[0010] A first semiconductor structure includes a memory array and / or peripheral circuitry, wherein the memory array and / or peripheral circuitry includes a stress structure that extends along a first direction, the first direction being parallel to the plane in which the first semiconductor structure is located.

[0011] A first stress-adjusting structure extends along a second direction, which intersects with the first direction and is parallel to the plane containing the first semiconductor structure; the first stress-adjusting structure is used to adjust the warpage of the first semiconductor structure.

[0012] In the semiconductor device fabrication method provided in this disclosure, the first semiconductor structure includes a stress structure extending along a first direction. When the stress structure causes warping in a certain region of the first semiconductor structure, a first stress adjustment structure extending along a second direction can be formed on the second semiconductor structure according to the warping degree of the first semiconductor structure, so that a region on the second semiconductor structure perpendicular to the warped region of the first semiconductor structure warps. After bonding the first semiconductor structure and the second semiconductor structure including the first stress adjustment structure, the first stress adjustment structure and the stress structure can cause two mutually perpendicular regions of the first semiconductor structure to form warping with substantially the same warping degree and the same warping direction, thereby reducing the warping degree difference (delta bow) of different regions of the first semiconductor structure, and further reducing the overlay error introduced by the bonding process to the first layer photolithography on the back side, and increasing the process window of the back lead process. Attached Figure Description

[0013] Figures 1a to 1d This is a schematic diagram of the structure of a semiconductor device during the fabrication process, provided by an embodiment of this disclosure;

[0014] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0015] Figures 3a to 3g This is a schematic diagram of the structure of another semiconductor device provided in the present disclosure during the fabrication process;

[0016] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in the present disclosure during the fabrication process;

[0017] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in the present disclosure during the fabrication process. Detailed Implementation

[0018] The technical solution of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0020] Figures 1a to 1d This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of this disclosure. Figure 1aAs shown, the device wafer 10 includes a transistor array, which comprises a plurality of transistors 11 arranged in an array. Each transistor 11 includes a drain, a channel, and a source sequentially arranged along the Z-direction. The device wafer 10 also includes a word line 12 extending along the X-direction and a bit line 13 extending along the Y-direction, which are electrically coupled to the transistors 11. It is understood that the word line 12 serves as the gate of the transistor 11. The bit line contacts the drain of the transistor 11.

[0021] During the formation of device wafer 10, the distribution of patterns in each thin film layer structure in the X and Y directions is not completely uniform. This uneven distribution of patterns in the X and Y directions leads to uneven distribution of materials such as metal, polysilicon, or silicon nitride. These materials generate significant stress during deposition, resulting in different warpages (Bow) of device wafer 10 in the X and Y directions, i.e., a warpage difference (DeltaBow) exists between the X and Y directions of device wafer 10.

[0022] In 3D memory architectures, backside pick-up technology is frequently used. In backside pick-up technology, a carrier wafer is typically bonded to the front side of the device wafer to be backside picked up, providing support for the device wafer.

[0023] Specifically, Figure 1b This is a schematic diagram of a carrier wafer 20 provided in an embodiment of this application. The carrier wafer 20 is used for bonding to the front side of the device wafer 10 to provide support. Figure 1c This is a schematic diagram of the structure of the device wafer and the carrier wafer after bonding, as provided in the embodiments of this application. Wafer bonding refers to bonding two wafers face to face and applying certain external conditions such as pressure, temperature and voltage to generate atomic or molecular bonding forces at the interface between the two wafers, thus making the two wafers a single unit.

[0024] After bonding the device wafer and the carrier wafer, the back side of the device wafer (e.g., the exposed silicon substrate or dielectric layer) can be thinned. Then, vias are formed by etching the silicon substrate or etching the dielectric layer deposited on the back side of the device wafer. Conductive material is deposited in the vias to form via interconnect structures, thereby electrically leading out the device formed on the front side of the device wafer from the back side of the device wafer for electrical connection with other components.

[0025] However, as mentioned above, the device wafer 10 typically exhibits a certain degree of warpage, which reduces the alignment window during photolithography on the back side of the back-side wiring process, resulting in lower alignment accuracy. Furthermore, the device wafer also experiences deformation during the bonding process, further reducing the process window in the back-side wiring process.

[0026] In the wafer bonding process, a vacuum chuck can be used to vacuum-adsorb the device wafer 10, forcibly flattening the warped device wafer 10 for bonding. After bonding is complete, the device wafer 10 is released.

[0027] Understandably, the warped device wafer 10 is forcibly flattened under the force of the vacuum chuck, which subjectes it to significant external forces that can deform it. After bonding, the warped device wafer 10 will recover to its warped state, but it cannot fully return to its original shape, resulting in changes to the shape and position of the patterns on the device wafer 10.

[0028] During the back-side wire bonding process after bonding, changes in the shape and position of the patterns on the device wafer 10 can be corrected during back-side photolithography using overlay (OVL) alignment measurement equipment. However, the overlay alignment measurement equipment can only partially correct these changes in shape and position, not completely. Especially when the warpage of the device wafer 10 differs in the X and Y directions, the degree of deformation in the X and Y directions is different, leading to different degrees of recovery of the device wafer 10 in the X and Y directions after bonding. This results in inconsistent changes in the shape and position of the patterns on the device wafer 10 in the X and Y directions, making it even more difficult to completely correct these changes in shape and position.

[0029] The portion of the device wafer 10 that cannot be corrected due to the wafer bonding process can be called additional alignment residue introduced by the bonding process. The back alignment of small-sized patterns is the part with the smallest alignment process window, and the additional alignment residue further restricts the back alignment of small-sized patterns, thereby reducing the process window of the back alignment process.

[0030] like Figure 1d As shown, after thinning the back side of the device wafer 10 and forming an oxide layer, when the source of the transistor array is brought out, the additional alignment residue causes the through-hole interconnect structure 30 to be misaligned, so that the through-hole interconnect structure 30 is not fully in contact with the source of the transistor 11, and there are even some through-hole interconnect structures 30 that are not in contact with the source of the corresponding transistor 11 (i.e., forming an open circuit), causing abnormal control of the memory array by the transistor array, and thus causing device defects.

[0031] In view of the above problems, this disclosure provides a method for fabricating a semiconductor device. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. See also... Figure 2 The method for fabricating this semiconductor device includes the following steps:

[0032] S100: Provide a first semiconductor structure; wherein the first semiconductor structure includes a stress structure, the stress structure extends along a first direction, the first direction being parallel to the plane in which the first semiconductor structure is located;

[0033] S200: Provides a second semiconductor structure;

[0034] S300: A first stress-adjusting structure is formed on the second semiconductor structure; wherein the first stress-adjusting structure extends along a second direction, the second direction intersects with the first direction and is parallel to the plane of the first semiconductor structure;

[0035] S400: Bonding a first semiconductor structure and a second semiconductor structure including a first stress-adjusting structure; wherein the first stress-adjusting structure is used to adjust the warpage of the first semiconductor structure.

[0036] For example, the first semiconductor structure includes a device wafer on which a memory array and / or peripheral circuitry may be formed. For example, in dynamic random access memory (DRAM), the memory array includes a capacitor array and a transistor array. For example, in phase-change memory (PCM), the memory array includes phase-change memory cells arranged in an array. For example, in non-volatile memory (NVH), the memory array may include memory blocks. It should be noted that the memory array in this disclosure includes bit lines and word lines. For example, the peripheral circuitry includes transistors, interconnect layers, and via interconnect structures, and the peripheral circuitry is used to control the memory array to store data.

[0037] For example, the second semiconductor structure may be a carrier wafer used to support the front side of the first semiconductor structure in the back-side wiring process of the first semiconductor structure. The second semiconductor structure may also be a device wafer used to bond with the first semiconductor structure to achieve electrical connection to form a complete memory device, while simultaneously supporting the front side of the first semiconductor structure in the back-side wiring process of the first semiconductor structure.

[0038] Here, the direction of warping includes positive and negative. Correspondingly, the types of warping include positive warping and negative warping. Negative warping refers to a concave warping where the edge of the warped area lies above the horizontal plane containing the center of the area. Positive warping refers to a convex warping where the edge of the warped area lies below the horizontal plane containing the center of the area.

[0039] It is understandable that the warpage direction of a semiconductor structure is not absolute, but depends on its placement. For example, a first semiconductor structure placed face up has positive warpage, while placing it face down has negative warpage. Here, for ease of description, the first semiconductor structure is defined to include a first and a second surface positioned opposite each other, and the second semiconductor structure includes a third and a fourth surface positioned opposite each other.

[0040] For semiconductor structures, the warp state is typically described by the degree of warp along two mutually perpendicular horizontal directions. For example, a semiconductor structure may have positive warp in a first direction and negative warp in a second direction. For instance, one of the first and second directions may be the word line extension direction, and the other the bit line extension direction.

[0041] The degree of warping can be characterized by warping degree, which is the distance between the two points that are furthest apart in the height direction of the warped plane.

[0042] For example, the warpage of the first semiconductor structure in the first direction refers to the distance between two points selected on a straight line from the first surface along the first direction, which are the furthest apart along the thickness direction of the first semiconductor structure. The warpage of the first semiconductor structure in the first direction can be represented by the distance between these two points along the thickness direction of the first semiconductor structure.

[0043] For example, the warpage difference can refer to the difference in warpage of the first semiconductor structure in the first direction and the second direction.

[0044] In this disclosure, the stress structure can be a single integral structure or it can comprise multiple stress elements. In some embodiments, the stress structure may include multiple stress elements extending along a first direction. In other embodiments, the stress structure may also include multiple stress elements arranged side-by-side along the first direction. Here, it should be understood that the stress structure extending along the first direction may cause the first semiconductor structure to warp in the first direction, or it may cause the first semiconductor structure to warp in the second direction, or it may cause the first semiconductor structure to warp in both the first and second directions, and the degree of warping and / or the direction of warping are different, resulting in a warping difference.

[0045] Here, the first stress adjustment structure can be a single unit or comprise multiple stress adjustment units. The first stress adjustment structure can apply stress to the second semiconductor structure, thereby adjusting the area, arrangement, and composition of the first stress adjustment structure according to the warpage state of the first semiconductor structure to induce warpage in the second semiconductor structure. This reduces the warpage difference of the first semiconductor structure after the second semiconductor structure and the first semiconductor structure are bonded together.

[0046] In some embodiments, when the stress structure includes a plurality of stress elements extending along a first direction and the plurality of stress elements are arranged side by side along a second direction, the first stress adjustment structure may include a plurality of stress adjustment elements, wherein the stress adjustment elements extend along the second direction, the plurality of stress adjustment elements are arranged side by side along the first direction, the size of the stress adjustment elements along the first direction is substantially equal to the size of the stress elements along the second direction, and the spacing between two adjacent stress adjustment elements is substantially equal to the spacing between two adjacent stress elements.

[0047] Thus, when the stress structure causes the first semiconductor structure to warp significantly in the second direction, the first stress structure can cause the second semiconductor structure to warp significantly in the first direction. After bonding the first and second semiconductor structures, the first stress adjustment structure and the stress structure can cause the first semiconductor structure to warp in the first and second directions with the same warp direction and essentially the same warp degree, thereby reducing the warp degree difference of the first semiconductor structure. This reduces the additional alignment residue introduced by the bonding process, reduces the overlay error introduced by the bonding process to the first layer of photolithography on the back side, and reduces the impact on the alignment window in the back lead process.

[0048] In some embodiments, the first stress adjustment structure and the stress structure are made of the same material.

[0049] In some embodiments, the material of the first stress-adjusting structure includes at least one of metal, silicon nitride, or polycrystalline silicon. Metal films, silicon nitride films, and polycrystalline silicon films generate significant stress during deposition, which can substantially alter the warpage of the second semiconductor structure. Here, the metal may include tungsten, aluminum, copper, and tantalum, etc.

[0050] In some embodiments, when the first stress-adjusting structure needs to contact a film layer including a metal wire or via interconnect structure on the first semiconductor structure and / or the second semiconductor structure, the material of the first stress-adjusting structure is selected to be an insulating material (e.g., silicon nitride) to avoid affecting the electrical performance of the first semiconductor structure and / or the second semiconductor structure.

[0051] Figures 3a to 3f This is a schematic diagram of the structure of a semiconductor device during its fabrication process, provided as an embodiment of the present disclosure. Figure 3b yes Figure 3a The first semiconductor structure shown is a cross-sectional view along line AA. Figure 3d yes Figure 3c The second semiconductor structure shown is a cross-sectional view along line BB. Figure 3f yes Figure 3d The semiconductor device shown is a cross-sectional view along the CC line. Figure 3f The structures marked 311 and 312 in the diagram are not actually visible; they are projections of the actual first sub-stress adjustment unit 311 and second sub-stress adjustment unit 312 onto this cross-sectional view. The following section will combine... Figures 3a to 3f A method for fabricating a semiconductor device provided in this disclosure is described in detail.

[0052] For example, the first direction and the second direction are perpendicular to each other, with the first direction being the X direction and the second direction being the Y direction. In other embodiments, the first direction and the second direction may intersect but not be perpendicular.

[0053] It should be noted that, in the context of Figures 3a to 3fThe positive and negative warpages mentioned in the detailed description are based on the fact that the third surface 210 of the second semiconductor structure 200, including the first stress adjustment structure 310, is positioned toward the first surface 110 of the first semiconductor structure 100.

[0054] Please refer to Figure 3a and Figure 3b A first semiconductor structure 100 is provided. In this embodiment, the first semiconductor structure 100 is a device wafer including a transistor array. Correspondingly, S100 includes the following steps:

[0055] Provide a base;

[0056] A transistor array is formed on one side of the substrate. The transistor array includes a plurality of transistors 101 arranged in an array. Each transistor 101 includes a source, a channel, and a drain arranged in parallel along a third direction.

[0057] Multiple conductive lines 102 extending along a first direction (X direction) are formed, and the conductive lines 102 are coupled to the channels of multiple transistors 101 arranged in parallel along the first direction; the stress structure includes multiple conductive lines 102.

[0058] For example, conductor 102 is a word line.

[0059] In some embodiments, step S100 further includes:

[0060] Multiple bit lines 103 extending along a second direction (Y direction) are formed; wherein the bit lines 103 are in contact with the drains of multiple transistors 101 arranged in parallel along the second direction.

[0061] For example, the third direction is perpendicular to the first and second directions. The third direction is the Z direction.

[0062] like Figure 3a and 3b As shown, the substrate includes a first surface and a second surface disposed opposite to each other (the first surface and the second surface of the substrate are also the first surface 110 and the second surface 120 of the first semiconductor structure 100). The first surface 110 of the substrate forms a transistor pillar array, which includes a plurality of transistors 101 arranged in an array. Each transistor 101 includes a drain, a channel and a source disposed sequentially from the first surface 110 to the second surface 120 along a first direction.

[0063] See further Figure 3aThe transistor 101 provided in this embodiment is a dual-gate transistor. The conductive line 102 includes a first sub-conductive line 1021 and a second sub-conductive line 1022, which are located on opposite sides of the channel of the same transistor 101. Specifically, the first sub-conductive line 1021 and the second sub-conductive line 1022 are located on opposite sides of the channel along a second direction, and a gate dielectric layer is further provided between the first sub-conductive line 1021 and the second sub-conductive line 1022 and the side walls of the channel.

[0064] Furthermore, along the first direction, the relatively close ends of adjacent first sub-conducting lines 1021 and 1022 have a predetermined distance L. In a dual-gate transistor with a vertical channel (meaning the channel extends along the Z direction), the spacing between the first sub-conducting lines 1021 and 1022 is small. If conductive plugs are placed on the same side of the first and second sub-conducting lines 1021 and 1022 along the first direction for lead-out, the process is difficult. Therefore, the first and second sub-conducting lines 1021 and 1022 are staggered, so that along the first direction, the relatively close ends of adjacent first and second sub-conducting lines 1021 and 1022 have a predetermined distance L. That is, one end of the first sub-conducting line 1021 protrudes beyond the second sub-conducting line 1022 along the first direction, and one end of the second sub-conducting line 1022 protrudes beyond the first sub-conducting line 1021 along the first direction. This increases the process window for lead-out of the conductive line 102 and reduces the process difficulty of lead-out of the conductive line 102.

[0065] Here, the first sub-conducting line 1021 and the second sub-conducting line 1022 are word lines. When a voltage is applied to the word line, a channel along the third direction (Z direction) is formed between the drain and source of the transistor, and charge carriers flow in the channel to conduct the source and drain.

[0066] During the formation of the transistor array, word lines extend along a first direction, resulting in an uneven distribution of word lines in the first and second directions. This leads to different warpages of the first semiconductor structure in the first (X) and second (Y) directions, creating a warpage difference. Therefore, in this embodiment, the conductive lines are stress units, and the stress structure includes multiple conductive lines extending along the first direction.

[0067] For example, the first semiconductor structure 100 including the stress structure is negatively warped in a first direction and positively warped in a second direction, and the degree of warping in the second direction is less than the degree of warping in the first direction, resulting in a warping difference between the first semiconductor structure 100 in the first and second directions.

[0068] Please refer to Figure 3c and Figure 3dA first stress-adjusting structure is formed on the second semiconductor structure. Here, the second semiconductor structure 200 is a carrier wafer.

[0069] This disclosure does not limit the warpage of the second semiconductor structure 200 before the first stress adjustment structure 310 is formed. For example, the warpage of the second semiconductor structure 200 before the first stress adjustment structure 310 is formed is essentially zero.

[0070] In some embodiments, the first stress adjustment structure 310 may be disposed on the third surface 210 or the fourth surface 220 of the second semiconductor structure 200.

[0071] The first stress adjustment structure 310 is disposed on the third surface 210 or the fourth surface 220 of the second semiconductor structure 200, depending on the warpage of the first semiconductor structure and the material of the first stress adjustment structure.

[0072] For example, when a positive warping of the second semiconductor structure along the second direction is required, a tungsten layer can be deposited on the fourth surface of the second semiconductor structure. The tungsten layer applies compressive stress to the second semiconductor structure, causing positive warping. When a negative warping of the second semiconductor structure along the second direction is required, a tungsten layer can be deposited on the third surface of the second semiconductor structure. The tungsten layer applies compressive stress to the second semiconductor structure, causing negative warping.

[0073] Figure 3c and Figure 3d In the second semiconductor structure 200, a first stress adjustment structure 310 is formed. This first stress adjustment structure 310 includes a plurality of first sub-stress adjustment units 311 and a plurality of second sub-stress adjustment units 312 arranged alternately in a first direction. The first sub-stress adjustment units 311 and the second sub-stress adjustment units 312 extend along a second direction. By adjusting the number, spacing, length, arrangement, and materials of the first sub-stress adjustment units 311 and the second sub-stress adjustment units 312, different warpages can be generated in the first and second directions.

[0074] In this embodiment, the warping directions of the first semiconductor structure 100 in the first and second directions are opposite, and the warping degree in the first direction is less than that in the second direction. Based on this, a first sub-stress adjustment unit 311 and a second sub-stress adjustment unit 312 extending along the second direction are formed on the second semiconductor to cause the second semiconductor structure 200 to undergo a larger degree of negative warping in the second direction and a smaller degree of positive warping (or almost no warping) in the first direction. Thus, after the first semiconductor structure 100 and the second semiconductor structure 200 are bonded, the negative warping of the first semiconductor structure 100 in the first direction can be slightly reduced, and its positive warping in the second direction can be changed to a smaller negative warping, thereby reducing the difference in warping degree between the first semiconductor structure 100 in the first and second directions.

[0075] In subsequent processes, a second stress adjustment structure 320 can be formed on the second semiconductor structure 200 to generate positive warping of the second semiconductor structure 200 as a whole, which is used to reduce the negative warping of the first semiconductor structure as a whole after bonding, thereby obtaining a relatively flat first semiconductor structure 100.

[0076] In some embodiments, the arrangement of the first sub-stress adjustment unit 311 and the second sub-stress adjustment unit 312 is based on the material, spacing, and arrangement of the first sub-conductive wire 1021 and the second sub-conductive wire 1022. Specifically, S300 includes:

[0077] Multiple first sub-stress adjustment units 311 and multiple second sub-stress adjustment units 312 are formed to cover the second semiconductor structure; wherein, the material of the first sub-stress adjustment unit 311 is the same as that of the second sub-stress adjustment unit 312, the size and spacing of the first sub-stress adjustment unit 311 and the second sub-stress adjustment unit 312 along the first direction are substantially equal to the size and spacing of the first sub-conductive line 1021 and the second sub-conductive line 1022 along the second direction, and the relatively close ends of adjacent first sub-stress adjustment units 311 and second sub-stress adjustment units 312 along the second direction have a preset distance L.

[0078] In other words, the spacing between two adjacent first sub-stress adjustment units 311 is basically equal to the spacing between two adjacent first sub-conductive lines 1021, the spacing between two adjacent second sub-stress adjustment units 312 is basically equal to the spacing between two adjacent second sub-conductive lines 1022, and the spacing between adjacent first sub-stress adjustment units 311 and second sub-stress adjustment units 312 is basically equal to the spacing between adjacent first sub-conductive lines 1021 and second sub-conductive lines 1022.

[0079] For example, the first sub-stress adjustment unit 311 and the second sub-stress adjustment unit 312 are made of at least one of metal, silicon nitride, or polycrystalline silicon. Metal films, silicon nitride films, and polycrystalline silicon films generate significant stress during deposition, which can significantly alter the warpage of the second semiconductor structure 200.

[0080] For example, the first sub-stress adjustment unit 311 is made of the same material as the first sub-conductive wire 1021, and the second sub-stress adjustment unit 312 is made of the same material as the first sub-conductive wire 1021. Here, the first sub-stress adjustment unit 311, the second sub-stress adjustment unit 312, the first sub-conductive wire 1021, and the second sub-conductive wire 1022 can all be made of tungsten.

[0081] In this embodiment, the arrangement of the first sub-stress adjustment unit 311 and the second sub-stress adjustment unit 312 allows the warpage of the second semiconductor structure 200 in the second direction to be approximately equal to the warpage of the first semiconductor structure 100 in the first direction. This reduces the positive warpage of the first semiconductor structure 100 in the second direction after bonding, while also better controlling the warpage of the second semiconductor structure 200.

[0082] It is understandable that when the warpage of the second semiconductor structure 200 in the second direction is approximately equal to the warpage of the first semiconductor structure 100 in the first direction, the warpage difference of the first semiconductor structure 100 after bonding will necessarily be less than before bonding. Therefore, in this embodiment, the arrangement of the first sub-stress adjustment unit 311 and the second sub-stress adjustment unit 312 can better control the warpage of the second semiconductor structure 200, thereby better controlling the warpage of the first semiconductor structure 100 in the second direction, and reducing the warpage difference of the first semiconductor structure 100 after bonding. Furthermore, the mask used to form the conductive line 102 can be used to form the first stress adjustment structure 310, thereby saving costs.

[0083] In some embodiments, when the warpage difference of the first semiconductor structure 100 in the first direction and the second direction is greater, the spacing between the first sub-stress adjustment unit 311 and the second sub-stress adjustment unit 312 can be reduced, or the spacing between adjacent first sub-stress adjustment units 311 can be reduced, or the spacing between adjacent second sub-stress adjustment units 312 can be reduced; or the distance between the same ends of adjacent first sub-stress adjustment units 311 and second sub-stress adjustment units 312 can be shortened, thereby increasing the negative warpage of the second semiconductor structure 200 in the second direction to a greater extent, and reducing the positive warpage of the first semiconductor structure 100 in the second direction to a greater extent after bonding, thereby reducing the warpage difference of the first semiconductor structure 100.

[0084] It is understood that in some embodiments, the transistor 101 may be a single-gate transistor, with the conductive line 102 located on one side of the channel along the second direction, and each conductive line being a stress unit. Correspondingly, step S300 includes:

[0085] Multiple stress-adjusting units are formed to cover the third surface 210 or the fourth surface 220 of the second semiconductor structure; wherein the stress-adjusting units extend along the second direction, the multiple stress-adjusting units are arranged side by side along the first direction, the size of the stress-adjusting unit along the first direction is basically equal to the size of the conductive line along the second direction, and the spacing between two adjacent stress-adjusting units is basically equal to the spacing between two adjacent conductive lines.

[0086] For example, the first stress adjustment structure 310 and the conductive wire 102 are made of the same material. Here, both the first stress adjustment structure 310 and the conductive wire 102 are made of tungsten.

[0087] It is understood that the first stress adjustment structure 310 is not limited to the structure provided in the above embodiments of this disclosure. In other embodiments, the first stress adjustment structure 310 can be adaptively adjusted according to the warpage of the first semiconductor structure 100. For example, for Figure 3a and Figure 3b The first semiconductor structure shown may further include a plurality of semi-circular stress units, which are arranged in parallel along a first direction.

[0088] In addition, such as Figure 3c As shown, the fabrication method further includes forming a filling structure 330 in the region of the third surface 210 not covered by the first stress-adjusting structure 310. The filling structure 330 is made of materials including, but not limited to, silicon oxide, and the filling structure 330 contributes little to the stress of the second semiconductor structure 200.

[0089] In some embodiments, such as Figure 3c As shown, S300 also includes:

[0090] Before forming the first stress adjustment structure 310, a second stress adjustment structure 320 is formed on the second semiconductor structure 200; wherein, the second stress adjustment structure 320 is located between the second semiconductor structure 200 and the first stress adjustment structure 310, and the orthogonal projection of the second stress adjustment structure 320 onto the plane of the second semiconductor structure 200 covers the second semiconductor structure 200, and the second stress adjustment structure 320 is used to reduce the overall warpage of the first semiconductor structure 100.

[0091] like Figure 3cAs shown, the second stress adjustment structure 320 covers the entire surface of the second semiconductor structure 200 and is used to warp the second semiconductor structure 200 as a whole, so as to reduce the warpage of the first semiconductor structure 100 as a whole after the second semiconductor structure 200 and the first semiconductor structure 100 are bonded.

[0092] For example, the material of the second stress adjustment structure 320 includes at least one of metal, silicon nitride, or polycrystalline silicon.

[0093] The present disclosure does not limit the positions of the second stress adjustment structure 320 and the first stress adjustment structure 310. In this embodiment, the second stress adjustment structure 320 is disposed between the first stress adjustment structure 310 and the second semiconductor structure 200. In other embodiments, the first stress adjustment structure 310 may also be disposed between the second stress adjustment structure 320 and the second semiconductor structure 200, or the second stress adjustment structure 320 and the first stress adjustment structure 310 may be disposed on different surfaces of the second semiconductor structure 200. In this embodiment, the first stress adjustment structure 310 and the second stress adjustment structure 320 are disposed on the same surface (e.g., the third surface 210) so that the second semiconductor structure 200 can be removed while retaining the first stress adjustment structure 310 and the second stress adjustment structure 320 during the subsequent formation of the semiconductor device.

[0094] It should be noted that, in some embodiments, a third stress adjustment structure may also be formed on the first surface 110 of the first semiconductor structure 100, wherein the orthographic projection of the third stress adjustment structure onto the plane of the first semiconductor structure 100 covers the first semiconductor structure 100, and the third stress adjustment structure is used to reduce the warpage of the first semiconductor structure 100.

[0095] The third stress adjustment structure serves the same purpose as the second stress adjustment structure: to reduce the overall warpage of the first semiconductor structure. However, compared to setting the first and second stress adjustment structures on the second semiconductor structure, this embodiment sets the first stress adjustment structure on the second semiconductor structure and the third stress adjustment structure on the first semiconductor structure, which can shorten the process cycle of the semiconductor device and improve production efficiency.

[0096] like Figure 3e and Figure 3f As shown, the third surface 210 of the second semiconductor structure 200 and the first surface 110 of the first semiconductor structure 100 are bonded together.

[0097] The bonding methods for the first semiconductor structure 100 and the second semiconductor structure 200 include, but are not limited to, hot-press bonding, eutectic bonding, anodic bonding, or fusion bonding.

[0098] In some embodiments, when hot-press bonding the first semiconductor structure 100 and the second semiconductor structure 200 is used, it is required that both the bonding surfaces of the first semiconductor structure 100 and the second semiconductor structure 200 are hydrophilic or hydrophobic. Therefore, before bonding the third surface 210 of the second semiconductor structure 200 and the first surface 110 of the first semiconductor structure 100, the fabrication method further includes:

[0099] A first bonding layer 401 is formed on the first surface 110 of the first semiconductor structure 100;

[0100] A second bonding layer 402 is formed on the first stress adjustment structure 310; wherein the second bonding layer 402 has essentially the same hydrophilicity as the first bonding layer 401.

[0101] Correspondingly, the S400 includes:

[0102] Bonding the second bonding layer 402 and the first bonding layer 401.

[0103] It should be noted that if the first stress-adjusting structure 310 is formed on the fourth surface 220 of the second semiconductor structure 200, then the second bonding layer 402 is formed on the third surface 210 of the second semiconductor structure 200 where the first stress-adjusting structure 310 is not formed. If a third stress-adjusting structure is formed on the first semiconductor structure 100, then the first bonding layer 401 is formed on the third stress-adjusting structure.

[0104] It should be noted that hot-press bonding only requires hydrophilicity or hydrophobicity, and does not restrict the specific material of the bonding surface. Therefore, in some embodiments, the materials of the first bonding layer 401 and the second bonding layer 402 can be different. In other embodiments, the materials of the first bonding layer 401 and the second bonding layer 402 can be the same.

[0105] For example, both the first bonding layer 401 and the second bonding layer 402 are hydrophilic. The material of the first bonding layer 401 may include at least one of silicon oxide or silicon nitride, and the material of the second bonding layer 402 may include one of silicon oxide or silicon nitride.

[0106] In this embodiment, the first bonding layer 401 is made of silicon oxide, and the second bonding layer 402 is also made of silicon oxide.

[0107] For example, the first bonding layer 401 and the second bonding layer 402 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, silicon oxide can be formed on the third surface 210 of the second semiconductor structure 200 where the first stress adjustment structure 310 is not formed by a thermal oxidation process.

[0108] like Figure 3e and 3g As shown, after bonding the first stress-adjusting structure and the first semiconductor structure, the fabrication method further includes:

[0109] A through-hole interconnect structure 510 and a through-silicon via (TSV) interconnect structure 520 are formed on the side of the first semiconductor structure 100 that is relatively far away from the second semiconductor structure 200; wherein, the through-hole interconnect structure 510 is coupled to the source of the transistor, and the through-silicon via interconnect structure 520 is coupled to the bit line 103.

[0110] After forming the through-hole interconnect structure 510 and the through-silicon via (TSV) interconnect structure 520, the second semiconductor structure 200 is removed.

[0111] In some embodiments, the step of forming a via interconnect structure 510 coupled to the source of transistor 101 includes:

[0112] Thin the second surface 120 of the first semiconductor structure 100 to expose the source of the transistor 101;

[0113] A first dielectric layer is formed on the second surface 120 of the thinned first semiconductor structure 100;

[0114] The first dielectric layer is etched to form the first via, and the first via exposes the source of the transistor;

[0115] A conductive material is filled into the first through-hole to form a through-hole interconnect structure 510.

[0116] like Figure 3e As shown, when the second semiconductor structure 200, including the first stress adjustment structure 310, and the first semiconductor structure 100 are bonded, the first semiconductor structure 100 has a small warpage and warpage difference. Therefore, when forming the via interconnect structure 510, the via can be well aligned with the source of the transistor 101, ensuring good contact between the via interconnect structure 510 and the source of the transistor 101, thereby ensuring good electrical connection of the device and improving the reliability of the device.

[0117] Furthermore, in some embodiments, the step of forming the through-silicon via interconnect structure 520 coupled to bit line 103 includes:

[0118] After forming a first dielectric layer on the second surface 120 of the thinned first semiconductor structure 100, the first dielectric layer is etched to form a second via, and the second via exposes bit line 103.

[0119] The second via is filled with conductive material to form a through-silicon via interconnect structure 520.

[0120] Here, a via interconnect structure 510 coupled to the source of the transistor is formed. This via interconnect structure 510 can be electrically connected to a capacitor array to control the capacitor array via the transistor array. A through-silicon via interconnect structure 520 coupled to the bit line 103 is formed to electrically connect the bit line to peripheral circuitry.

[0121] Furthermore, in this embodiment, the second semiconductor structure 200 is a carrier wafer; therefore, the method for fabricating the semiconductor device further includes removing the second semiconductor structure 200.

[0122] like Figure 3g As shown, the second semiconductor structure 200 is removed while the first stress adjustment structure 310 and the second stress adjustment structure 320 are retained, so that in subsequent processes, the first stress adjustment structure 310 and the second stress adjustment structure 320 can maintain the first semiconductor structure 100 with a small warpage.

[0123] In this disclosure, the first semiconductor structure includes a stress structure extending along a first direction. When the stress structure causes warping in a certain region of the first semiconductor structure, a first stress adjustment structure extending along a second direction can be formed on the second semiconductor structure according to the warping degree of the first semiconductor structure, causing warping in a region of the second semiconductor structure perpendicular to the warped region of the first semiconductor structure. After bonding the first semiconductor structure and the second semiconductor structure including the first stress adjustment structure, the first stress adjustment structure and the stress structure can cause two mutually perpendicular regions of the first semiconductor structure to form warping with substantially the same warping degree and the same warping direction, thereby reducing the warping degree difference between different regions of the first semiconductor structure, thereby reducing the additional alignment residue introduced by the bonding process, reducing the overlay error introduced by the bonding process to the first back-side photolithography, and increasing the process window of the back-side lead process.

[0124] Furthermore, in this embodiment of the present disclosure, a second stress adjustment structure can also be formed on the second semiconductor structure. The projection of the second stress adjustment structure onto the plane of the second semiconductor structure covers the second semiconductor structure, thereby reducing the overall warpage of the first semiconductor structure after bonding and obtaining a relatively flat first semiconductor structure, further increasing the process window of the back lead process.

[0125] Furthermore, in the semiconductor device fabrication method provided in this disclosure, since the first stress-adjusting structure does not completely cover the surface of the second semiconductor structure, photolithography and etching processes are required when forming the first stress-adjusting structure. In this disclosure, choosing to form the first stress-adjusting structure on the second semiconductor structure can eliminate the need for photolithography and etching processes when forming the first stress-adjusting structure on the first semiconductor structure, thereby reducing contamination of the first semiconductor structure.

[0126] This disclosure also provides a method for reducing the warpage and / or warpage difference of a first semiconductor structure, wherein in some embodiments, step S300 includes:

[0127] A first stress-adjusting structure is formed on the second semiconductor structure, wherein the warping direction of the second semiconductor structure including the first stress-adjusting structure is opposite to the warping direction of the first semiconductor structure.

[0128] This embodiment does not limit the specific form of the first stress adjustment structure. Any first stress adjustment structure that can achieve the above-mentioned warping is within the protection scope of this disclosure.

[0129] Figure 4 and Figure 5 This is a schematic diagram showing the warping of the first and second semiconductor structures provided in the embodiments of this disclosure before bonding. The following is in conjunction with... Figure 4 and Figure 5 This disclosure describes yet another method for reducing the warpage and / or warpage difference of a first semiconductor structure.

[0130] In this disclosure, the warping direction of the second semiconductor structure, including the first stress adjustment structure, is opposite to the warping direction of the first semiconductor structure, based on the situation where the third surface of the second semiconductor structure and the first surface of the first semiconductor structure are arranged opposite to each other.

[0131] In some embodiments, such as Figure 4 As shown, the third surface 210 of the second semiconductor structure 200, including the first stress adjustment structure 310, is disposed facing the first surface 110 of the first semiconductor structure 100. When the first semiconductor structure 100 warps negatively along the second direction, the second semiconductor structure 200, including the first stress adjustment structure 310, can warp positively along the second direction. Thus, when the first semiconductor structure 100 and the second semiconductor structure 200 are bonded, the warpage of the first semiconductor structure 100 along the second direction can be reduced, thereby reducing the warpage difference of the first semiconductor structure.

[0132] In some embodiments, the first semiconductor structure may have a positive warp along a first direction and a negative warp along a second direction, and the first semiconductor structure as a whole may have a saddle-shaped warp.

[0133] Correspondingly, the second semiconductor structure, including the first stress adjustment structure, should form negative warpage in the first direction and positive warpage in the second direction, thereby reducing the degree of warpage of the first semiconductor structure in the first and second directions after bonding, and reducing the warpage difference and overall warpage of the first semiconductor structure.

[0134] In some embodiments, such as Figure 5As shown, the first semiconductor structure 100 exhibits negative warping in the central region and positive warping in the edge region surrounding the central region, resulting in an overall M-shaped warping. Correspondingly, the second semiconductor structure 200, including the first stress structure 310, should exhibit positive warping in the central region and negative warping in the edge region, thereby reducing the overall warping degree of the first semiconductor structure after bonding.

[0135] Therefore, it is understood that the warping direction of the second semiconductor structure including the first stress adjustment structure described in this disclosure is opposite to the warping direction of the first semiconductor structure. This can be either the overall warping direction of the second semiconductor structure being opposite to the overall warping direction of the first semiconductor structure, or the warping direction of the second semiconductor structure being opposite to the warping direction of the first semiconductor structure in at least one horizontal direction (e.g., the first direction or the second direction), or the warping direction of the second semiconductor structure being opposite to the warping direction of the first semiconductor structure in a region corresponding to at least one region where the first semiconductor structure warps.

[0136] In this embodiment, a first stress adjustment structure is formed on the third and / or fourth surface of the second semiconductor structure according to the warpage of the first semiconductor structure. This makes the warpage direction of the second semiconductor structure, including the first stress adjustment structure, opposite to the warpage direction of the first semiconductor structure. After the second semiconductor structure and the first semiconductor structure are bonded, when the second semiconductor structure recovers its warpage, it can apply stress to the first semiconductor structure, adjusting the warpage of the first semiconductor structure in a certain direction or a certain region to reduce the warpage difference of the first semiconductor structure, or to reduce the overall warpage of the first semiconductor structure. This reduces the overlay error introduced by the bonding process to the first layer of photolithography on the back side, and increases the process window of the back lead process.

[0137] In some embodiments, the degree of warpage of the second semiconductor structure, which includes the first stress-adjusting structure, is substantially the same as the degree of warpage of the first semiconductor structure.

[0138] Here, the warpage degree of the second semiconductor structure, including the first stress-adjusting structure, is substantially the same as that of the first semiconductor structure. This can mean that the overall warpage degree of the second semiconductor structure is the same as that of the first semiconductor structure, or that the warpage degree of the second semiconductor structure is the same as that of the first semiconductor structure in at least one horizontal direction, or that the warpage degree of the second semiconductor structure is the same as that of the first semiconductor structure in at least one region corresponding to the warpage region of the first semiconductor structure. The purpose of ensuring that the warpage degree of the second semiconductor structure, including the first stress-adjusting structure, is substantially the same as that of the first semiconductor structure is to ensure that the warpage degree of the first semiconductor structure is essentially zero after bonding, i.e., that the first semiconductor structure is relatively flat, thereby minimizing the overlay error introduced by the bonding process to the first layer of photolithography on the back side.

[0139] In this disclosure, when the first semiconductor structure has a large positive warp in the first direction and a small negative warp in the second direction, a first stress adjustment structure can be formed on the second semiconductor structure to cause the second semiconductor structure to have negative warp in the first direction, with the degree of warp being almost the same as the positive warp of the first semiconductor structure, and positive warp in the second direction, with the degree of warp being almost the same as the negative warp of the first semiconductor structure. In this way, when the first semiconductor structure and the second semiconductor structure are bonded, the warp difference and warp of the first semiconductor structure are reduced.

[0140] When the first semiconductor structure still exhibits the same warp state—that is, a large positive warp in the first direction and a small negative warp in the second direction—a first stress-adjusting structure can be formed first on the third surface of the second semiconductor structure. This causes the second semiconductor structure to form a small negative warp in the first direction and a large positive warp in the second direction. Then, a second stress-adjusting structure can be formed on the third surface of the second semiconductor structure, causing the second semiconductor as a whole to form a negative warp. The first stress-adjusting structure is used to ensure that the bonded first semiconductor structure maintains a small positive warp in the first direction, while changing from negative warp to a small positive warp in the second direction. The second stress-adjusting structure is used to reduce the overall positive warp of the first semiconductor structure after bonding, thereby making the first semiconductor structure more flat.

[0141] It is evident that when a combination of the first stress adjustment structure and the second stress adjustment structure is adopted, the warpage state of the second semiconductor structure, including the first stress adjustment structure and the second stress adjustment structure, can be better matched with the warpage state of the first semiconductor structure, resulting in a flatter first semiconductor structure.

[0142] This disclosure provides a semiconductor device, such as Figure 3gAs shown, the semiconductor device includes:

[0143] A first semiconductor structure 100 includes a memory array and / or peripheral circuitry, wherein the memory array and / or peripheral circuitry includes a stress structure that extends along a first direction.

[0144] The first stress adjustment structure 310 extends along the second direction and is used to adjust the warpage of the first semiconductor structure.

[0145] The semiconductor device provided in this disclosure includes a first semiconductor structure comprising a stress structure extending along a first direction, and a first stress adjustment structure extending along a second direction. The first stress adjustment structure is configured according to the stress structure. The first stress adjustment structure and the stress structure enable two mutually perpendicular regions (or two horizontal directions) of the first semiconductor structure to form warps with substantially the same warp degree and the same warp direction, thereby reducing the warp degree difference (delta bow) of different regions (or different directions) of the first semiconductor structure, thereby reducing the overlay error introduced by the bonding process to the first layer photolithography on the back side, and increasing the process window of the back lead process.

[0146] In some embodiments, the stress structure includes a plurality of stress elements extending along a first direction, and the plurality of stress elements are arranged side by side along a second direction;

[0147] The first stress adjustment structure includes multiple stress adjustment units extending along the second direction. The multiple stress adjustment units are arranged side by side along the first direction. The size of the stress adjustment unit along the first direction is basically equal to the size of the stress unit along the second direction. The spacing between two adjacent stress adjustment units is basically equal to the spacing between two adjacent stress units.

[0148] For example, the material of the first stress-adjusting structure includes at least one of metal, silicon nitride, or polycrystalline silicon.

[0149] In some embodiments, the first semiconductor structure 100 includes:

[0150] A substrate, on one side of which is a transistor array, the transistor array including multiple transistors 101, the transistors including source, channel and drain arranged in parallel along a third direction;

[0151] Multiple conductive lines 102 extend along a first direction and are coupled to the channels of multiple transistors 101 arranged in parallel along the first direction; the stress structure includes multiple conductive lines 102.

[0152] Multiple bit lines 103 extend along a second direction and are coupled to the drains of multiple transistors 101 arranged in parallel along the second direction.

[0153] In some embodiments, transistor 101 in the transistor array is a single-gate transistor;

[0154] The first stress adjustment structure 310 includes a plurality of stress adjustment units arranged in parallel along a first direction, wherein the spacing between two adjacent stress adjustment units is substantially equal to the spacing between two adjacent conductive lines 102.

[0155] In some embodiments, the transistor 101 in the transistor array is a dual-gate transistor, and the conductive line 102 includes a first sub-conductive line 1021 and a second sub-conductive line 1022. The first sub-conductive line 1021 and the second sub-conductive line 1022 are respectively located on both sides of the channel of the same transistor 101. Along the first direction, the relatively close ends of adjacent first sub-conductive lines and second sub-conductive lines have a preset distance.

[0156] The first stress adjustment structure 310 includes a plurality of first sub-stress adjustment units 311 and a plurality of second sub-stress adjustment units 312 arranged alternately in parallel along a first direction. The composition materials of the first sub-stress adjustment units 311 and the second sub-stress adjustment units 312 are the same. Both the first sub-stress adjustment units 311 and the second sub-stress adjustment units 312 extend along a second direction. The size and spacing of the first sub-stress adjustment units 311 and the second sub-stress adjustment units 312 along the first direction are basically equal to the size and spacing of the first sub-conductive wire 1021 and the second sub-conductive wire 1022 along the second direction. Along the second direction, the relatively close ends of adjacent first sub-stress adjustment units 311 and second sub-stress adjustment units 312 have a preset distance.

[0157] In other words, the spacing between two adjacent first sub-stress adjustment units 311 is basically equal to the spacing between two adjacent first sub-conductive lines 1021, the spacing between two adjacent second sub-stress adjustment units 312 is basically equal to the spacing between two adjacent second sub-conductive lines 1022, and the spacing between adjacent first sub-stress adjustment units 311 and second sub-stress adjustment units 312 is basically equal to the spacing between adjacent first sub-conductive lines 1021 and second sub-conductive lines 1022.

[0158] For example, the first sub-stress adjustment unit 311 and the second sub-stress adjustment unit 312 are made of at least one of metal, silicon nitride or polycrystalline silicon.

[0159] For example, the first sub-stress adjustment unit 311 and the first sub-conductive wire 1021 are made of the same material, and the second sub-stress adjustment unit 312 and the second sub-conductive wire 1022 are made of the same material. Here, the materials of the first sub-stress adjustment unit 311, the second sub-stress adjustment unit 312, the first sub-conductive wire 1021, and the second sub-conductive wire 1022 include tungsten.

[0160] In some embodiments, the semiconductor device further includes a second stress adjustment structure 320, which is located on the side of the first stress adjustment structure 310 that is relatively far away from the first semiconductor structure 100. The orthographic projection of the second stress adjustment structure 320 onto the plane of the first semiconductor structure 100 covers the first semiconductor structure 100. The second stress adjustment structure 320 is used to reduce the overall warpage of the first semiconductor structure 100.

[0161] In some embodiments, the material of the second stress adjustment structure 320 includes one of metal, silicon nitride, or polycrystalline silicon.

[0162] In some embodiments, the semiconductor device further includes: a third stress adjustment structure located between the first stress adjustment structure and the first semiconductor structure, wherein the orthographic projection of the third stress adjustment structure onto the plane of the first semiconductor structure covers the first semiconductor structure, and the third stress adjustment structure is used to reduce the overall warpage of the first semiconductor structure.

[0163] In some embodiments, the semiconductor device further includes a first bonding layer 401 and a second bonding layer 402, wherein the first bonding layer 401 and the second bonding layer 402 have substantially the same hydrophilicity.

[0164] In some embodiments, the first bonding layer 401 and the second bonding layer 402 are located between the first semiconductor structure 100 and the first stress adjustment structure 310, and the first bonding layer 401 is located between the first semiconductor structure 100 and the second bonding layer 402.

[0165] In some embodiments, when a second stress-adjusting structure is formed on the first semiconductor structure 100, the first bonding layer 401 and the second bonding layer 402 are located between the second stress-adjusting structure and the first stress-adjusting structure 310, and the first bonding layer 401 is located between the second stress-adjusting structure and the second bonding layer 402.

[0166] In some embodiments, the semiconductor device further includes a through-hole interconnect structure 510 located on the side of the first semiconductor structure 100 relatively away from the first stress-adjusting structure 310, the interconnect structure being coupled to the source of the transistor; and / or,

[0167] The semiconductor device also includes a through-silicon via interconnect structure 520 located on the side of the first semiconductor structure 100 that is relatively far from the first stress adjustment structure 310, and the through-silicon via interconnect structure 520 is coupled to bit line 103.

[0168] In some embodiments, the semiconductor device includes one of phase-change memory, dynamic random access memory, or non-volatile memory.

[0169] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A first semiconductor structure is provided; wherein the first semiconductor structure includes a stress structure extending along a first direction, the first direction being parallel to the plane in which the first semiconductor structure is located; Provide a second semiconductor structure; A first stress-adjusting structure is formed on the second semiconductor structure; wherein the first stress-adjusting structure extends along a second direction, the second direction intersects the first direction and is parallel to the plane in which the first semiconductor structure is located; The first semiconductor structure and the second semiconductor structure including the first stress-adjusting structure are bonded together; wherein the first stress-adjusting structure is used to adjust the warpage of the first semiconductor structure.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The stress structure includes a plurality of stress elements extending along the first direction, and the plurality of stress elements are arranged side by side along the second direction; The formation of the first stress-adjusting structure on the second semiconductor structure includes: A plurality of stress-adjusting units are formed covering the second semiconductor structure; wherein the stress-adjusting units extend along the second direction, the plurality of stress-adjusting units are arranged side by side along the first direction, the size of the stress-adjusting unit along the first direction is substantially equal to the size of the stress unit along the second direction, and the spacing between two adjacent stress-adjusting units is substantially equal to the spacing between two adjacent stress units.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The provision of the first semiconductor structure includes: Provide a base; A transistor array is formed on one side of the substrate; wherein the transistor array includes a plurality of transistors, each transistor including a source, a channel, and a drain arranged in parallel along a third direction, the third direction being perpendicular to the first direction and the second direction; Multiple conductive lines are formed extending along the first direction; wherein the conductive lines are coupled to the channels of multiple transistors arranged in parallel along the first direction; the stress structure includes the multiple conductive lines.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The transistor is a dual-gate transistor, and the conductive line includes a first sub-conductive line and a second sub-conductive line, which are located on opposite sides of the channel of the same transistor; along the first direction, the relatively close ends of adjacent first sub-conductive lines and second sub-conductive lines have a predetermined distance; The formation of the first stress-adjusting structure on the second semiconductor structure includes: A plurality of first sub-stress adjustment units and a plurality of second sub-stress adjustment units are formed covering the second semiconductor structure; wherein, the material of the first sub-stress adjustment unit is the same as that of the second sub-stress adjustment unit, and both the first and second sub-stress adjustment units extend along the second direction, and the plurality of first and second sub-stress adjustment units are arranged alternately side by side along the first direction; the size and spacing of the first and second sub-stress adjustment units along the first direction are substantially equal to the size and spacing of the first and second sub-conductive lines along the second direction; along the second direction, the relatively close ends of adjacent first and second sub-stress adjustment units have the preset distance.

5. The method for fabricating a semiconductor device according to claim 3, characterized in that, The bonding of the first semiconductor structure and the second semiconductor structure including the first stress-adjusting structure includes: Bonding the first stress-adjusting structure and the first semiconductor structure; After bonding the first semiconductor structure and the second semiconductor structure including the first stress-adjusting structure, the fabrication method further includes: A via interconnect structure is formed on the side of the first semiconductor structure that is relatively far from the second semiconductor structure; wherein the via interconnect structure is coupled to the source of the transistor; After forming the via interconnect structure, the second semiconductor structure is removed.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the first stress adjustment structure includes at least one of metal, silicon nitride, or polycrystalline silicon.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The preparation method further includes: Before forming the first stress-adjusting structure, a second stress-adjusting structure is formed on the second semiconductor structure; wherein the second stress-adjusting structure is located between the second semiconductor structure and the first stress-adjusting structure, the orthographic projection of the second stress-adjusting structure onto the plane of the second semiconductor structure covers the second semiconductor structure, and the second stress-adjusting structure is used to reduce the warpage of the first semiconductor structure.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The material of the second stress adjustment structure includes one of metal, silicon nitride, or polycrystalline silicon.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The preparation method further includes: A first bonding layer is formed on the first semiconductor structure; A second bonding layer is formed on the first stress-adjusting structure; wherein the second bonding layer has the same hydrophilicity as the first bonding layer; The bonding of the first semiconductor structure and the second semiconductor structure including the first stress-adjusting structure includes: The second bonding layer and the first bonding layer are bonded together.

10. The method for fabricating a semiconductor device according to claim 1, characterized in that, The preparation method further includes: A third stress-adjusting structure is formed on the first semiconductor structure; wherein the orthographic projection of the third stress-adjusting structure onto the plane of the first semiconductor structure covers the first semiconductor structure, and the third stress-adjusting structure is used to reduce the warpage of the first semiconductor structure. The bonding of the first semiconductor structure and the second semiconductor structure including the first stress-adjusting structure includes: The third stress adjustment structure and the first stress adjustment structure are bonded together.

11. A semiconductor device, characterized in that, include: A first semiconductor structure includes a memory array and / or peripheral circuitry, wherein the memory array and / or peripheral circuitry includes a stress structure that extends along a first direction, the first direction being parallel to the plane in which the first semiconductor structure is located. A first stress-adjusting structure extends along a second direction, which intersects the first direction and is parallel to the plane containing the first semiconductor structure. The first stress adjustment structure is used to adjust the warpage of the first semiconductor structure; A first bonding layer and a second bonding layer are located between the first semiconductor structure and the first stress-adjusting structure, with the first bonding layer located between the first semiconductor structure and the second bonding layer.

12. The semiconductor device according to claim 11, characterized in that, The stress structure includes a plurality of stress elements extending along the first direction, and the plurality of stress elements are arranged side by side along the second direction; The first stress adjustment structure includes a plurality of stress adjustment units extending along the second direction. The plurality of stress adjustment units are arranged side by side along the first direction. The size of the stress adjustment unit along the first direction is substantially equal to the size of the stress unit along the second direction. The spacing between two adjacent stress adjustment units is substantially equal to the spacing between two adjacent stress units.

13. The semiconductor device according to claim 12, characterized in that, The first semiconductor structure includes: A substrate, wherein a transistor array is provided on one side of the substrate, the transistor array including a plurality of transistors, the transistors including a source, a channel and a drain arranged in parallel along a third direction, the third direction being perpendicular to the first direction and the second direction; Multiple conductive lines extend along the first direction and are coupled to the channels of multiple transistors arranged side-by-side along the first direction; the stress structure includes the multiple conductive lines.

14. The semiconductor device according to claim 13, characterized in that, The transistor is a dual-gate transistor, and the conductive line includes a first sub-conductive line and a second sub-conductive line, which are located on opposite sides of the channel of the same transistor; along the first direction, the relatively close ends of adjacent first sub-conductive lines and second sub-conductive lines have a predetermined distance; The first stress adjustment structure includes a plurality of first sub-stress adjustment units and a plurality of second sub-stress adjustment units arranged alternately in parallel along the first direction. The composition material of the first sub-stress adjustment units is the same as that of the second sub-stress adjustment units. Both the first sub-stress adjustment units and the second sub-stress adjustment units extend along the second direction. The size and spacing of the first sub-stress adjustment units and the second sub-stress adjustment units along the first direction are substantially equal to the size and spacing of the first sub-conductive wire and the second sub-conductive wire along the second direction. Along the second direction, the relatively close ends of the first sub-stress adjustment unit and the second sub-stress adjustment unit have the preset distance.

15. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes a via interconnect structure located on the side of the first semiconductor structure relatively far from the first stress adjustment structure, the via interconnect structure being coupled to the source of the transistor.

16. The semiconductor device according to claim 11, characterized in that, The material of the first stress adjustment structure includes at least one of metal, silicon nitride, or polycrystalline silicon.

17. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: a second stress adjustment structure located on the side of the first stress adjustment structure that is relatively far away from the first semiconductor structure, the orthographic projection of the second stress adjustment structure onto the plane where the first semiconductor structure is located covers the first semiconductor structure, and the second stress adjustment structure is used to reduce the warpage of the first semiconductor structure.

18. The semiconductor device according to claim 17, characterized in that, The material of the second stress adjustment structure includes one of metal, silicon nitride, or polycrystalline silicon.

19. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes a third stress adjustment structure located between the first stress adjustment structure and the first semiconductor structure. The orthographic projection of the third stress adjustment structure onto the plane of the first semiconductor structure covers the first semiconductor structure. The third stress adjustment structure is used to reduce the warpage of the first semiconductor structure.

20. The semiconductor device according to claim 11, characterized in that, The first bonding layer and the second bonding layer have the same hydrophilicity.

21. The semiconductor device according to claim 11, characterized in that, The semiconductor device includes one of phase-change memory, dynamic random access memory, or non-volatile memory.

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