Seam filling of metal gates with si-containing layers

Abstract

The present disclosure relates to seam filling of metal gates with Si-containing layers. A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source / drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work function layer over the gate dielectric layer. The work function layer includes a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, excess portions of the work function layer, and excess portions of the gate dielectric layer. Remaining portions of the silicon-containing layer, remaining portions of the work function layer, and remaining portions of the gate dielectric layer form a gate stack.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to seam filling of metal gates using a Si-containing layer. Background Technology

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured using the following process: depositing insulating or dielectric layers, conductive layers, and semiconductor material layers sequentially on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given chip area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] A first aspect of this disclosure relates to a method comprising: forming a dummy gate stack over a semiconductor region; forming an epitaxial source / drain region on the opposite side of the dummy gate stack; removing the dummy gate stack to form a trench; depositing a gate dielectric layer extending into the trench; depositing a work function layer over the gate dielectric layer, wherein the work function layer includes a seam; depositing a silicon-containing layer to fill the seam; and performing a planarization process to remove excess portions of the silicon-containing layer, the work function layer, and the gate dielectric layer, wherein the remaining portions of the silicon-containing layer, the work function layer, and the gate dielectric layer form a gate stack.

[0005] A second aspect of this disclosure relates to an integrated circuit structure comprising: a semiconductor region; a source / drain region on one side of the semiconductor region; and a gate stack over the semiconductor region, the gate stack comprising: a gate dielectric; and a work function layer over the gate dielectric, wherein the work function layer comprises: a bottom portion over the gate dielectric; a first sidewall portion and a second sidewall portion located on and connected to the opposite end of the bottom portion; and a silicon-containing layer comprising: a first sidewall contacting the first sidewall portion; and a second sidewall contacting the second sidewall portion.

[0006] A third aspect of this disclosure relates to an integrated circuit structure comprising: a semiconductor region; a first gate spacer and a second gate spacer over the semiconductor region; and a gate stack over the semiconductor region and between the first gate spacer and the second gate spacer, the gate stack including a silicon-containing layer extending to a midline between the first gate spacer and the second gate spacer, wherein the silicon-containing layer has a peak silicon concentration at the midline, and the silicon concentration in the gate stack gradually decreases in a region away from the midline. Attached Figure Description

[0007] The various aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be arbitrarily enlarged or reduced.

[0008] Figures 1-4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B and Figure 19C Perspective views, cross-sectional views, and top views of intermediate stages in the process of forming a gate all-around (GAA) transistor are shown according to some embodiments.

[0009] Figure 20Some embodiments illustrate the percentage of silicon atoms and the percentage of titanium atoms in the gate stack as a function of the distance from the midpoint of the gate stack.

[0010] Figure 21 A process flow for forming GAA transistors is shown according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as “under,” “below,” “below,” “over,” “above,” etc., may be used herein to describe the relationship of an element or feature to other elements(s) or features(s) shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0013] A method for forming an alternative gate stack for a transistor and a corresponding transistor structure are provided. According to some embodiments, the alternative gate stack includes a work function layer formed by a conformal deposition method. A silicon-containing seam fill layer can be formed, for example, by an immersion process to fill the seams in the work function layer. In the description of this disclosure, the concepts of the disclosure are explained by discussing Gate All-Around (GAA) transistors. Embodiments of this disclosure can also be applied to other types of transistors, such as FinFETs, planar transistors, etc. The embodiments discussed herein are intended to provide examples to enable the manufacture or use of the subject matter of this disclosure, and modifications that can be made while remaining within the contemplated scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figures 1-4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B and Figure 19C Various views of intermediate stages in forming some GAA transistors are shown according to some embodiments of this disclosure. The corresponding processes are also schematically reflected in… Figure 21 The process flow shown is as follows.

[0015] refer to Figure 1 A perspective view of wafer 10 is shown. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, etc., but other substrates and / or structures may also be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, etc. Substrate 20 may be doped to be a p-type semiconductor, but in other embodiments, it may be doped to be an n-type semiconductor.

[0016] According to some embodiments, a multilayer stack 22 is formed through a series of deposition processes for depositing alternating materials. The corresponding processes are described in... Figure 21 The process flow 200 shown is referred to as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0017] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or includes the following: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed to have approximately Peace Treaty The first thickness is within the range between [specific thicknesses]. However, any suitable thickness can be used, as long as it remains within the range of the embodiment.

[0018] Once the first layer 22A is deposited on the substrate 20, a second layer 22B is deposited on top of the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, etc., wherein the second semiconductor material differs from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon-germanium, the second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0019] According to some embodiments, a second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to have a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to have a thickness different from that of the first layer 22A. According to some embodiments, the second layer 22B may be formed to have, for example, a thickness of approximately... Peace Treaty The second thickness within the range between.

[0020] Once the second layer 22B is formed on top of the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the respective first layers 22A have the same or similar thickness, and the respective second layers 22B have the same or similar thickness. The thickness of the first layer 22A may be the same as or different from the thickness of the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to throughout the specification as sacrificial layer 22A. According to an alternative embodiment, the second layer 22B is sacrificial and is removed in a subsequent process.

[0021] According to some embodiments, a plurality of pad oxide layers and a plurality of hard mask layers (not shown) are formed on the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0022] Reference Figure 2 In one or more etching processes, a portion of the multilayer stack 22 and the underlying substrate 20 are patterned to form trenches 23. The corresponding process is... Figure 21 The process flow 200 shown is designated as process 204. Trench 23 extends into substrate 20. The remainder of the multilayer stack is hereinafter referred to as multilayer stack 22'. Below multilayer stack 22', a portion of substrate 20 is retained, hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layers 22A and 22B. Semiconductor layer 22A is hereinafter alternatively referred to as a sacrificial layer, and semiconductor layer 22B is hereinafter alternatively referred to as a nanostructure. These portions of multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0023] In the above embodiments, the GAA transistor structure can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with spacing, for example, smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Using a self-alignment process, spacers are formed next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can subsequently be used to pattern the GAA structure.

[0024] Figure 3 The diagram illustrates the formation of isolation region 26, also referred to throughout this specification as the Shallow Trench Isolation (STI) region. The corresponding process is described in... Figure 21The process flow 200 shown is designated as process 206. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, etc. The STI region 26 may also include a dielectric material on top of the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, may then be performed to flatten the top surface of the dielectric material, and the remaining portion of the dielectric material constitutes the STI region 26.

[0025] The STI region 26 is then recessed such that the top portion of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top portion of the substrate strip 20' and the multilayer stack 22'. The recess of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon gas may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 26 is performed by a wet etching process. For example, the etching chemicals may include HF.

[0026] refer to Figure 4 A dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is as follows: Figure 21 The process flow 200 shown is designated as process 208. A dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on top of the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. The dummy gate electrode 34 may be formed using polycrystalline silicon or amorphous silicon, or other materials such as amorphous carbon. Each dummy gate stack 30 may also include one (or more) hard mask layers 36 on top of the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stack 30 may span one or more protruding fins 28 and an STI region 26 between these protruding fins 28. Furthermore, the length direction of the dummy gate stack 30 is perpendicular to the length direction of the protruding fins 28. The formation of the dummy gate stack 30 includes: forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layer by one or more patterning processes.

[0027] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), or silicon oxycarbonitride (SiOCN), and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include depositing one or more dielectric layers, and then performing one or more anisotropic etching processes on the dielectric layers(one or more). The remaining portion of the dielectric layers(one or more) constitutes the gate spacers 38.

[0028] Figure 5A and Figure 5B It shows Figure 4 The cross-sectional view of the structure shown is shown. Figure 5A It shows Figure 4 Reference section A1-A1 is shown, which passes through the portion of the protruding fin 28 not covered by the gate stack 30 and the gate spacer 38, and is perpendicular to the gate length direction. The fin spacer 38 on the sidewall of the protruding fin 28 is also shown. Figure 5B It shows Figure 4 The reference section BB is parallel to the length direction of the protruding fin 28.

[0029] refer to Figure 6A and Figure 6B The portion of the protruding fin 28 that is not directly below the dummy gate stack 30 and the gate spacer 38 is recessed using an etching process to form a recess 42. The corresponding process is as follows: Figure 21 The process flow 200 shown is designated as process 210. For example, a dry etching process can be performed using mixtures of C2F6, CF4, SO2, HBr, Cl2, and O2, or mixtures of HBr, Cl2, O2, and CH2F2, to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or may be lower than the bottom of the multilayer semiconductor stack 22' (e.g., ...). Figure 6B (As shown). Etching can be anisotropic, such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown. Figure 6B As shown.

[0030] refer to Figure 7A and Figure 7B The sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed relative to the edges of the corresponding overlay and underlay nanostructures 22B. The corresponding process is performed in... Figure 21The process flow 200 shown is designated as process 212. Lateral recesses in the sacrificial semiconductor layer 22A can be achieved using a wet etching process with an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon-germanium (SiGe)) compared to the materials of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon-germanium and the nanostructure 22B is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using immersion processes, spraying processes, etc., and can be performed using any suitable process temperature (e.g., between about 400°C and about 600°C) and a suitable process time (e.g., between about 100 seconds and about 1,000 seconds). According to an alternative embodiment, lateral recesses in the sacrificial semiconductor layer 22A can be achieved using an isotropic dry etching process or a combination of dry and wet etching processes.

[0031] Figure 8A and Figure 8B The formation of the internal spacer 44 is shown. The corresponding process is as follows: Figure 21 The process flow 200 shown is designated as process 214. The forming process includes: depositing a spacer layer extending into the recess 41, and performing an etching process to remove the portion of the inner spacer layer outside the recess 41, thereby leaving an inner spacer 44 in the recess 41. The inner spacer 44 may be formed of or include the following: SiOCN, SiON, SiOC, SiCN, etc. The inner spacers 44 may be porous, such that they have a low k value below, for example, about 3.5. According to some embodiments, the etching of the spacer layer may be performed by a wet etching process, wherein the etching chemicals may include H2SO4, diluted HF, ammonia solution (NH4OH, ammonia in water), etc., or combinations thereof.

[0032] refer to Figure 9A and Figure 9B An epitaxial source / drain region 48 is formed in the recess 42. The corresponding process is as follows: Figure 21The process flow 200 shown is designated as process 216. According to some embodiments, the source / drain region 48 can stress the nanostructure 22B used as the channel for the corresponding GAA transistor, thereby improving performance. P-type or n-type impurities can be doped in situ during epitaxy, depending on whether the resulting transistor is a p-type or n-type transistor. For example, when the resulting transistor is a p-type transistor, silicon-germanium-boron (SiGeB), germanium-boron (GeB), silicon-boron (SiB), etc., can be grown. Conversely, when the resulting transistor is an n-type transistor, silicon-phosphorus (SiP), silicon-carbon-phosphorus (SiCP), etc., can be grown. After filling the recess 42 with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 results in horizontal expansion of the epitaxial region 48 and can form a small facet. Further growth of the epitaxial region 48 can also cause adjacent epitaxial regions 48 to fuse together.

[0033] Following the epitaxial process, the epitaxial region 48 can be further implanted with p-type or n-type impurities to form source and drain regions (which are also indicated by reference numeral 48). According to an alternative embodiment of this disclosure, when the epitaxial region 48 is in-situ doped with p-type or n-type impurities during the epitaxial process, the implantation process is skipped, and the epitaxial region 48 is also the source / drain region.

[0034] Figure 10A , Figure 10B and Figures 10C to 19A , Figure 19B and Figure 19C Subsequent figures in the diagram may be numbered with the letters A, B, or C. The letter A indicates that the corresponding figure shows a reference section and... Figure 4 The reference sections A2-A2 are the same, and the letter B indicates that the corresponding reference section shown in the attached figure is the same. Figure 4 The reference section BB is the same, and the letter C indicates the corresponding figure (except for...). Figure 15C and Figure 17C The reference section shown is... Figure 4 The reference section A1-A1 is the same.

[0035] Figure 10A , Figure 10B and Figure 10C A cross-sectional view of the structure after the formation of the contact etch stop layer (CESL) 50 and the interlayer dielectric (ILD) 52 is shown. The corresponding process is described in... Figure 21The process flow 200 shown is designated as process 218. CESL 50 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 52 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based material formed using the following as precursors: tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0036] Figure 11A and Figures 11B to 17A , Figure 17B , Figure 17C and Figure 17D The process for forming the replacement gate stack is illustrated. Figure 11A and Figure 11B In this process, planarization processes such as CMP or mechanical polishing are performed to flatten the top surface of the ILD 52. The corresponding processes are described in... Figure 21 The process flow 200 shown is illustrated as process 220. According to some embodiments, the planarization process can remove the hard mask 36 to expose the dummy gate electrode 34, such as… Figure 11A As shown. According to an alternative embodiment, the planarization process can expose and stop the hard mask 36. According to some embodiments, after the planarization process, the top surface of the dummy gate electrode 34 (or the top surface of the hard mask 36), the top surface of the gate spacer 38, and the top surface of the ILD 52 are flush with each other within the process variation range.

[0037] Next, the dummy gate electrode 34 (and hard mask 36, if any) is removed in one or more etching processes to form the recess 58, as shown. Figure 12A and Figure 12B As shown. The corresponding process is in Figure 21 The process flow 200 shown is designated as process 222. A portion of the dummy gate dielectric 32 within the recess 58 is also removed. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by a dry etching process. For example, the etching process can be performed using one or more reactive gases that selectively etch the dummy gate electrode 34 at a faster rate (compared to ILD 52). Each recess 58 exposes and / or covers portions of the multilayer stack 22' that include future channel regions in the subsequently completed nanostructured FET. These portions of the multilayer stack 22' are located between adjacent epitaxial source / drain regions 48.

[0038] The sacrificial layer 22A is then removed to extend the recess 58 between the nanostructures 22B, and the resulting structure is shown in Figure 13A and Figure 13B The corresponding process is in... Figure 21 The process flow 200 shown is designated as process 224. The sacrificial layer 22A can be removed by performing an isotropic etching process, such as a wet etching process (which uses an etchant selective for the material of the sacrificial layer 22A). Compared to the sacrificial layer 22A, the nanostructure 22B, the substrate 20, and the STI region 26 remain relatively unetched. Depending on some embodiments where the sacrificial layer 22A comprises, for example, SiGe and the nanostructure 22B comprises, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the sacrificial layer 22A.

[0039] refer to Figure 14A and Figure 14B as well as Figure 14C This forms the gate dielectric 62. The corresponding process is as follows: Figure 21 The process flow 200 shown is designated as process 226. An example of the gate dielectric 62 is shown in... Figure 14C As shown in the figure. According to some embodiments, each gate dielectric 62 includes an interface layer 62A and a high-k dielectric layer 62B on the interface layer 62A. The interface layer 62A may be formed of or contain silicon oxide, and the silicon oxide may be deposited by a conformal deposition process such as ALD or CVD. According to some embodiments, the high-k dielectric layer 62B includes one or more dielectric layers. For example, the high-k dielectric layer 62B may include metal oxides or silicates of the following: hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The high-k dielectric layer 62B may also be formed by a conformal deposition process.

[0040] refer to Figure 15A and Figure 15B This forms a 68-layer function. The corresponding process is... Figure 21 The process flow 200 shown is designated as process 228. In its formation, a conductive layer is first deposited on a high-k dielectric layer 62B, and the recess 58 is filled. The work function layer 68 may comprise a metallic material, such as TiN, TaN, TiAl, TiAlC, combinations thereof, and / or multiple layers thereof. For example, although details of the work function layer 68 are not shown... Figure 16A and Figure 16B As shown, the work function layer 68 may include any number of layers. For example, when the corresponding transistor is a p-type transistor, the work function layer 68 may have a high work function suitable for forming a PMOS device, which may be between about 4.9 eV and about 5.2 eV, and may be close to or equal to a band-edge work function of about 5.2 eV. For example, the work function layer 68 may include a TiN layer.

[0041] When the corresponding transistor is an n-type transistor, the work function layer 68 can have a low work function suitable for forming an NMOS device, which can be between about 4.0 eV and about 4.4 eV, and can be a band-edge work function of about 4.1 eV. For example, the work function layer 68 may include a TiAl layer, a composite layer including a TiN layer and a TiAl layer above the TiN layer, or a composite layer including a TiAl layer and a TiN layer above the TiAl layer. The TiAl layer may include TiAlC, TiAlN, etc. When the work function layer 68 includes multiple layers, the multiple layers can be deposited in situ in the same manufacturing tool without vacuum disruption between these layers. The gate dielectric 62 and the work function layer 68 also fill the space between adjacent nanostructures 22B, and fill the space between the bottom nanostructure 22B and the underlying substrate strip 20'.

[0042] According to some embodiments, the deposition of the work function layer 68 is performed using an ALD or CVD process. When depositing TiN in the work function layer 68, a Ti-containing precursor and a nitrogen-containing precursor are used to perform the deposition. The Ti-containing precursor may include TiCl4, TiCl5, or combinations thereof. The nitrogen-containing precursor may include NH3.

[0043] When depositing the TiAl-containing layer in the work function layer 68, the precursor may include a titanium-containing precursor and an aluminum-containing precursor. The titanium-containing precursor may include TiCl4, TaCl5, etc. The aluminum-containing precursor may include triethylaluminum (TEA), tri-tert-butylaluminum (TTBA), trimethylaluminum (TMA), etc., or combinations thereof. When using ALD, the ALD cycle may include a series of processes, including: pulsed and purged titanium-containing precursors, pulsed and purged nitrogen-containing precursors, pulsed and purged aluminum-containing precursors, and pulsed and purged nitrogen-containing precursors.

[0044] In the formation of the work function layer 68, opposing portions of the work function layer 68 (these opposing portions are deposited on opposing gate spacers 38—with gate dielectric 62 in between) grow toward each other until some of the opposing portions are interconnected. When the deposition of the work function layer 68 stops, a seam 64 is formed in the work function layer 68. It should be understood that... Figure 15A , Figure 15B and Figure 15C The seam 64 shown is schematic, and the actual shape, location, and relative dimensions of the seam 64 may differ from those shown. The seam 64 is centrally formed between opposite portions of the work function layer 68.

[0045] According to some embodiments, the deposition of the work function layer 68 can be stopped when at least some portions of the work function layer 68 deposited on opposing portions of the opposing gate spacer 38 fuse with each other. According to these embodiments, a silicon immersion process is performed to fill the seam 64, as will be discussed in subsequent paragraphs. Figure 15C A top view of the work function layer 68 is shown, in which the seam 64, visible from the top, is shown using solid lines. Dashed lines indicate portions where no seam is formed and portions where the seam 64 is formed but sealed by the work function layer 68. Therefore, these portions of the seam 64 are covered by the work function layer 68 and are not visible from the top. The portions of the seam 64 indicated by dashed lines may or may not interconnect with the portions of the seam 64 indicated by solid lines. According to some embodiments, the width W1 of the seam 64 may be less than approximately or less than approximately

[0046] According to an alternative embodiment, the deposition of the work function layer 68 can be stopped before the opposing portions of the work function layer 68 merge with each other. For example, as... Figure 15D As shown, the resulting seam 64 can be relatively wide and is elongated and continuous when viewed from the top. According to these embodiments, the seam 64 can be filled with silicon by silicon impregnation, or it can be filled with TiSiN, TaSiN, TiAlSi, WSiCN, or combinations thereof, as discussed in subsequent paragraphs.

[0047] Reference Figure 16A and Figure 16B The seam 64 is filled with a seam filler layer 66, which, according to some embodiments, is a silicon-containing layer. The corresponding process is as follows: Figure 21 In the process flow 200 shown, it is indicated as process 230. In, as... Figure 16B In the cross-sectional view shown, the seam filler layer 66 extends between opposite portions of the work function layer 68. According to some embodiments, the seam filler layer 66 is a silicon layer comprising elemental silicon (in a non-compound form). A silicon-containing precursor can be used to perform impregnation to form the silicon layer 66. The silicon-containing precursor may include silane (SiH4), disilane (Si2H6), propane (Si3H8), dichlorosilane (DCS), etc., or combinations thereof. According to some embodiments, the wafer impregnation temperature can be in the range of about 250°C to about 600°C. Other carrier gases may be used, such as argon. The impregnation gas may not contain compound gases including Ti, N, Al, etc. The chamber pressure can be in the range of about 0.5 Torr to about 50 Torr. The impregnation time can be in the range of about 2 seconds to about 30 minutes.

[0048] According to some embodiments, when the seam 64 is very narrow, small molecules such as silanes are needed to form the seam filling layer 66. Since the molecular size of silanes is approximately... Smaller than the molecular size of TiCl4 Therefore, this seam filling process may be more efficient than seam filling using TiCl4. When the seam 64 is relatively wide, macromolecules are also efficient in seam filling.

[0049] The immersion time can be long enough that no more seam filler layer 66 can be filled into the seam 64. Alternatively, immersion can be performed indefinitely, even beyond the immersion time, with additional silicon deposited in the region above the top surface of ILD 52, so that on the outside and above the trench 58 ( Figure 14A and Figure 14B Silicon is present. After the impregnation process, virtually all (e.g., more than 90% by volume) of the seams 64 can be filled with silicon. A small portion of the seams 64 may or may not remain unfilled.

[0050] According to alternative embodiments, the seam filler layer 66 comprises a silicon-containing compound, which may include TiSiN, TaSiN, TiAlSi, WSiCN, etc., or combinations thereof. According to some embodiments, the seam filler layer 66 comprises TiSiN that can be formed by an ALD process. The ALD process can be performed using precursors including TiCl4, NH3, and SiH4, which can be sequentially pulsed into and purged out of the respective chambers where wafer 10 is located. According to alternative embodiments using TaSiN, precursors including pentapentanyl(dimethylamide)tantalum (PDMAT), NH3, and SiH4 can be used. According to further alternative embodiments using TiAlSi, ALD precursors TiCl4, TEA, and SiH4 can be used. According to further alternative embodiments using WSiCN, ALD precursor C can be used. 12 H 30 N4W, TEA, and SiH4.

[0051] Since silicon-containing compounds such as TiSiN, TaSiN, TiAlSi, and WSiCN are amorphous, they can form in small seams that TiN cannot fill. This is because TiN may contain grains, thus restricting its placement. To ensure the formation of amorphous structures, the wafer temperature in ALD or CVD processes can be relatively low, for example, below approximately 200°C. Therefore, for amorphous structures, silicon-containing compounds can fill seams left by TiN that cannot be filled by TiN. This, combined with small-sized silane molecules, makes the filling of small seams 64 more efficient.

[0052] After filling the recess 58, a planarization process, such as CMP or mechanical polishing, is performed to remove excess portions of the gate dielectric 62, the work function layer 68, and the seam fill layer 66, which lie on the top surface of the ILD 52. The corresponding processes are as follows: Figure 21The process flow 200 shown is designated as process 232. The remaining seam fill layer 66 and work function layer 68 are collectively referred to as gate electrode 69. The remaining seam fill layer 66, work function layer 68, and gate dielectric 62 are collectively referred to as gate stack 70 of the resulting nanostructured FET. The resulting structure is as follows: Figure 17A and Figure 17B As shown. Since some portions of joint 64 can be sealed by the overlying portion of work function layer 68, the top surface of the corresponding portion of joint filling layer 66 can be below and spaced apart from the top surface of work function layer 68, as shown in Figure 17B As schematically shown, the top surface of other portions of the joint filler layer 66 can be exposed.

[0053] For a portion of the gate electrode to function as a work function layer, this portion needs to be within a certain distance from the transistor channel (e.g., within a range of approximately 3 nm). Gate electrode portions too far from the channel have too little impact on the work function and are therefore not part of the transistor's work function layer. According to some embodiments, the top of the work function layer 68 is larger than the required distance, so the seam filler layer 66 does not affect the work function and is not part of the transistor's work function layer. According to an alternative embodiment, the work function layer 68 is very thin, so the bottom portion of the seam filler layer 66 is also part of the work function layer. (Dashed line 71) Figure 17B The diagram is schematically shown to indicate the possible location of the top of the effective work function layer of the transistor.

[0054] Figure 17C A top view of the gate stack 70 is shown according to some embodiments. Due to the seam 64 ( Figure 15A and Figure 15B The formation of the joint filler layer 66 is random, therefore the shape, position, and size of the resulting joint filler layer 66 are random. According to some embodiments, such as... Figure 17C As shown, some portions of the seam fill layer 66 in the first gate stack are embedded in and covered by the work function layer 68. Therefore, these portions of the seam fill layer 66 are indicated by dashed lines because they are not visible. In the second gate stack within the same device die, the seam fill layer 66 does not extend into the area marked with dashed lines. Therefore, in the second gate stack, the seam fill layer 66 includes discrete portions separated by the work function layer 68.

[0055] Figure 17D A top view of a gate stack 70 according to an alternative embodiment is shown. In this top view, a seam-filling layer 66, which may include silicon, TiSiN, TaSiN, TiAlSi, WSiCN, etc., is a continuous elongated strip surrounded by a work function layer 68. Figure 17DThe embodiments described above may also appear in a third gate stack, which is located in the same device die as the first and second gate stacks discussed in the preceding paragraphs.

[0056] exist Figure 18A , Figure 18B and Figure 18C In the illustrated process, the gate stack 70 is recessed, thereby forming a recess directly on the gate stack 70 and between the opposing portions of the gate spacer 38. The gate mask 74 includes one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., which are filled in each recess, followed by a planarization process to remove excess dielectric material extending onto the ILD 52. The corresponding process is described in... Figure 21 The process flow 200 shown is referred to as process 234. Figure 18A and Figure 18B A top view of the gate stack 70 shown is not shown, but it can be compared with... Figure 17C or Figure 17D The basic structure is the same as shown. For example, the top of some portions of the seam filler layer 66 may extend to the gate mask 74, while the top of some other portions of the seam filler layer 66 may be below the gate mask 74 and separated from the overlying gate mask 74 by some portions of the work function layer 68.

[0057] like Figure 18A , Figure 18B and Figure 18C As further shown, ILD 76 is deposited on top of ILD 52 and gate mask 74. The corresponding process is as follows: Figure 21 The process flow 200 shown is designated as process 236. An etch stop layer (not shown) may or may not be deposited prior to the formation of the ILD 76. According to some embodiments, the ILD 76 is formed by FCVD, CVD, PECVD, etc. The ILD 76 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0058] exist Figure 19A , Figure 19B and Figure 19C In this process, ILD 76, ILD 52, CESL 50, and gate mask 74 are etched to form recesses (occupied by contact plugs 80A and 80B) that expose the surfaces of the epitaxial source / drain regions 48 and / or the gate stack 70. These recesses can be formed by etching using anisotropic etching processes such as RIE or NBE. According to some embodiments, the recesses can be formed by etching through ILD 76 and ILD 52 using a first etching process, etching through the gate mask 74 using a second etching process, and possibly etching through CESL 50 using a third etching process. Although... Figure 19BThe diagram shows that contact plugs 80A and 80B are in the same cross section, but in various embodiments, contact plugs 80A and 80B may be formed in different cross sections, thereby reducing the risk of short circuits between them.

[0059] After the recess is formed, a silicide region 78 is formed above the epitaxial source / drain region 48. Figure 19B and Figure 19C The corresponding processes are in Figure 21 The process flow 200 shown is designated as process 238. In some embodiments, the silicide region 78 is formed by first depositing a metal layer (not shown) capable of reacting with the underlying epitaxial source / drain region 48 semiconductor material (e.g., silicon, silicon-germanium, germanium) to form a silicide and / or germanide region, followed by a thermal annealing process to form the silicide region 78. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, etc. Unreacted portions of the deposited metal are then removed, for example, by an etching process.

[0060] Then, a contact plug 80B is formed over the silicide region 78. Furthermore, a contact 80A (also referred to as a gate contact plug) is formed in the recess and contacts the work function layer 68 and the seam fill layer 66. The corresponding process is described in... Figure 21 The process flow 200 shown is designated as process 240. Certain portions of the seam filler layer 66 may or may not be present, their top surfaces being spaced apart from the contact 80A by portions of the work function layer 68. Contact plugs 80A and 80B may each comprise one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, according to some embodiments, contact plugs 80A and 80B each comprise a barrier layer and a conductive material, and are electrically coupled to an underlying conductive feature (e.g., the gate stack 70 or silicide region 78 in the illustrated embodiment). The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the ILD 76. This forms a nanostructured FET 82.

[0061] It should be understood that the gate contact plug 80A can contact a portion, but not all, of the corresponding gate stack 70. Therefore, Figure 19B The cross-sectional view shown illustrates a first portion of the gate stack 70. On the other hand, a second portion of the same gate stack 70 may have the same... Figure 18B The same cross-sectional view is shown, in which the gate mask 74 is still retained.

[0062] Figure 20 Gate stack 70 is shown Figure 19BThe percentage of silicon atoms and titanium atoms in the array is a function of distance from the center line of the gate stack. The X-axis represents the distance from the center line of the gate stack at 70° to 84°. Figure 19B The distance is 0. An X-axis value of 0 indicates the position of the centerline at 84. Figure 19B As shown. Along Figure 19B Arrow 86 measures the percentage of silicon atoms and the percentage of titanium atoms. According to some embodiments, the percentage of silicon atoms has a peak at the center line 84, and decreases gradually and continuously with increasing distance. According to some embodiments, the silicon in the gate stack 70 is uncompounded (does not form compounds with other elements in the gate stack 70). According to alternative embodiments, the silicon in the gate stack 70 is part of a compound, for example, as part of TiAlSi, TiSiN, TaSiN, etc.

[0063] Similarly, Figure 20 As shown, the percentage of titanium atoms has a peak in the work function layer 68, and decreases in the seam fill layer 66 and the high-k dielectric layer 62.

[0064] The embodiments of this disclosure have several advantageous features. By forming a seam-filling layer to fill the seams in the work function layer, the seams in the resulting gate electrode are filled, and problems caused by the seams are avoided. The seam-filling layer employs a silicon-impregnated or amorphous structure, and this filling layer is capable of filling fine seams.

[0065] According to some embodiments of this disclosure, a method includes: forming a dummy gate stack over a semiconductor region; forming an epitaxial source / drain region on the opposite side of the dummy gate stack; removing the dummy gate stack to form a trench; depositing a gate dielectric layer such that the gate dielectric layer extends into the trench; depositing a work function layer over the gate dielectric layer, wherein the work function layer includes a seam; depositing a silicon-containing layer to fill the seam; performing a planarization process to remove excess portions of the silicon-containing layer, excess portions of the work function layer, and excess portions of the gate dielectric layer, wherein the remaining portions of the silicon-containing layer, the remaining portions of the work function layer, and the remaining portions of the gate dielectric layer form a gate stack. In one embodiment, depositing the silicon-containing layer includes: immersing a corresponding wafer containing the work function layer in a silicon-containing process gas. In one embodiment, the silicon-containing layer includes a silicon layer. In one embodiment, depositing the silicon-containing layer includes: depositing a compound layer comprising silicon and a metal. In one embodiment, the metal is selected from titanium, tantalum, and aluminum. In one embodiment, no additional conductive layer is deposited over the silicon-containing layer between the deposition of the silicon-containing layer and the planarization process. In one embodiment, depositing a work function layer includes depositing layers containing titanium and silicon. In one embodiment, the deposition of the work function layer is performed by atomic layer deposition, wherein opposing portions of the work function layers grow toward each other during the deposition process. In one embodiment, at the start of silicon-containing layer deposition, some portions of the seam are sealed by the work function layer, and in a top view of the work function layer, the seam is divided into a plurality of discrete portions. In one embodiment, in a top view of the work function layer, at least a portion of the seam covered by the work function layer interconnects two discrete and visible portions of the seam.

[0066] According to some embodiments of this disclosure, an integrated circuit structure includes: a semiconductor region; a source / drain region located on one side of the semiconductor region; and a gate stack above the semiconductor region, the gate stack including: a gate dielectric; and a work function layer above the gate dielectric, wherein the work function layer includes: a bottom portion above the gate dielectric; a first sidewall portion and a second sidewall portion located above and connected to the opposite end of the bottom portion; and a silicon-containing layer including a first sidewall contacting the first sidewall portion; and a second sidewall contacting the second sidewall portion. In one embodiment, the work function layer includes a top surface, and the silicon-containing layer includes a first portion extending to the height of the top surface and a second portion fully embedded in the work function layer. In one embodiment, the silicon-containing layer includes elemental silicon. In one embodiment, the silicon-containing layer includes silicon as a compound portion. In one embodiment, the silicon in the gate stack has a peak atomic percentage at the middle of the gate stack. In one embodiment, the silicon-containing layer includes TiSiN.

[0067] According to some embodiments of this disclosure, an integrated circuit structure includes: a semiconductor region; a first gate spacer and a second gate spacer over the semiconductor region; and a gate stack over the semiconductor region and between the first gate spacer and the second gate spacer, the gate stack including a silicon-containing layer extending to a centerline between the first gate spacer and the second gate spacer, wherein the silicon-containing layer has a peak silicon concentration at the centerline, and the silicon concentration in the gate stack gradually decreases in a region away from the centerline. In one embodiment, the gate stack further includes a work function layer, wherein opposite sidewalls of the silicon-containing layer contact additional sidewalls of the work function layer. In one embodiment, the integrated circuit structure further includes a dielectric gate mask over and in contact with the gate stack, wherein the silicon-containing layer includes: a first portion having a first top surface in contact with the dielectric gate mask body; and a second portion having a second top surface spaced apart from the dielectric gate mask by a portion of the work function layer. In one embodiment, the silicon-containing layer includes elemental silicon.

[0068] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to this document without departing from the spirit and scope of this disclosure.

[0069] Example 1. A method comprising:

[0070] A dummy gate stack is formed on top of the semiconductor region;

[0071] An epitaxial source / drain region is formed on the opposite side of the dummy gate stack;

[0072] Remove the dummy gate stack to form a trench;

[0073] A gate dielectric layer is deposited, the gate dielectric layer extending into the trench;

[0074] A work function layer is deposited on the gate dielectric layer, wherein the work function layer includes a seam;

[0075] A silicon-containing layer is deposited to fill the seam; and

[0076] A planarization process is performed to remove excess portions of the silicon-containing layer, the work function layer, and the gate dielectric layer, wherein the remaining portions of the silicon-containing layer, the work function layer, and the gate dielectric layer form a gate stack.

[0077] Example 2. According to the method of Example 1, wherein depositing the silicon-containing layer comprises: immersing the corresponding wafer containing the work function layer in a silicon-containing process gas.

[0078] Example 3. The method according to Example 1, wherein the silicon-containing layer comprises a silicon layer.

[0079] Example 4. The method according to Example 1, wherein depositing the silicon-containing layer comprises: depositing a compound layer comprising silicon and metal.

[0080] Example 5. The method according to Example 4, wherein the metal is selected from titanium, tantalum and aluminum.

[0081] Example 6. The method according to Example 1, wherein no additional conductive layer is deposited on the silicon-containing layer between the deposition of the silicon-containing layer and the planarization process.

[0082] Example 7. The method according to Example 1, wherein depositing the work function layer includes depositing a titanium-containing layer.

[0083] Example 8. The method according to Example 1, wherein the deposition of the work function layer is performed by atomic layer deposition, wherein opposite portions of the work function layer grow toward each other in the deposition.

[0084] Example 9. The method according to Example 1, wherein, when the deposition of the silicon-containing layer begins, some portions of the seam are sealed by the work function layer, and in a top view of the work function layer, the seam is divided into a plurality of discrete portions.

[0085] Example 10. The method according to Example 1, wherein, in a top view of the work function layer, at least a portion of the seam covered by the work function layer interconnects two separate and visible portions of the seam.

[0086] Example 11. An integrated circuit structure, comprising:

[0087] Semiconductor region;

[0088] The source / drain region on one side of the semiconductor region; and

[0089] A gate stack above the semiconductor region, the gate stack comprising:

[0090] Gate dielectric;

[0091] A work function layer above the gate dielectric, wherein the work function layer comprises:

[0092] The bottom portion above the gate dielectric;

[0093] The first sidewall portion and the second sidewall portion are located above and connected to the opposite end of the bottom portion; and

[0094] Silicon-containing layer, including:

[0095] The first sidewall that contacts the first sidewall portion; and

[0096] The second sidewall of the second sidewall portion contacts the second sidewall portion.

[0097] Example 12. The integrated circuit structure according to Example 11, wherein the work function layer includes a top surface, and the silicon-containing layer includes:

[0098] A first portion, the first portion extending to the height of the top surface; and

[0099] The second part is completely embedded in the work function layer.

[0100] Example 13. The integrated circuit structure according to Example 11, wherein the silicon-containing layer comprises elemental silicon.

[0101] Example 14. An integrated circuit structure according to Example 11, wherein the silicon-containing layer comprises silicon as part of a compound.

[0102] Example 15. An integrated circuit structure according to Example 11, wherein the silicon in the gate stack has a peak atomic percentage at the middle of the gate stack.

[0103] Example 16. The integrated circuit structure according to Example 11, wherein the silicon-containing layer comprises TiSiN.

[0104] Example 17. An integrated circuit structure, comprising:

[0105] Semiconductor region;

[0106] The first gate spacer and the second gate spacer are located above the semiconductor region; and

[0107] A gate stack above the semiconductor region and between the first gate spacer and the second gate spacer, the gate stack including a silicon-containing layer extending to a midline between the first gate spacer and the second gate spacer, wherein the silicon-containing layer has a peak silicon concentration at the midline, and the silicon concentration in the gate stack gradually decreases in the region away from the midline.

[0108] Example 18. The integrated circuit structure according to Example 17, wherein the gate stack further includes:

[0109] A work function layer, wherein the opposite sidewall of the silicon-containing layer is in contact with an additional sidewall of the work function layer.

[0110] Example 19. The integrated circuit structure according to Example 18 further includes a dielectric gate mask on and in contact with the gate stack, wherein the silicon-containing layer comprises:

[0111] The first portion has a first top surface that contacts the dielectric gate mask entity; and

[0112] The second part has a second top surface, which is spaced apart from the dielectric gate mask by a portion of the work function layer.

[0113] Example 20. An integrated circuit structure according to Example 17, wherein the silicon-containing layer comprises elemental silicon.

Claims

1. A method for forming an integrated circuit structure, comprising: A dummy gate stack is formed on top of the semiconductor region; An epitaxial source / drain region is formed on the opposite side of the dummy gate stack; Remove the dummy gate stack to form a trench; A gate dielectric layer is deposited, the gate dielectric layer extending into the trench; A work function layer is deposited on the gate dielectric layer, wherein the work function layer includes a seam; A silicon-containing layer is deposited to fill the seam, wherein, at the start of the deposition of the silicon-containing layer, some portions of the seam are sealed by the work function layer, and, in a top view of the work function layer, the seam is divided into a plurality of discrete portions; and A planarization process is performed to remove excess portions of the silicon-containing layer, the work function layer, and the gate dielectric layer, wherein the remaining portions of the silicon-containing layer, the work function layer, and the gate dielectric layer form a gate stack.

2. The method according to claim 1, wherein, Depositing the silicon-containing layer includes immersing the corresponding wafer containing the work function layer in a silicon-containing process gas.

3. The method according to claim 1, wherein, The silicon-containing layer includes a silicon layer.

4. The method according to claim 1, wherein, Depositing the silicon-containing layer includes depositing a compound layer comprising silicon and metal.

5. The method according to claim 4, wherein, The metal is selected from titanium, tantalum and aluminum.

6. The method according to claim 1, wherein, No additional conductive layer is deposited on the silicon-containing layer between the deposition of the silicon-containing layer and the planarization process.

7. The method according to claim 1, wherein, Depositing the work function layer includes depositing a titanium-containing layer.

8. The method according to claim 1, wherein, The deposition of the work function layer is performed by atomic layer deposition, in which opposite portions of the work function layer grow toward each other.

9. The method according to claim 1, wherein, In the top view of the work function layer, at least a portion of the seam is located directly below a portion of the work function layer.

10. An integrated circuit structure, comprising: Semiconductor region; The source / drain region on one side of the semiconductor region; as well as A gate stack above the semiconductor region, the gate stack comprising: Gate dielectric; A work function layer above the gate dielectric, wherein the work function layer comprises: The bottom portion above the gate dielectric; A first sidewall portion and a second sidewall portion are located above and connected to the opposite end of the bottom portion, wherein the first sidewall portion and the second sidewall portion grow toward each other and merge at a point; and Silicon-containing layer, including: The first sidewall that contacts the first sidewall portion; and The second sidewall of the second sidewall portion contacts the second sidewall portion.

11. The integrated circuit structure according to claim 10, wherein, The work function layer includes a top surface, and the silicon-containing layer includes: A first portion, the first portion extending to the height of the top surface; and The second part is completely embedded in the work function layer.

12. The integrated circuit structure according to claim 10, wherein, The silicon-containing layer includes elemental silicon.

13. The integrated circuit structure according to claim 10, wherein, The silicon-containing layer includes silicon as part of a compound.

14. The integrated circuit structure according to claim 10, wherein, The silicon in the gate stack has a peak atomic percentage at the middle of the gate stack.

15. The integrated circuit structure according to claim 10, wherein, The silicon-containing layer comprises TiSiN.

16. An integrated circuit structure, comprising: Semiconductor region; A first gate spacer and a second gate spacer above the semiconductor region; as well as A gate stack above the semiconductor region and between the first gate spacer and the second gate spacer, the gate stack including a conductive layer and a silicon-containing layer located within the conductive layer, the silicon-containing layer extending to a centerline between the first gate spacer and the second gate spacer, wherein the silicon-containing layer has a peak silicon concentration at the centerline, and the silicon concentration in the gate stack gradually decreases in a region away from the centerline, wherein, in a top view of the conductive layer, the silicon-containing layer is divided into a first portion and a second portion by the conductive layer.

17. The integrated circuit structure according to claim 16, wherein, The conductive layer includes: A work function layer, wherein the opposite sidewall of the silicon-containing layer is in contact with the sidewall of the work function layer.

18. The integrated circuit structure of claim 17, further comprising a dielectric gate mask on and in contact with the gate stack, wherein, The silicon-containing layer includes: The first portion has a first top surface that contacts the dielectric gate mask entity; and The second part has a second top surface, which is spaced apart from the dielectric gate mask by a portion of the work function layer.

19. The integrated circuit structure according to claim 16, wherein, The silicon-containing layer includes elemental silicon.

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