METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

Abstract

A method for manufacturing a semiconductor device, comprising: forming an interface layer (81) over a channel region, forming a gate dielectric layer (82) over the interface layer (81), forming a first conductive layer (83) over the gate dielectric layer (82), forming a shielding layer (84) over the first conductive layer (83), forming a cover layer (85) over the shielding layer (84), performing a first curing operation after the cover layer (85) has been formed, removing the cover layer (85) after the first curing operation, and forming a gate electrode layer (88) over the gate dielectric layer (82) after the cover layer (85) has been removed, the method further comprising performing a second curing operation before the cover layer (85) is formed and after the shielding layer (84) has been formed, and furthermore, after the cover layer (85) was removed,includes removing the shielding layer (84).

Description

RELATED REGISTRATION

[0001] This application claims priority over preliminary US patent application No. 62 / 753,033, which was filed on October 30, 2018, the entire disclosure of which is incorporated herein by reference. STATE OF THE ART

[0002] With the increasing miniaturization of integrated circuits and ever more demanding requirements regarding their speed, transistors must deliver higher drive currents in increasingly smaller dimensions. Fin field-effect transistors (FinFETs) were therefore developed. FinFETs feature vertical semiconductor fins over a substrate. These fins form source and drain regions, as well as channel regions between them. Shallow trench insulation (STI) regions are used to define the semiconductor fins. FinFETs also feature gate stacks formed on the sidewalls and top surfaces of the semiconductor fins. Because FinFETs have a three-dimensional channel structure, ion implantation processes on the channel require special care to minimize any geometric effects. List of characters

[0003] The present disclosure is best understood from the detailed description below, when read together with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are used for illustrative purposes only. Rather, the dimensions of the various features may be enlarged or reduced as desired for clarity of discussion. Fig. Figure 1A shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 1B shows a general process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D shows cross-sectional views of different stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E and Fig. Figure 3F shows cross-sectional views of different stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 3G shows a process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, Fig. 4E, Fig. 4F, Fig. 4G and Fig. Figure 4H shows different gas supply times for ALD processes. Fig. Figure 5 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6E and Fig. Figure 6F shows cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 6G shows a process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 7 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 8A, Fig. 8B, Fig. 8C, Fig. 8D, Fig. 8E and Fig. Figure 8F shows cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 8G shows a process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 9 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 10E and Fig. Figure 10F shows cross-sectional views of various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 10G shows a process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 11A, Fig. 11B, Fig. 11C and Fig. Figure 11D shows elemental analysis results along a depth direction of gate structures. Fig. 11E shows XPS spectra (X-ray photoelectron spectroscopy) of peaks of a 2p 3 / 2 -Titan orbitals (Ti2p 3 / 2) of a first conductive layer for the structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0004] It is understood that the following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values ​​but may depend on process conditions and / or desired properties of the device.Furthermore, the formation of a first feature over or on top of a second feature, as described below, may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. For the sake of simplicity and clarity, various features may be drawn at different scales. Some layers / features may be omitted from the accompanying drawings for simplification.

[0005] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise oriented), and the terms used herein relating to spatial relativity may likewise be interpreted accordingly. Additionally, the term "made of" may mean either "comprising" or "consisting of."Furthermore, in the subsequent manufacturing process, one of several additional operations may be present in or between the described operations, and the sequence of operations may be changed. In this disclosure, the expression "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C) and does not mean one element of A, one element of B, and one element of C, unless otherwise specified. Throughout this disclosure, a source and a drain are used interchangeably, and a source / drain refers to one or both of the source and the drain.

[0006] The disclosed embodiments relate to a semiconductor device, in particular a fin field-effect transistor (FinFET), and its manufacturing process. The embodiments, such as those disclosed herein, can generally be applied not only to FinFETs, but also to double-gate, surround-gate, omega-gate, or gate-all-around (GAA) transistors and / or nanowire transistors, or any suitable device having a three-dimensional channel structure.

[0007] In FinFET structures, building multiple Vt devices with a low Vt is crucial for low power consumption and increased device performance. The composition and thickness of metal gate films play a critical role in defining the device work function, Vt. Incorporating fluorine (F) into a silicon cover (a fluorinated silicon cover (FSI)) promotes PMOS improvement and increased device reliability. However, forming an FSI is incompatible with a TiN film due to etching and TiN loss caused by fluorine. A semiconductor device has a source and a drain with a gate stack in between. The gate stack has a gate dielectric layer over a substrate, a dielectric cover layer (e.g., a titanium nitride (TiN)) over the gate dielectric layer, and a barrier layer (e.g., a titanium dioxide (TiN)).The dielectric layer consists of a TaN or similar metal nitride over the dielectric cover layer and a gate electrode layer over the barrier layer. The gate dielectric layer comprises an interface layer (IL) and a high-k dielectric layer (HK). The gate electrode comprises a metal gate exit layer and a body metal layer.

[0008] In the fabrication of the semiconductor device, a high-k cover film, i.e., a simple layer of a metal nitride film, e.g., TiN or TSN (TiSiN), is deposited onto a high-k film. A silicon cover layer is then deposited on top of the high-k cover film, followed by curing, removal of the silicon cover, and deposition of the barrier layer (e.g., TaN) and the gate electrode over the high-k cover film. The silicon deposition process could involve the deposition of amorphous silicon or the deposition of fluorinated silicon (FSI), i.e., fluorine-based silicon, which includes impregnation in a fluorine-based gas (e.g., F₂, CF₄, etc.) followed by silicon deposition.

[0009] Metal nitride cover films, such as TiN, are preferred over TiSiN (TSN) films because TiSiN exhibits a Vt (voltage-to-temperature) interference problem compared to other metal nitride films, such as commonly used TiN cover films. When using a fluorinated silicon (F) cover film, fluorine diffuses into the cover film and the gate dielectric during curing, which helps to enhance the PMOS Vt and balances the NMOS and PMOS. Using silicon with incorporated fluorine (FSI) can help improve the PMOS Vt, but it is incompatible with a TiN high-k cover film because fluorine-rich gases damage the cover films. Therefore, a scheme with a more robust cover film is needed to protect / shield the TiN film from fluorine damage and oxidation damage, and to improve the PMOS Vt and device performance.

[0010] The present disclosure relates to the use of a thin protective shielding layer to form a two-layer covering scheme for TiN to enable a fluorinated silicon cover to improve PMOS voltage, device reliability and device performance.As will be discussed below, the present disclosure provides devices and methods that can protect the dielectric cover film and a gate dielectric from damage caused by F2 impregnation processes for forming fluorinated silicon cover films, protect the dielectric cover film from natural oxidation, prevent diffusion of a metal from the gate electrode into the gate dielectric, improve device performance and speed, reduce leakage current, act as an oxygen scavenger to reduce interfacial growth regeneration (ILRG) on the gate dielectric layer, and reduce the thickness of a gate stack.

[0011] Fig. Figure 1A shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0012] In some embodiments, a semiconductor device has a gate stack.80 on, which is above a canal area of ​​a fin structure 20 is arranged. The gate stack 80 exhibits a boundary layer 81 , a gate dielectric layer 82 , a first conductive layer 83 , a shielding layer 84 , a second conductive layer 86 as a barrier layer, an exit work / hiring layer 87 and a gate electrode layer 88 up, as in Fig. Figure 1A is shown. In some embodiments, the fin structure 20 over a substrate 10 provided and is surrounded by an insulating insulating layer 30 stand out. Gate sidewall spacers are also used. 46 on opposite sides of the gate stack 80 arranged and one or more dielectric layers 50 are trained to install the gate sidewall spacers 46to cover. In some embodiments, a piece of insulating material is used. 42 between the gate side wall spacer 46 and the insulating insulating layer 30 arranged. In some embodiments, the first conductive layer has 83 a metal nitride, such as WN, TaN, and TiN. In some embodiments, TiN is used. The thickness of the first conductive layer 83 In some embodiments, the thickness lies in a range of approximately 0.3 nm to approximately 30 nm, and in other embodiments, it lies in a range of approximately 0.5 nm to approximately 25 nm. In some embodiments, the first conductive layer 83 crystalline, exhibiting, for example, columnar crystal grains.

[0013] In some embodiments, the shielding layer 84 one of silicon nitride Si x N y (where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1), Ti, Tix C y , Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide (e.g. TiSi, TiSi2, Ti3Si, Ti5Si3, Ti5Si4 etc.), Ti x Si y (where 0.25≤5 x < 0.99, 0.01 ≤ y ≤ 0.75 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Si x Ti y N z (where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1). In some embodiments, the shielding layer 84 one of Si, Si x C y , Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y , Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide (e.g. TiSi, TiSi2, Ti3Si, Ti5Si3, Ti5Si4 etc.), Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x Ny (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Si x Ti y N z (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1).

[0014] In some embodiments, the shielding layer 84 Titanium silicide (e.g. TiSi, TiSi2, Ti3Si, Ti5Si3, Ti5Si4 etc.), i.e. Ti x Si y , where 0.25 ≤ 5, x < 0.99, 0.01 ≤ y ≤ 0.75, and x + y = 1. In some embodiments, where the shielding layer 84 In a final structure, y is not more than 0.75 and x is not less than 0.25, since such a high silicon content remaining in the finished device can degrade the work function, the threshold voltage Vt of the device, and / or the gate resistance. In some embodiments, the shielding layer 84 Titanium silicide (e.g. TiSi, TiSi2, Ti3Si, Ti5Si3, Ti5Si4 etc.), i.e. Ti x Si y, where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1. In some embodiments, where the shielding layer 84 If the shielding layer is removed and not retained in a finished structure, y can be greater than 0.75 and as high as 0.99, in which case the shielding layer is a Si-enriched titanium silicide or pure Si film with a small amount of titanium.

[0015] In some embodiments, where the shielding layer 84 Since it is not present in a finished structure, the shielding layer 84 from a pure Si, Si x C y , Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1). In some embodiments, where the shielding layer 84 if present in a final structure, the shielding layer 84 not from one of pure Si, Si x C y , Si x Cl ybe manufactured because such a high Si content remaining in the finished device can degrade the work function, the threshold voltage Vt of the device and / or the gate resistance.

[0016] In some embodiments, the shielding layer 84 Silicon nitride, i.e., Si x N y , where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1. In some embodiments, where the shielding layer 84 In a final structure, x is not more than 0.75, since such a high silicon content remaining in the finished device can degrade the work function, the threshold voltage Vt of the device, and / or the gate resistance. The upper limit for y is due to process limitations in some embodiments. In some embodiments, the shielding layer 84 Silicon nitride, i.e., Si x N y, where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1. In some embodiments, where the shielding layer 84 If the shielding layer is removed and not retained in a finished structure, x can be greater than 0.75, in which case the shielding layer is a silicon nitride-enriched or pure silicon film with a small amount of nitrogen. The upper limit for y is due to process limitations in some embodiments.

[0017] In some embodiments, the shielding layer 84 Ti x N y , where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1. In this case, the shielding layer acts as a sacrificial layer to protect the underlying first conductive layer. 83 to protect. In some embodiments, x is not less than 0.3 and y is not greater than 0.7. The upper limit for y in some embodiments is due to process constraints.

[0018] In some embodiments, the shielding layer 84 one made of pure Ti or Ti x C y or Ti x Cl y , where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1. In this case, the shielding layer acts as a sacrificial layer to protect the underlying first conductive layer. 83 to protect. In some embodiments, x is greater than 0.9 and y is not greater than 0.1. The upper limit for y aims to avoid excessive C, Cl impurities in the finished structure, thereby reducing gate resistance and dielectric defects. The C, Cl impurities in the Ti x C y - or Ti x Cl y -Film, i.e. the value for y, can be reduced by impregnation with hydrogen gas after film deposition.

[0019] In some embodiments, the shielding layer 84 Si x Ti y N z, where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 < y ≤ 0.7 and x+y+z=1. In some embodiments, where the shielding layer 84 In a final structure, x is not more than 0.75, since such a high silicon content remaining in the finished device can degrade the work function, the threshold voltage Vt of the device, and / or the gate resistance. The upper limit for y is due to process limitations in some embodiments. In some embodiments, the shielding layer 84 Si x Ti y N z , where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1. In some embodiments, where the shielding layer 84When removed and not retained in a finished structure, x can be greater than 0.75 and as high as 0.99, in which case the shielding layer is a Si-enriched film, such as pure Si or silicon nitride or titanium silicide film with a small amount of titanium and nitrogen. In some embodiments, x is [value missing], in which case the shielding layer [value missing] 84 either pure Ti or TiN, which acts as a sacrificial layer to protect the underlying first conductive layer 83 to protect. In some embodiments, y is 0, where in this case the shielding layer 84 either pure Si or silicon nitride. In some embodiments, y is 1 (in other words, the shielding layer is 84 pure Ti or Ti with very minute amounts of Si and / or N). In some embodiments, zo is, in this case the shielding layer 84a titanium silicide (e.g., TiSi, TiSi2, Ti3Si, Ti5Si3, Ti5Si4, etc.). The upper limit for z is due to process limitations in some embodiments.

[0020] Regarding the properties of the shielding layer 84 A silicon-rich film and / or a titanium silicide film can offer more protection against oxidation and / or fluorine damage to the underlying layers. Furthermore, if the shielding layer is a silicon-rich amorphous film, it suppresses [something - likely a specific effect or effect]. 84 Due to the absence of grain boundary diffusion pathways, Al diffusion is more effective. A Si-rich film, on the other hand, can cause a problem with a high Vt shift. A Ti-rich film (e.g., a film with low Si content) can cause a lower Vt effect, but it may provide less protection for the underlying layers. During the deposition of the shielding layer 84and / or during the healing operation, oxygen (O) can pass from the oxidized first conductive layer into the shielding layer. 84 diffuse and form an O-rich shielding layer (i.e., SiON, SiO₂). x , SiTiNO x ) and form an oxygen-poor first conductive layer. A silicon-rich shielding layer provides a more effective trap of oxygen from the first conductive layer and more efficient control of renewed interface layer growth.

[0021] The thickness of the shielding layer 84 is smaller than the thickness of the first conductive layer 83 and in some embodiments it lies in a range of approximately 0.1 nm to approximately 30 nm. The thickness of the shielding layer 84 In other embodiments, the thickness ranges from approximately 0.5 nm to approximately 15 nm. In some embodiments, a thickness of T1 the first conductive layer 83 and a thicknessT2 the shielding layer 84 0.05 ≤ T2 / (T1 + T2) < 0.85. A shielding layer with a thickness less than approximately 0.5 nm or where T2 / (T1 + T2) < 0.05 may not provide sufficient protection for the first conductive layer. 83 prior to oxidation and / or F-damage, it may not reduce interfacial layer regeneration (ILRG) and may not prevent diffusion of metal from the work function setting layers. 87 and / or the gate electrode layer 88 into the gate dielectric layer 82 In some embodiments, T2 / (T1 + T2) is not more than 0.85; otherwise, it may degrade the work function, the resistance of the device, the device threshold voltage (Vt), and / or the speed performance of the device.

[0022] The shielding layer 84 , the first conductive layer 83, the gate dielectric layer 82 , the dielectric layer 50 and / or the gate sidewall spacers 46 Some embodiments contain fluorine (F). Fluorine is present in the gate dielectric layer. 82 can cause defects, such as lattice gaps and unsaturated bonds, in the gate dielectric layer 82 This reduces leakage current problems and improves device reliability. Incorporating fluorine into the gate sidewall spacers helps block aluminum diffusion from the metal gate layers into the source / drain regions. However, if the amount of fluorine is too high, it can damage the first conductive layer. 83 and the gate dielectric layer 82 cause and also worsen the Vt of an NMOS device (by increasing NMOS Vt).

[0023] The concentration of fluorine in the shielding layer 84The fluorine concentration in the first conductive layer ranges from approximately 0.02 atomic percent to approximately 75 atomic percent in some embodiments and from approximately 1 atomic percent to approximately 25 atomic percent in other embodiments. 83 In some embodiments, the fluorine content ranges from approximately 0.02 atomic percent to approximately 55 atomic percent, and in other embodiments, it ranges from approximately 1 atomic percent to approximately 25 atomic percent. If fluorine is present in a higher quantity in the shielding layer... 84 and the first conductive layer 83 If fluorine is incorporated, these layers can offer a higher effective work function, which helps to reduce the Vt of a PMOS device. However, due to the diffusion of fluorine into the first conductive layer and the gate dielectric layer in general, it is possible that the shielding layer 82contains more than approximately 75 atomic percent fluorine. If the amount of fluorine in the first conductive layer 83 If the concentration exceeds approximately 55 atomic percent, it can lead to a loss of the first conductive layer due to the formation of volatile metal fluorides, such as TiF. x and WF x , cause.

[0024] The concentration of fluorine in the gate dielectric layer 82 In some embodiments, the fluorine content ranges from approximately 0.01 atomic percent to approximately 40 atomic percent, and in other embodiments, it ranges from approximately 0.5 atomic percent to approximately 10 atomic percent. The amount of fluorine in the gate dielectric layer... 82 If the concentration exceeds approximately 40 atomic percent, it can be caused by the formation of, for example, HfF. x Damage to the gate dielectric layer 82 cause and reduce their effective dielectric constant.

[0025] In some embodiments, the shielding layer84 partially amorphous or completely amorphous. The percentage of crystallinity of the shielding layer. 84 In some embodiments, the percentage of crystallinity ranges from approximately 0% (essentially completely amorphous) to approximately 90%. In some embodiments, the percentage of crystallinity depends on the shielding layer composition and the deposition temperature. In some embodiments, the percentage of crystallinity decreases with increasing Si content (i.e., as the x-value increases). In other embodiments, the percentage of crystallinity increases with increasing deposition temperature and when the temperature of one or more subsequent curing processes is increased. The shielding layer 84 helps to prevent the diffusion of metal (e.g. Al) from the work function adjustment layers. 87 and / or the gate electrode layer 88 into the gate dielectric layer 82to block, especially when the shielding layer 84 The film is more amorphous (low crystallinity). This helps improve the gate oxide quality by reducing Al defects in the dielectric, thereby improving the device's leakage current behavior. This involves the diffusion of metal (e.g., Al) from the gate stack into the gate dielectric layer. 82 due to the amorphous nature of the shielding layer 84 effectively reduced (absence of grain boundaries in the amorphous structure avoids the phenomenon of grain boundary diffusion).

[0026] The shielding layer 84 In some embodiments, the first conductive layer may become thin or be lost. 83 (e.g., TiN layer) during fluorine uptake operations, thus enabling the use of F-based gas without damage to the first conductive layer. 83 and / or the gate dielectric layer 82This is made possible by the fluorine in the first conductive layer and / or the gate dielectric layers, which compensates for the threshold voltages of the PMOS and NMOS semiconductor device, i.e., it reduces the PMOS threshold voltage. It also helps to reduce trapping sites in the dielectric layers, such as oxygen lattice gaps and / or unsaturated bonds, thereby improving the dielectric quality.

[0027] In some embodiments, the shielding layer helps 84 also involved, the first conductive layer 83 to protect against natural oxidation by creating the first conductive layer 83 is insulated from atmospheric oxygen and / or moisture. In some embodiments, the shielding layer helps 84 thereby determining the atomic percentage of oxygen in the first conductive layer 83from the range of approximately 22 atomic% to approximately 90 atomic% (i.e., without the use of the shielding layer). 84 ) to the range of approximately 1.5 atomic % to approximately 65 atomic % (i.e., when using the shielding layer) 84 ) to reduce. In some embodiments, the shielding layer acts 84 as an oxygen-trapping layer, i.e., the shielding layer helps to prevent the oxygen from escaping the first conductive layer. 83 and / or from the gate dielectric layer 82 to capture oxygen released during one or more subsequent healing processes. This oxygen-capturing ability reduces renewed interfacial layer growth during healing, thereby decreasing the interfacial layer thickness, which in turn helps to increase device velocity. on -I off-to improve the device's performance and / or the operating frequency performance of the ring oscillator. In some embodiments, the oxygen trapping capability and the ability to control the interface layer growth of the shielding layer can be improved. 84 by controlling the composition and thickness of the shielding layer 84 can be improved. A higher Si content (i.e., a higher x-value in Si) x N z , Si x C y , Si x Cl y , Si x Ti y , Si x Ti y N z ) and a greater thickness of the shielding layer 84 In some embodiments, they offer greater oxidation protection and further improved control of interfacial layer growth.

[0028] Fig. Figure 1B shows a general process flow for manufacturing a semiconductor device according to an embodiment of the present disclosure. One or more additional operations may be performed during the manufacturing ramp-up of Fig. 1. The process will be carried out, and some of the processes may not be carried out. The order of the processes can be changed. In S101 from Fig. 1B A boundary layer is formed above the canal area in the fin structure. S103 from Fig. In 1B, a gate dielectric layer is formed above the interface layer. S105 from Fig. In step 1B, a first conductive layer is formed over the gate dielectric layer, and a shielding layer is formed over the first conductive layer. S107 from Fig. 1B involves initial healing (e.g., healing after metallization). In S109 from Fig. 1B A cover layer is formed. S111 from Fig. 1B involves a second healing process (healing after covering). S113 from Fig. 1B The covering layer is removed after healing. In S115 from Fig. In some embodiments, the shielding layer is removed. In other embodiments, the shielding layer is not removed. S117 from Fig. In 1B, an additional first conductive layer is optionally formed to compensate for the loss of the first conductive layer. S119 from Fig. In 1B, a second conductive layer is formed. S212 A gate electrode layer is formed, comprising one or more exit work setting layers and a body gate electrode layer.

[0029] Fig. 2A to Fig. Figure 3F shows cross-sectional views of different stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 3G shows a process sequence for manufacturing a semiconductor device according to an embodiment of the present disclosure. It is understood that in the sequential manufacturing process, for additional embodiments of the method, one or more additional operations may be performed before, during, and after the steps described in Figure 3G. Fig. 2A to Fig. The stages shown in 3F can be implemented, and some of the operations described below can be replaced or eliminated. The sequence of operations / processes can be interchangeable.

[0030] As in Fig. As shown in 2A, one or more fin structures are depicted. 20 over a substrate 10 manufactured. The substrate 10For example, a p-type silicon substrate with an impurity concentration in the range of approximately 1 × 10 15 cm 3 up to approximately 1 × 10 18 cm -3 In other embodiments, the substrate 10 an n-type silicon substrate with an impurity concentration in the range of approximately 1 × 10 15 cm -3 up to approximately 1 × 10 18 cm -3 Alternatively, the substrate can be 10 another elemental semiconductor, such as germanium, a compound semiconductor comprising group IV-IV compound semiconductors, such as SiC and SiGe, group III-V compound semiconductors, such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof. In one embodiment, the substrate 10A silicon layer on an SOI substrate (silicon on an insulator). Amorphous substrates, such as amorphous Si or amorphous SiC, or an insulating material, such as silicon oxide, can also serve as the substrate. 10 can be used. The substrate 10 It can have different areas that have been suitably doped with impurities (e.g., p-type or n-type conductivity).

[0031] The fin structures 20 can be structured using any suitable method. For example, the fin structures can be 20The structures are structured using one or more photolithographic processes that incorporate dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, smaller pitches than would otherwise be achievable using a single direct photolithographic process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithographic process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fin structures. 20 be used.

[0032] As in Fig. Figure 2A shows two fin structures extending in the Y direction. 20 The fin structures are arranged adjacent to each other in the X-direction. However, the number of fin structures is not limited to two. The number can be one, three, four, five, or more. Furthermore, one or more dummy fin structures can be adjacent to both sides of the main fin structures. 20 They are arranged to improve structural accuracy in structuring processes. The width of the fin structure 20 In some embodiments, the height lies in a range of approximately 5 nm to approximately 40 nm, and in certain embodiments, it can lie in a range of approximately 7 nm to approximately 15 nm. The height of the fin structure 20In some embodiments, the distance lies in a range of approximately 100 nm to approximately 300 nm, and in other embodiments, it can lie in a range of approximately 50 nm to approximately 100 nm. The distance between the fin structures 20 In some embodiments, the n-value ranges from approximately 5 nm to approximately 80 nm, and in other embodiments, it ranges from approximately 7 nm to approximately 15 nm. However, a person skilled in the art will understand that the dimensions and values ​​cited in the descriptions are merely examples and can be modified to suit different scales of integrated circuits. In some embodiments, the FinFET device is an n-channel FinFET. In some embodiments, the FinFET device is a p-channel FinFET.

[0033] After the fin structures 20 have been trained, an insulating insulating layer is applied. 30above the fin structures 20 trained, as in Fig. 2B is shown.

[0034] The insulating insulating layer 30It features one or more layers of insulating materials, such as silicon oxide, silicon oxynitride, or silicon nitride, formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, flowable dielectric materials are deposited instead of silicon oxide. Flowable dielectric materials, as their name suggests, can "flow" during deposition to fill gaps or spaces with a high aspect ratio. Various chemistries are typically added to silicon-containing precursors to enable the deposited film to flow. In some embodiments, nitrogen hydride bonds are added.Examples of flowable dielectric precursors, particularly flowable silicon dioxide precursors, include a silicate, a siloxane, a methylsilsesquioxane (MSQ), a hydrogensilsesquioxane (HSQ), a mixture of MSQ and HSQ, a perhydrosilazane (TCPS), a perhydropolysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silylamine, such as trisilylamine (TSA). These flowable silicon dioxide materials are formed in a multi-step process. After the flowable film is deposited, it is hardened and then cured to remove any unwanted elements to form silicon dioxide. The flowable film may be doped with boron and / or phosphorus. The insulating layer... 30 In some embodiments, it can be formed by one or more layers of spin-on glass (SOG), SiO, SiON, SiOCN and / or fluorine-doped silicate glass (FSG).

[0035] After the formation of the insulating layer 30 above the fin structures 20 A planarization process is performed to remove part of the insulating insulation layer. 30 and to remove the mask layer (the pad oxide layer and the silicon nitride mask layer). The planarization process may involve a chemical-mechanical polishing (CMP) and / or a re-etching process. Then the insulating layer is removed. 30 further away, so that an upper part of the fin structure 20 , which becomes a channel layer, is exposed, as in Fig. 2B is shown.

[0036] In certain embodiments, the partial removal of the insulating layer may 30This can be carried out using a wet etching process, for example by immersing the substrate in hydrofluoric acid (HF). In another embodiment, the insulating layer can be partially removed. 30 This can be carried out using a dry etching process. For example, a dry etching process using CHF3 or BF3 as etching gases can be used.

[0037] After the formation of the insulating layer 30 Can a thermal process, for example a curing process, be carried out to improve the quality of the insulating layer? 30 to improve. In certain embodiments, the thermal process is carried out using rapid thermal annealing (RTA) at a temperature in the range of approximately 900 °C to approximately 1050 °C for approximately 1.5 seconds to approximately 10 seconds in an inert gas environment, such as an N2, Ar or He environment.

[0038] Then a dummy gate structure is created. 40 over part of the fin structures 20 trained, as in Fig. 2C shown.

[0039] A dielectric layer and a polysilicon layer are applied over the insulating insulating layer. 30 and the exposed fin structures 20 trained, and then structuring processes are carried out to achieve a dummy gate structure, which is a dummy gate electrode layer made of polysilicon. 44 and a dummy gated dielectric layer 42 The structuring of the polysilicon layer is carried out using a hard mask, which in some embodiments includes a silicon nitride layer and an oxide layer. The dummy gated dielectric layer 42It can be silicon oxide formed by CVD, PVD, ALD, electron beam evaporation, or another suitable process. In some embodiments, the dummy gated dielectric layer can be 42 The devices comprise one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some embodiments, the thickness of the dummy gated dielectric layer ranges from approximately 1 nm to approximately 5 nm.

[0040] In some embodiments, the dummy gate electrode layer 44 The polysilicon used can be doped with uniform or non-uniform doping. In the present embodiment, a width of the dummy gated dielectric layer is defined. 44in the range of approximately 30 nm to approximately 60 nm. In some embodiments, the thickness of the dummy gate electrode layer is in the range of approximately 30 nm to approximately 50 nm. Furthermore, one or more dummy gate structures can be located adjacent to both sides of the dummy gate structure. 40 They are arranged to improve structural accuracy in structuring processes. The width of the dummy gate structure 40 In some embodiments, it lies in a range of approximately 5 nm to approximately 40 nm, and in certain embodiments it may lie in a range of approximately 7 nm to approximately 15 nm.

[0041] Furthermore, as in Fig. 2C shown, side wall spacer 46 on opposite side surfaces of the dummy gate structures 40 trained. An insulating material layer for the side wall spacers. 46 is above the dummy gate structure 40The insulating material layer is deposited in a conformal manner, so that it is formed in such a way that it has essentially the same thickness on vertical surfaces, such as the side walls, horizontal surfaces, and the top of the dummy gate structure. 49 In some other embodiments, the insulating material layer has a thickness in the range of approximately 5 nm to approximately 20 nm. The insulating material layer comprises one or more of SiN, SiON, and SiCN, or any other suitable dielectric material. The insulating material layer can be formed by ALD or CVD, or any other suitable method. Next, lower portions of the insulating material layer are removed by anisotropic etching, creating sidewall spacers. 46 are formed. In some embodiments, the side wall spacers have 46two to four layers of different insulating materials. In some embodiments, part of the dummy gated dielectric layer is 42 between the side wall spacers 46 and the insulating insulating layer 30 arranged. In other embodiments, no part of the dummy gated dielectric layer is present. 42 between the side wall spacers 46 and the insulating insulating layer 30 arranged.

[0042] Subsequently, in some embodiments, a source / drain region of the fin structure is formed. 20 , which is not related to the dummy gate structure 40The surface is covered and etched downwards (recessed) to form a source / drain cavity. After the source / drain cavity is formed, one or more source / drain epitaxial layers are formed within it. In some embodiments, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer are formed. In other embodiments, no cavity is formed, and the epitaxial layers are formed over the fin structure.

[0043] In some embodiments, the first epitaxial layer comprises SiP or SiCP for an n-channel FinFET, and in some embodiments, B-doped SiGe for a p-channel FinFET. The amount of P (phosphorus) in the first epitaxial layer ranges from approximately 1 × 10¹⁸ atoms / cm³ to approximately 1 × 10²⁰ atoms / cm³ in some embodiments. The thickness of the first epitaxial layer ranges from approximately 5 nm to 20 nm in some embodiments and from approximately 5 nm to approximately 15 nm in others. If the first epitaxial layer is SiGe, the amount of Ge ranges from approximately 25 atomic% to approximately 32 atomic% in some embodiments and from approximately 28 atomic% to approximately 30 atomic% in others. The second epitaxial layer features SiP or SiCP for an n-channel FinFET, and in some embodiments, B-doped SiGe for a p-channel FinFET.In some embodiments, the amount of phosphorus in the second epitaxial layer is higher than the amount of phosphorus in the first epitaxial layer and ranges from approximately 1 × 10²⁰ atoms / cm³ to approximately 2 × 10²⁰ atoms / cm³. The thickness of the second epitaxial layer in this embodiment ranges from approximately 20 nm to 40 nm, while in other embodiments it ranges from approximately 25 nm to approximately 35 nm. If the second epitaxial layer is SiGe, the amount of Ge is approximately 35 atomic percent to approximately 55 atomic percent in some embodiments and approximately 41 atomic percent to approximately 46 atomic percent in other embodiments. The third epitaxial layer may be a SiP epitaxial layer. The third epitaxial layer serves as a sacrificial layer for silicide formation in the source / drain.The amount of phosphorus in the third epitaxial layer is smaller than the amount of phosphorus in the second epitaxial layer and, in some embodiments, is in the range of approximately 1 × 10. 18 atoms / cm³ up to approximately 1 × 10 21 atoms / cm3. If the third epitaxial layer is SiGe, the amount of Ge in some embodiments is less than approximately 20 atomic %, and in other embodiments is approximately 1 atomic % to approximately 18 atomic %.

[0044] In at least one embodiment, the epitaxial layers are epitaxially grown using an LPCVD process, molecular beam epitaxy, atomic layer deposition, or another suitable method. The LPCVD process is carried out at a temperature of approximately 400 to 850 °C and a pressure of approximately 1 Torr to 200 Torr using a silicon source gas, such as SiH4, Si2H6, or Si2H8, a germanium source gas, such as GeH4 or G2H6, a carbon source gas, such as CH4 or SiH3CH3, and a phosphorus source gas, such as PH3.

[0045] Then, as in Fig. 2C is shown, a dielectric intermediate layer (ILD) 50 above the epitaxial S / D layer and the dummy gate structure 40 trained. The materials for the ILD layer 50They contain compounds that have Si, O, C and / or H, such as silicon dioxide, SiCOH and SiOC. Organic materials, such as polymers, can be used for the ILD layer. 50 be used.

[0046] After the ILD layer 50 Once trained, a planarization process, such as CMP, is performed so that the upper section of the dummy gate electrode layer 44 is exposed, as in Fig. 2C is shown. In some embodiments, before the ILD layer 50 A contact etch stop layer, such as a silicon nitride layer or a silicon oxynitride layer, is formed.

[0047] Then the dummy gate electrode layer 44 and the dummy gated dielectric layer 42 removed, creating a gate room 47 is trained, as in Fig. Shown in 2D. The dummy gate structures can be removed using plasma dry etching and / or wet etching. When the dummy gate electrode layer... 44 Polysilicon is and the ILD layer 40 If silicon oxide is present, a wet etchant, such as a TMAH solution, can be used to etch the dummy gate electrode layer. 44 to selectively remove the dummy gated dielectric layer. 42 is then removed using plasma dry etching and / or wet etching.

[0048] Fig. 3A shows the structure after the channel area of ​​the fin structure. 20 in the Gatespacer 47 was uncovered. Fig. 3A to Fig. 3F are the side wall spacers 46 and the ILD layer 50 omitted.

[0049] As in Fig. 3B is shown, at S301 by Fig. 3G a boundary layer 81 on the fin structure 20trained, and at S303 from Fig. 3G will have a gate dielectric layer 82 on the interface layer 81 formed. In some embodiments, the interface layer is formed using chemical oxidation. In some embodiments, the interface layer has 81 one of silicon oxide, silicon nitride, and a mixed silicon-germanium oxide. The thickness of the interface layer 81 In some embodiments, the thickness lies in a range of approximately 0.2 nm to approximately 6 nm. In some embodiments, the gate dielectric layer has 82one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials include HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, a hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃), La₂O₃, HfO₂-La₂O₃, Y₂O₃, or other suitable high-k dielectric materials and / or combinations thereof. The gate dielectric layer 82 can be formed using a CVD, an ALD, or any suitable method. In one embodiment, the gate dielectric layer 82Using a highly conformal deposition process, such as ALD, a gate dielectric layer with a uniform thickness around each channel layer is formed. 82 In one embodiment, the wavelength lies in a range of approximately 1 nm to approximately 100 nm.

[0050] Then, as in Fig. 3C shown, at S305 of Fig. 3G a first conductive layer 83 and a shielding layer 84 trained. The first conductive layer 83 and the shielding layer 84 In some embodiments, the shielding layer can be formed using a CVD, an ALD, or any suitable method. In some embodiments, the shielding layer is... 84 after the formation of the first conductive layer 83designed without interrupting the vacuum, thus avoiding any contamination from the atmosphere or oxidation of the film. In other embodiments, the shielding layer 94 after the formation of the first conductive layer 83 formed with an interruption of the vacuum.

[0051] In some embodiments, the shielding layer 84 Made from Si, silicon nitride, titanium silicide (e.g., TiSi, TiSi2, Ti3Si, Ti5Si3, Ti5Si4, etc.), SiC, SiCl, Ti, TiC, TiCl, TiN, and SiTiN. In some embodiments, the shielding layer is formed using CVD, ALD, or any other suitable film formation process. In some embodiments, the shielding layer 84 trained using a highly conformal deposition process, such as an ALD, to form the shielding layer 84, which have a substantially uniform thickness above the first conductive layer 83 to ensure each channel layer. In other embodiments, the shielding layer 84formed by thermal decomposition at high temperature, chemical reaction of precursors of Si and / or precursors of Ti and / or precursors of N. In some embodiments, a silicon source (precursor) comprises one or more of silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorosilane (Si2Cl6), dimethyldichlorosilane (Si(CH3)2Cl2), TEOS (Si(OC2H5)4), trichlorosilane (SiHCl3), trichlorodisilane (Si2H3Cl3), hexamethyldisilane (Si(CH3)3)2, and tetraethylsilane (Si(C2H5)4). In some embodiments, a titanium source (precursor) comprises one or more of titanium tetrachloride (TiCl4), tetrakis-dimethylamido-titanium (Ti(N(CH3)2)4), and tris(dimethylamido)-(dimethylamino-2-propanolato)titanium (Ti(NMe2)3(dmap)). In some embodiments, a nitrogen source (precursor) comprises one or more of ammonia. (NH3), hydrazine (N2H4) and N2. In some embodiments, atomic layer deposition (ALD) is used.In some embodiments, the film formation temperature ranges from approximately 250 °C to approximately 600 °C, and in other embodiments, it ranges from approximately 400 °C to 500 °C. In some embodiments, the pressure during the film formation process ranges from approximately 1 Torr to approximately 150 Torr.

[0052] Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D shows different gas injection times for ALD processes to form a SiTiN layer for the shielding layer. 84 to train. Fig. 4E, Fig. 4F, Fig. 4G and Fig. Figure 4H shows different gas injection times for ALD processes to form a SiN, Ti, Si, or TiSi layer for the shielding layer. 84 to develop. In some embodiments, a CVD is used with the gas supply times shown.

[0053] In a Fig. In the embodiment shown in Figure 4A, the ALD is performed by a first cycle of feeding a Ti precursor (e.g., TiCl4) and an N precursor "NPc" (e.g., NH3), and a second cycle of feeding a Si precursor "SiPc" (e.g., BSiH4) and an N precursor. The first cycle is repeated m times (n = 1, 2, 3,...), and the second cycle is repeated n times (n = 1, 2, 3,...). Therefore, the feeding of Ti, N, Si, and N precursors is repeated in this sequence. A purge gas (e.g., Ar) is supplied to flush out the excess precursor during precursor changes.

[0054] In a Fig. In the embodiment shown in Figure 4B, the ALD is performed by feeding a silicon precursor, a titanium precursor, and an nitrogen precursor in that order, which can be repeated two or more times. Therefore, the feeding of silicon, titanium, and nitrogen precursors is repeated in this sequence. A purge gas is introduced when changing precursors. The order of gas feeding can be changed.

[0055] In a Fig. In the embodiment shown in Figure 4C, the ALD is performed by feeding a Ti precursor, a Si precursor, and an N precursor in that order, which can be repeated two or more times. Therefore, the feeding of Ti, Si, and N precursors is repeated in this sequence. A purge gas is introduced when changing precursors. The order of gas feeding can be changed.

[0056] In a Fig. In the embodiment shown in 4D, the ALD is carried out by supplying a Ti precursor and a mixed gas, followed by a Si precursor and an N precursor in that sequence, which can be repeated two or more times. Therefore, the supply of Ti precursors and a mixture of Si and N is repeated in this sequence. A purge gas is supplied when changing the precursor. The order of the gas supply can be changed.

[0057] In a Fig. In the embodiment shown in 4E, the ALD for a SiN layer is carried out by feeding a Si precursor and an N precursor, which can be repeated two or more times. Therefore, the feeding of Si and N precursors is repeated in this sequence. One or more purging operations with the purge gas are carried out when changing the precursor.

[0058] In a Fig. In the embodiment shown in 4F, the ALD for a Ti layer is carried out by supplying a Ti precursor and a purge gas containing at least one of Ar or H2 gas, which can be repeated two or more times.

[0059] In a Fig. In the embodiment shown in Figure 4G, the ALD for a Si layer is carried out by supplying a Si precursor and a purging gas, which can be repeated two or more times.

[0060] In a Fig. In the embodiment shown in Figure 4H, the ALD for a TiSi layer is carried out by feeding a Ti precursor and a Si precursor in that order, which can be repeated two or more times. A purge gas is supplied when changing the precursor. The order of gas supply can be changed.

[0061] In some embodiments, S307 is used by Fig. 3G, after the shielding layer 84In some embodiments, a first healing process was carried out for approximately 1 ns (spike healing, such as laser healing) to approximately 360 s at a temperature of approximately 600 °C to approximately 800 °C.

[0062] The first healing process can help to repair the gate dielectric layer. 82 to compact and introduce nitrogen into the gate dielectric layer 82 Nitrogen helps to passivate oxygen grid vacancies, reducing leakage current and improving device reliability. The initial curing can also help form a stable mixed layer, which provides a stable platform for subsequent deposition of a metal gate film onto the dielectric layer. If the temperature is too high, the initial curing can lead to crystallization and grain boundary formation in the high-k gate dielectric layer. 82cause leakage current behavior and renewed growth on the interface layer 81 This has an effect, slowing down the device's speed. Conversely, if the temperature is too low, the initial curing may not provide sufficient density in the high-k gate dielectric layer and could cause device instability / fluctuations during subsequent metal gate deposition processes.

[0063] Subsequently, in some embodiments, the stacked structure, which forms the interface layer, is 81 , the gate dielectric layer 82 , the first conductive layer 83 and the shielding layer 84 exhibits, in a fluorine-containing gas (e.g. F2 and / or NF3) for 4 s to approximately 15 min at a temperature of approximately room temperature ( 25The temperature range is from approximately 550 °C to around 550 °C. As explained above, the incorporation of fluorine helps to improve the work function adjustment property, reduce the Vt of a PMOS device, and eliminate oxygen lattice gaps in the gate dielectric layer. 82 to passivate, reduce leakage current, and reduce unsaturated bonds in the gate dielectric layer. On the other hand, impregnation in fluorine can damage the first conductive layer. 83 (e.g., etching by fluorine precursor gases) and / or of the gate dielectric layer (e.g., reduction of a dielectric constant). The use of the shielding layer 84 can suppress or avoid this problem.

[0064] Then, at S309, from Fig. 3G a covering layer 85 e.g. a crystalline, polycrystalline or amorphous Si layer above the shielding layer 84 trained, as in Fig. 3D representation, and at S311 from Fig. In some embodiments, a second curing process is performed for approximately 1 ns (spike curing, such as laser curing) to approximately 360 s at a temperature of approximately 550 °C to approximately 1300 °C. In some embodiments, the temperature is from 900 °C to 1100 °C. This leads, in some embodiments, to the diffusion of fluorine into the cover layer. 85 , the shielding layer 84 , the first conductive layer 83 and the gate dielectric layer 82 . At S313 from Fig. After the second healing process, 3G becomes the covering layer. 85 removed, as in Fig. 3E is shown.

[0065] The second healing process with the Si covering layer 85 It also helps to improve the quality of the gate dielectric layer. 82to improve. A gate dielectric layer, such as a high-k dielectric layer, is formed at a comparatively low temperature to avoid crystallization and grain boundary formation, while metal gate films are deposited at comparatively high temperatures. Accordingly, it is desirable to make the high-k dielectric layer more thermally stable before the metal gate deposition. The second curing with the cover layer 85 Within the temperature ranges outlined above, the high-k dielectric layer can become denser and more thermally stable without thermal oxide inversion during metal gate deposition. The second annealing also helps to transfer fluorine from the outer layers (e.g., the cover layer and the shielding layer) into the first conductive layer. 85 , the gate dielectric layer 82 and the interface layer 81to diffuse thermally. The cover layer 85 is used to create the gate dielectric layer 82 and the first conductive layer 83 to protect against unwanted oxidation damage and to isolate these films from the curing atmosphere. After thermal stabilization of the gate dielectric layer, the cover layer is applied. 85 It is no longer needed in the finished device structure and is therefore removed.

[0066] Then, at S315, from Fig. 3G the barrier layer 86 trained, and then at S317 by Fig. 3G the gate metal layers, which contain one or more exit work setting layers 87 and a body metal layer (gate electrode layer) 88 exhibit, above the shielding layer 84 trained.

[0067] In some embodiments, the barrier layer 86Made of TaN, it serves as an etch-stop barrier layer. The barrier layer 86 It acts as a wet etch stop layer during the structuring of p-type and n-type output work setting layers, which are subsequently formed to create multiple Vt devices. In some embodiments, a p-type output work setting layer is removed from one n-type device area, while the p-type output work setting layer remains on another PMOS.

[0068] In some embodiments, the exit work setting layer 87The output function layer is made from a conductive material, such as a single layer of TiN, WN, TaAlC, TiC, TaC, Co, Al, TiAl, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more layers of TaN, TaAlC, TiN, TiC, Co, or TiAl are used as the output function layer, and for the p-channel FET, one or more layers of TiAlC, Al, TiAl, TaN, TaAlC, TiN, WN, TiC, and Co are used as the output function layer. The output function layer can be formed using ALD, PVD, CVD, electron beam evaporation, or another suitable process. Furthermore, the output function layer can be formed separately for the n-channel FET and the p-channel FET, which may use different metal layers. In some embodiments, the exit work setting layer 87deposited and selectively removed from some transistors using one or more lithographic and etching processes.

[0069] The gate electrode layer (body metal layer) 88 It has one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The body metal layer 88 can be formed using CVD, ALD, electroplating or another suitable method.

[0070] The sequence of fluorine impregnation and the formation of the cover layer (e.g., Si cover layer) 85 is not limited to the sequence described above. In some embodiments, the fluorine impregnation is carried out before the formation of the Si cover layer. 85The fluoride treatment is carried out simultaneously with the formation of the cover layer. 85 carried out, i.e., fluorination impregnation during the deposition of the Si cover layer by introducing an F2 gas at a temperature, for example, in a range of approximately 300 °C to approximately 450 °C, or fluorination impregnation is carried out after the formation of the Si cover layer. 85 carried out.

[0071] Fig. Figure 5 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 6A to Fig. Figure 6F shows cross-sectional views of various stages of a sequential manufacturing process of the semiconductor device. Fig. 5 according to one embodiment of the present disclosure. Fig. Figure 6G shows a process sequence for manufacturing a semiconductor device according to an embodiment of the present disclosure. It is understood that in the sequential manufacturing process, for additional embodiments of the method, one or more additional operations may be performed before, during, and after the steps described in Figure 6G. Fig. 6A to Fig. The stages shown in 6F can be provided, and some of the operations described below can be replaced or eliminated. The sequence of operations / processes can be interchangeable. Materials, configurations, dimensions, processes, and / or operations as described in relation to the preceding embodiments can be used in the embodiment below, and a detailed description thereof can be omitted.

[0072] In this embodiment, the finished semiconductor device structure does not have a shielding layer, as in Fig. 5 shown. In some embodiments, the shielding layer has 84 Si x Ti y N z on, where 0 ≤ x < 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 0.7. In other embodiments, the shielding layer 84 Made of silicon. In other embodiments, the shielding layer 84 made from silicon nitride, Ti, titanium nitride, titanium silicide (e.g. TiSi, TiSi2, Ti3Si, Ti5Si3, Ti5Si4 etc.).

[0073] The processes S601 , S603 , S605 , S607 , S609 , S611 and S613 from Fig. 6G and Fig. 6A to Fig. 6D each correspond to the processes S301 , S303 , S305 , S307 , S309 , S311 and S313 from Fig. 3G and Fig. 3A to Fig. 3D is the same. As in Fig. 6E is shown, after the cover layer 85 was removed S615 from Fig. 6G the shielding layer 84 also removed. Then, at S619 and S621 from Fig. 6G, as in Fig. 6F is shown, a barrier layer 86 , one or more exit work adjustment shifts 87 and a gate electrode layer 88 formed. In some embodiments, the shielding layer 84 after the first healing process and before the deposition of the covering layer 85 removed. In some embodiments, the shielding layer is removed. 84 The shielding layer is removed after the second healing process and after the removal of the covering layer. In some embodiments, the shielding layer is removed. 84 simultaneously during the removal process of the cover layer 85 removed. The shielding layer 84can be removed by dry etching and / or wet etching chemicals (e.g., the combination of HCl, NH4OH, H2O2, and deionized water) at a temperature in the range of approximately 25 °C to approximately 200 °C. In some embodiments, where the shielding layer 84 When the shielding layer is removed after the first curing process, a reduction in renewed interface layer growth of approximately 0.13 nm (i.e., approximately 0.13 nm less than the normally formed interface layer thickness) is observed. In some embodiments where the shielding layer is removed after the first curing process, a reduction in renewed interface layer growth of approximately 0.2 nm to 0.4 nm (i.e., approximately 0.2 nm to 0.4 nm less than the normally formed interface layer thickness) is observed. In some embodiments, S617 of Fig. 6G, after the shielding layer 84was removed and before the barrier layer and / or the second conductive layer is deposited, the first conductive layer 83 redeposited to compensate for the loss or damage to the first conductive layer during the shielding layer removal process.

[0074] Fig. Figure 7 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 8A to Fig. Figure 8F shows cross-sectional views of various stages of a sequential manufacturing process of the semiconductor device of Fig. 7 according to one embodiment of the present disclosure. Fig. Figure 8G shows a process sequence for manufacturing a semiconductor device according to an embodiment of the present disclosure. It is understood that in the sequential manufacturing process, for additional embodiments of the method, one or more additional operations may be performed before, during, and after the steps described in Figure 8G. Fig. 8A to Fig. The stages shown in 8F can be provided, and some of the operations described below can be replaced or eliminated. The sequence of operations / processes can be interchangeable. Materials, configurations, dimensions, processes, and / or operations as described in relation to the foregoing embodiments can be used in the embodiment below, and a detailed description thereof can be omitted.

[0075] In this embodiment, no fluorine impregnation is performed, and therefore the gate structure and channel regions of the semiconductor device are free of fluorine, as in Fig. 7 shown. In some embodiments, the shielding layer has 84 Si x N y (where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.25 ≤ x < 0.99, 0.01 ≤ y < 0.75 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Si x Ti y N z (where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1) on.

[0076] The processes S801 , S803 and S805 from Fig. 8G and Fig. 8A to Fig. 8C are each corresponding to the processes S301 , S303 , and S305 from Fig. 3G and Fig. 3A to Fig. 3C is the same. As in Fig. 8D representation, after the first conductive layer 83 and the shielding layer 84 were trained and a first healing process at S807 from Fig. 8G was carried out at S809 from Fig. 8G a cover layer 85 trained without a fluoride impregnation process being carried out, as in Fig. 8D representation. After the second healing process at S811 from Fig. 8G was carried out at S813 from Fig. 8G the cover layer 85 removed, while the shielding layer 84 is not removed, as in Fig. 8E is shown. Then, as in Fig. 8F is shown, a second conductive layer 86 at S815 from Fig. 8G trained, and one or more exit work recruitment shifts 87 and a gate electrode layer 88 will be S817 from Fig. 8G trained.

[0077] Fig. Figure 9 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Fig. 10A to Fig. Figure 10F shows cross-sectional views of various stages of a sequential manufacturing process of the semiconductor device of Fig. 9 according to one embodiment of the present disclosure. Fig. Figure 10G shows a process sequence for manufacturing a semiconductor device according to an embodiment of the present disclosure. It is understood that in the sequential manufacturing process, for additional embodiments of the method, one or more additional operations may be performed before, during, and after the steps described in Figure 10G. Fig. 10A to Fig. The stages shown in 10F can be provided, and some of the operations described below can be replaced or eliminated. The sequence of operations / processes can be interchangeable. Materials, configurations, dimensions, processes, and / or operations as described in relation to the foregoing embodiments can be used in the embodiment below, and a detailed description thereof can be omitted.

[0078] In this embodiment, no fluorine impregnation is carried out and no shielding layer is incorporated into the finished gate structure, as in Fig. 9 shown. In some embodiments, the shielding layer 84 one of Si, Si x C y , Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y , Ti x Cl y(where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Si x Ti y N z (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1). In other embodiments, the shielding layer 84 Made from Si, Si-enriched SiN, SiC, SiCl, TiSi or SiTiN.

[0079] The processes S1001 , S1003 and S1005 from Fig. 10G and Fig. 10A to Fig. 10D each correspond to the processes S801 , S803 , and S805 from Fig. 8G and Fig. 8A to Fig. 8D is the same. As in Fig. 8D representation, after the first conductive layer 83 and the shielding layer 84 were trained and a first healing process at S1007 from Fig. 10G was performed, at S1009 from Fig. 10G a cover layer 85 trained without a fluoride impregnation process being carried out, as in Fig. 8D representation. After the second healing process at S1011 from Fig. 10G was performed, at S1013 and S1015 from Fig. 10G the cover layer 85' and the shielding layer 84 removed, as in Fig. 10E is shown. Then, as in Fig. 10F shown, at S1019 from Fig. 10G a second conductive layer 86 trained, and one or more exit work hiring shifts 87 and a gate electrode layer 88 will be S1021 from Fig. 10G. In some embodiments, the shielding layer 84removed after the first curing process and before the deposition of the cover layer. In some embodiments, the shielding layer 84 after the second healing process and the removal of the covering layer. In some embodiments, during S1017 from Fig. 10G, after the shielding layer 84 was removed and before the barrier layer and / or the second conductive layer is deposited, the first conductive layer 83 redeposited to compensate for the loss or damage to the first conductive layer during the shielding layer removal process.

[0080] The various embodiments or examples described here offer several advantages over the prior art, as explained above. For example, in the present disclosure, a thin shielding layer (e.g., Si, Ti, TiSi, SiN, Si) is used. x Ti y N zA fluorinated silicon (FSI) layer is deposited on a first conductive layer (e.g., a TiN layer) to shield the first conductive layer from fluorine etching and oxidation damage, thus forming a two-layer cover structure. This two-layer cover structure allows the use of a fluorinated silicon cover (FSI) to successfully introduce fluorine into the TiN layer and the high-k gated dielectric layer without damaging the TiN layer. Using the fluorinated silicon cover layer together with the two-layer cover structure significantly improves the PMOS voltage and device reliability. 84 It also helps to protect the first conductive layer (e.g., TiN layer) from atmospheric oxidation damage by isolating the first conductive layer from atmospheric oxygen and / or moisture. The shielding layer 84It also helps to prevent the diffusion of metal (e.g., Al) from the work function adjustment layers. 87 and / or from the gate electrode layer 88 into the gate dielectric layer 82 to block, as in Fig. 11A and Fig. 11B is shown. Fig. Figure 11A shows an EDAX (energy-dispersive X-ray spectroscopy) result of an aluminium concentration profile for a structure without the formation of a shielding layer. 84 and Fig. Figure 11B shows an EDAX result of an aluminium concentration profile for a structure with a shielding layer. 84 according to the embodiments of the present disclosure, as set forth above. As in Fig. As shown in Figure 11B, an Al diffusion into the gate dielectric layer occurs. 82 , 81Effectively suppressed. In some embodiments, the Al concentration, when no shielding layer is used, ranges from approximately 1 atomic percent to approximately 10 atomic percent, and when a shielding layer is formed, the Al concentration is less than approximately 0.05 atomic percent. This helps to improve the gate oxide quality by suppressing Al defects in the dielectric layer. 82 , 81 This reduces the leakage current, thereby improving the device's leakage current behavior. In some embodiments, if the shielding layer remains in the finished structure, the gate dielectric layer is included. 82 Al in an amount of less than 0.05 atomic % and in other embodiments less than 0.02 atomic %.

[0081] Furthermore, the shielding layer 84 To capture or trap oxygen from the first conductive layer to control renewed interface layer growth, as in Fig. 11C and Fig. 11D representation. Fig. 11C shows a ToF-SIMS (time-of-flight secondary ion mass spectrometry) result for oxygen and Fig. Figure 11D shows a Tof-SIMS result for TiO2 for the structure with a shielding layer and also for the structure without a shielding layer according to an embodiment of the present disclosure. As in Fig. 11C and Fig. As shown in 11D, renewed growth of the interface layer is observed. 81 and / or oxidation of the first conductive layer 83Effectively suppressed. The shielding layer helps to trap oxygen released from the first conductive layer and / or the gate dielectric layer during one or more subsequent curing processes. This oxygen-trapping capability reduces re-growth of the interface layer during curing, thereby decreasing the interface layer thickness, which in turn helps to improve the device speed, ion-Ioff performance of the device, and / or operating frequency performance of the ring oscillator. Fig. 11E shows XPS spectra (X-ray photoelectron spectroscopy) of peaks of a 2p 3 / 2 -Titan orbitals (Ti2p 3 / 2 ) from the first conductive layer 83 for the structure with a shielding layer and for the structure without a shielding layer. As in Fig. As shown in Figure 11E, when a shielding layer is used, the titanium bonding to oxygen is significantly suppressed and the titanium bonding to a nitrogen peak is improved, indicating the oxidation protection of the first conductive layer (e.g., TiN layer) by the shielding layer. In some embodiments, the shielding layer helps 84 where the ratio of the number of Ti atoms bonded to an oxygen atom (Ti-O) to the number of Ti bonded to a nitrogen atom (Ti-N) (i.e., Ti-O / Ti-N ratio) of the first conductive layer 83 from the range of approximately 0.25 to 0.95 (i.e., without using the shielding layer) 84 ) to reduce to the range of approximately 0.03 to 0.48 (i.e., using the shielding layer). In some embodiments, the gate dielectric layer 82 Made from HfO2-La2O3. In such a case, the shielding layer helps. 84in this case, the metal, such as lanthanum, in the gate dielectric layer 82 from the channel, the interface layer 81 to move away. Fig. Figure 11F shows a ToF-SIMS (time-of-flight secondary ion mass spectrometry) result of a lanthanum concentration profile for a structure without the formation of a shielding layer. 84 and Fig. Figure 11G shows a ToF-SIMS result of a lanthanum concentration profile for a structure with a shielding layer. 84 according to the embodiments of the present disclosure, as set forth above. As in Fig. Figure 11G shows a diffusion of lanthanum from the gate dielectric layer. 82 to the shielding layer 84 enhanced, resulting from a reduced amount of lanthanum and dipole scattering at the interface of the HfO2-La2O3 gated dielectric layer 82 and the interface layer 81A PMOS device threshold voltage and a device flicker noise problem are reduced. In some embodiments, the La concentration is located at the interface of the HfO2-La2O3 gated dielectric layer. 82 and the interface layer 81 Without a shielding layer, the La concentration ranges from approximately 1 atomic percent to approximately 60 atomic percent, and with a shielding layer, it ranges from less than approximately 0.05 atomic percent to approximately 10 atomic percent. A larger amount of Si in the shielding layer causes more La to diffuse out.

[0082] The embodiments described above are not limited to FinFETs and can be applied to other types of n-channel and / or p-channel transistors, such as gate-all-around (GAA) transistors, including lateral gate-all-around (LGAA) transistors and vertical gate-all-around (VGAA) transistors.

[0083] It is understood that not all advantages have necessarily been discussed here, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages.

[0084] According to one aspect of the present disclosure, in a method for manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shielding layer is formed over the first conductive layer, a cover layer is formed over the shielding layer, a first curing process is carried out after the cover layer has been formed, the cover layer is removed after the first curing process, and a gate electrode layer is formed after the cover layer has been removed. In one or more of the preceding or following embodiments, the first conductive layer comprises a metal nitride layer. In one or more of the preceding or following embodiments, the first conductive layer is made of TiN.In one or more of the preceding or following embodiments, the thickness of the first conductive layer is in the range of 0.3 nm to 30 nm. In one or more of the preceding or following embodiments, the shielding layer is made of a Si, Si. x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y , Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z(where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1). In one or more of the preceding or following embodiments, the thickness of the shielding layer is in the range of 0.5 nm to 30 nm. In one or more of the preceding or following embodiments, the cover layer is made of crystalline, polycrystalline, or amorphous silicon. In one or more of the preceding or following embodiments, the cover layer contains fluorine. In one or more of the preceding or following embodiments, a second curing process is carried out before the cover layer is formed and after the shielding layer has been formed. In one or more of the preceding or following embodiments, the curing temperature of the first curing process is higher than the curing temperature of the second curing process.In one or more of the preceding or following embodiments, the curing temperature of the first curing process is in the range of 900 °C to 1300 °C. In one or more of the preceding or following embodiments, the curing temperature of the second curing process is in the range of 600 °C to 800 °C. In one or more of the preceding or following embodiments, after the cover layer has been removed, the shielding layer is removed. In one or more of the preceding or following embodiments, after the shielding layer has been removed, an additional metal nitride layer, made of the same material as the first conductive metal nitride layer, is formed over the metal nitride layer.

[0085] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shielding layer is formed over the first conductive layer, a first curing process is carried out after the shielding layer has been formed, a fluorine impregnation process is carried out, a cover layer is formed over the shielding layer, a second curing process is carried out after the cover layer has been formed, the cover layer is removed after the second curing process, and a gate electrode layer is formed after the cover layer has been removed. In one or more of the foregoing or following embodiments, the first conductive layer is made of TiN.In one or more of the preceding or following embodiments, the shielding layer is made of a material consisting of SiN, Ti, TiSi, Si. x Ti y N z , where 0 ≤ x < 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1 and x+y+z=1. In one or more of the preceding or following embodiments, the curing temperature of the first curing process is lower than the curing temperature of the second curing process. In one or more of the preceding or following embodiments, the curing temperature of the first curing process is in the range of 600 °C to 800 °C, and the curing temperature of the second curing process is in the range of 900 °C to 1300 °C.

[0086] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shielding layer is formed over the first conductive layer, a first curing process is carried out after the shielding layer has been formed, a cover layer is formed over the shielding layer, a second curing process is carried out after the cover layer has been formed, the cover layer and the shielding layer are removed after the second curing process, and a gate electrode layer is formed after the cover layer has been removed.

[0087] According to another aspect of the present disclosure, a semiconductor device comprises a channel layer, a gate dielectric layer arranged over the channel layer, a metal nitride layer arranged over the gate dielectric layer, a shielding layer arranged over the metal nitride layer, and a gate electrode layer arranged over the shielding layer. The metal nitride layer is made of TiN, and the shielding layer is made of a material selected from the group consisting of Si x N y (where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.25 ≤ x < 0.99, 0.01 ≤ y ≤ 0.75 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Tiy N z (where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1). In one or more of the preceding or following embodiments, a thickness satisfies T1 the metal nitride layer and a thickness T2The thickness of the shielding layer is 0.05 ≤ T2 / (T1+T2) < 0.85. In one or more of the preceding or following embodiments, the thickness of the metal nitride layer is in the range of 0.3 nm to 30 nm. In one or more of the preceding or following embodiments, the thickness of the shielding layer is in the range of 0.5 nm to 30 nm. In one or more of the preceding and following embodiments, the shielding layer contains fluorine in an amount of 0.02 atomic percent to 75 atomic percent. In one or more of the preceding and following embodiments, the metal nitride layer contains fluorine in an amount of 0.02 atomic percent to 55 atomic percent. In one or more of the preceding and following embodiments, the gate dielectric layer contains fluorine in an amount of approximately 0.01 atomic percent to 40 atomic percent. In one or more of the preceding or following embodiments, the shielding layer is made of SiN.

[0088] According to another aspect of the present disclosure, a semiconductor device comprises a channel layer, a gate dielectric layer arranged above the channel layer, a metal nitride layer arranged above the gate dielectric layer, and a gate electrode layer arranged above the metal nitride layer. The metal nitride layer is made of TiN, and the metal nitride layer and the gate dielectric layer contain fluorine. In one or more of the foregoing and following embodiments, the amount of fluorine in the gate dielectric layer is less than the amount of fluorine in the metal nitride layer. In one or more of the foregoing and following embodiments, the metal nitride layer contains fluorine in an amount of 0.02 atomic percent to 55 atomic percent. In one or more of the foregoing and following embodiments, the gate dielectric layer contains fluorine in an amount of approximately 0.01 atomic percent to 40 atomic percent.In one or more of the preceding or following embodiments, the thickness of the metal nitride layer is in the range of 0.3 nm to 30 nm. In one or more of the preceding or following embodiments, the semiconductor device has gate sidewall spacers made of a silicon-based insulating material containing fluorine.

[0089] According to another aspect of the present disclosure, a semiconductor device has a fin structure comprising: a channel layer, an insulating layer, a gate dielectric layer arranged above the channel layer, a metal nitride layer arranged above the gate dielectric layer, a shielding layer arranged above the metal nitride layer, and a gate electrode layer arranged above the shielding layer. The metal nitride layer is made of TiN, and the shielding layer is made of a material selected from the group consisting of Si, Si x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y(where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7, and x+y+z=1). In one or more of the preceding or following embodiments, a thickness satisfies T1 the metal nitride layer and a thickness T2The shielding layer 0.05 ≤ T2 / (T1+T2) < 0.85. In one or more of the preceding or following embodiments, the metal nitride layer, the shielding layer, and the gate dielectric layer contain fluorine, and the amount of fluorine in the gate dielectric layer is less than the amount of fluorine in the metal nitride layer and the amount of fluorine in the shielding layer. In one or more of the preceding and following embodiments, the shielding layer contains fluorine in an amount of 0.02 atomic percent to 75 atomic percent. In one or more of the preceding and following embodiments, the metal nitride layer contains fluorine in an amount of 0.02 atomic percent to 55 atomic percent. In one or more of the preceding and following embodiments, the gate dielectric layer contains fluorine in an amount of approximately 0.01 atomic percent to 40 atomic percent.

[0090] According to one aspect of the present disclosure, in a method for manufacturing a semiconductor device, an interface layer is formed over a channel region, a gate dielectric layer is formed over the interface layer, a first conductive layer is formed over the gate dielectric layer, a shielding layer is formed over the first conductive layer, a cover layer is formed over the shielding layer, a first curing process is carried out after the cover layer has been formed, the cover layer is removed after the first curing process, a second conductive layer as a barrier layer and a gate electrode layer are formed over the shielding layer after the cover layer has been removed.In one or more of the preceding or following embodiments, the first conductive layer is made of TiN, and the thickness of the first conductive layer is in the range of 0.3 nm to 30 nm. In one or more of the preceding or following embodiments, the shielding layer is made of a material selected from the group consisting of Si. x N y (where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.25 ≤ x < 0.99, 0.01 ≤ y ≤ 0.75 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z(where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1). In one or more of the preceding or following embodiments, the shielding layer is formed without interrupting the vacuum after the formation of the first conductive layer. In one or more of the preceding or following embodiments, the shielding layer is formed using an ALD and a CVD process at a temperature in the range of 250 °C to 600 °C and at a pressure in the range of 1 Torr to 150 Torr. In one or more of the preceding or following embodiments, the thickness of the shielding layer is in the range of 0.5 nm to 30 nm, and wherein a thickness T1 the metal nitride layer and a thickness T2The shielding layer must meet the requirements of 0.05 ≤ T2 / (T1+T2) < 0.85. In one or more of the preceding or following embodiments, the cover layer is made of crystalline, polycrystalline, or amorphous silicon. In one or more of the preceding or following embodiments, the cover layer contains fluorine. In one or more of the preceding or following embodiments, a second curing process is carried out before the cover layer is formed and after the shielding layer has been formed. In one or more of the preceding or following embodiments, the curing temperature of the first curing process is higher than the curing temperature of the second curing process, wherein the curing temperature of the first curing process is in the range of 900 °C to 1300 °C, and the curing temperature of the second curing process is in the range of 600 °C to 800 °C.In one or more of the preceding or following embodiments, the shielding layer is made of a material consisting of Si, Si. x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1, and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z(where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7, and x+y+z=1). In one or more of the preceding or following embodiments, the shielding layer is removed after the cover layer has been removed. In one or more of the preceding or following embodiments, a second curing process is carried out before the cover layer is formed and after the shielding layer has been formed. In one or more of the preceding or following embodiments, the second curing process is carried out in a temperature range of 450 °C to 850 °C. In one or more of the preceding or following embodiments, the shielding layer is removed after the second curing process and before the cover layer is formed.In one or more of the preceding or following embodiments, after the shielding layer has been removed, an additional metal nitride layer, made of the same material as the metal nitride layer, is formed over the metal nitride layer.

[0091] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shielding layer is formed over the first conductive layer, a first curing process is carried out after the shielding layer has been formed, a fluorine impregnation process is carried out, a cover layer is formed over the shielding layer, a second curing process is carried out after the cover layer has been formed, the cover layer is removed after the second curing process, the shielding layer is removed after the cover layer has been removed, and a second conductive layer as a barrier layer and a gate electrode layer are formed over the first conductive layer.In one or more of the foregoing or following embodiments, the shielding layer is made from a material selected from the group consisting of Si, Si. x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7, and x+y=1), Ti, Ti x C y (where 0.9 ≤x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z(where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7, and x+y+z=1). In one or more of the preceding or following embodiments, after the shielding layer has been removed, a third curing process is carried out at a temperature range of 450 °C to 850 °C. In one or more of the preceding or following embodiments, after the shielding layer has been removed, an additional metal nitride layer, made of the same material as the metal nitride layer, is formed over the metal nitride layer.

[0092] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shielding layer is formed over the first conductive layer, a first curing process is carried out after the shielding layer has been formed, a fluorine impregnation process is carried out, the shielding layer is removed, a cover layer is formed over the first conductive layer, a second curing process is carried out after the cover layer has been formed, the cover layer is removed after the second curing process, and a second conductive layer as a barrier layer and a gate electrode layer are formed over the first conductive layer.In one or more of the foregoing or following embodiments, the shielding layer is made from a material selected from the group consisting of Si, Si. x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7, and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7, and x+y=1) and Si x Ti y N z(where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7, and x+y+z=1). In one or more of the preceding or following embodiments, after the shielding layer has been removed, an additional metal nitride layer, made of the same material as the metal nitride layer, is formed over the metal nitride layer.

[0093] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shielding layer is formed over the first conductive layer, a first curing process is carried out after the shielding layer has been formed, a fluorine impregnation process is carried out, a cover layer is formed over the shielding layer, a second curing process is carried out after the cover layer has been formed, the cover layer is removed after the second curing process, and a gate electrode layer is formed over the gate dielectric layer after the cover layer has been removed. In one or more of the preceding or following embodiments, the shielding layer is made of a material consisting of Si, Si x C y(where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1). In one or more of the preceding or following embodiments, the curing temperature of the first curing process is in the range of 600 °C to 800 °C, and the curing temperature of the second curing process is in the range of 900 °C to 1300 °C.

[0094] According to one aspect of the present disclosure, a semiconductor device comprises a channel layer, an interface layer, and a gate dielectric layer arranged above the channel layer; a metal nitride layer arranged above the gate dielectric layer; a shielding layer arranged above the metal nitride layer; and a barrier layer and a gate electrode layer arranged above the shielding layer. The metal nitride layer is made of a metal nitride, such as TiN, and the shielding layer is made of one selected from the group consisting of Si x N y (where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.25 ≤ x < 0.99, 0.01 ≤ y ≤ 0.75 and x+y=1), Ti x Ny (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z (where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1). In one or more of the preceding or following embodiments, the thickness of the metal nitride layer is in the range of 0.3 nm to 30 nm, the thickness of the shielding layer is in the range of 0.5 nm to 30 nm, and a thickness T1 the metal nitride layer and a thickness T2 The shielding layer must meet the requirements of 0.05 ≤ T2 / (T1+T2) < 0.85. In one or more of the preceding and following embodiments, the metal nitride layer contains oxygen in an amount of 1.5 atomic percent to 65 atomic percent. In one or more of the preceding and following embodiments, the gate dielectric layer contains aluminum in an amount of less than 0.05 atomic percent.

[0095] According to another aspect of the present disclosure, a semiconductor device comprises a channel layer, an interface layer, a gate dielectric layer arranged above the channel layer, a metal nitride layer arranged above the gate dielectric layer, and a barrier layer and a gate electrode layer arranged above the metal nitride layer. The metal nitride layer is made of TiN. In one or more of the preceding or following embodiments, the semiconductor device further comprises a mixed layer on an upper surface of the metal nitride layer, formed by depositing a shielding layer on the metal nitride layer and removing the shielding layer from the upper surface of the metal nitride layer. The shielding layer used is one selected from the group consisting of Si, Si x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x Cl y(where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7, and x+y+z=1). In one or more of the preceding and following embodiments, the gate dielectric layer comprises aluminum in an amount of approximately 0.1% to 6% atomic percent.

[0096] According to another aspect of the present disclosure, a semiconductor device comprises a channel layer, an interface layer arranged above the channel layer, a gate dielectric layer arranged above the interface layer, a metal nitride layer arranged above the gate dielectric layer, a shielding layer arranged above the metal nitride layer, a barrier layer arranged above the shielding layer, and a gate electrode layer arranged above the barrier layer. The metal nitride layer is made of TiN, and the shielding layer is made of a material selected from the group consisting of Si x N y (where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y(where 0.25 ≤ x < 0.99, 0.01 ≤ y ≤ 0.75 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Si x Ti y N z (where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1). In one or more of the preceding or following embodiments, the thickness of the metal nitride layer is in the range of 0.3 nm to 30 nm, the thickness of the shielding layer is in the range of 0.5 nm to 30 nm, and a thickness T1 the metal nitride layer and a thickness T2The shielding layer must meet the requirements of 0.05 ≤ T2 / (T1+T2) < 0.85. In one or more of the preceding or following embodiments, the shielding layer is partially crystalline or completely amorphous, and the percentage of crystallinity of the shielding layer is in the range of 0% to 90%. In one or more of the preceding or following embodiments, the metal nitride layer, the shielding layer, and the gate dielectric layer contain fluorine, and the amount of fluorine in the gate dielectric layer is less than the amount of fluorine in the metal nitride layer and the amount of fluorine in the shielding layer. In one or more of the foregoing or following embodiments, the shielding layer contains fluorine in an amount of 0.02 atomic% to 75 atomic%, the metal nitride layer contains fluorine in an amount of 0.02 atomic% to 55 atomic%, and the gate dielectric layer contains fluorine in an amount of 0.01 atomic% to 40 atomic%.In one or more of the preceding or following embodiments, the semiconductor device further comprises gate sidewall spacers made of a silicon-based insulating material containing fluorine. In one or more of the preceding and following embodiments, the shielding layer, the metal nitride layer, and the gate dielectric layer contain no fluorine or contain fluorine in an amount of less than 0.6 atomic percent. In one or more of the preceding or following embodiments, the shielding layer is made of SiN. In one or more of the preceding and following embodiments, the metal nitride layer contains oxygen in an amount of 1.5 to 65 atomic percent.In one or more of the preceding or following embodiments, the metal nitride layer contains a ratio of titanium atoms bonded to oxygen (Ti-O) to titanium atoms bonded to nitrogen (Ti-N) in the range of 0.03 to 0.48. In one or more of the preceding and following embodiments, the gate dielectric layer contains aluminum in an amount of less than 0.05 atomic percent.

[0097] According to another aspect of the present disclosure, a semiconductor device comprises a channel layer, an interface layer arranged above the channel layer, a gate dielectric layer arranged above the interface layer, a metal nitride layer arranged above the gate dielectric layer, a barrier layer arranged above the metal nitride layer, and a gate electrode layer arranged above the barrier layer. The metal nitride layer is made of TiN. In one or more of the preceding or following embodiments, the semiconductor device further comprises a mixed layer on an upper surface of the metal nitride layer, formed by depositing a shielding layer on the metal nitride layer and removing the shielding layer from the upper surface of the metal nitride layer. The shielding layer is one selected from the group consisting of Si, Si x C y, Si x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y , Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z(where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7, and x+y+z=1). In one or more of the preceding or following embodiments, the metal nitride layer, the shielding layer, and the gate dielectric layer contain fluorine, and the amount of fluorine in the gate dielectric layer is less than the amount of fluorine in the metal nitride layer. In one or more of the preceding or following embodiments, the metal nitride layer contains fluorine in an amount of 0.02 atomic% to 55 atomic%, and the gate dielectric layer contains fluorine in an amount of 0.01 atomic% to 40 atomic%. In one or more of the preceding or following embodiments, the thickness of the metal nitride layer is in the range of 0.3 nm to 30 nm. In one or more of the preceding and following embodiments, the metal nitride layer contains oxygen in an amount of 1.5 atomic percent to 65 atomic percent.In one or more of the preceding or following embodiments, the metal nitride layer has a ratio of titanium atoms bonded to oxygen to titanium atoms bonded to nitrogen in the range of 0.03 to 0.48. In one or more of the preceding and following embodiments, the gate dielectric layer contains aluminum in an amount of approximately 0.1% to 65 atomic percent. In one or more of the preceding or following embodiments, the semiconductor device further comprises gate sidewall spacers made of a silicon-based insulating material containing fluorine. In one or more of the preceding and following embodiments, the shielding layer, the metal nitride layer, and the gate dielectric layer contain no fluorine or contain fluorine in an amount of less than 0.6 atomic percent.

[0098] The foregoing outlines features of several embodiments or examples so that a person skilled in the art may better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing and modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments or examples presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62753033

[0001]

Claims

[1] Method for manufacturing a semiconductor device, comprising: Formation of a boundary layer over a canal area, Formation of a gate dielectric layer above the interface layer, Formation of a first conductive layer above the gate dielectric layer, Forming a shielding layer over the first conductive layer, Forming a cover layer over the shielding layer, Performing an initial healing process after the covering layer has formed, Removing the covering layer after the initial healing process, and Formation of a gate electrode layer over the gate dielectric layer after the cover layer has been removed. [2] Method according to claim 1, wherein the first conductive layer is made of a metal nitride, and The thickness of the first conductive layer is in the range of 0.3 nm to 30 nm. [3] Method according to claim 1 or 2, wherein the shielding layer is made from a material selected from the group consisting of Si x N y (where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.25 ≤ x < 0.99, 0.01 ≤ y ≤ 0.75 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z (where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1) exists. [4] Method according to any one of the preceding claims, wherein: a thickness Ti of the first conductive layer and a thickness T2 of the shielding layer must meet 0.05 ≤ T2 / (T1+T2) < 0.85, and The thickness T2 of the shielding layer lies in a range of 0.5 nm to 30 nm. [5] Method according to any of the preceding claims, wherein the cover layer is made of crystalline, polycrystalline or amorphous silicon. [6] Method according to claim 5, wherein the covering layer contains fluorine. [7] Method according to any of the preceding claims, further comprising carrying out a second curing process before the cover layer is formed and after the shielding layer has been formed. [8] Method according to claim 7, wherein a healing temperature of the first healing process is higher than a healing temperature of the second healing process. [9] Method according to any one of the preceding claims, wherein the shielding layer is made of Si x Ti y N z is manufactured where 0 ≤ x < 1, 0 ≤ y ≤ 1 and 0 ≤ z ≤ 0.

7. [10] The method of claim 9, further comprising, after the covering layer has been removed, the removal of the shielding layer. [11] Method claim 9 or 10, further comprising carrying out a second curing process before the cover layer is formed and after the shielding layer has been formed. [12] Method according to claim 10, wherein, after the shielding layer has been removed, an additional metal nitride layer, made of the same material as the metal nitride layer, is formed over the metal nitride layer. [13] Method for manufacturing a semiconductor device, comprising: Formation of a gate dielectric layer over a channel region, Formation of a first conductive layer above the gate dielectric layer, Forming a shielding layer over the first conductive layer, Performing an initial healing process after the shielding layer has formed, Performing a fluoride impregnation process, Forming a cover layer over the shielding layer, Performing a second healing process after the covering layer has formed, Removing the covering layer after the second healing process, and Formation of a gate electrode layer over the gate dielectric layer after the cover layer has been removed, the shielding layer is removed after the first healing process. [14] Method according to claim 13, wherein the first conductive layer is made of TiN. [15] Method according to claim 13 or 14, wherein the shielding layer is made from a material selected from the group consisting of Si, Si x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x Cl y(where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Si x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z (where 0.01 ≤ x < 0.99, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1) exists. [16] Method according to any one of the preceding claims 13 to 15, wherein: the healing temperature of the first healing process is in a range of 600 °C to 800 °C, and The healing temperature of the second healing process lies in a range of 900 °C to 1300 °C. [17] Semiconductor device comprising: a channel layer a gate dielectric layer positioned above the channel layer, a metal nitride layer positioned above the gate dielectric layer, a shielding layer arranged over the metal nitride layer, a gate electrode layer comprising one or more work function setting layers and one or more body metal gate electrode layers, arranged above the shielding layer, wherein the metal nitride layer is made of TiN, and the shielding layer is made from one selected from the group consisting of Si x N y (where 0.3 ≤ x < 0.75, 0.25 ≤ y ≤ 0.7 and x+y=1), Ti, Ti x C y (where 0.9 ≤x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), Ti x Cl y (where 0.9 ≤ x < 0.99, 0.01 ≤ y ≤ 0.1 and x+y=1), titanium silicide, Ti x Si y(where 0.25 ≤ x < 0.99, 0.01 ≤ y ≤ 0.75 and x+y=1), Ti x N y (where 0.3 ≤ x < 0.99, 0.01 ≤ y ≤ 0.7 and x+y=1) and Si x Ti y N z (where 0.01 ≤ x < 0.75, 0.01 ≤ y ≤ 0.99, 0.01 ≤ y ≤ 0.7 and x+y+z=1) exists. [18] Semiconductor device according to claim 17, wherein the shielding layer contains fluorine in an amount of 0.02 atomic % to 75 atomic %. [19] Semiconductor device according to claim 18, wherein the metal nitride layer contains fluorine in an amount of 0.02 atomic % to 55 atomic %. [20] Semiconductor device according to claim 19, wherein the gate dielectric layer contains fluorine in an amount of 0.01 atomic % to 40 atomic % and the gate dielectric layer contains aluminum in an amount of less than 0.05 atomic %.