Package substrate, package substrate design method and related equipment

Abstract

The present invention provides a packaging substrate, a packaging substrate design method and related equipment. The packaging substrate includes a substrate body, the substrate body includes a plurality of conductive layers stacked, the conductive layers located on opposite sides of the substrate body respectively have a plurality of first solder pads and a plurality of second solder pads, each second solder pad is connected to a solder ball, the first solder pad is used to electrically connect to a bare chip, and the second solder pad is used to electrically connect to a power supply device. Since a power supply path includes at least a solder ball, a second solder pad electrically connected to the solder ball, a via electrically connecting the second solder pad and a wire, a wire, a via electrically connecting the wire and the first solder pad, and the first solder pad, and in the process of the power supply device supplying power to the bare chip through a plurality of power supply paths, the magnitude of current flowing through the solder balls corresponding to any two power supply paths is the same, therefore, it is possible to avoid excessive current flowing through some solder balls causing the solder balls to melt, thereby avoiding the problem of poor contact such as short circuit of the solder balls.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a packaging substrate, a packaging substrate design method and related equipment. Background Art

[0002] With the emergence of advanced technologies such as autonomous driving and artificial intelligence, people's demand for server computing power has increased exponentially, which requires server chips to integrate more cores to meet the computing needs of the market. However, as chip computing performance improves, chips are more likely to have poor contact problems such as partial solder ball short circuits, which affects the working performance of the chip. Summary of the invention

[0003] In view of this, the present invention is dedicated to providing a packaging substrate, a packaging substrate design method and related equipment to solve the problem of poor contact such as short circuit of some solder balls of the chip.

[0004] In a first aspect, the present invention discloses a packaging substrate, comprising a substrate body; the substrate body comprises a plurality of conductive layers stacked and an insulating layer located between two adjacent conductive layers;

[0005] The conductive layers located on opposite sides of the substrate body respectively have a plurality of first pads and a plurality of second pads, each of the second pads is connected to a solder ball; the conductive layer located in the middle of the substrate body includes a plurality of wires, and the wires located in different conductive layers are electrically connected through vias penetrating the insulating layer between the two;

[0006] The first pad is used to be electrically connected to the bare die; the second pad is used to be electrically connected to the power supply device through the solder ball; the power supply device supplies power to the bare die through multiple power supply paths; one power supply path at least includes a solder ball, a second pad electrically connected to the solder ball, a via electrically connecting the second pad and at least one wire, the at least one wire, a via electrically connecting multiple wires in the at least one wire, a via electrically connecting the at least one wire and a first pad, and the first pad;

[0007] In the process of the power supply device supplying power to the bare chip through the multiple power supply paths, the currents flowing through the solder balls corresponding to any two power supply paths are the same, so as to avoid excessive current flowing through some solder balls causing the solder balls to melt, thereby avoiding problems such as short circuits in the solder balls and other poor contact problems.

[0008] Optionally, in the process of the power supply device supplying power to the bare chip through the multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and / or the currents flowing through any two power supply paths are the same, so that in the process of the power supply device supplying power to the bare chip through the multiple power supply paths, the currents flowing through the solder balls corresponding to any two power supply paths are the same.

[0009] Optionally, the packaging substrate and the power supply device are arranged on a printed circuit board, the power supply device is electrically connected to the packaging substrate through the printed circuit board, and the power supply device is located on the other side of the packaging substrate away from the bare chip;

[0010] Each of the power supply paths includes a first sub-path, which includes a solder ball, a second solder pad, a wire, a via and a first solder pad located in the packaging substrate; and the impedance of the first sub-path where the solder ball close to the power supply device is located is greater than the impedance of the first sub-path where the solder ball far from the power supply device is located, so that in the process of the power supply device supplying power to the bare chip through the multiple power supply paths, the current flowing through the solder balls corresponding to any two power supply paths is the same.

[0011] Optionally, the packaging substrate satisfies at least one of the following conditions:

[0012] The density of solder balls in the region where the first sub-path close to the power supply device is located is greater than the density of solder balls in the region where the first sub-path far from the power supply device is located;

[0013] The total area of ​​the wires in the first sub-path close to the power supply device is smaller than the total area of ​​the wires in the first sub-path far from the power supply device;

[0014] The number of vias in the first sub-path close to the power supply device is less than the number of vias in the first sub-path away from the power supply device; so that when the power supply device supplies power to the bare chip through the multiple power supply paths, the current flowing through the solder balls corresponding to any two power supply paths is the same.

[0015] Optionally, in the direction from the second solder pad to the first solder pad, the areas of the multiple conductive layers increase successively, and the multiple conductive layers all overlap in a region far away from the power supply device, and the multiple conductive layers partially overlap in a region close to the power supply device, so that the total area of ​​the conductive wires in the first sub-path close to the power supply device is smaller than the total area of ​​the conductive wires in the first sub-path far away from the power supply device.

[0016] In a second aspect, the present invention discloses a chip, comprising a packaging substrate as described in any one of the above items and a bare chip, wherein the bare chip is electrically connected to a first pad of the packaging substrate.

[0017] In a third aspect, the present invention discloses an integrated circuit system, comprising a printed circuit board, a power supply device and the above-mentioned chip, wherein the chip and the power supply device are mounted on the printed circuit board, and the power supply device supplies power to the chip through the printed circuit board.

[0018] In a fourth aspect, the present invention discloses an electronic device, comprising the integrated circuit system as described above.

[0019] In a fifth aspect, the present invention discloses a packaging substrate design method, including the packaging substrate including a substrate body, the substrate body including a plurality of conductive layers stacked and an insulating layer located between two adjacent conductive layers, the conductive layers located on opposite sides of the substrate body respectively having a plurality of first pads and a plurality of second pads, each of the second pads being connected to a solder ball, the first pads being used to be electrically connected to a bare chip, the second pads being used to be electrically connected to a power supply device, the conductive layer located in the middle of the substrate body including a plurality of conductive wires, the conductive wires located in different conductive layers being electrically connected through vias penetrating the insulating layer therebetween, the packaging substrate design method comprising:

[0020] Determine a structure of a plurality of power supply paths, the power supply device supplies power to the bare die through the plurality of power supply paths, one power supply path at least comprising a solder ball, a second pad electrically connected to the solder ball, a via electrically connecting the second pad and at least one wire, the at least one wire, a via electrically connecting a plurality of wires in the at least one wire, a via electrically connecting the at least one wire and a first pad, and the first pad;

[0021] Adjust the structural parameters of at least one of the solder balls, pads, wires and vias in any of the power supply paths so that, in the process of the power supply device supplying power to the bare chip through the multiple power supply circuits, the currents flowing through the solder balls corresponding to any two power supply paths are the same, so as to avoid excessive current flowing through some solder balls causing the solder balls to melt, thereby avoiding problems such as short circuits in the solder balls and other poor contact.

[0022] Optionally, in the process of the power supply device supplying power to the bare chip through the multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and / or the currents flowing through any two power supply paths are the same, so that in the process of the power supply device supplying power to the bare chip through the multiple power supply paths, the currents flowing through the solder balls corresponding to any two power supply paths are the same.

[0023] Optionally, the packaging substrate and the power supply device are arranged on a printed circuit board, the power supply device is electrically connected to the packaging substrate through the printed circuit board, and the power supply device is located on a side of the packaging substrate away from the bare chip, each of the power supply paths includes a first sub-path, and the first sub-path includes a solder ball, a second solder pad, a wire, a via and a first solder pad located in the packaging substrate, then the adjusting of the structural parameters of at least one of the solder ball, the solder pad, the wire and the via in any of the power supply paths includes:

[0024] Adjust at least one of the position of the solder ball, the area of ​​the wire and the number of vias in any of the power supply paths so that the impedance of the first sub-path where the solder ball close to the power supply device is located is greater than the impedance of the first sub-path where the solder ball close to the bare chip is located, so that when the power supply device supplies power to the bare chip through the multiple power supply paths, the currents flowing through the solder balls corresponding to any two power supply paths are the same.

[0025] Optionally, adjusting the position of the solder balls in any of the power supply paths includes: making the density of the solder balls in the region where the first sub-path close to the power supply device is located greater than the density of the solder balls in the region where the first sub-path far from the power supply device is located;

[0026] Adjusting the area of ​​the wires in any of the power supply paths includes: making the total area of ​​the wires in a first sub-path close to the power supply device smaller than the total area of ​​the wires in a first sub-path far from the power supply device;

[0027] Adjusting the number of vias in any of the power supply paths includes: making the number of vias in a first sub-path close to the power supply device smaller than the number of vias in a first sub-path far from the power supply device;

[0028] Therefore, when the power supply device supplies power to the bare chip through the multiple power supply paths, the magnitude of current flowing through the solder balls corresponding to any two power supply paths is the same.

[0029] Optionally, making the total area of ​​the wires in the first sub-path where the solder ball close to the power supply device is located smaller than the total area of ​​the wires in the first sub-path where the solder ball close to the bare chip is located comprises:

[0030] The areas of the multiple conductive layers increase sequentially in the direction from the second pad to the first pad, and the multiple conductive layers overlap in the area close to the bare chip and partially overlap in the area close to the power supply device, so that the total area of ​​the conductive wires in the first sub-path close to the power supply device is smaller than the total area of ​​the conductive wires in the first sub-path away from the power supply device.

[0031] Optionally, the structure for determining multiple power supply paths includes:

[0032] Determining structural information of the packaging substrate based on the design information of the packaging substrate;

[0033] Based on the structural information of the packaging substrate, structures of multiple power supply paths are determined.

[0034] In a sixth aspect, the present invention discloses a computer device, characterized in that it includes a memory and a processor;

[0035] The memory is used to store instructions;

[0036] The processor is used to execute the packaging substrate design method as described in any one of the above items according to the instructions stored in the memory.

[0037] In a seventh aspect, the present invention discloses a computer-readable storage medium, characterized in that instructions for executing the packaging substrate design method as described in any one of the above items are stored thereon.

[0038] The present invention provides a packaging substrate, a packaging substrate design method and related equipment. The packaging substrate includes a substrate body, the substrate body includes a plurality of conductive layers stacked and an insulating layer located between two adjacent conductive layers, the conductive layers located on opposite sides of the substrate body respectively have a plurality of first pads and a plurality of second pads, each second pad is connected to a solder ball, the first pad is used to electrically connect to a bare chip, and the second pad is used to electrically connect to a power supply device. Since a power supply path includes at least a solder ball, a second pad electrically connected to a solder ball, a via electrically connecting a second pad to at least one wire, at least one wire, a via electrically connecting a plurality of wires in at least one wire, a via electrically connecting at least one wire to a first pad and a first pad, and in the process of the power supply device supplying power to the bare chip through a plurality of power supply paths, the currents flowing through the solder balls corresponding to any two power supply paths are the same, therefore, it is possible to avoid the solder balls being burned due to excessive current flowing through some solder balls, thereby avoiding the problem of poor contact such as short circuit of the solder balls. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0040] Figure 1 The present invention is a schematic diagram of a cross-sectional structure of a packaging substrate disclosed in an embodiment of the present invention.

[0041] Figure 2This is a schematic diagram of the planar structure of a first conductive layer disclosed in an embodiment of the present invention.

[0042] Figure 3 It is a schematic diagram of the planar structure of a sixth conductive layer disclosed in an embodiment of the present invention.

[0043] Figure 4 It is a schematic diagram of the planar structure of a second conductive layer disclosed in an embodiment of the present invention.

[0044] Figure 5 The present invention is a schematic diagram of a cross-sectional structure of a packaging substrate, a bare chip and a power supply device disclosed in an embodiment of the present invention.

[0045] Figure 6 The present invention is a top view schematic diagram of a packaging substrate, a bare chip and a power supply device disclosed in an embodiment of the present invention.

[0046] Figure 7 The present invention is a top view schematic diagram of another packaging substrate, a bare chip and a power supply device disclosed in an embodiment of the present invention.

[0047] Figure 8 It is a schematic diagram of the planar structure of multiple solder balls disclosed in an embodiment of the present invention.

[0048] Fig. 9 A schematic diagram of the planar structure of another packaging substrate disclosed in an embodiment of the present invention.

[0049] Fig.10 for Fig. 9 A schematic diagram of the cross-sectional structure of the packaging substrate shown.

[0050] Fig.11 A schematic diagram of the planar structure of another packaging substrate disclosed in an embodiment of the present invention.

[0051] Fig.12 The cross-sectional structure diagram of another bare chip, packaging substrate and power supply device disclosed in an embodiment of the present invention.

[0052] Fig.13 The figure is a schematic diagram of the cross-sectional structure of a chip disclosed in an embodiment of the present invention.

[0053] Fig.14 A schematic diagram of the structure of an integrated circuit system disclosed in an embodiment of the present invention.

[0054] Fig.15 The present invention discloses a flow chart of a packaging substrate design method.

[0055] Fig.16 The present invention is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present invention will be described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] As the computing performance of chips improves, the power consumption of chips is constantly increasing, and the power supply current of chips is also increasing. The inventors have found that although the solder balls in the chip are evenly distributed, the currents flowing through different solder balls are not the same. When the chip power supply current continues to increase, it is easy to cause the current flowing through some solder balls to be too large, causing these solder balls to melt, and then causing these solder balls to have short circuits and other poor contact problems.

[0058] Based on this, the present invention discloses a packaging substrate, which makes the currents flowing through the solder balls corresponding to the multiple power supply paths from the power supply device to the bare chip of the packaging substrate the same, so as to avoid excessive current flowing through some solder balls and causing the solder balls to melt, thereby avoiding problems such as short circuit and other poor contact of the solder balls.

[0059] As an optional implementation of the contents disclosed in the present invention, an embodiment of the present invention discloses a packaging substrate, which includes a substrate body, wherein the substrate body includes a plurality of conductive layers stacked together, and an insulating layer located between two adjacent conductive layers.

[0060] like Figure 1 As shown, Figure 1 This is a schematic diagram of the cross-sectional structure of a packaging substrate disclosed in an embodiment of the present invention. The substrate body includes a first conductive layer L1 to a sixth conductive layer L6, and a first insulating layer R1 to a fifth insulating layer R5. The first insulating layer R1 to the fifth insulating layer R5 are respectively located between the first conductive layer L1 to the sixth conductive layer L6.

[0061] It should be noted that in the embodiment of the present invention, only the substrate body including six conductive layers is used for illustration, but it is not limited to this. In other embodiments, the substrate body of the packaging substrate can also include three, four, five or even more conductive layers, which will not be repeated here.

[0062] In the embodiment of the present invention, the conductive layers located on opposite sides of the substrate body respectively have a plurality of first pads and a plurality of second pads, and each second pad is connected to a solder ball. Figure 1As shown, the first conductive layer L1 and the sixth conductive layer L6 are respectively located on opposite sides of the substrate body, and the first conductive layer L1 has a plurality of first pads H1, and the sixth conductive layer L6 has a plurality of second pads H2, each of which is connected to a solder ball H3.

[0063] like Figure 2 As shown, Figure 2 This is a schematic diagram of a planar structure of a first conductive layer disclosed in an embodiment of the present invention. The plurality of first pads H1 may be a plurality of square pads arranged in an array. Of course, in other embodiments, the plurality of first pads H1 may also be a plurality of circular pads arranged in an array or a plurality of strip pads arranged in parallel, etc., which will not be described in detail here.

[0064] like Figure 3 As shown, Figure 3 This is a schematic diagram of a planar structure of a sixth conductive layer disclosed in an embodiment of the present invention. The plurality of second pads H2 may be a plurality of square pads arranged in an array, and the central area of ​​each square pad has a solder ball H3. Of course, in other embodiments, the plurality of second pads H2 may also be a plurality of circular pads arranged in an array or a plurality of strip pads arranged in parallel, etc., which will not be described in detail here.

[0065] It can be understood that the solder balls H3 in the embodiment of the present invention are made of solder or the like, and a plurality of solder balls H3 arranged in an array constitute a ball grid array (BGA for short), through which the package substrate can be loaded and connected to a printed circuit board.

[0066] The first pad H1 and the second pad H2 in the embodiment of the present invention are both power pads. The package substrate in the embodiment of the present invention includes not only power pads, but also ground pads and signal pads. Figure 2 In the structure shown, the third pad H4 may be a ground pad, and the other pads may be signal pads. Figure 3 In the structure shown, the fourth pad H5 may be a ground pad, and the other pads may be signal pads. Figure 2 and Figure 3 Only one pad layout is used as an example for explanation, and the present invention is not limited to this.

[0067] In an embodiment of the present invention, the conductive layer located in the middle of the substrate body includes multiple conductive wires, and the conductive wires located in different conductive layers are electrically connected through vias penetrating the insulating layer therebetween, and the pads and conductive wires are also electrically connected through vias penetrating the insulating layer therebetween.

[0068] like Figure 1As shown, the second conductive layer L2 to the fifth conductive layer L5 are located in the middle of the substrate body, and the conductive wires of two adjacent conductive layers in the second conductive layer L2 to the fifth conductive layer L5 are electrically connected through a via G penetrating the insulating layer therebetween, the first pad H1 is electrically connected to the conductive wire of the second conductive layer L2 through the via G penetrating the first insulating layer R1, and the second pad H2 is electrically connected to the conductive wire of the fifth conductive layer L5 through the via G penetrating the fifth insulating layer R5.

[0069] like Figure 4 As shown, Figure 4 Schematic diagram of a planar structure of a second conductive layer disclosed in an embodiment of the present invention, wherein a plurality of conductive wires D are arranged in parallel, and adjacent conductive wires D are insulated by an insulating layer. It can be understood that the structures of the third to fifth conductive layers may be the same as or different from the structure of the second conductive layer, for example, the shape, size, and position of the conductive wires may be different.

[0070] In the embodiment of the present invention, the first pad H1 is used to be electrically connected to the bare die (DIE), and the second pad H2 is used to be electrically connected to the power supply device through the solder ball H3, and the power supply device supplies power to the bare die through multiple power supply paths. Figure 1 The description only takes several power supply paths indicated by arrows as examples, but is not limited to these.

[0071] See also Figure 1 A power supply path includes at least one solder ball H3, a second solder pad H2 electrically connected to the solder ball H3, a via electrically connecting the second solder pad H2 and at least one wire, at least one wire, a via electrically connecting multiple wires in at least one wire, a via electrically connecting at least one wire and a first solder pad H1, and a first solder pad H1.

[0072] In other words, a power supply path includes at least one solder ball H3, a second solder pad H2, multiple vias, at least one wire and a first solder pad H1, wherein a solder ball H3 is electrically connected to a second solder pad H2, a second solder pad H2 is electrically connected to at least one wire through a via, multiple wires in at least one wire are electrically connected through vias, and at least one wire is electrically connected to a first solder pad H1 through a via.

[0073] In some optional examples, a power supply path includes at least a solder ball H3, a second solder pad H2 electrically connected to the solder ball H3, a via electrically connecting the second solder pad H2 and a wire in the fifth conductive layer L5, a wire in the fifth conductive layer L5, a via electrically connecting the wire in the fifth conductive layer L5 and a wire in the fourth conductive layer L4, a wire in the fourth conductive layer L4, a via electrically connecting the wire in the fourth conductive layer L4 and a wire in the third conductive layer L3, a wire in the third conductive layer L3, a via electrically connecting the wire in the third conductive layer L3 and a wire in the second conductive layer L2, a wire in the second conductive layer L2, a via electrically connecting the wire in the second conductive layer L2 and a first solder pad H1, and a first solder pad H1.

[0074] Of course, the present invention is not limited to this, and in other optional examples, a second pad H2 can also be electrically connected to a first pad H1 through wires in some conductive layers from the second conductive layer L2 to the fifth conductive layer L5, which will not be described in detail here. It can be understood that the structures of different power supply paths can be the same or different.

[0075] In the embodiment of the present invention, when the power supply device supplies power to the bare die through multiple power supply paths, the currents flowing through the solder balls H3 corresponding to any two power supply paths are the same. In other words, when the power supply device supplies power to the bare die through multiple power supply paths, the currents flowing through any two solder balls H3 corresponding to the multiple power supply paths are the same.

[0076] Based on this, it is possible to avoid excessive current flowing through the packaging substrate and some solder balls H3 of the chip including the packaging substrate, thereby preventing some solder balls H3 from melting due to excessive current, thereby preventing some solder balls H3 from short circuiting or other poor contact problems due to melting.

[0077] In some embodiments of the present invention, when the power supply device supplies power to the bare chip through multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and / or the currents flowing through any two power supply paths are the same, so that the currents flowing through the solder balls H3 corresponding to any two power supply paths are the same.

[0078] It is understandable that, although the power supply device outputs the same power supply voltage or current to multiple power supply paths, the impedances of the power supply paths are different, which results in different currents flowing through the power supply paths, and thus different currents flowing through the solder balls of the power supply paths. Based on this, in some optional examples, by making the impedances corresponding to any two power supply paths the same, the currents flowing through the solder balls H3 corresponding to any two power supply paths are made the same.

[0079] However, in actual applications, under the influence of factors such as manufacturing process and path division method, the same impedance corresponding to any two power supply paths does not necessarily make the current flowing through the solder balls H3 corresponding to any two power supply paths the same. Based on this, in other optional examples, the current flowing through any two power supply paths is made the same, so that the current flowing through the solder balls H3 corresponding to any two power supply paths is made the same.

[0080] Of course, in some other optional examples, the magnitude of the current flowing through the solder balls H3 corresponding to any two power supply paths may be made the same by making the impedances corresponding to any two power supply paths and the magnitude of the current flowing through the solder balls H3 corresponding to any two power supply paths the same.

[0081] In some embodiments of the present invention, Figure 5 As shown, Figure 5 It is a schematic diagram of the cross-sectional structure of a packaging substrate, a bare chip and a power supply device disclosed in an embodiment of the present invention. The packaging substrate 10 and the power supply device 30 are both arranged on a printed circuit board 40, the bare chip 20 is arranged on the packaging substrate 10, the power supply device 30 is located on one side of the packaging substrate 10, and different solder balls of the packaging substrate 10 have different distances from the power supply device 30.

[0082] In some optional examples, the die 20 is located on one side of the package substrate 10, and the power supply device 30 is located on the other side of the package substrate 10 away from the die 20. Figure 6 As shown, Figure 6 The schematic diagram of the top view of a package substrate, a bare chip and a power supply device disclosed in an embodiment of the present invention, the bare chip 20 is located on the left side of the package substrate 10, and the power supply device 30 is located on the right side of the package substrate 10 away from the bare chip 20. Of course, the present invention is not limited to this. In other embodiments, the bare chip 20 is located on one side of the package substrate 10, and the power supply device 30 is located on the other side of the package substrate 10. Figure 7 As shown, Figure 7 It is a schematic diagram of a top view of another packaging substrate, a bare chip and a power supply device disclosed in an embodiment of the present invention. The bare chip 20 is located on the left side of the packaging substrate 10, and the power supply device 30 is located on the upper side of the packaging substrate 10.

[0083] In the embodiment of the present invention, the structural parameters of the solder balls, pads, vias and wires in the packaging substrate 10 can be adjusted based on the positional relationship among the power supply device 30, the packaging substrate 10 and the bare chip 20, so that when the power supply device 30 supplies power to the bare chip 20 through multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and / or the currents flowing through any two power supply paths are the same, thereby making the currents passing through the solder balls corresponding to any two power supply paths the same.

[0084] In the embodiment of the present invention, Figure 5 As shown, the first pad H1 of the package substrate 10 is electrically connected to the bare die 20, the second pad H2 of the package substrate 10 is electrically connected to the power supply device 30 through the solder ball H3 and the printed circuit board 40, and the power supply device 30 supplies power to the bare die 20 through multiple power supply paths S. In some optional examples, each power supply path includes a first sub-path and a second sub-path, the first sub-path includes the solder ball H3, the second pad H2, the wire D, the via G and the first pad H1 located in the package substrate 10, and the second sub-path includes the pad, the wire and the via located in the printed circuit board 40.

[0085] Since the distances from different solder balls of the package substrate 10 to the power supply device 30 are different, the impedance of the second sub-path close to the power supply device 30 in different power supply paths is smaller than the impedance of the second sub-path far from the power supply device 30. Based on this, in some embodiments of the present invention, the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located is greater than the impedance of the first sub-path where the solder ball H3 far from the power supply device 30 is located, so that when the power supply device 30 supplies power to the bare die 20 through multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and / or the magnitudes of the currents flowing through any two power supply paths are the same, thereby making the magnitudes of the currents flowing through the solder balls corresponding to any two power supply paths the same.

[0086] It can be understood that the impedance of each power supply path is equal to the sum of the impedance of the first sub-path and the impedance of the second sub-path. Therefore, by adjusting the impedance of the solder ball H3, the second solder pad H2, the wire D, the via G and the first solder pad H1 in the first sub-path, the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located can be greater than the impedance of the first sub-path where the solder ball H3 far away from the power supply device 30 is located.

[0087] It should be noted that, in an embodiment of the present invention, multiple power supply paths can be divided according to the connection relationship between multiple first solder pads H1 and multiple second solder pads H2 in the packaging substrate. Among them, different power supply paths may include the same wire, or may respectively include different wires. In the case where different power supply paths include different wires, the impedance and current of different power supply paths can be calculated based on the impedance of the wires of different power supply paths. In the case where different power supply paths include the same wire, although multiple solder balls H3 are electrically connected to the same wire, each solder ball H3 conducts electricity or transmits current through a partial line segment of the wire closest to it. Therefore, in some optional examples, the wire can be divided into multiple line segments, and the multiple line segments can be made to belong to multiple power supply paths respectively to calculate the impedance and current of multiple power supply paths.

[0088] In some embodiments of the present invention, the packaging substrate 10 satisfies at least one of multiple conditions so that the current flowing through the solder balls H3 corresponding to any two power supply paths is the same, and the above multiple conditions include: the density of the solder balls H3 in the area where the first sub-path close to the power supply device 30 is located is greater than the density of the solder balls H3 in the area where the first sub-path away from the power supply device 30 is located; the total area of ​​the wires D in the first sub-path close to the power supply device 30 is smaller than the total area of ​​the wires D in the first sub-path away from the power supply device 30; the number of vias G in the first sub-path close to the power supply device 30 is smaller than the number of vias G in the first sub-path away from the power supply device 30.

[0089] like Figure 8 As shown, Figure 8 This is a schematic diagram of the planar structure of multiple solder balls disclosed in an embodiment of the present invention, wherein the spacing between solder balls H3 in area Q1 where the first sub-path close to the power supply device 30 is located is smaller than the spacing between solder balls H3 in area Q2 where the first sub-path away from the power supply device 30 is located, and the density of solder balls H3 in area Q1 where the first sub-path close to the power supply device 30 is located is greater than the density of solder balls H3 in area Q2 where the first sub-path away from the power supply device 30 is located.

[0090] Since the distances from different solder balls of the package substrate 10 to the power supply device 30 are different, the current flowing through the region Q1 where the first sub-path close to the power supply device 30 is located is greater than the current flowing through the region Q2 where the first sub-path is located away from the power supply device 30. Based on this, in some embodiments of the present invention, by making the density of solder balls H3 in the region Q1 where the first sub-path close to the power supply device 30 is located greater than the density of solder balls H3 in the region Q2 where the first sub-path is located away from the power supply device 30, it can be made that in the process of the power supply device 30 supplying power to the bare die 20 through multiple power supply paths, the currents flowing through the solder balls H3 corresponding to any two power supply paths are the same.

[0091] It should be noted that, in the embodiment of the present invention, only the example of dividing the surface of the packaging substrate with the solder ball H3 into two areas is used for explanation, and it is not limited to this. In other embodiments, the surface of the packaging substrate with the solder ball H3 can also be evenly divided into three or more areas, and in multiple areas close to the power supply device 30, the density or number of the solder ball H3 increases successively.

[0092] In some embodiments of the present invention, the length and width of the wire D in the first sub-path can be adjusted so that the total area of ​​the wire D in the first sub-path where the solder ball H3 close to the power supply device 30 is located is smaller than the total area of ​​the wire D in the first sub-path where the solder ball H3 close to the bare chip 20 is located.

[0093] Of course, the present invention is not limited to this. In other embodiments, the area of ​​each conductive layer in the packaging substrate 10 can be adjusted to make the total area of ​​the wire D in the first sub-path where the solder ball H3 close to the power supply device 30 is located smaller than the total area of ​​the wire D in the first sub-path where the solder ball H3 close to the bare chip 20 is located.

[0094] like Fig. 9 and Fig.10 As shown, Fig. 9 FIG. 1 is a schematic diagram of a planar structure of another packaging substrate disclosed in an embodiment of the present invention. Fig.10 for Fig. 9 As shown in the schematic cross-sectional structure diagram of the package substrate, in the direction from the second pad H2 to the first pad H1, the areas of the multiple conductive layers increase sequentially. Fig. 9 or Fig.10 As shown, the lengths of the first conductive layer L1 to the sixth conductive layer L6 increase sequentially, so that the areas of the first conductive layer L1 to the sixth conductive layer L6 increase sequentially.

[0095] Moreover, multiple conductive layers overlap in an area far away from the power supply device 30 , and multiple conductive layers partially overlap in an area close to the power supply device 30 , so that the total area of ​​the wire D in the first sub-path where the solder ball H3 close to the power supply device 30 is located is smaller than the total area of ​​the wire D in the first sub-path where the solder ball H3 close to the bare chip 20 is located.

[0096] exist Figure 8 In the structure shown, the packaging substrate 10 is a regular square substrate, but the present invention is not limited thereto. In some optional examples, such as Fig.11 As shown, Fig.11 This is a schematic diagram of the planar structure of another packaging substrate disclosed in an embodiment of the present invention. The packaging substrate 10 can also be a substrate having a bridge-shaped area 100, and the bridge-shaped area 100 is located between the bare chip 20 and the power supply device 30. The width of the bridge-shaped area 100 is smaller than the width of the packaging substrate 10, so as to extend the length of the conductive layer in the packaging substrate 10 while reducing the area of ​​the packaging substrate 10, thereby reducing the occupied space of the packaging substrate 10.

[0097] In some embodiments of the present invention, Fig.12 As shown, Fig.12It is a schematic diagram of the cross-sectional structure of another bare chip, a packaging substrate and a power supply device disclosed in an embodiment of the present invention, in which the number of vias G in the first sub-path where the solder ball H3 close to the power supply device 30 is located is less than the number of vias G in the first sub-path where the solder ball H3 far from the power supply device 30 is located, so as to increase the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located by reducing the number of vias G in the first sub-path where the solder ball H3 close to the power supply device 30, so that the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is greater than the impedance of the first sub-path where the solder ball H3 close to the bare chip 20 is located.

[0098] In the above embodiments of the present invention, only one impedance adjustment method of solder balls, wires and vias is used as an example for explanation, but the present invention is not limited to this. In other embodiments, at least two of the impedance of the solder balls, the impedance of the wires and the impedance of the vias can be adjusted simultaneously, which will not be repeated here.

[0099] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a chip, which may be a server chip or a processor chip. Fig.13 As shown, Fig.13 It is a schematic diagram of the cross-sectional structure of a chip disclosed in an embodiment of the present invention, wherein the chip includes a packaging substrate 10 and a bare chip 20 as disclosed in any of the above embodiments, wherein the bare chip 20 is packaged on the packaging substrate 10, and the bare chip 20 is electrically connected to the first pad of the packaging substrate 10.

[0100] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses an integrated circuit system, such as Fig.14 As shown, Fig.14 This is a schematic diagram of the structure of an integrated circuit system disclosed in an embodiment of the present invention. The integrated circuit system includes a printed circuit board 40, a power supply device 30 and the chip as above. The chip and the power supply device 30 are mounted on the printed circuit board 40, and the power supply device 30 supplies power to the chip through the printed circuit board 40.

[0101] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses an electronic device, which includes the integrated circuit system disclosed in the above embodiment. The electronic device includes a smart phone, a tablet computer, a digital camera, a server, etc.

[0102] As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a packaging substrate design method, such as Figure 1As shown, the package substrate includes a substrate body, the substrate body includes a plurality of conductive layers stacked, such as the first conductive layer L1 to the sixth conductive layer L6, and an insulating layer located between two adjacent conductive layers, such as the first insulating layer R1 to the fifth insulating layer R5, the conductive layers located on opposite sides of the substrate body respectively have a plurality of first pads and a plurality of second pads, each of which is connected to a solder ball, such as the first conductive layer L1 has a plurality of first pads H1, the sixth conductive layer L6 has a plurality of second pads H2, each of which is connected to a solder ball H3. The first pad H1 is used to electrically connect to the bare chip, and the second pad H2 is used to electrically connect to the power supply device. The conductive layer located in the middle of the substrate body includes a plurality of wires, and the wires located in different conductive layers are electrically connected through vias that penetrate the insulating layer between the two.

[0103] like Fig.15 As shown, Fig.15 The present invention discloses a flow chart of a packaging substrate design method, which includes:

[0104] S101: Determine structures of multiple power supply paths, where the power supply device supplies power to the bare die through the multiple power supply paths, where one power supply path at least includes a solder ball, a second solder pad electrically connected to the solder ball, a via electrically connecting the second solder pad and at least one wire, at least one wire, a via electrically connecting multiple wires in the at least one wire, a via electrically connecting the at least one wire and a first solder pad, and a first solder pad;

[0105] In an embodiment of the present invention, the power supply path between the power supply device and the bare chip can be divided into multiple power supply paths according to the structure of the packaging substrate, and each power supply path includes at least one solder ball, a second solder pad electrically connected to the solder ball, a via electrically connecting the second solder pad and at least one wire, at least one wire, a via electrically connecting multiple wires in the at least one wire, a via electrically connecting at least one wire to a first solder pad, and a first solder pad.

[0106] S102: adjusting structural parameters of at least one of solder balls, pads, wires and vias in any power supply path so that when the power supply device supplies power to the bare chip through multiple power supply circuits, the currents flowing through the solder balls corresponding to any two power supply paths are the same.

[0107] In an embodiment of the present invention, by dividing the power supply path between the power supply device and the bare chip into multiple power supply paths, and by adjusting the structural parameters of at least one of the solder balls, pads, wires and vias in any power supply path, when the power supply device supplies power to the bare chip through multiple power supply circuits, the currents flowing through the solder balls corresponding to any two power supply paths are the same, thereby avoiding excessive current flowing through some solder balls of the package substrate and the chip including the package substrate, thereby avoiding some solder balls from being burned due to excessive current, and thereby avoiding problems such as short circuits and other poor contact caused by some solder balls being burned.

[0108] In an embodiment of the present invention, the packaging substrate may be a packaging substrate in the integrated circuit design process, or may be a packaging substrate after tape-out, so as to optimize the structure of the packaging substrate by redesigning the packaging substrate after tape-out. In some optional examples, the packaging substrate is a packaging substrate in the integrated circuit design process, and determining the structure of the multiple power supply paths includes: determining the structural information of the packaging substrate based on the design information of the packaging substrate; and determining the structure of the multiple power supply paths based on the structural information of the packaging substrate.

[0109] In some embodiments of the present invention, when the power supply device supplies power to the bare chip through multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and / or the currents flowing through any two power supply paths are the same, so that the currents flowing through the solder balls H3 corresponding to any two power supply paths are the same.

[0110] In some optional examples, the power supply path between the power supply device and the bare chip can be first divided into multiple power supply paths. For example, the area where the multiple first pads H1 are located or the area where the bare chip is located can be evenly divided into multiple parts, each of which can include at least one first pad H1, wherein the size of each part after division can be determined manually or according to a certain division strategy, and then the vias, wires, second pads H2 and solder balls H3 that are electrically connected to the first pad H1 in each part are determined, thereby finally determining each power supply path.

[0111] Then, numerical analysis methods such as finite element method can be used to calculate the impedance of pads, vias, wires and solder balls in each power supply path based on the structural parameters of pads, vias, wires and solder balls in the power supply path, such as length, width, impedance per unit area, etc., to obtain the impedance of each power supply path. If the impedances corresponding to any two power supply paths are different in the process of the power supply device supplying power to the bare chip through multiple power supply paths, adjust the structural parameters of at least one of the solder balls, pads, wires and vias in any power supply path until the impedances corresponding to any two power supply paths are the same.

[0112] Then, determine whether the magnitude of the current passing through the solder balls corresponding to any two power supply paths is the same during the process of the power supply device supplying power to the bare chip through multiple power supply paths. If different, adjust the structural parameters of at least one of the solder balls, pads, wires and vias in any power supply path until the magnitude of the current passing through the solder balls corresponding to any two power supply paths is the same.

[0113] Then, it is determined whether the magnitude of the current passing through the solder balls corresponding to any two power supply paths is the same during the process of the power supply device supplying power to the bare chip through multiple power supply paths. If different, the structural parameters of at least one of the solder balls, pads, wires and vias in any power supply path are adjusted until the magnitude of the current passing through the solder balls corresponding to any two power supply paths is the same.

[0114] In some embodiments of the present invention, Figure 5 As shown, the package substrate 10 and the power supply device 30 are arranged on the printed circuit board 40, the power supply device 30 is electrically connected to the package substrate 10 through the printed circuit board 40, and the power supply device 30 is located on the side of the package substrate 10 away from the bare chip 20, each power supply path includes a first sub-path, and the first sub-path includes a solder ball, a second solder pad, a wire, a via and a first solder pad located in the package substrate, then adjusting the structural parameters of at least one of the solder ball, the solder pad, the wire and the via in any power supply path includes:

[0115] At least one of the position of the solder ball, the area of ​​the wire and the number of vias in any power supply path is adjusted so that the impedance of the first sub-path where the solder ball close to the power supply device 30 is located is greater than the impedance of the first sub-path where the solder ball is far from the power supply device 30.

[0116] like Figure 5 As shown, each power supply path includes a first sub-path and a second sub-path, the first sub-path includes a solder ball H3, a second solder pad H2, a wire D, a via G, and a first solder pad H1 located in the package substrate 10, and the second sub-path includes a solder pad, a wire, and a via located in the printed circuit board 40. Since the distances from different solder balls of the package substrate 10 to the power supply device 30 are different, the impedance of the second sub-path close to the power supply device 30 in different power supply paths is smaller than the impedance of the second sub-path far from the power supply device 30.

[0117] Based on this, in some embodiments of the present invention, at least one of the position of the solder ball, the area of ​​the wire and the number of vias in any power supply path is adjusted so that the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located is greater than the impedance of the first sub-path where the solder ball H3 far away from the power supply device 30 is located, so that in the process of the power supply device 30 supplying power to the bare chip 20 through multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and / or the currents flowing through any two power supply paths are the same, thereby making the currents flowing through the solder balls corresponding to any two power supply paths the same.

[0118] On this basis, in some embodiments of the present invention, adjusting the position of the solder balls in any power supply path includes: making the density of the solder balls in the area where the first sub-path close to the power supply device is located greater than the density of the solder balls in the area where the first sub-path far from the power supply device is located.

[0119] like Figure 8 As shown, since the distances from different solder balls of the package substrate 10 to the power supply device 30 are different, the current flowing through the region Q1 where the first sub-path close to the power supply device 30 is located is greater than the current flowing through the region Q2 where the first sub-path is located away from the power supply device 30. Based on this, in some embodiments of the present invention, by making the density of solder balls H3 in the region Q1 where the first sub-path close to the power supply device 30 is located greater than the density of solder balls H3 in the region Q2 where the first sub-path is located away from the power supply device 30, it can be made that in the process of the power supply device 30 supplying power to the bare die 20 through multiple power supply paths, the currents flowing through the solder balls H3 corresponding to any two power supply paths are the same.

[0120] In some embodiments of the present invention, adjusting the area of ​​the wires in any power supply path includes: making the total area of ​​the wires in a first sub-path close to the power supply device smaller than the total area of ​​the wires in a first sub-path far from the power supply device.

[0121] In some optional examples, the areas of the multiple conductive layers may be increased in sequence in the direction from the second pad H2 to the first pad H1, such as Fig. 9 or Fig.10 As shown, the lengths of the first conductive layer L1 to the sixth conductive layer L6 increase sequentially, so that the areas of the first conductive layer L1 to the sixth conductive layer L6 increase sequentially. In addition, multiple conductive layers overlap in the area far from the power supply device 30, and multiple conductive layers partially overlap in the area close to the power supply device 30, so that the total area of ​​the wire D in the first sub-path where the solder ball H3 close to the power supply device 30 is located is smaller than the total area of ​​the wire D in the first sub-path where the solder ball H3 close to the bare chip 20 is located.

[0122] In some embodiments of the present invention, adjusting the number of vias in any power supply path includes: making the number of vias in a first sub-path close to the power supply device smaller than the number of vias in a first sub-path far from the power supply device.

[0123] like Fig.12 As shown, the number of vias G in the first sub-path where the solder ball H3 close to the power supply device 30 is located can be made smaller than the number of vias G in the first sub-path where the solder ball H3 far from the power supply device 30 is located, so as to increase the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 by reducing the number of vias G in the first sub-path where the solder ball H3 close to the power supply device 30 is located, so that the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is greater than the impedance of the first sub-path where the solder ball H3 close to the bare chip 20 is located.

[0124] As an optional implementation of the content disclosed in the present invention, the embodiment of the present invention discloses a computer device, such as Fig.16 As shown, Fig.16 The present invention is a schematic diagram of a computer device disclosed in an embodiment of the present invention, wherein the computer device includes:

[0125] A memory 81, used for storing instructions;

[0126] The processor 82 is used to execute the instructions stored in the memory 81 to implement the packaging substrate design method provided in any of the above embodiments.

[0127] Specifically, the computer device may also include a bus, a communication interface 83, an input device 84, and an output device 85. The processor 82, the memory 81, the communication interface 83, the input device 84, and the output device 85 are interconnected via the bus.

[0128] A bus may include a pathway that transfers information between components of a computer system.

[0129] The processor 82 may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the scheme of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Among them, the processor 82 may include a main processor, and may also include a baseband chip, a modem, etc.

[0130] The memory 81 stores a program for executing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include a program code, and the program code includes computer operation instructions. More specifically, the memory 81 may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk storage, a flash, and the like.

[0131] The input device 84 may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer or a gravity sensor, etc. The output device 85 may include a device that allows information to be output to the user, such as a display screen, a printer, a speaker, etc. The communication interface 83 may include a device such as a transceiver to communicate with other devices or communication networks, such as Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0132] As an optional implementation of the contents disclosed in the present invention, an embodiment of the present invention discloses a computer-readable storage medium, characterized in that instructions for executing the packaging substrate design method disclosed in any of the above embodiments are stored thereon.

[0133] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0134] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging substrate, characterized in that: The substrate comprises a substrate body; the substrate body comprises a plurality of conductive layers stacked in layers and an insulating layer between two adjacent conductive layers; The conductive layers located on opposite sides of the substrate body respectively have a plurality of first pads and a plurality of second pads, each of the second pads is connected to a solder ball; the conductive layer located in the middle of the substrate body includes a plurality of wires, and the wires located in different conductive layers are electrically connected through vias penetrating the insulating layer between the two; The first pad is used to be electrically connected to the bare die; the second pad is used to be electrically connected to the power supply device through the solder ball; the power supply device supplies power to the bare die through multiple power supply paths; one power supply path at least includes a solder ball, a second pad electrically connected to the solder ball, a via electrically connecting the second pad and at least one wire, the at least one wire, a via electrically connecting multiple wires in the at least one wire, a via electrically connecting the at least one wire and a first pad, and the first pad; In the process of the power supply device supplying power to the bare chip through the multiple power supply paths, the currents flowing through the solder balls corresponding to any two power supply paths are of the same magnitude; in the direction from the second pad to the first pad, the areas of the multiple conductive layers increase successively, and the multiple conductive layers overlap in the area far away from the power supply device, and partially overlap in the area close to the power supply device.

2. The packaging substrate according to claim 1, characterized in that: In the process of the power supply device supplying power to the bare chip through the multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and / or the magnitudes of the currents flowing through any two power supply paths are the same.

3. The packaging substrate according to claim 1, characterized in that: The packaging substrate and the power supply device are arranged on a printed circuit board, the power supply device is electrically connected to the packaging substrate through the printed circuit board, and the power supply device is located on the other side of the packaging substrate away from the bare chip; Each of the power supply paths includes a first sub-path, which includes a solder ball, a second solder pad, a via and a first solder pad located in the packaging substrate; and the impedance of the first sub-path where the solder ball close to the power supply device is located is greater than the impedance of the first sub-path where the solder ball far from the power supply device is located.

4. The packaging substrate according to claim 3, characterized in that: The packaging substrate meets at least one of the following conditions: The density of solder balls in the region where the first sub-path close to the power supply device is located is greater than the density of solder balls in the region where the first sub-path far from the power supply device is located; The number of via holes in the first sub-path close to the power supply device is less than the number of via holes in the first sub-path far from the power supply device.

5. A chip, characterized in that: The invention comprises a packaging substrate as claimed in any one of claims 1 to 4 and a bare chip, wherein the bare chip is electrically connected to a first pad of the packaging substrate.

6. An integrated circuit system, characterized in that: The invention comprises a printed circuit board, a power supply device and the chip according to claim 5, wherein the chip and the power supply device are mounted on the printed circuit board, and the power supply device supplies power to the chip through the printed circuit board.

7. An electronic device, characterized in that: A system comprising the integrated circuit of claim 6.

Images