Memory Component and Method of Forming the Same

Abstract

The present invention provides a memory component, comprising: a substrate, a plurality of bit line structures, a plurality of bit line contact windows, and a plurality of protection structures. The substrate has a plurality of active regions. The plurality of bit line structures are arranged in parallel on the substrate along the X direction. The plurality of bit line contact windows are respectively arranged at the overlapped portions of the plurality of bit line structures and the plurality of active regions and electrically connect the plurality of bit line structures and the plurality of active regions. The plurality of protection structures are at least arranged on a first sidewall and a second sidewall of the plurality of bit line contact windows. Another method for forming a memory component is provided.

Description

Technical Field

[0001] The present invention relates to a memory component and a method for forming the same. Background Art

[0002] Dynamic random access memory (DRAM) belongs to a kind of volatile memory, which is composed of a plurality of memory cells. Specifically, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other through a word line and a bit line. In order to improve the integration of dynamic random access memory to accelerate the operation speed of components and meet the needs of consumers for miniaturized electronic devices, in recent years, buried word line dynamic random access memory has been developed to meet the above various needs.

[0003] With the progress of technology, various electronic products are developing towards the trend of being thin, light, short and small. However, under this trend, the critical dimensions of DRAM are gradually reduced, which causes the DRAM process to face many challenges. For example, when forming a bit line contact window opening in a silicon substrate, silicon residue will remain in the corner of the active region, which may lead to a short circuit between the capacitor contact window and the bit line contact window. Or, when defining the bit line contact window, poly-silicon residue will also remain in the corner of the active region, which may lead to a short circuit between the capacitor contact window and the bit line contact window. Summary of the Invention

[0004] The present invention provides a memory component, including: a substrate, a plurality of bit line structures, a plurality of bit line contact windows, and a plurality of protection structures. The substrate has a plurality of active regions. The plurality of bit line structures are arranged in parallel on the substrate along the X direction. The plurality of bit line contact windows are respectively arranged at the overlaps of the plurality of bit line structures and the plurality of active regions and electrically connect the plurality of bit line structures and the plurality of active regions. The plurality of protection structures are at least arranged on the first sidewall and the second sidewall of the plurality of bit line contact windows.

[0005] The present invention provides a method for forming a memory component, comprising: providing a substrate having a plurality of active regions; forming a plurality of buried word lines in the substrate, wherein the plurality of buried word lines extend along the Y direction and pass through the plurality of active regions; forming a first opening between two adjacent buried word lines to expose the corresponding active regions; forming a protective layer to cover the sidewalls of the first opening; forming a conductive material in the first opening; forming a plurality of bit line structures on the substrate, wherein the plurality of bit line structures extend along the X direction and cover a first portion of the conductive material; performing a first etching process to remove a second portion of the conductive material not covered by the plurality of bit line structures, so that the first portion of the conductive material forms a bit line contact window and a second opening is formed between the protective layer and the bit line contact window; performing a second etching process to remove a portion of the protective layer not covered by the plurality of bit line structures, so that the remaining portion of the protective layer forms a plurality of protection structures and the second opening is enlarged to form a third opening; and forming a dielectric layer in the third opening.

[0006] The present invention provides another method for forming a memory component, comprising: providing a substrate having a plurality of active regions; forming a plurality of buried word lines in the substrate, wherein the plurality of buried word lines extend along the Y direction and pass through the plurality of active regions; forming a first opening between two adjacent buried word lines to expose the corresponding active regions; forming a protection structure to cover the sidewalls of the first opening; forming a conductive material in the first opening; forming a plurality of bit line structures on the substrate, wherein the plurality of bit line structures extend along the X direction and cover a first portion of the conductive material; removing a second portion of the conductive material not covered by the plurality of bit line structures, so that the first portion of the conductive material forms a bit line contact window and a second opening is formed between the protection structure and the bit line contact window; and forming a dielectric layer in the second opening.

[0007] Based on the above, in the embodiments of the present invention, the protection structure and the dielectric layer surround the bit line contact window in a closed path to electrically isolate the bit line contact window from the capacitor contact window and avoid a short circuit between the bit line contact window and the capacitor contact window, thereby improving the reliability of the memory component.

[0008] To make the above features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. Description of the Drawings

[0009] Figure 1 is a top view schematic diagram of a memory component according to an embodiment of the present invention;

[0010] Figures 2A to 2E is a top view schematic diagram of a manufacturing process of a memory component according to the first embodiment of the present invention;

[0011] Figures 3A to 3E are respectively along Figure 2ACross-sectional schematic diagram of the manufacturing process of the memory component along the I-I line segment;

[0012] Figures 3F to 3J respectively along Figures 2B to 2E Cross-sectional schematic diagram of the manufacturing process of the memory component along the I-I line segment;

[0013] Figures 4A to 4D respectively along Figures 2B to 2E Cross-sectional schematic diagram of the manufacturing process of the memory component along the II-II line segment;

[0014] Figures 4E to 4G respectively Figure 4D Cross-sectional schematic diagram of the subsequent manufacturing process of the memory component;

[0015] Figures 5A to 5B is a top view schematic diagram of the manufacturing process of a memory component according to the second embodiment of the present invention;

[0016] Figures 6A to 6B respectively along Figures 5A to 5B Cross-sectional schematic diagram of the manufacturing process of the memory component along the I-I line segment;

[0017] Figures 7A to 7B respectively along Figures 5A to 5B Cross-sectional schematic diagram of the manufacturing process of the memory component along the II-II line segment;

[0018] Figures 7C to 7E respectively Figure 7B Cross-sectional schematic diagram of the subsequent manufacturing process of the memory component. Detailed implementation manners

[0019] The present invention will be described more comprehensively with reference to the accompanying drawings of this embodiment. However, the present invention can be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of the layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar components, and will not be repeated in the following paragraphs.

[0020] Figure 1 is a top view schematic diagram of a memory component according to an embodiment of the present invention. The memory component in the following embodiments is described by taking a dynamic random access memory as an example, but the present invention is not limited thereto.

[0021] Please refer to Figure 1 , this embodiment provides a memory component 10 including: a substrate 100, a plurality of isolation structures 101, a plurality of active regions AA, a plurality of bit line structures 102, a plurality of buried word lines 202, a plurality of capacitor contact windows CC, a plurality of bit line contact windows BC, and a plurality of electrical insulation structures IS. For clarity of the drawing, Figure 1Only the above components are shown. Other structures can be seen in the subsequent Figures 3A to 3J and Figures 4A to 4G cross-sectional views.

[0022] As Figure 1 shown, the substrate 100 includes a plurality of active areas AA. In one embodiment, the active areas AA can be formed by forming isolation structures 101 in the substrate 100 to define a plurality of active areas AA in the substrate 100. That is, there is an isolation structure 101 between two adjacent active areas AA. In one embodiment, only one memory cell is formed on one active area AA, and each memory cell is separated by an isolation structure 101 to effectively reduce the interference problem between memory cells.

[0023] The bit line structure 102 is located on the substrate 100 and traverses the active areas AA. In one embodiment, the bit line structure 102 extends along the X direction and is arranged along the Y direction. The buried word line 202 is located in the substrate 100. In one embodiment, the buried word line 202 extends along the Y direction and is arranged along the X direction. In this embodiment, the X direction and the Y direction are substantially perpendicular to each other.

[0024] As Figure 1 shown, each active area AA has a long side L1 and a short side L2, and the long side L1 straddles two corresponding buried word lines 202 and a bit line structure 102. There is a bit line contact window BC at the overlapping portion of each active area AA and the corresponding bit line structure 102. In this case, the bit line contact window BC can be used to electrically connect the bit line structure 102 and the doped region (not shown) in the corresponding active area AA. The doped region can be located between two buried word lines 202.

[0025] The capacitor contact windows CC are respectively arranged in the space surrounded by the buried word line 202 and the bit line structure 102. Specifically, the capacitor contact windows CC are respectively arranged at the two end points of the long side L1 of the active area AA, and they can electrically connect the active area AA and a subsequently formed capacitor (not shown). In addition, although the capacitor contact windows CC are shown as rectangles in Figure 1 they are actually formed to be slightly circular, and their sizes can be designed according to process requirements.

[0026] It should be noted that, as Figure 1 shown, the electrical insulation structure IS can laterally surround the side walls of the bit line contact window BC in the form of a closed path to electrically isolate the bit line contact window BC from the capacitor contact window CC and avoid a short circuit between the bit line contact window BC and the capacitor contact window CC, thereby improving the reliability of the memory component 10. Although Figure 1The electrical insulation structure IS shown has a square annular layout, but the present invention is not limited thereto. In other embodiments, the electrical insulation structure IS may also be applicable to other suitable layouts, such as a circular annular layout, an elliptical annular layout, etc.

[0027] Figures 2A to 2E is a top view schematic diagram of a manufacturing process of a memory component according to a first embodiment of the present invention. Figures 3A to 3E are respectively along Figure 2A a cross-sectional schematic diagram of the manufacturing process of the memory component along the I-I line segment of. Figures 3F to 3J are respectively along Figures 2B to 2E a cross-sectional schematic diagram of the manufacturing process of the memory component along the I-I line segment of. Figures 4A to 4D are respectively along Figures 2B to 2E a cross-sectional schematic diagram of the manufacturing process of the memory component along the II-II line segment of. Figures 4E to 4G are respectively Figure 4D a cross-sectional schematic diagram of the subsequent manufacturing process of the memory component of.

[0028] This embodiment provides a method for forming a memory component 20, which includes the following steps. First, please refer to Figure 3A , and provide an initial structure, which includes a substrate 100, a plurality of isolation structures 101, and a plurality of buried word lines 202. In one embodiment, the substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor-on-insulator (SOI) substrate. In this embodiment, the substrate 100 is a silicon substrate.

[0029] As Figure 3A shown, the isolation structures 101 are disposed in the substrate 100 to divide the substrate 100 into a plurality of active regions AA. In one embodiment, the isolation structure 101 includes a dielectric material, and the dielectric material may be silicon oxide, silicon nitride, or a combination thereof. Additionally, the isolation structure 101 may include a single-layer structure, a double-layer structure, or a multi-layer structure. For example, the isolation structure 101 may include a first isolation layer and a second isolation layer that encapsulates the first isolation layer to separate the first isolation layer from the substrate 100. The first isolation layer may be a silicon nitride layer, and the second isolation layer may be a thermal oxide layer. In an alternative embodiment, the isolation structure 101 may be, for example, a shallow trench isolation (STI) structure.

[0030] As Figure 3AAs shown, each embedded word line 202 includes a conductor layer 204, a barrier layer 206, a sealing layer 208 and a gate dielectric layer 210. The gate dielectric layer 210 coats the surface of the conductor layer 204 to electrically isolate the conductor layer 204 from the substrate 100. The barrier layer 206 is located between the conductor layer 204 and the gate dielectric layer 210. The sealing layer 208 covers the top surface of the conductor layer 204, the top surface of the barrier layer 206 and the top surface of the gate dielectric layer 210. In one embodiment, the conductor layer 204 can be regarded as a gate, and the material of the conductor layer 204 can include a metal material, such as W. The material of the barrier layer 206 can include a barrier metal material, such as Ti, TiN, Ta, TaN or a combination thereof. The material of the gate dielectric layer 210 can include a dielectric material, such as silicon oxide. The material of the sealing layer 208 can include a dielectric material, such as silicon nitride. In this embodiment, the sealing layer 208 and the gate dielectric layer 210 can have different dielectric materials.

[0031] In addition, the initial structure further includes a silicon oxide layer 212, a silicon nitride layer 214 and a silicon oxide layer 216. Specifically, the silicon oxide layer 212 is disposed on the substrate 100 and extends to cover the top surface of the sealing layer 208. The silicon nitride layer 214 is disposed on the silicon oxide layer 212. The silicon oxide layer 216 is disposed on the silicon nitride layer 214, so that the silicon nitride layer 214 is located between the silicon oxide layer 212 and the silicon oxide layer 216.

[0032] After forming the initial structure, an opening 12 (also referred to as the first opening) is formed between two adjacent embedded word lines 202, as Figure 3A shown. Specifically, the opening 12 penetrates through the silicon oxide layer 216, the silicon nitride layer 214 and the silicon oxide layer 212 to expose the active region AA. In one embodiment, the opening 12 also penetrates through a part of the sealing layer 208. In one embodiment, the opening 12 corresponds to Figure 1 the position of the bit line contact window BC. In one embodiment, the width 12w of the opening 12 is greater than the distance 202d between two adjacent embedded word lines 202, as Figure 2A shown. The sidewall 12s of the opening 12 can exceed half of the width 202w of the corresponding embedded word line 202. That is to say, the width 12w of the opening 12 can be greater than the sum of the width 202w of the word line 202 and the distance 202d between two adjacent embedded word lines 202. In this case, the contact area between the subsequently formed bit line contact window BC (as Figure 2D shown) and the active region AA can be enlarged, thereby reducing the resistance value therebetween.

[0033] Please refer to Figure 3B, after forming the opening 12, a protective material 220 is formed on the substrate 100. Specifically, the protective material 220 conformally covers the surface of the opening 12 and the top surface of the silicon oxide layer 216. In one embodiment, the protective material 220 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The method of forming the protective material 220 can be an atomic layer deposition method (ALD), a chemical vapor deposition method (CVD), or other similar methods. It should be noted that when the opening 12 is formed, silicon residues generated by etching the substrate 100 will remain in the corners of the opening 12. The silicon residues will cause a short circuit between the subsequently formed bit line contact window BC and the capacitor contact window CC (as Figure 4G shown). In this embodiment, the protective material 220 covering the opening 12 can effectively block the silicon residues to electrically isolate the bit line contact window BC and the capacitor contact window CC.

[0034] Please refer to Figure 3C , perform an etching process to remove a portion of the protective material 220 to expose the active region AA and form a protective layer 220a. In one embodiment, the etching process includes a dry etching process, such as a reactive ion etching process (RIE). In this case, the protective layer 220a can be formed in the form of a spacer on the sidewall 12s of the opening 12.

[0035] Please refer to Figure 3D , form a conductor material 222 to fill the opening 12 and extend to cover the top surface of the silicon oxide layer 216. In one embodiment, the conductor material 222 includes doped polysilicon or silicon germanium. The doped polysilicon can be, for example, polysilicon doped with an N-type dopant (such as phosphorus), which can effectively reduce the resistance value between the conductor material 222 and the active region AA. The method of forming the conductor material 222 can be a chemical vapor deposition method (CVD), an epitaxial growth method, etc.

[0036] Please refer to Figure 3E , perform a re-etching process to remove a portion of the conductor material 222, the silicon oxide layer 216, and a portion of the protective layer 220a to expose the silicon nitride layer 214 and form a conductor layer 222a. After the re-etching process, as Figure 2A shown, the protective layer 220a laterally surrounds the sidewall of the conductor layer 222a in a closed path. Additionally, a chemical mechanical polishing process (CMP) can also be used to form the conductor layer 222a. In this case, the protective layer 220a, the conductor layer 222a, and the silicon nitride layer 214 can have flush top surfaces.

[0037] Please refer to Figure 3F, a barrier layer 104, a bit line 106, a capping layer 108, and a mask layer 110 are sequentially formed on a substrate 100. In one embodiment, the material of the barrier layer 104 includes a barrier metal material, which can be, for example, Ti, TiN, Ta, TaN, or a combination thereof. The material of the bit line 106 can be a metal material, which can be, for example, W. Additionally, a thin metal silicide layer, such as tungsten silicide (WSi x ) can also be provided between the barrier layer 104 and the bit line 106. The material of the capping layer 108 can be silicon nitride. The material of the mask layer 110 can be silicon oxide, carbon, silicon oxynitride, or a combination thereof. In this embodiment, the mask layer 110 can be a hard mask layer with a multi-layer structure, but the present invention is not limited thereto.

[0038] Please refer to Figure 2B , Figure 3G and Figure 4A , the barrier layer 104, the bit line 106, the capping layer 108, and the mask layer 110 are patterned to form a plurality of bit line structures 102. Specifically, each bit line structure 102 includes, from bottom to top, a barrier layer 104a, a bit line 106a, a capping layer 108a, and a mask layer 110a. As shown in the top view Figure 2B , the bit line structure 102 extends along the X direction and crosses the active region AA and two buried word lines 202. As shown in the cross-sectional view Figure 3G and the cross-sectional view Figure 4A , the bit line structure 102 can be electrically connected to the substrate 100 (or the active region AA) through a conductor layer 222a.

[0039] Please refer to Figure 2C , Figure 3H and Figure 4B , a first etching process is performed to remove a part of the conductor layer 222a not covered by the bit line structure 102, so that the remaining part of the conductor layer 222a forms a bit line contact window BC. In this case, an opening 14 (also referred to as a second opening) can be formed between the protective layer 220a and the bit line contact window BC, as shown in Figure 2C and Figure 4B . In one embodiment, the first etching process includes a dry etching process, a wet etching process, or a combination thereof. In this embodiment, there is a high etching selectivity between the conductor layer 222a and the protective layer 220a. That is, in the first etching process, the etching rate of the conductor layer 222a is greater than the etching rate of the protective layer 220a. Therefore, after the first etching process, the exposed conductor layer 222a is completely removed, while the exposed protective layer 220a is retained.

[0040] Note that, during the first etching process, polysilicon residues generated from etching the conductor layer 222a will remain in the corners of the opening 14. The polysilicon residues may cause a short circuit between the subsequently formed bit line contact window BC and the capacitor contact window CC (as Figure 4G shown). In this embodiment, the protective layer 220a laterally surrounds the opening 14, which can effectively block the polysilicon residues to electrically isolate the bit line contact window BC and the capacitor contact window CC.

[0041] Please refer to Figure 2D , Figure 3I and Figure 4C , and perform a second etching process to remove a part of the protective layer 220a not covered by the bit line structure 102, so that the remaining part of the protective layer 220a forms a plurality of protection structures 220b. In this case, the opening 14 can be enlarged to form an opening 16 (also referred to as the third opening). As Figure 2D and Figure 4C shown, the protection structures 220b are respectively disposed on the first sidewall S1 and the second sidewall S2 of the bit line contact window BC, and the opening 16 exposes the third sidewall S3 and the fourth sidewall S4 of the bit line contact window BC. The protection structures 220b respectively extend from the first sidewall S1 and the second sidewall S2 of the bit line contact window BC into the corresponding buried word lines 202. In this embodiment, the second etching process can be a wet etching process. Since the protective layer 220a is isotropically etched, the sidewalls 220s of the protection structures 220b can be concave with respect to the third sidewall S3 or the fourth sidewall S4 of the bit line contact window BC. In this case, as Figure 2D the enlarged view of

[0042] shown, the width W1 of the protection structure 220b in the Y direction can be smaller than the width W2 of the bit line structure 102 in the Y direction, and can be smaller than the width W3 of the bit line contact window BC in the Y direction. However, the present invention is not limited thereto. In other embodiments, the width of the protection structure 220b in the Y direction can also be equal to the width of the bit line structure 102 in the Y direction, and can be equal to the width of the bit line contact window BC in the Y direction. Please refer to Figure 2E , Figure 3J and Figure 4D , and a liner layer 112 is formed on the substrate 100. Specifically, the liner layer 112 conformally covers Figure 4C the structure shown in Figure 4D to protect the bit line structure 102, as Figure 2EAs shown, the dielectric layer 114 and the protection structure 220b can be regarded as an electrical insulation structure IS. This electrical insulation structure IS can horizontally surround all sidewalls (i.e., S1, S2, S3, S4) of the bit line contact window BC in the form of a closed path. Therefore, the electrical insulation structure IS can electrically isolate the bit line contact window BC from the subsequently formed capacitor contact window CC (as Figure 4G shown), and avoid a short circuit between the bit line contact window BC and the capacitor contact window CC, thereby improving the reliability of the memory component. In an alternative embodiment, this electrical insulation structure IS further includes a partial liner 112 disposed between the dielectric layer 114 and the bit line contact window BC and between the dielectric layer 114 and the protection structure 220b. In one embodiment, the material of the dielectric layer 114 includes a nitrogen-containing dielectric material, which can be, for example, silicon nitride, silicon oxynitride, or a combination thereof.

[0043] After forming the dielectric layer 114, capacitor contact windows CC can be formed at both end points of the active region AA. Since the capacitor contact windows CC only appear in the cross-section of the II-II line segment, the subsequent drawings only show the cross-section of the II-II line segment Figures 4E to 4G , and the cross-sectional view of the I-I line segment is omitted.

[0044] After forming the dielectric layer 114, as Figure 4E shown, using the bit line structure 102 as a mask, a part of the liner 112, a part of the silicon nitride layer 214, a part of the silicon oxide layer 212, and a part of the dielectric layer 114 are removed to expose the surface of the active region AA.

[0045] Next, please refer to Figure 4F , a conductor material 116 is formed to fill the opening between the bit line structures 102 and cover the top surface of the bit line structures 102. In one embodiment, the conductor material 116 includes polysilicon, and its forming method can be CVD.

[0046] Please refer to Figure 4G , an etch-back process is performed to remove a part of the conductor material 116 so that the top surface of the conductor layer 116a is lower than the top surface of the bit line structure 102. Then, a metal layer 118 is formed on the conductor layer 116a. In one embodiment, the material of the metal layer 118 can be, for example, W, and its forming method can be physical vapor deposition (PVD). Additionally, a thin metal silicide layer, such as silicided tungsten (WSi x ), can also be present between the conductor layer 116a and the metal layer 118.

[0047] As Figure 4G shown, the composite structure of the conductor layer 116a and the metal layer 118 can be regarded as the capacitor contact window CC. The capacitor contact window CC can be disposed at both end points of the active region AA to electrically connect the active region AA to a subsequently formed capacitor (not shown).

[0048] Figures 5A to 5B is a top view schematic diagram of a manufacturing process of a memory component according to a second embodiment of the present invention. Figures 6A to 6B respectively are Figures 5A to 5B a cross-sectional schematic diagram of the manufacturing process of the memory component along the I-I line segment of Figures 7A to 7B respectively are Figures 5A to 5B a cross-sectional schematic diagram of the manufacturing process of the memory component along the II-II line segment of Figures 7C to 7E respectively Figure 7B a cross-sectional schematic diagram of the subsequent manufacturing process of the memory component of

[0049] This embodiment provides another method for forming a memory component 30. The difference from the memory component 20 is that: the memory component 30 does not perform the above-mentioned second etching process. That is to say, the memory component 30 retains the annular protection structure 320 to surround the bit line contact window BC. In addition, the Figure 5A , Figure 6A and Figure 7A structures of Figure 2C , Figure 3H and Figure 4B in the first embodiment are the same, and will not be elaborated here.

[0050] Next, referring to Figure 5B , Figure 6B and Figure 7B , a dielectric layer 314 is formed in the opening 14. The dielectric layer 314 covers the third sidewall S3 and the fourth sidewall S4 of the bit line contact window BC, and is disposed between the bit line contact window BC and the protection structure 320. Specifically, as shown in the top view Figure 5B , the protection structure 320 can laterally surround the bit line contact window BC and the dielectric layer 314 in a closed path form to achieve the effect of double protection. In this case, the dielectric layer 314 and the protection structure 320 can be regarded as an electrical insulation structure IS to electrically isolate the bit line contact window BC from the subsequently formed capacitor contact window CC (as shown in Figure 7E ), and avoid the short circuit between the bit line contact window BC and the capacitor contact window CC, thereby improving the reliability of the memory component.

[0051] It should be noted that, in one embodiment, the materials of the dielectric layer 314 and the protection structure 320 include a nitrogen-containing dielectric material, which can be, for example, silicon nitride, silicon oxynitride, or a combination thereof. In this embodiment, the dielectric layer 314 and the protection structure 320 can have the same dielectric material, for example, silicon nitride. In this case, the dielectric layer 314 and the protection structure 320 can be used as a barrier structure to avoid over-etching during the formation of the capacitor opening, which may cause a short circuit problem due to the electrical connection of two adjacent capacitor contact windows CC.

[0052] Afterwards, please refer to Figure 7C , using the bit line structure 102 as a mask, a portion of the liner 112 , a portion of the silicon nitride layer 214 , a portion of the silicon oxide layer 212 , a portion of the dielectric layer 314 , and a portion of the protection structure 320 are removed to expose the surface of the active area AA.

[0053] Then, please refer to Figure 7D and Figure 7E , a capacitor contact window CC is formed in the opening between the bit line structures 102 to electrically connect the active area AA with a capacitor (not shown) formed subsequently. Figure 7E The structure, material and forming method of capacitor contact window CC Figure 4G The structure, material and forming method of the capacitor contact window CC have been described in detail in the above embodiments and will not be repeated here.

[0054] In summary, the embodiment of the present invention has an electrical insulation structure composed of a protection structure and a dielectric layer. The electrical insulation structure can surround the bit line contact window in the form of a closed path to electrically isolate the bit line contact window from the capacitor contact window and avoid a short circuit between the bit line contact window and the capacitor contact window, thereby improving the reliability of the memory component.

[0055] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the attached claims.

Claims

1. A memory component, characterized in that, Comprising: A substrate having a plurality of active regions; A plurality of bit line structures arranged in parallel on the substrate along the X direction; A plurality of bit line contact windows respectively arranged at the overlaps of the plurality of bit line structures and the plurality of active regions and electrically connecting the plurality of bit line structures and the plurality of active regions; And A plurality of protection structures, wherein the tops of the plurality of protection structures are lower than the plurality of bit line structures, wherein: Each protection structure surrounds the first sidewall, the second sidewall, the third sidewall and the fourth sidewall of the corresponding bit line contact window in the form of a closed path, or The plurality of protection structures are at least arranged on the first sidewall and the second sidewall of the plurality of bit line contact windows, and further comprising a plurality of dielectric layers respectively arranged on the third sidewall and the fourth sidewall of the plurality of bit line contact windows to surround the first sidewall, the second sidewall, the third sidewall and the fourth sidewall of the corresponding bit line contact window in the form of a closed path; And A plurality of buried word lines are arranged in parallel in the substrate along the Y direction, wherein each bit line contact window is arranged between two adjacent buried word lines, wherein each protection structure is arranged at a position exceeding half of the width between two adjacent buried word lines, and wherein each protection structure extends from the first sidewall or the second sidewall of the corresponding bit line contact window into the corresponding buried word line.

2. The memory component according to claim 1, wherein Wherein each active region straddles two buried word lines and a bit line structure.

3. The memory component according to claim 1, wherein Further comprising: A plurality of capacitor contact windows are respectively arranged at the two end points of the long sides of the plurality of active regions and are respectively arranged in the space surrounded by the plurality of buried word lines and the plurality of bit line contact windows.

4. The memory component according to claim 1, wherein Wherein the width of the plurality of protection structures in the Y direction is less than or equal to the width of the plurality of bit line contact windows in the Y direction.

5. A method for forming a memory component, characterized in that Comprising: Providing a substrate having a plurality of active regions; Forming a plurality of buried word lines in the substrate, wherein the plurality of buried word lines extend along the Y direction and pass through the plurality of active regions; Forming a first opening between two adjacent buried word lines to expose the corresponding active region; Forming a protective layer to cover the sidewalls of the first opening; Forming a conductive material in the first opening; Forming a plurality of bit line structures on the substrate, wherein the plurality of bit line structures extend along the X direction and cover a first portion of the conductive material; Performing a first etching process to remove a second portion of the conductive material not covered by the plurality of bit line structures, so that the first portion of the conductive material forms a bit line contact window and a second opening is formed between the protective layer and the bit line contact window; Performing a second etching process to remove a portion of the protective layer not covered by the plurality of bit line structures, so that the remaining portion of the protective layer forms a plurality of protection structures and expands the second opening to form a third opening; And Forming a dielectric layer in the third opening.

6. The method for forming a memory component according to claim 5, wherein Wherein the width of the first opening is greater than the distance between two adjacent buried word lines.

7. The method for forming a memory component according to claim 5, wherein Further comprising respectively forming a plurality of capacitor contact windows between the plurality of bit line structures, so that the plurality of capacitor contact windows are respectively arranged at the two end points of the long sides of the plurality of active regions.

8. A method for forming a memory component, characterized in that, Comprising: Providing a substrate having a plurality of active regions; Form a plurality of buried word lines in the substrate, wherein the plurality of buried word lines extend along the Y direction and pass through the plurality of active regions; Form a first opening between two adjacent buried word lines to expose the corresponding active region; Form a protection structure to cover the side walls of the first opening; Form a conductive material in the first opening; Form a plurality of bit line structures on the substrate, wherein the plurality of bit line structures extend along the X direction and cover a first portion of the conductive material; Remove a second portion of the conductive material not covered by the plurality of bit line structures, so that the first portion of the conductive material forms a bit line contact window and a second opening is formed between the protection structure and the bit line contact window; And Form a dielectric layer in the second opening.

9. The method for forming a memory component according to claim 8, wherein It further includes forming a plurality of capacitor contact windows respectively between the plurality of bit line structures, so that the plurality of capacitor contact windows are respectively arranged at two end points of the long sides of the plurality of active regions.

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