Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, and relate to the technical field of display, to reduce the coupling between data lines. The display panel comprises: a plurality of pixel columns arranged along a first direction, the pixel column comprising a plurality of pixel circuits arranged along a second direction; a first data line and a second data line extending along the second direction, one first data line being electrically connected with the pixel circuits at odd rows in one pixel column, and one second data line being electrically connected with the pixel circuits at even rows in one pixel column; a power signal line extending along the second direction, the power signal line being electrically connected with the pixel circuits, and the power signal line being arranged in a layer different from the first data line and the second data line, and in a direction perpendicular to the plane where the display panel is located, the power signal line and at least one of the first data line and the second data line overlap.

Description

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device.

[0002] With the development of display technology, the refresh frequency of display panel is also increasing. Under high refresh rate, the row scanning time of pixel circuit in display panel is shortened, and the threshold compensation time of pixel circuit is also shortened accordingly.

[0003] In the existing design, in order to increase the threshold compensation time of pixel circuit, a double data line driving mode can be used, that is, the pixel circuits in odd rows and the pixel circuits in even rows in the same pixel column are electrically connected to different data lines. However, in this setting mode, the coupling between the two data lines is large, the signal crosstalk is serious, and the display problem is prone to occur.

[0004] Therefore, the embodiments of the present application provide a display panel and a display device to reduce the coupling between data lines.

[0005] In one aspect, the embodiments of the present application provide a display panel, comprising:

[0006] a plurality of pixel columns arranged along a first direction, the pixel columns comprising a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction;

[0007] a first data line and a second data line extending along the second direction, one of the first data lines being electrically connected to the pixel circuits in odd rows in one of the pixel columns, and one of the second data lines being electrically connected to the pixel circuits in even rows in one of the pixel columns;

[0008] a power signal line extending along the second direction, the power signal line being electrically connected to the pixel circuits, and the power signal line being disposed in a layer different from the first data line and the second data line, and in a direction perpendicular to the plane on which the display panel is located, the power signal line overlaps at least one of the first data line and the second data line.

[0009] In another aspect, the embodiments of the present application provide a display device comprising the above display panel.

[0010] One of the above technical solutions has the following beneficial effects:

[0011] ​​​When the display panel adopts the driving mode of double data lines, the original setting mode of the power signal line in the display panel is adjusted in the embodiment of the present application, so that the power signal line is arranged in a layer different from the first data line and the second data line, and overlaps at least one of the first data line and the second data line. At this time, the power signal line can also act as a shielding line to reduce the coupling between the first data line and the second data line.

[0012] For example, the first data line and the second data line have a first coupling capacitance. In the prior art, when the second data line is used to write a data signal to the pixel circuit, the potential on the second data line jumps by ΔV1, and based on the action of the first coupling capacitance, the potential on the first data line in the floating state also jumps by ΔV1, thereby causing serious horizontal crosstalk. In the embodiment of the present application, taking the overlap of the power signal line and the first data line as an example, at this time, a second coupling capacitance is formed between the power signal line and the first data line, and based on the voltage division effect of the second coupling capacitance, the voltage jump on the first data line can be reduced from ΔV1 to Thus, the influence of the voltage jump on the second data line on the signal on the first data line is effectively reduced.

[0013] Therefore, by using the technical solution provided in the embodiment of the present application, the coupling between the first data line and the second data line can be effectively reduced, and the mutual crosstalk of the signals on the first data line and the second data line is reduced.

[0014] Moreover, it needs to be emphasized that the embodiment of the present application uses the original power signal line in the display panel as a shielding line, so that no other shielding line needs to be additionally arranged, thereby realizing the optimized use of the original signal line and simplifying the wiring design of the display panel.

[0015] In addition, based on the setting mode of the power signal line in the embodiment of the present application, on the one hand, the power signal line extends in the same direction as the first data line and the second data line, and when the power signal line overlaps the first data line and / or the second data line, the overlapping length of the power signal line and the data line overlapping with it in the first direction can be further increased, thereby increasing the overlapping area. On the other hand, since the line width of the signal line is usually much larger than the film thickness, compared with the case where the power signal line is arranged in the same layer as the first data line and the second data line, arranging the power signal line in a layer different from the first data line and the second data line can further increase the overlapping area of the power signal line and the data line overlapping with it. When the overlapping area between the power signal line and the first data line and / or the second data line is large, the parasitic capacitance between the power signal line and the first data line and / or the second data line can be further increased, and the shielding effect of the power signal line is better, which can more greatly reduce the coupling between the first data line and the second data line. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A top view of a display panel provided by an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0020] Figure 4 Another top view of the display panel provided by the embodiment of the present invention;

[0021] Figure 5 Another top view of the display panel provided by the embodiment of the present invention;

[0022] Figure 6 for Figure 3 A cross-sectional view along the A1-A2 direction;

[0023] Figure 7 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0024] Figure 8 for Figure 7 A cross-sectional view along the B1-B2 direction;

[0025] Figure 9 A schematic cross-sectional view of a display panel provided by the present invention;

[0026] Figure 10 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0027] Figure 11 for Figure 2 A corresponding timing diagram;

[0028] Figure 12 A schematic structural diagram of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0029] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] It should be noted that the described embodiments are merely some of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0031] The terms used in the embodiments of the present application are merely for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0032] It should be understood that the term "and / or" used herein merely describes an association relationship of associated objects, which means that there can be three relationships, for example, A and / or B can represent three cases of A alone, A and B together, and B alone. In addition, the character " / " herein generally represents that the front and rear associated objects are in an "or" relationship.

[0033] The embodiments of the present application provide a display panel, such as Figures 1-3 as shown, Figure 1 a top view of the display panel provided by the embodiments of the present application, Figure 2 a circuit structure schematic diagram of the pixel circuit provided by the embodiments of the present application, Figure 3 a film layer structure schematic diagram of the display panel provided by the embodiments of the present application, the display panel comprising a plurality of pixel columns 1, a first data line D1, a second data line D2 and a power signal line PVDD.

[0034] Among them, the plurality of pixel columns 1 are arranged along a first direction x, the pixel column 1 comprises a plurality of pixel circuits 2 arranged along a second direction y, and the first direction x intersects the second direction y.

[0035] The first data line D1 and the second data line D2 respectively extend along the second direction y, one first data line D1 is electrically connected with the pixel circuit 2 located in the odd-numbered row in one pixel column 1, and one second data line D2 is electrically connected with the pixel circuit 2 located in the even-numbered row in one pixel column 1. It needs to be explained that one first data line D1 and one second data line D2 constitute a data line group, and one data line group corresponds to one pixel column 1. In one data line group, the first data line D1 is electrically connected with the pixel circuit 2 located in the odd-numbered row in the pixel column 1 corresponding to the first data line D1, and the second data line D2 is electrically connected with the pixel circuit 2 located in the even-numbered row in the pixel column 1 corresponding to the second data line D2. In one setting mode, the first data line D1 and the second data line D2 in one data line group can be respectively located on the opposite sides of the pixel column 1 in the first direction x, that is, one first data line D1 and one second data line D2 are arranged between adjacent pixel columns 1. The first data line D1 and the second data line D2 are used for transmitting data signals to the pixel circuit 2 connected therewith in time sharing mode.

[0036] The power supply signal line PVDD extends along the second direction y, and the power supply signal line PVDD is electrically connected with the pixel circuit 2. Moreover, the power supply signal line PVDD is arranged in a layer different from the first data line D1 and the second data line D2, and at least one of the first data line D1 and the second data line D2 overlaps with the power supply signal line PVDD in the direction perpendicular to the plane where the display panel is located.

[0037] When the display panel adopts the driving mode of double data lines, the setting mode of the original power supply signal line PVDD in the display panel is adjusted in the embodiment of the present application, so that the power supply signal line PVDD is arranged in a layer different from the first data line D1 and the second data line D2, and at least one of the first data line D1 and the second data line D2 overlaps with the power supply signal line PVDD. At this time, the power supply signal line PVDD can also act as a shielding line to reduce the coupling between the first data line D1 and the second data line D2.

[0038] For example, the first data line D1 and the second data line D2 have a first coupling capacitance C1. In the prior art, when the data signal is written into the pixel circuit 2 by using the second data line D2, the potential on the second data line D2 jumps by ΔV1, and based on the action of the first coupling capacitance C1, the potential on the first data line D1 in the floating state also jumps by ΔV1, thereby causing serious horizontal crosstalk. In the embodiment of the present application, taking the overlap between the power supply signal line PVDD and the first data line D1 as an example, a second coupling capacitance C2 is formed between the power supply signal line PVDD and the first data line D1, and based on the voltage division action of the second coupling capacitance C2, the voltage jump on the first data line D1 can be reduced from ΔV1 to Thus, the influence of the voltage jump on the second data line D2 on the signal on the first data line D1 is effectively reduced.

[0039] Therefore, by using the technical solution provided by the embodiment of the present application, the coupling between the first data line D1 and the second data line D2 can be effectively reduced, and in turn the mutual crosstalk of signals on the first data line D1 and the second data line D2 can be reduced.

[0040] Furthermore, it is also needed to emphasize that the embodiment of the present application uses the original power signal line PVDD in the display panel as a shielding line, so that no other shielding line needs to be additionally set, and the original signal line is optimally used, and the wiring design of the display panel is simplified.

[0041] In addition, based on the setting mode of the power signal line PVDD in the embodiment of the present application, on the one hand, the power signal line PVDD extends in the same direction as the first data line D1 and the second data line D2, and when the power signal line PVDD overlaps the first data line D1 and / or the second data line D2, the overlapping length of the power signal line PVDD and the data line overlapping the power signal line PVDD in the first direction x can be further increased, so as to increase the overlapping area. On the other hand, since the line width of the signal line is usually much larger than the film thickness, compared with the case that the power signal line PVDD is arranged in the same layer as the first data line D1 and the second data line D2, the case that the power signal line PVDD is arranged in different layers from the first data line D1 and the second data line D2 can further increase the overlapping area of the power signal line PVDD and the data line overlapping the power signal line PVDD. When the overlapping area between the power signal line PVDD and the first data line D1 and / or the second data line D2 is larger, the parasitic capacitance between the power signal line PVDD and the first data line D1 and / or the second data line D2 can be further increased, and the shielding effect of the power signal line PVDD is better, and the coupling between the first data line D1 and the second data line D2 can be reduced to a greater extent.

[0042] In a feasible implementation manner, referring again to Figure 1 and Figure 3 In the direction perpendicular to the plane where the display panel is located, at least part of the power signal line PVDD respectively overlaps the first data line D1 and the second data line D2.

[0043] When the power signal line PVDD overlaps the first data line D1 and the second data line D2 respectively, the power signal line PVDD can play a shielding role on the first data line D1 and the second data line D2. Specifically, when the first data line D1 has a voltage jump, the coupling capacitor formed by the power signal line PVDD overlapping the second data line D2 can be used to weaken the influence of the voltage jump of the first data line D1 on the signal on the second data line D2; when the second data line D2 has a voltage jump, the coupling capacitor formed by the power signal line PVDD overlapping the first data line D1 can also be used to weaken the influence of the voltage jump of the second data line D2 on the signal on the first data line D1. This arrangement not only weakens the influence of the voltage jump of the first data line D1 on the signal of the second data line D2, but also weakens the influence of the voltage jump of the second data line D2 on the signal of the first data line D1, and the shielding effect of the power signal line PVDD is better, which can more greatly reduce the coupling between the first data line D1 and the second data line D2.

[0044] Moreover, the power signal line PVDD overlaps the first data line D1 and the second data line D2 respectively, and the power signal line PVDD can also have a larger line width, which also helps to reduce the load of the power signal line PVDD, and further reduce the voltage drop of the power signal in the transmission process.

[0045] Further, referring again to Figure 1 and Figure 3 In the direction perpendicular to the plane where the display panel is located, at least part of the power signal line PVDD covers the first data line D1 and the second data line D2. That is, in the direction perpendicular to the plane where the display panel is located, the orthographic projection of the first data line D1 and the orthographic projection of the second data line D2 are both located within the orthographic projection of at least part of the power signal line PVDD.

[0046] In this way, on the one hand, the overlapping area between the power signal line PVDD and the first data line D1 and the second data line D2 is larger, so that a larger coupling capacitor can be formed between the power signal line PVDD and the first data line D1 and between the power signal line PVDD and the second data line D2, which can more greatly weaken the influence of the voltage jump on one data line on the signal on the other data line, further improving the crosstalk phenomenon. On the other hand, the power signal line PVDD has a larger line width, and the corresponding load is smaller.

[0047] In a feasible implementation manner, as shown in Figure 4 and Figure 5 , Figure 4 is another top view of the display panel provided by the embodiments of the present application, Figure 5In another top view of the display panel provided by the embodiments of the present application, the power supply signal line PVDD overlaps the first data line D1 or the second data line D2 in the direction perpendicular to the plane where the display panel is located.

[0048] Referring to Figure 4 , the power supply signal line PVDD overlaps the first data line D1. In this arrangement, a second coupling capacitor C2 is formed between the power supply signal line PVDD and the first data line D1. When the second data line D2 is used to write a data signal to the pixel circuit 2, the voltage on the second data line D2 jumps by ΔV1, and based on the voltage division effect of the second coupling capacitor C2, the voltage jump on the first data line D1 can be reduced from ΔV1 to At this time, the power supply signal line PVDD can shield the influence of the voltage jump on the second data line D2 on the signal on the first data line D1 to a certain extent.

[0049] Referring to Figure 5 , the power supply signal line PVDD overlaps the second data line D2. In this arrangement, a third coupling capacitor C3 is formed between the power supply signal line PVDD and the second data line D2. When the first data line D1 is used to write a data signal to the pixel circuit 2, the voltage on the first data line D1 jumps by ΔV2, and based on the voltage division effect of the third coupling capacitor C3, the voltage jump on the second data line D2 can be reduced from ΔV2 to At this time, the power supply signal line PVDD can shield the influence of the voltage jump on the first data line D1 on the signal on the second data line D2 to a certain extent.

[0050] In a possible implementation, as shown in Figure 6 , Figure 6 is Figure 3 a sectional view along the direction of A1-A2, the first data line D1 and the second data line D2 are located in the first metal layer 3, and the power supply signal line PVDD is located in the second metal layer 4, wherein the second metal layer 4 and the first metal layer 3 are two metal layers arranged adjacently. In an arrangement, the first metal layer 3 is located on the side of the second metal layer 4 away from the substrate 9.

[0051] In this arrangement, the power supply signal line PVDD is close to the first data line D1 and / or the second data line D2 overlapping the power supply signal line PVDD, and the formula for calculating the capacitance is Wherein, ε is a constant, S is the facing area of the capacitor plate, d is the distance between the capacitor plates, k is the electrostatic force constant. It can be seen that the closer the power signal line PVDD and the first data line D1 and / or the second data line D2 overlapping with the power signal line PVDD, the smaller the d is, the larger the coupling capacitance formed between the power signal line PVDD and the first data line D1 and / or the second data line D2 is, and accordingly, the shielding effect of the power signal line PVDD is better.

[0052] In a possible implementation, as shown in Figure 7 and Figure 8 , Figure 7 is another film layer structure diagram of the display panel provided by the embodiment of the present application, Figure 8 is Figure 7 a sectional view along the direction of B1-B2. The power signal line PVDD includes a first sub-power signal line PVDD1 and a second sub-power signal line PVDD2 arranged in different layers. The first data line D1 and the second data line D2 are located in the first metal layer 3. The first sub-power signal line PVDD1 is located in the third metal layer 7. The second sub-power signal line PVDD2 is located in the fourth metal layer 8. The first metal layer 3 is located between the third metal layer 7 and the fourth metal layer 8.

[0053] In the direction perpendicular to the plane where the display panel is located, the first sub-power signal line PVDD1 overlaps with at least one of the first data line D1 and the second data line D2. The second sub-power signal line PVDD2 overlaps with at least one of the first data line D1 and the second data line D2.

[0054] By arranging the first sub-power signal line PVDD1 and the second sub-power signal line PVDD2 on the upper and lower sides of the first data line D1 and the second data line D2 respectively, the coupling capacitance formed between the power signal line PVDD and the first data line D1 and / or the second data line D2 can be further increased by using double-layer wiring, so that the power signal line PVDD has a better shielding effect. Moreover, the power signal line PVDD is double-layered, which can reduce the load of the power signal line PVDD to a greater extent.

[0055] In a possible implementation, as shown in Figure 9 , Figure 9 is a sectional view of the display panel provided by the present application. The display panel further includes a substrate 9, a semiconductor layer 10 located on one side of the substrate 9, and a light shielding layer 11 located between the substrate 9 and the semiconductor layer 10. Wherein, the power signal line PVDD is arranged in the same layer as the light shielding layer 11.

[0056] It can be understood that the pixel circuit 2 includes a plurality of transistors 12, in combination with Figure 2For example, the pixel circuit 2 includes a driving transistor M0, a gate reset transistor M1, a data write transistor M2, a threshold compensation transistor M3, an anode reset transistor M4, a first light emitting control transistor M5, and a second light emitting control transistor M6. The transistor 12 includes an active layer p, a gate g, a first electrode s, and a second electrode d, wherein the active layer p is located in the semiconductor layer 10. In a direction perpendicular to the plane where the substrate 9 is located, the light shielding layer 11 can overlap the active layer p of the transistor 12 to avoid the influence of external ambient light on the channel of the active layer p, thereby improving the reliability of the working state of the transistor 12. In the embodiment of the present application, the power signal line PVDD and the light shielding layer 11 are arranged in the same layer, and the power signal line PVDD can be formed by the same patterning process as the light shielding layer 11, thereby simplifying the manufacturing process.

[0057] In a feasible implementation manner, as shown in Figure 10 Figure 10 FIG. 6 is another schematic diagram of a film layer structure of a display panel provided by the embodiment of the present application, and the display panel further includes a reset signal line Vref, which includes a first reset signal line Vref1 and a second reset signal line Vref2.

[0058] The first reset signal line Vref1 is electrically connected with the pixel circuit 2 and extends along a first direction x, and the second reset signal line Vref2 is electrically connected with the first reset signal line Vref1 and extends along a second direction y. The second reset signal line Vref2 is arranged in a layer different from the first data line D1 and the second data line D2, and in a direction perpendicular to the plane where the display panel is located, the second reset signal line Vref2 overlaps at least one of the first data line D1 and the second data line D2.

[0059] In this arrangement, the first reset signal line Vref1 and the second reset signal line Vref2 cross each other to form a grid structure, which can reduce the overall load of the reset signal line Vref, thereby reducing the voltage drop of the reset signal in the transmission process. Moreover, by arranging the second reset signal line Vref2 in a layer different from the first data line D1 and the second data line D2 and overlapping at least one of the first data line D1 and the second data line D2, the second reset signal line Vref2 can also act as a shielding line to reduce the coupling between the first data line D1 and the second data line D2, thereby reducing the mutual crosstalk of signals on the first data line D1 and the second data line D2.

[0060] Further referring to Figure 10 ​The second reset signal line Vref2 is arranged on the same layer as the power signal line PVDD. In the direction perpendicular to the plane where the display panel is located, the power signal line PVDD overlaps with one of the first data line D1 and the second data line D2, and the second reset signal line Vref2 overlaps with the other of the first data line D1 and the second data line D2.

[0061] For example, a power signal line PVDD overlaps with the first data line D1, and a second reset signal line Vref2 overlaps with the second data line D2. A coupling capacitor is formed between the power signal line PVDD and the first data line D1, shielding the first data line D1. When writing a data signal to the pixel circuit 2 via the second data line D2, this coupling capacitor reduces the effect of voltage jumps on the second data line D2 on the signal on the first data line D1. A coupling capacitor is formed between the second reset signal line Vref2 and the second data line D2, shielding the second data line D2. When writing a data signal to the pixel circuit 2 via the first data line D1, this coupling capacitor reduces the effect of voltage jumps on the first data line D1 on the signal on the second data line D2. This effectively reduces crosstalk between the signals on the first and second data lines D1 and D2, and reduces coupling between the first and second data lines D1 and D2.

[0062] Moreover, the second reset signal line Vref2 and the power signal line PVDD are provided in the same layer and formed by the same patterning process, and the second reset signal line Vref2 does not need to occupy additional film thickness.

[0063] In addition, Figure 2 Taking the pixel circuit 2 shown as an example, the structure and working principle of the pixel circuit 2 are described in the embodiment of the present invention:

[0064] See also Figure 2 The pixel circuit 2 includes a driving transistor M0, a gate reset transistor M1, a data writing transistor M2, a threshold compensation transistor M3, an anode reset transistor M4, a first light emission control transistor M5, a first light emission control transistor M6 and a storage capacitor Cst.

[0065] The gate of the gate reset transistor M1 is electrically connected to the first scan signal line S1 , the first electrode of the gate reset transistor M1 is electrically connected to the reset signal line Vref, and the second electrode of the gate reset transistor M1 is electrically connected to the gate of the driving transistor M0 .

[0066] The gate of the anode reset transistor M4 is electrically connected with the second scan signal line S2, the first pole of the anode reset transistor M4 is electrically connected with the reset signal line Vref, and the second pole of the anode reset transistor M4 is electrically connected with the anode of the light emitting element D.

[0067] The gate of the data write transistor M2 is electrically connected with the second scan signal line S2, the first pole of the data write transistor M2 is electrically connected with the first data line D1 or the second data line D2, and the second pole of the data write transistor M2 is electrically connected with the first pole of the drive transistor M0.

[0068] The gate of the threshold compensation transistor M3 is electrically connected with the second scan signal line S2, the first pole of the threshold compensation transistor M3 is electrically connected with the second pole of the drive transistor M0, and the second pole of the threshold compensation transistor M3 is electrically connected with the gate of the drive transistor M0.

[0069] The gate of the first light emitting control transistor M5 is electrically connected with the light emitting control signal line Emit, the first pole of the first light emitting control transistor M5 is electrically connected with the power signal line PVDD, and the second pole of the first light emitting control transistor M5 is electrically connected with the first pole of the drive transistor M0.

[0070] The gate of the second light emitting control transistor M6 is electrically connected with the light emitting control signal line Emit, the first pole of the second light emitting control transistor M6 is electrically connected with the second pole of the drive transistor M0, and the second pole of the second light emitting control transistor M6 is electrically connected with the anode of the light emitting element D.

[0071] The first pole plate of the storage capacitor Cst is electrically connected with the power signal line PVDD, and the second pole plate of the storage capacitor Cst is electrically connected with the gate of the drive transistor M0.

[0072] It should be noted that, for the two adjacent rows of pixel circuits 2, the second scan signal line S2 electrically connected with the previous row of pixel circuits 2 and the first scan signal line S1 electrically connected with the next row of pixel circuits 2 receive the same signal, that is, the second scan signal line S2 corresponding to the previous row of pixel circuits 2 and the first scan signal line S1 corresponding to the next row of pixel circuits 2 are electrically connected with each other, so that, in the initialization period t1, the anode reset transistor M4 of the pixel circuit 2 in the previous row of pixel circuits 2 is in the on state, and the anode reset transistor M4 of the pixel circuit 2 in the next row of pixel circuits 2 is also in the on state. Figure 3 In the schematic film layer structure, the gate of the anode reset transistor M4 in the pixel circuit 2 is connected to the first scan signal line S1 of the next row, which can also be regarded as being electrically connected with the second scan signal line S2 corresponding to the pixel circuit 2.

[0073] Based on the above circuit structure, as shown in Figure 11 , Figure 11 for Figure 2 a corresponding timing diagram, the driving period of the pixel circuit 2 includes an initialization period t1, a data write period t2, and a light emitting control period t3.

[0074] In the initialization period t1, the first scan signal line S1 provides a low level, the gate reset transistor M1 writes the reset signal provided by the reset signal line Vref into the gate of the drive transistor M0, and the gate of the drive transistor M0 is reset.

[0075] In the data writing period t2, the second scan signal line S2 provides a low level, the data writing transistor M2 writes the data signal provided by the data line Data into the first electrode of the drive transistor M0, the threshold compensation transistor M3 writes the data signal into the gate of the drive transistor M0, and the drive transistor M0 is threshold compensated. At the same time, the anode reset transistor M4 writes the reset signal provided by the reset signal line Vref into the anode of the light emitting element D, and the anode of the light emitting element D is reset.

[0076] In the light emitting control period t3, the light emitting control signal line Emit provides a low level, the first light emitting control transistor M5 writes the power signal provided by the power signal line PVDD into the first electrode of the drive transistor M0, the second light emitting control transistor M6 transmits the drive current converted by the drive transistor M0 according to the power signal and the data signal to the anode of the light emitting element D, and the light emitting element D is driven to emit light.

[0077] Based on the same inventive concept, the embodiment of the present application also provides a display device, as shown in Figure 12 as shown in Figure 12 A structural schematic diagram of the display device provided by the embodiment of the present application is shown in the figure, and the display device comprises the above-mentioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above-mentioned embodiment, and will not be described here again. Of course, Figure 12 The display device shown in the figure is only for illustrative purposes, and the display device can be any electronic device with display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper or a television.

[0078] The above-mentioned is only the preferred embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0079] Finally, it should be pointed out that: the above-mentioned embodiments are only used to illustrate the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above-mentioned embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: a plurality of pixel columns arranged along a first direction, the pixel columns including a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; a first data line and a second data line extending along the second direction, wherein one of the first data lines is electrically connected to the pixel circuits located in odd rows in one of the pixel columns, and one of the second data lines is electrically connected to the pixel circuits located in even rows in one of the pixel columns; a power signal line extending along the second direction, the power signal line being electrically connected to the pixel circuit, and the power signal line being arranged in a different layer from the first data line and the second data line, and overlapping with at least one of the first data line and the second data line in a direction perpendicular to a plane of the display panel; The power signal line includes a first sub-power signal line and a second sub-power signal line arranged in different layers; Wherein, the first data line and the second data line are located in a first metal layer, the first sub-power signal line is located in a third metal layer, the second sub-power signal line is located in a fourth metal layer, and the first metal layer is located between the third metal layer and the fourth metal layer; In a direction perpendicular to the plane of the display panel, the first sub-power signal line overlaps with at least one of the first data line and the second data line, and the second sub-power signal line overlaps with at least one of the first data line and the second data line.

2. A display panel, characterized in that: include: a plurality of pixel columns arranged along a first direction, the pixel columns including a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; a first data line and a second data line extending along the second direction, wherein one of the first data lines is electrically connected to the pixel circuits located in odd rows in one of the pixel columns, and one of the second data lines is electrically connected to the pixel circuits located in even rows in one of the pixel columns; a power signal line extending along the second direction, the power signal line being electrically connected to the pixel circuit, and the power signal line being arranged in a different layer from the first data line and the second data line, and overlapping with at least one of the first data line and the second data line in a direction perpendicular to a plane of the display panel; The display panel further includes a reset signal line, and the reset signal line includes: a first reset signal line extending along the first direction, the first reset signal line being electrically connected to the pixel circuit; a second reset signal line extending along the second direction, the second reset signal line being electrically connected to the first reset signal line; The second reset signal line is arranged in a different layer from the first data line and the second data line, and overlaps with at least one of the first data line and the second data line in a direction perpendicular to the plane of the display panel.

3. The display panel according to claim 2, wherein: The second reset signal line is arranged on the same layer as the power signal line; In a direction perpendicular to a plane where the display panel is located, the power signal line overlaps with one of the first data line and the second data line, and the second reset signal line overlaps with the other of the first data line and the second data line.

4. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 3.

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