Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same, wherein the semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source / drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, the first gate oxide layer including a main portion and an edge portion, and the edge portion has an inclined sidewall. The first source / drain doped region is disposed in the semiconductor substrate and adjacent to the edge portion of the first gate oxide layer. The first source / drain doped region includes a first portion and a second portion. The first portion is disposed vertically below the edge portion of the first gate oxide layer, and the second portion is connected to the first portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device with a gate oxide layer and a manufacturing method thereof. Background Art

[0002] In integrated circuits, transistor components often have different structures to meet the requirements of different operating voltages. For example, transistors corresponding to lower operating voltages can be used in core components, input / output (I / O) components, etc., while transistors with high-voltage processing capabilities can be used in high-voltage operating environments, such as central processing unit power supply (CPU power supply), power management system (power management system), DC / AC converter (AC / DC converter) and power amplifier, etc. However, in order to form transistors corresponding to different operating voltages on the same wafer or chip, the overall manufacturing process is often complicated and the manufacturing processes of different transistors affect each other. Therefore, how to improve the operating performance of related semiconductor devices or / and simplify the manufacturing process steps through structural and / or manufacturing process design is a direction of continuous research by people in related fields. Summary of the Invention

[0003] The invention provides a semiconductor device and a manufacturing method thereof, which utilizes a gate oxide layer with an inclined sidewall to improve the leakage performance of the semiconductor device.

[0004] One embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate, a first gate oxide layer, and a first source / drain doped region. The first gate oxide layer is disposed on the semiconductor substrate. The first gate oxide layer includes a main portion and an edge portion, and the edge portion has an inclined sidewall. The first source / drain doped region is disposed in the semiconductor substrate and adjacent to the edge portion of the first gate oxide layer. The first source / drain doped region includes a first portion and a second portion. The first portion is disposed vertically below the edge portion of the first gate oxide layer, and the second portion is connected to the first portion.

[0005] One embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. A first gate oxide layer is formed on a semiconductor substrate. The first gate oxide layer includes a main portion and an edge portion, and the edge portion has an inclined sidewall. A first source / drain doped region is formed in the semiconductor substrate. The first source / drain doped region is disposed adjacent to the edge portion of the first gate oxide layer. The first source / drain doped region includes a first portion and a second portion. The first portion is disposed vertically below the edge portion of the first gate oxide layer, and the second portion is connected to the first portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention;

[0007] Figure 2 is a schematic diagram of a first transistor structure according to a first embodiment of the present invention;

[0008] Figures 3 to 10 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein

[0009] Figure 4 for Figure 3 Schematic diagram of the subsequent production method;

[0010] Figure 5 for Figure 4 Schematic diagram of the subsequent production method;

[0011] Figure 6 for Figure 5 Schematic diagram of the subsequent production method;

[0012] Figure 7 for Figure 6 Schematic diagram of the subsequent production method;

[0013] Figure 8 for Figure 7 Schematic diagram of the subsequent production method;

[0014] Figure 9 for Figure 8 A schematic diagram of the subsequent production method; and

[0015] Figure 10 for Figure 9 Schematic diagram of the subsequent production method;

[0016] Figure 11 FIG. 1 is a schematic diagram of a semiconductor device according to a second embodiment of the present invention.

[0017] Description of main component symbols

[0018] 10 Semiconductor substrate

[0019] 12 Lightly doped source / drain regions

[0020] 14 Lightly doped source / drain regions

[0021] 20 Oxide layer

[0022] 22. First gate oxide layer

[0023] 22A Edge

[0024] 22B Main part

[0025] 24 Second gate oxide layer

[0026] 30 dummy gate material layer

[0027] 30A first dummy gate structure

[0028] 30B Second dummy gate structure

[0029] 32 Covering layer

[0030] 32A gate cap layer

[0031] 32B gate cap layer

[0032] 34 cap layer

[0033] 34A gate cap layer

[0034] 34B gate cap layer

[0035] 42 first source / drain doping region

[0036] 42A Part 1

[0037] 42B Part 2

[0038] 44 Second source / drain doping region

[0039] 52 first metal silicide layer

[0040] 54 second metal silicide layer

[0041] 62 Etch stop layer

[0042] 64 dielectric layer

[0043] 70 gate dielectric layer

[0044] 90 Doping Process

[0045] 101 Semiconductor Devices

[0046] 102 Semiconductor devices

[0047] AG angle

[0048] BS bottom surface

[0049] BS1 bottom surface

[0050] BS2 bottom surface

[0051] D1 First direction

[0052] D2 Second direction

[0053] D3 third direction

[0054] DP1 Depth

[0055] DP2 Depth

[0056] DS1 distance

[0057] DS2 distance

[0058] DS3 distance

[0059] DS4 distance

[0060] DS5 distance

[0061] GS1 first gate structure

[0062] GS2 second gate structure

[0063] L1 length

[0064] L2 length

[0065] L3 length

[0066] MG1 first metal gate structure

[0067] MG2 second metal gate structure

[0068] R1 Zone 1

[0069] R2 Second Zone

[0070] S1 First spacer structure

[0071] S11 spacer

[0072] S12 spacer

[0073] S13 spacer

[0074] S2 Second spacer structure

[0075] S21 spacer

[0076] S22 spacer

[0077] S23 spacer

[0078] SW Sloping Sidewall

[0079] T1 first transistor structure

[0080] T2 Second transistor structure

[0081] TK1 thickness

[0082] TK2 thickness

[0083] TK3 thickness

[0084] TS top surface

[0085] TS1 top surface

[0086] TS2 top surface DETAILED DESCRIPTION

[0087] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the present invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present invention.

[0088] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0089] The terms “on,” “over,” and “over” should be interpreted in the broadest sense, so that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0090] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify claim elements. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0091] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0092] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0093] See also Figure 1 and Figure 2 . Figure 1 FIG. 1 is a schematic diagram of a semiconductor device 101 according to a first embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram of the first transistor structure T1 of this embodiment, and Figure 2 Can be considered as Figure 1 The left half is enlarged. Figure 1 and Figure 2 As shown, the present embodiment provides a semiconductor device 101, which includes a semiconductor substrate 10, a first gate oxide layer 22, and a first source / drain doping region 42. The first gate oxide layer 22 is disposed on the semiconductor substrate 10. The first gate oxide layer 22 includes an edge portion 22A and a main portion 22B, and the edge portion 22A has an inclined sidewall SW. The first source / drain doping region 42 is disposed in the semiconductor substrate 10 and is adjacent to the edge portion 22A of the first gate oxide layer 22. The first source / drain doping region 42 includes a first portion 42A and a second portion 42B, the second portion 42B is connected to the first portion 42A, and the first portion 42A is perpendicular to the direction (e.g., Figure 1 The first gate oxide layer 22 is disposed below the edge portion 22A of the first gate oxide layer 22 in the first direction D1 shown in FIG. The edge portion 22A having the sloped sidewall SW can have an impact during the fabrication process of forming the first source / drain doped region 42, thereby correspondingly forming the first portion 42A of the first source / drain doped region 42. Therefore, the first gate oxide layer 22 having the sloped sidewall SW can be used to control the range and shape of the first source / drain doped region 42, thereby achieving the effect of improving the electrical performance of the semiconductor device 101.

[0094] In some embodiments, the first direction D1 can be considered as the thickness direction of the semiconductor substrate 10, and the semiconductor substrate 10 can have a top surface TS and a bottom surface BS opposite to each other in the first direction D1, and the first gate oxide layer 22 can be disposed on one side of the top surface TS, but is not limited thereto. A horizontal direction substantially perpendicular to the first direction D1 (e.g. Figure 1 The second direction D2 and the third direction D3 shown in the figure may be substantially parallel to the top surface TS and / or the bottom surface BS of the semiconductor substrate 10, but are not limited thereto. Furthermore, as described herein, the distance between a relatively higher position or / and component in the vertical direction (e.g., the first direction D1) and the bottom surface BS of the semiconductor substrate 10 in the first direction D1 is greater than the distance between a relatively lower position or / and component in the first direction D1 and the bottom surface BS of the semiconductor substrate 10 in the first direction D1. The lower portion or bottom of each component may be closer to the bottom surface BS of the semiconductor substrate 10 in the first direction D1 than the upper portion or top of the component. A component above a component may be considered to be relatively farther from the bottom surface BS of the semiconductor substrate 10 in the first direction D1, while a component below a component may be considered to be relatively closer to the bottom surface BS of the semiconductor substrate 10 in the first direction D1.

[0095] To further illustrate, in some embodiments, the semiconductor substrate 10 may include a first region R1 and a second region R2, the first gate oxide layer 22 may be disposed on the first region R1 of the semiconductor substrate 10, and the first source / drain doped region 42 may be disposed in the first region R1 of the semiconductor substrate 10. Furthermore, in some embodiments, the semiconductor device 101 may further include a lightly doped source / drain region 12, a first gate structure GS1, a first spacer structure S1, and a first metal silicide layer 52. The lightly doped source / drain region 12 may be disposed in the first region R1 of the semiconductor substrate 10 and partially below the first gate oxide layer 22 in the first direction D1, and the first source / drain doped region 42 may be disposed in the lightly doped source / drain region 12. The first gate structure GS1 may be disposed on the main portion 22B of the first gate oxide layer 22, the first spacer structure S1 may be disposed on the main portion 22B of the first gate oxide layer 22 and located on the sidewalls of the first gate structure GS1, and the first metal silicide layer 52 may be at least partially disposed in the second portion 42B of the first source / drain doped region 42. An edge portion 22A of the first gate oxide layer 22 may be located between the first spacer structure S1 and the first metal silicide layer 52 in a first horizontal direction (e.g., the second direction D2 described above), and the first portion 42A of the first source / drain doped region 42 may also be located between the first spacer structure S1 and the first metal silicide layer 52 in the second direction D2.

[0096] In some embodiments, the semiconductor device 101 may include two lightly doped source / drain regions 12, two first source / drain doped regions 42, and two first metal silicide layers 52, respectively located on two opposite sides of the first gate structure GS1 in the first horizontal direction, thereby forming Figure 1 , but is not limited thereto. In other words, the first transistor structure T1 may include a lightly doped source / drain region 12, a first source / drain doped region 42, a first metal silicide layer 52, a first gate oxide layer 22, a first gate structure GS1, and a first spacer structure S1. In some embodiments, the dopant concentration of the first source / drain doped region 42 may be higher than the dopant concentration of the lightly doped source / drain region 12. For example, the lightly doped source / drain region 12 may be an n-type lightly doped region and the first source / drain doped region 42 may be an n-type heavily doped region, but is not limited thereto. In some embodiments, the lightly doped source / drain region 12 may be a p-type lightly doped region and the first source / drain doped region 42 may be a p-type heavily doped region.

[0097] In some embodiments, the first portion 42A of the first source / drain doped region 42 can be considered a protrusion of the first source / drain doped region 42 toward the first gate structure GS1. Therefore, the first portion 42A of the first source / drain doped region 42 can be located between the main portion 22B of the first gate oxide layer 22 and the second portion 42B of the first source / drain doped region 42 in a first horizontal direction (e.g., the second direction D2). Furthermore, a bottom surface BS2 of the second portion 42B of the first source / drain doped region 42 can be lower than a bottom surface BS1 of the first portion 42A of the first source / drain doped region 42 in the first direction D1. In other words, a depth DP2 of the second portion 42B of the first source / drain doped region 42 in the first direction D1 can be greater than a depth DP1 of the first portion 42A of the first source / drain doped region 42 in the first direction D1, and a dopant concentration of the first portion 42A of the first source / drain doped region 42 can be substantially equal to a dopant concentration of the second portion 42B of the first source / drain doped region 42. In some embodiments, the depth in the first direction D1 can also be regarded as the length in the first direction D1, so the length of the first portion 42A of the first source / drain doping region 42 in the first direction D1 can be smaller than the length of the second portion 42B of the first source / drain doping region 42 in the first direction D1, but is not limited thereto.

[0098] In some embodiments, the edge portion 22A of the first gate oxide layer 22 may surround the main portion 22B in a horizontal direction (e.g., the second direction D2 or other horizontal directions orthogonal to the first direction D1) and be directly connected to the main portion 22B. The length L2 of the main portion 22B in the second direction D2 may be greater than the length L1 of the edge portion 22A in the second direction D2. In addition, in some embodiments, due to the influence of the manufacturing process, the thickness of the main portion 22B of the first gate oxide layer 22 located below the first gate structure GS1 in the first direction D1 may be greater than the thickness of the main portion 22B of the first gate oxide layer 22 located below the first spacer structure S1 in the first direction D1. Therefore, the top surface TS2 of the first gate oxide layer 22 located below the first spacer structure S1 may be lower than the top surface TS1 of the first gate oxide layer 22 located below the first gate structure GS1 in the first direction D1, but this is not limited to this. Furthermore, in some embodiments, the inclined sidewall SW of the edge portion 22A may be directly connected to the aforementioned top surface TS2, and the edge portion 22A of the first gate oxide layer 22 may be regarded as a region of the first gate oxide layer 22 that is not below the top surface TS1 and the top surface TS2. Therefore, the thickness TK3 of the edge portion 22A of the first gate oxide layer 22 may be less than the thickness TK1 of the main portion 22B of the first gate oxide layer 22, and the thickness TK3 may be regarded as the maximum thickness of the edge portion 22A, but is not limited thereto.

[0099] In some embodiments, the edge portion 22A having the inclined sidewall SW may be used to form the first portion 42A of the first source / drain doped region 42 and may increase the distance between the first metal silicide layer 52 and the first gate structure GS1 in the horizontal direction (eg, the second direction D2) (eg, Figure 1), thereby changing the electric field distribution between the first metal silicide layer 52 and the first gate structure GS1 and reducing the leakage current (leakage current, Ioff) of the first transistor structure T1. In other words, the edge portion 22A having the inclined sidewall SW can increase the distance between the first source / drain doping region 42 and the first gate structure GS1 without significantly increasing the distance in the horizontal direction between the first source / drain doping region 42 and the first gate structure GS1. In addition, in some embodiments, the angle AG between the inclined sidewall SW of the edge portion 22A of the first gate oxide layer 22 and the upper surface TS of the semiconductor substrate 10 can be less than or equal to 45 degrees, thereby avoiding the length L1 of the edge portion 22A in the horizontal direction being too short and affecting the effect of increasing the distance between the first metal silicide layer 52 and the first gate structure GS1, but the present invention is not limited thereto. In some embodiments, influenced by the fabrication process, the inclined sidewall SW of the edge portion 22A of the first gate oxide layer 22 may include a downwardly recessed surface, and the bottom surface BS1 of the first portion 42A of the first source / drain doped region 42 may correspondingly include a curved surface disposed below the inclined sidewall SW of the edge portion 22A of the first gate oxide layer 22 in the first direction D1. In other words, the shape of the interface between the first portion 42A of the first source / drain doped region 42 and the lightly doped source / drain region 12 may be similar to, but is not limited to, the shape of the inclined sidewall SW of the edge portion 22A of the first gate oxide layer 22.

[0100] In some embodiments, the semiconductor device 101 may further include an etch stop layer 62 and a dielectric layer 64. The etch stop layer 62 may be disposed on the edge portion 22A of the first metal silicide layer 52 and the first gate oxide layer 22 and on the sidewalls of the first spacer structure S1, and the dielectric layer 64 may be disposed on the etch stop layer 62. In some embodiments, because the first metal silicide layer 52 and the first spacer structure S1 are separated from each other, the length L3 of the first spacer structure S1 in the second direction D2 may be less than the distance DS1 between the first metal silicide layer 52 and the first gate structure GS1 in the second direction D2. Furthermore, in some embodiments, because the shape and area of ​​the first source / drain doped region 42 are not primarily defined by the first spacer structure S1, the top surface TS2 of the main portion 22B of the first gate oxide layer 22 may not be completely covered by the first spacer structure S1, but this is not limited to this. In this case, the distance DS3 between the first metal silicide layer 52 and the first spacer structure S1 in the second direction D2 may be greater than the length L1 of the edge portion 22A of the first gate oxide layer 22 in the second direction D2, the length L2 of the main portion 22B of the first gate oxide layer 22 in the second direction D2 may be greater than the sum of the lengths of the first spacer structure S1 and the first gate structure GS1 in the second direction D2, and the etching stop layer 62 may directly contact a portion of the upper surface TS2 and the inclined side wall SW of the edge portion 22A, but is not limited to this.

[0101] In some embodiments, the semiconductor device 101 may further include a second transistor structure T2 at least partially disposed on the second region R2 of the semiconductor substrate 10. The second transistor structure T2 may include a second gate oxide layer 24, a second gate structure GS2, a second spacer structure S2, a lightly doped source / drain region 14, a second source / drain doped region 44, and a second metal silicide layer 54. The second gate oxide layer 24 may be disposed on the second region R2 of the semiconductor substrate 10, and the thickness TK1 of the first gate oxide layer 22 may be greater than the thickness TK2 of the second gate oxide layer 24. In some embodiments, gate oxide layers of different thicknesses may be used to achieve relatively high voltage and relatively low voltage operation. Therefore, the operating voltage of the first transistor structure T1 may be higher than the operating voltage of the second transistor structure T2. The first region R1 may be considered a relatively high voltage transistor region, and the second region R2 may be considered a relatively low voltage transistor region, but the present invention is not limited thereto. The second gate structure GS2 may be disposed on the second gate oxide layer 24, and the second spacer structure S2 may be disposed on the sidewalls of the second gate structure GS2 and the sidewalls of the second gate oxide layer 24. The lightly doped source / drain region 14 may be disposed in the second region R2 of the semiconductor substrate 10 and partially below the second gate oxide layer 24 in the first direction D1, while the second source / drain doped region 44 may be disposed in the semiconductor substrate 10 and in the lightly doped source / drain region 14, and the second source / drain doped region 44 may be disposed adjacent to the second spacer structure S2.

[0102] In some embodiments, the second metal silicide layer 54 may be at least partially disposed in the second source / drain doped region 44, and the second metal silicide layer 54 may be directly connected to the second spacer structure S2, so that the distance between the first metal silicide layer 52 and the first gate structure GS1 in the first horizontal direction (e.g., the distance DS1 described above) may be greater than the distance between the second metal silicide layer 54 and the second gate structure GS2 in the second horizontal direction (e.g., the distance DS2 described above). Figure 1 ). In some embodiments, the first horizontal direction and the second horizontal direction may be the same direction (for example, both may be the second direction D2) or different horizontal directions. In some embodiments, the semiconductor device 101 may include two lightly doped source / drain regions 14, two second source / drain doped regions 44, and two second metal silicide layers 54, respectively located on two opposite sides of the second gate structure GS2 in the second horizontal direction. In addition, in some embodiments, the etch stop layer 62 and the dielectric layer 64 may also be partially disposed on the second region R2 of the semiconductor substrate 10 and cover the sidewalls of the second metal silicide layer 54 and the second spacer structure S2, and the second gate oxide layer 24 may be covered by the second gate structure GS2 and the second spacer structure S2 without directly contacting the etch stop layer 62, but the present invention is not limited thereto.

[0103] In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. The lightly doped source / drain regions 12, the lightly doped source / drain regions 14, the first source / drain doping regions 42, and the second source / drain doping regions 44 may each include a doped region formed in the semiconductor substrate 10 using a doping process (e.g., an implantation process). In some embodiments, the lightly doped source / drain regions 12 and the lightly doped source / drain regions 14 may be formed simultaneously by the same process and have the same conductivity type, dopant, or / and similar dopant concentration. The first source / drain doping regions 42 and the second source / drain doping regions 44 may also be formed simultaneously by the same process and have the same conductivity type, dopant, or / and similar dopant concentration, but the present invention is not limited thereto. The above-mentioned dopants may include n-type dopants or p-type dopants. The n-type dopant may include phosphorus (P), arsenic (As) or other suitable n-type dopant materials, while the p-type dopant may include boron (B), gallium (Ga) or other suitable p-type dopant materials.

[0104] In some embodiments, the first gate structure GS1 may include a gate dielectric layer 70 and a first metal gate structure MG1, and the second gate structure GS2 may include the gate dielectric layer 70 and a second metal gate structure MG2, but the present invention is not limited thereto. The gate dielectric layer 70 may include a high-k dielectric material or other suitable dielectric material, and the first metal gate structure MG1 and the second metal gate structure MG2 may each include a metal gate structure formed by stacking a work function layer (not shown) and a low resistance layer (not shown), but the present invention is not limited thereto. The work function layer may include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium tri-aluminide (TiAl3), aluminum titanium nitride (TiAlN), or other suitable conductive work function materials. The low resistance layer may include, for example, tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable low resistance materials. In some embodiments, depending on the specifications of the first transistor structure T1 and the second transistor structure T2, the first metal gate structure MG1 and the second metal gate structure MG2 may have the same or different work function layer stack structures.

[0105] In some embodiments, the first metal silicide layer 52 and the second metal silicide layer 54 may include cobalt-silicide, nickel-silicide, or other suitable metal silicides. In addition, the first spacer structure S1 and the second spacer structure S2 may each include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. For example, the first spacer structure S1 may include a spacer S11 and a spacer S12 disposed outside the spacer S11 and made of a different material than the spacer S11, while the second spacer structure S2 may include a spacer S21 and a spacer S22 disposed outside the spacer S21 and made of a different material than the spacer S21, but the present invention is not limited thereto. In some embodiments, spacers S11 and S21 may be formed together using the same manufacturing process and have the same material composition (e.g., silicon nitride), while spacers S12 and S22 may be formed together using the same manufacturing process and have the same material composition (e.g., silicon oxide), but the present invention is not limited thereto. Furthermore, etch stop layer 62 may include silicon nitride or other suitable insulating materials, while dielectric layer 64 may include silicon oxide or other dielectric materials different from etch stop layer 62.

[0106] See also Figures 1 to 10 . Figures 3 to 10 The figure shows a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 4 Draws Figure 3 Schematic diagram of the subsequent production method, Figure 5 Draws Figure 4 Schematic diagram of the subsequent production method, Figure 6 Draws Figure 5 Schematic diagram of the subsequent production method, Figure 7 Draws Figure 6 Schematic diagram of the subsequent production method, Figure 8 Draws Figure 7 Schematic diagram of the subsequent production method, Figure 9 Draws Figure 8 Schematic diagram of the subsequent production method, Figure 10 Draws Figure 9 The following is a schematic diagram of the production method. Figure 1 can be considered as depicting Figure 10 Schematic diagram of the situation afterward. Figure 1 and Figure 2As shown, the method for manufacturing the semiconductor device 101 of this embodiment may include the following steps. A first gate oxide layer 22 is formed on a semiconductor substrate 10. The first gate oxide layer 22 includes a main portion 22B and an edge portion 22A, and the edge portion 22A may have a sloped sidewall SW. A first source / drain doped region 42 is formed in the semiconductor substrate 10, and the first source / drain doped region 42 is disposed adjacent to the edge portion 22A of the first gate oxide layer 22. The first source / drain doped region 42 includes a first portion 42A and a second portion 42B. The second portion 42B is connected to the first portion 42A, and the first portion 42A is disposed below the edge portion 22A of the first gate oxide layer 22 in a vertical direction (e.g., a first direction D1).

[0107] To further illustrate, the manufacturing method of this embodiment may include but is not limited to the following steps. Figure 3 As shown, an oxide layer 20 can be formed on the entire semiconductor substrate 10, so the oxide layer 20 can be formed on the first region R1 and the second region R2. In some embodiments, the oxide layer 20 can be formed on the semiconductor substrate 10 using a thermal oxidation process, other suitable oxidation methods, or other suitable film formation methods (such as a deposition process). In addition, in some embodiments, before the oxide layer 20 is formed, a lightly doped source / drain region 12 can be formed in the first region R1 of the semiconductor substrate 10, and the lightly doped source / drain region 12 can be formed in the first region R1 of the semiconductor substrate 10 by a doping process, but is not limited thereto. Then, as Figures 3 and 4 As shown, a portion of the oxide layer 20 on the first region R1 and the oxide layer 20 on the second region R2 can be removed simultaneously to form a first gate oxide layer 22 on the first region R1 and simplify the manufacturing process steps. In some embodiments, a mask layer (not shown) can be used to cover the area of ​​the oxide layer 20 to be retained and the mask layer can be used as an etching mask to perform an etching process to remove the oxide layer 20 on the second region R2 and the oxide layer 20 on the first region R1 covering the area corresponding to the subsequent source / drain region. The edge portion 22A of the formed first gate oxide layer 22 can have a sloped sidewall SW due to the etching characteristics of the etching process. In some embodiments, the etching process can include a wet etching process or other etching methods that can be used to form the desired sloped sidewall SW.

[0108] Then, if Figures 3 to 5As shown, after removing the oxide layer 20 on the second region R2, a second gate oxide layer 24 may be formed on the second region R2, and the thickness of the first gate oxide layer 22 may be greater than the thickness of the second gate oxide layer 24. In some embodiments, the second gate oxide layer 24 may be formed on the semiconductor substrate 10 using a thermal oxidation process or other suitable oxidation method, so the second gate oxide layer 24 may also be partially formed on the first region R1, but the present invention is not limited thereto. Figures 5 and 6 As shown, a first dummy gate structure 30A, a gate cap layer 32A, and a gate cap layer 34A can be formed on the first gate oxide layer 22, and a second dummy gate structure 30B, a gate cap layer 32B, and a gate cap layer 34B can be formed on the second gate oxide layer 24. In some embodiments, the first dummy gate structure 30A and the second dummy gate structure 30B can be formed simultaneously by patterning the same material layer (e.g., the dummy gate material layer 30). Therefore, the first dummy gate structure 30A and the second dummy gate structure 30B can be composed of the same material, but are not limited to this. The dummy gate material layer 30 may include polysilicon or other suitable dummy gate materials. In some embodiments, the gate cap layer 32A, the gate cap layer 34A, the gate cap layer 32B, and the gate cap layer 34B can each include silicon oxide, silicon nitride, or other suitable insulating materials. Furthermore, the gate capping layer 32A and the gate capping layer 34A may have different material compositions, and the gate capping layer 32B and the gate capping layer 34B may have different material compositions, thereby providing a desired etching selectivity in subsequent fabrication processes, but the present invention is not limited thereto. For example, in some embodiments, the gate capping layer 32A and the gate capping layer 32B may be formed simultaneously by patterning the same material layer (e.g., the capping layer 32), and the gate capping layer 34A and the gate capping layer 34B may be formed simultaneously by patterning the same material layer (e.g., the capping layer 34). The material composition of the capping layer 34 (e.g., silicon oxide) may be different from the material composition of the capping layer 32 (e.g., silicon nitride), but the present invention is not limited thereto.

[0109] Then, spacers S11 may be formed on the sidewalls of the first dummy gate structure 30A, the gate cap layer 32A, and the gate cap layer 34A, and spacers S21 may be formed on the sidewalls of the second dummy gate structure 30B, the gate cap layer 32B, and the gate cap layer 34B. In some embodiments, a portion of the first gate oxide layer 22 may be removed during the steps of forming the first dummy gate structure 30A, the gate cap layer 32A, and / or the gate cap layer 34A. Therefore, the upper surface of the first gate oxide layer 22 below the spacer S11 may be slightly lower than the upper surface of the first gate oxide layer 22 below the first dummy gate structure 30A in the first direction D1, but the present invention is not limited thereto. Furthermore, the second gate oxide layer 24 formed on the first region R1 may be removed during the steps of forming the first dummy gate structure 30A, the gate cap layer 32A, the gate cap layer 34A, and / or the spacer S11. In some embodiments, the lightly doped source / drain regions 14 may be formed in the second region R2 of the semiconductor substrate 10 through a doping process after the spacers S21 are formed, but the present invention is not limited thereto.

[0110] like Figures 6 and 7 As shown, after the lightly doped source / drain region 14 is formed, a spacer S12 and a spacer S13 may be formed outside the spacer S11, and a spacer S22 and a spacer S23 may be formed outside the spacer S21. In some embodiments, the spacer S13 and the spacer S23 may be formed together using the same manufacturing process and have the same material composition (e.g., silicon nitride), and the spacers S12, S13, S22, and S23 may be formed together by patterning two spacer material layers (e.g., a silicon oxide layer and a silicon nitride layer) conformally formed on the semiconductor substrate 10, the first gate oxide layer 22, the spacer S11, the gate cap layer 34A, the spacer S21, and the gate cap layer 34B. Therefore, the spacers S12 and S22 may have an L-shaped structure in the cross-sectional view, but are not limited thereto.

[0111] Furthermore, in some embodiments, the spacers S13 and S23 may be removed together in subsequent fabrication processes. Therefore, the spacers S11 and S12 may be considered as a first spacer structure S1 formed on the sidewalls of the first dummy gate structure 30A, the gate cap layer 32A, and the gate cap layer 34A, while the spacers S21 and S22 may be considered as a second spacer structure S2 formed on the sidewalls of the second dummy gate structure 30B, the gate cap layer 32B, and the gate cap layer 34B, but the present invention is not limited thereto. In some embodiments, the first spacer structure S1 may be formed on the main portion 22B of the first gate oxide layer 22, and the upper surface of the first gate oxide layer 22 located below the first spacer structure S1 may be slightly lower in the first direction D1 than the upper surface of the first gate oxide layer 22 located below the first dummy gate structure 30A, but the present invention is not limited thereto. In some embodiments, the main portion 22B and the edge portion 22A of the first gate oxide layer 22 may be slightly etched by the process (e.g., etching process) for forming the above-mentioned spacers, but the edge portion 22A of the first gate oxide layer 22 may have the inclined sidewall SW before and after the first spacer structure S1 is formed. In other words, Figures 4 to 7 As shown, in some embodiments, the inclined sidewall SW of the edge portion 22A of the first gate oxide layer 22 may be formed before the first dummy gate structure 30A and the first spacer structure S1, and the edge portion 22A of the first gate oxide layer 22 may still have the inclined sidewall SW after the first spacer structure S1 and the spacer S13 are formed.

[0112] Then, if Figure 8As shown, a first source / drain doped region 42 and a second source / drain doped region 44 may be formed in the first region R1 and the second region R2 of the semiconductor substrate 10, respectively. In some embodiments, the first source / drain doped region 42 and the second source / drain doped region 44 may be formed in the lightly doped source / drain region 12 and the lightly doped source / drain region 14, respectively. The dopant concentration of the first source / drain doped region 42 may be higher than the dopant concentration of the lightly doped source / drain region 12, and the dopant concentration of the second source / drain doped region 44 may be higher than the dopant concentration of the lightly doped source / drain region 14. In some embodiments, the second source / drain doped region 44 and the first source / drain doped region 42 may be formed together by the same fabrication process (e.g., doping fabrication process 90), thereby achieving the effect of simplifying the fabrication process steps, but the present invention is not limited thereto. The doping fabrication process 90 may include an ion implantation process or other suitable doping methods. In some embodiments, because the first gate oxide layer 22 is relatively thick and the first spacer structure S1 does not cover the edge portion 22A of the first gate oxide layer 22, the shape of the first source / drain doped region 42 is primarily influenced by the edge portion 22A, resulting in the first portion 42A and the second portion 42B of the first source / drain doped region 42. For example, because the edge portion 22A of the first gate oxide layer 22 has a sloped sidewall SW, the thickness of the edge portion 22A of the first gate oxide layer 22 may decrease in a direction away from the first dummy gate structure 30A. Consequently, the depth of the first portion 42A of the first source / drain doped region 42 may increase in a direction away from the first dummy gate structure 30A. Furthermore, the second portion 42B of the first source / drain doped region 42 may not overlap with the first gate oxide layer 22 in the first direction D1 and, therefore, may be deeper than the first portion 42A of the first source / drain doped region 42.

[0113] Afterwards, if Figures 8 and 9As shown, a first metal silicide layer 52 and a second metal silicide layer 54 can be formed. In some embodiments, the first metal silicide layer 52 and the second metal silicide layer 54 can be formed simultaneously by the same manufacturing process and have the same material composition, thereby achieving the effect of simplifying the manufacturing process steps, but is not limited to this. For example, a metal layer (not shown) can be formed throughout, and this metal layer can directly contact the first source / drain doping region 42 and the second source / drain doping region 44. Then, a heat treatment can be performed to allow the metal layer to react with the first source / drain doping region 42 and the second source / drain doping region 44 to form the first metal silicide layer 52 and the second metal silicide layer 54. After the first metal silicide layer 52 and the second metal silicide layer 54 are formed, this metal layer can be removed. In some embodiments, the metal layer may include cobalt, nickel, or other suitable metal materials, and the first metal silicide layer 52 and the second metal silicide layer 54 may include cobalt-metal silicide, nickel-metal silicide, or other silicides of metal materials corresponding to the metal layers. In some embodiments, the edge portion 22A of the first gate oxide layer 22 may be located between the first spacer structure S1 and the first metal silicide layer 52 in a horizontal direction (e.g., the second direction D2), and the second metal silicide layer 54 may directly contact the second spacer structure S2. Therefore, the distance DS4 between the first metal silicide layer 52 and the first dummy gate structure 30A in the first horizontal direction (e.g., but not limited to the second direction D2) may be greater than the distance DS5 between the second metal silicide layer 54 and the second dummy gate structure 30B in the second horizontal direction (e.g., but not limited to the second direction D2).

[0114] Then, if Figures 9 and 10 As shown, an etch stop layer 62 and a dielectric layer 64 can be formed, and a planarization process can be used to remove the gate cap layer 32A, the gate cap layer 32B, the gate cap layer 34A, the gate cap layer 34B, a portion of the first spacer structure S1, a portion of the second spacer structure S2, a portion of the etch stop layer 62, and a portion of the dielectric layer 64, thereby exposing the first dummy gate structure 30A and the second dummy gate structure 30B. The above-mentioned planarization process may include a chemical mechanical polishing (CMP) process, an etch back process, or other suitable planarization methods. In addition, in some embodiments, the spacers S13 and the spacers S23 may be removed by other processes before the etch stop layer 62 is formed, so that the etch stop layer 62 may directly cover the first spacer structure S1 and the second spacer structure S2, but is not limited thereto. Then, as Figure 10 and Figure 1As shown, the first dummy gate structure 30A and the second dummy gate structure 30B can be removed to form the first gate structure GS1 and the second gate structure GS2 respectively, thereby forming the semiconductor device 101 described above. Figures 3 to 10 The illustrated condition is limited and other suitable manufacturing methods may be used to form the semiconductor device 101 depending on the design requirements.

[0115] The following description will focus on different embodiments of the present invention. To simplify the description, the following description will focus on the different parts of each embodiment, and will not repeat the same parts. In addition, the same components in each embodiment of the present invention are marked with the same reference numerals to facilitate cross-reference between the embodiments.

[0116] See also Figure 11 . Figure 11 FIG. 1 is a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention. Figure 11 As shown, in some embodiments, the first metal silicide layer 52 may partially extend into the first portion 42A of the first source / drain doping region 42, and the first metal silicide layer 52 may be partially located under the edge portion 22A of the first gate oxide layer 22 and the inclined sidewall SW in the first direction D1, but the required distance DS1 may still be maintained between the first metal silicide layer 52 and the first gate structure GS1, thereby achieving the effect of reducing the leakage current of the first transistor structure T1.

[0117] In summary, in the semiconductor device and its fabrication method of the present invention, a gate oxide layer with sloped sidewalls can be utilized to improve the leakage performance of the semiconductor device. Furthermore, the first gate oxide layer with sloped sidewalls can be formed on the first region by removing the oxide layer on the second region, or / and the source / drain doped regions in the first region and the source / drain doped regions in the second region can be formed simultaneously using the same fabrication process, thereby simplifying the fabrication process and reducing related production costs.

[0118] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: semiconductor substrates; A first gate oxide layer is disposed on the semiconductor substrate, wherein the first gate oxide layer comprises: the main part; and a rim portion having an inclined sidewall; A first source / drain doped region is disposed in the semiconductor substrate and adjacent to the edge portion of the first gate oxide layer, wherein the first source / drain doped region includes: a first portion disposed below the edge portion of the first gate oxide layer in a vertical direction; and a second portion connected to the first portion; and A lightly doped source / drain region is arranged in the semiconductor substrate and partially located below the first gate oxide layer in the vertical direction, wherein the first source / drain doping region is arranged in the lightly doped source / drain region, and the dopant concentration of the first source / drain doping region is higher than the dopant concentration of the lightly doped source / drain region. 2 . The semiconductor device of claim 1 , wherein a bottom surface of the first portion of the first source / drain doped region comprises a curved surface disposed below the inclined sidewall of the edge portion of the first gate oxide layer in the vertical direction. 3 . The semiconductor device of claim 1 , wherein the inclined sidewall of the edge portion of the first gate oxide layer comprises a recessed surface.

4. The semiconductor device of claim 1 , wherein the first portion of the first source / drain doped region is located between the main portion of the first gate oxide layer and the second portion of the first source / drain doped region in a first horizontal direction, and a bottom surface of the second portion is lower than a bottom surface of the first portion in the vertical direction. 5 . The semiconductor device as claimed in claim 1 , wherein a length of the first portion of the first source / drain doping region in the vertical direction is smaller than a length of the second portion of the first source / drain doping region in the vertical direction. 6 . The semiconductor device as claimed in claim 1 , wherein an angle between the inclined sidewall of the edge portion of the first gate oxide layer and the upper surface of the semiconductor substrate is less than or equal to 45 degrees.

7. The semiconductor device according to claim 1 , further comprising: a first gate structure disposed on the main portion of the first gate oxide layer; a first spacer structure disposed on the main portion of the first gate oxide layer and on a sidewall of the first gate structure; and A first metal silicide layer is at least partially disposed in the second portion of the first source / drain doped region, wherein the edge portion of the first gate oxide layer is located between the first spacer structure and the first metal silicide layer in a first horizontal direction.

8. The semiconductor device according to claim 7, further comprising: a second gate oxide layer disposed on the semiconductor substrate, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; a second gate structure disposed on the second gate oxide layer; a second spacer structure, disposed on a sidewall of the second gate structure; A second source / drain doped region is disposed in the semiconductor substrate and adjacent to the second spacer structure; as well as A second metal silicide layer is at least partially disposed in the second source / drain doping region, wherein a distance between the first metal silicide layer and the first gate structure in the first horizontal direction is greater than a distance between the second metal silicide layer and the second gate structure in the second horizontal direction. 9 . The semiconductor device of claim 1 , wherein a thickness of the edge portion of the first gate oxide layer is smaller than a thickness of the main portion of the first gate oxide layer.

10. A method for manufacturing a semiconductor device, comprising: Providing a semiconductor substrate, wherein the semiconductor substrate includes a first region and a second region; A first gate oxide layer is formed on the first region of the semiconductor substrate, wherein the first gate oxide layer comprises: the main part; and a rim portion having an inclined sidewall; A first source / drain doping region is formed in the first region of the semiconductor substrate, wherein the first source / drain doping region is disposed adjacent to the edge portion of the first gate oxide layer, and the first source / drain doping region comprises: a first portion disposed below the edge portion of the first gate oxide layer in a vertical direction; and a second portion connected to the first portion; and A lightly doped source / drain region is formed in the first region of the semiconductor substrate, wherein the first source / drain doping region is formed in the lightly doped source / drain region, and the dopant concentration of the first source / drain doping region is higher than the dopant concentration of the lightly doped source / drain region.

11. The method for manufacturing a semiconductor device according to claim 10 , wherein the step of forming the first gate oxide layer comprises: forming an oxide layer on the first region and the second region; as well as A portion of the oxide layer on the first region and the oxide layer on the second region are removed together to form the first gate oxide layer on the first region.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising: forming a first dummy gate structure on the first gate oxide layer; as well as A first spacer structure is formed on a sidewall of the first dummy gate structure, wherein the first spacer structure is formed on the main portion of the first gate oxide layer. 13 . The method for fabricating a semiconductor device as claimed in claim 12 , wherein the inclined sidewall of the edge portion of the first gate oxide layer is formed before the first dummy gate structure and the first spacer structure are formed.

14. The method for manufacturing a semiconductor device according to claim 12, further comprising: After removing the oxide layer on the second region, forming a second gate oxide layer on the second region of the semiconductor substrate, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; forming a second dummy gate structure on the second gate oxide layer; forming a second spacer structure on the sidewall of the second dummy gate structure; as well as A second source / drain doping region is formed in the second region of the semiconductor substrate, wherein the second source / drain doping region is adjacent to the second spacer structure and is formed together with the first source / drain doping region by the same manufacturing process.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising: forming a first metal silicide layer, wherein the first metal silicide layer is at least partially disposed in the second portion of the first source / drain doped region, and the edge portion of the first gate oxide layer is located between the first spacer structure and the first metal silicide layer in a first horizontal direction; as well as A second metal silicide layer is formed, wherein the second metal silicide layer is at least partially disposed in the second source / drain doped region, and a distance between the first metal silicide layer and the first dummy gate structure in the first horizontal direction is greater than a distance between the second metal silicide layer and the second dummy gate structure in the second horizontal direction. 16 . The method for manufacturing a semiconductor device according to claim 10 , wherein a bottom surface of the first portion of the first source / drain doped region comprises a curved surface disposed below the inclined sidewall of the edge portion of the first gate oxide layer in the vertical direction. 17 . The method for fabricating a semiconductor device as claimed in claim 10 , wherein the inclined sidewall of the edge portion of the first gate oxide layer comprises a recessed surface.

18. The method for manufacturing a semiconductor device as described in claim 10, wherein the first portion of the first source / drain doped region is located between the main portion of the first gate oxide layer and the second portion of the first source / drain doped region in the first horizontal direction, and a bottom surface of the second portion is lower than a bottom surface of the first portion in the vertical direction.

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