A multi-mode codec hardware implementation system, method, storage medium and device

Abstract

The application provides a multi-mode codec hardware implementation system, method, storage medium and device. The method comprises the following steps: a first data distribution control module distributes first input data to data selectors or mode control modules of different calculation engines according to first data distribution control parameters; the mode control module controls the exclusive OR operation of first data and second data, or controls the passing of the second data; a second data distribution control module distributes the output data of the mode control module to the data selectors of different calculation engines according to second data distribution control parameters; and a check control module controls whether an old check P or Q participates in calculation, and a calculation unit performs calculation based on the old check and the output data from the data selector. The application uses one calculation engine to realize three writing modes, adopts the calculation engine multiplexing mode to realize the RAID5 and RAID6 algorithms by using one hardware, so that the hardware resource utilization rate is significantly improved, and the hardware circuit area is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of encoding and decoding technology, and more particularly to the field of encoding and decoding testing technology, specifically to a multi-mode encoding and decoding hardware implementation system, method, storage medium, and device. Background Technology

[0002] RAID (Redundant Arrays of Independent Disks) technology, as a high-performance and highly reliable storage technology, has been widely adopted. RAID is a disk array with redundancy capabilities. A disk array combines multiple independent disks to create a large-capacity disk group. RAID primarily utilizes data striping, mirroring, and data verification techniques to achieve high performance, reliability, fault tolerance, and scalability. Many RAID algorithms have been derived based on the strategies and architectures that employ or combine these three technologies, with RAID 5 and RAID 6 being the most widely used.

[0003] In RAID, data is distributed across multiple disks in blocks. RAID 5 stores data and its corresponding parity information across the disks that make up the RAID 5 array. When one disk in a RAID 5 array fails, the remaining data and the corresponding parity information are used to recover the damaged data. Therefore, RAID 5 requires a hardware computing engine for encoding or decoding.

[0004] RAID 6 adds a parity disk to RAID 5, meaning it can recover data lost from two disks. RAID 6 requires two hardware computing engines for encoding or decoding. The RAID 5 and RAID 6 implementation algorithms are as follows:

[0005] (1) RAID5

[0006]

[0007] D1, D2, and Dn are data from different disks, P is the checksum, and the following operational relationship is satisfied:

[0008] K1*D1⊕K2*D2⊕K3*D3⊕…⊕Kn*Dn⊕P = 0;

[0009] In the formula, * represents Galois multiplication, and K1, K2, K3 … Kn are Galois multiplication operation parameters, which have the same meaning in the following text.

[0010] The encoding formula is: P = K1*D1⊕K2*D2⊕K3*D3⊕…⊕Kn*Dn;

[0011] The decoding formula is: Dx = *(K1*D1⊕K2*D2⊕K3*D3⊕…⊕Kn*Dn ⊕P)(excluding Dx terms);

[0012] If any data disk in a RAID5 array is lost, it can be recovered from the other data disks.

[0013] (2) RAID6

[0014]

[0015] D1, D2, and Dn are data, and P and Q are checksums, satisfying the following operational relationship:

[0016] P = K11*D1⊕K12*D2⊕K13*D3⊕…⊕K1n*Dn;

[0017] Q = K21*D1⊕K22*D2⊕K23*D3⊕…⊕K2n*Dn;

[0018] Based on the principle of solving a system of two linear equations, RAID6 can recover data lost from a maximum of two disks.

[0019] Therefore, different RAID algorithms require different numbers of parity calculations; consequently, different algorithms require different hardware circuits for encoding or decoding. Additionally, there are three modes for writing data to disk.

[0020] Mode 1: Full stripe write. The new data being written fills the entire stripe. In this case, the checksum information for the data to be written can be calculated beforehand, and the entire stripe can be written directly to disk. Since there is no old data in this scenario, the checksum can be calculated directly.

[0021] Mode 2: Read-Modify-Write. Read the old data to be modified (D) and the original checksum data, and calculate the checksum together with the newly written data (D').

[0022] Mode 3: Refactored Write. Read the data (D) that does not need to be modified from this stripe, calculate the checksum together with the data to be newly written (D'), and write it to disk.

[0023] The hardware engine circuits for calculating verification differ for different write modes. Additionally, modes two and three also require the calculation of PPL (Partial Parity Log).

[0024] The algorithm and functions of PPL are as follows:

[0025]

[0026] like Figure 1As shown, a RAID 5 stripe has been constructed, with data blocks D1-D7. If data updates occur on D2 and D3, updating to D2' and D3', then it's necessary to consider the possibility of disk failure (disk removal or damage) of unmodified data (D1, D4, D5, D6, D7 in this example) during the writing of D2' and D3'. RAID 5 needs to ensure that any one of the unmodified data lost during this process can be recovered. To protect the unmodified data, PPL is introduced, which is the checksum of the unmodified data. In this example, PPL = K1*D1⊕K4*D4⊕K5*D5⊕K6*D6⊕K7*D7.

[0027] The following describes the calculation methods for verifying P´ and PPL under three modes:

[0028] (1) Mode 1

[0029] In Mode 1, all data on all disks will be modified, and the checksum will be calculated using all the new data.

[0030] P´ = K1* D1´⊕K2* D2´⊕K3* D3´⊕…⊕Kn* Dn´.

[0031] (2) Mode Two

[0032] Mode 2 is used for scenarios where relatively little disk data is being modified (less than half the length of the stripe). For example, in n disks, D2 and D3 will be modified. The old data in the stripe satisfies:

[0033] P = K1*D1⊕K2*D2⊕K3*D3⊕…⊕Kn*Dn;

[0034] According to the principle of XOR operation, we can obtain:

[0035] K2*D2⊕K3*D3 = P⊕K1*D1⊕K4*D4⊕K5*D5⊕…⊕Kn*Dn;

[0036] The formula for calculating the new checksum P' after the old data D2 and D3 are replaced by the new data D2' and D3' is as follows:

[0037] P´ = K1*D1⊕(K2* D2´⊕K3* D3´)⊕…⊕Kn*Dn

[0038] = P⊕(K2*D2⊕K3*D3)⊕(K2* D2´⊕K3*D3´)

[0039] = P⊕K2*(D2⊕D2´)⊕K3(D3⊕D3´)

[0040] The PPL calculation formula under Mode 2 is as follows:

[0041] PPL = K1*D1⊕K4*D4⊕K5*D5⊕…⊕Kn*Dn

[0042] =P⊕(K2*D2⊕K3*D3)

[0043] (3) Mode 3

[0044] Mode 3 is suitable for scenarios involving a large amount of modified disk data (more than half of the stripe). For example, in n disks, D2 and D3 will be modified. The new parity calculation formula for P' is:

[0045] P´ = K1*D1⊕(K2* D2´⊕K3* D3´)⊕K4*D4…⊕Kn*Dn

[0046] PPL = K1*D1⊕K4*D4⊕K5*D5⊕…⊕Kn*Dn

[0047] Taking RAID5 as an example, the hardware architecture diagrams for the three modes are as follows: Figure 1 As shown.

[0048] In summary, the current method for implementing these three modes is to implement a separate computing engine for each mode. This results in a large number of hardware circuit modules and consumes significant hardware resources. For example, supporting the three write modes of RAID 5 requires designing three different computing engine circuits; supporting the three write modes of RAID 6 requires six computing engine circuits; and supporting both RAID 5 and RAID 6 requires a total of nine computing engine circuits. When using one or more computing engines, the others may be idle, leading to low hardware utilization. Therefore, a new design method is needed to minimize the hardware circuit area and improve hardware utilization. Summary of the Invention

[0049] In view of this, the design of independent circuits for different RAID algorithms and write modes has problems such as high hardware resource consumption and large circuit area. This invention starts from improving hardware reusability. The purpose of this invention is to propose a multi-mode encoding and decoding hardware implementation system, method, storage medium and device that supports RAID5 and RAID6 algorithms and different write modes, which can greatly improve the utilization of hardware resources and reduce the hardware circuit area.

[0050] To achieve the above objectives, in one aspect, the present invention provides a hardware implementation system for multi-mode encoding and decoding, wherein the system includes a first data distribution module, a mode control module, a second data distribution module, a data selector, and a verification control module.

[0051] The first data distribution module is used to distribute the module input data according to the first data distribution control parameters;

[0052] The mode control module has two modes: controlling the XOR operation of the first data channel and the second data channel, or controlling the passage of the second data channel.

[0053] The second data distribution module is used to distribute the data output by the mode control module according to the second data distribution control parameters;

[0054] The data selector is used to select one of the two input data streams to pass through;

[0055] The verification control module is used to control whether the old verification P or Q is included in the calculation.

[0056] As a further embodiment of the present invention, the verification control module and the data selector are disposed within the computing engine, and the verification control module and the data selector are also connected to the computing unit within the computing engine.

[0057] In view of the above objectives, and in a second aspect, the present invention provides a hardware implementation method for multi-mode encoding and decoding, wherein the method includes the following steps:

[0058] The first data distribution control module distributes the first input data to the data selectors or mode control modules of different computing engines according to the first data distribution control parameters.

[0059] The mode control module controls the XOR operation of the first and second data channels, or controls the passage of the second data channel; the second data distribution control module distributes the output data of the mode control module to the data selectors of different computing engines according to the second data distribution control parameters.

[0060] Based on the second data distribution control parameters, the mode control module outputs data to data selectors for different computing engines;

[0061] The verification control module controls whether the old verification P or Q is included in the calculation, and the calculation unit performs the calculation based on the old verification and the output data from the data selector.

[0062] As a further aspect of the present invention, three modes can be achieved through the aforementioned steps.

[0063] As a further embodiment of the present invention, mode one only requires calculating the verification on the new input data, including:

[0064] Calculate the checksum P' or perform decoding operations to calculate Dx.

[0065] The first data distribution module is used to distribute the module input data according to the first data distribution control parameters;

[0066] The first input data is the new data of the input data;

[0067] The second input data was not used; there is no input data.

[0068] As a further embodiment of the present invention, in Mode 1, the first data distribution module only distributes the first input data to the data selector, and the control parameters of the data selector are set to select the first channel data to pass through.

[0069] The verification control module operates in two ways: when calculating P', the old verification P is not allowed to participate in the calculation; when decoding, the old verification P is allowed to participate in the calculation.

[0070] The input data is given to the computing unit for calculation, and the calculation result is the result of encoding or decoding.

[0071] As a further aspect of the present invention, mode two is used to calculate P' and PPL, the first input data is the modified data D, the second input data is the new data D', and the method for calculating the P' data stream in mode two includes:

[0072] The first data distribution module distributes the first input data to the first control mode;

[0073] The mode control parameter is configured to use an XOR operation;

[0074] The verification control module allows P to participate in the calculation;

[0075] The data selector allows the second channel data to pass through, and the result calculated by the computing unit is P'.

[0076] As a further aspect of the present invention, the method for calculating the PPL data stream in Mode 2 includes:

[0077] The first data distribution module distributes the first input data to the data selector;

[0078] The verification control module allows P to participate in the calculation;

[0079] The data selector allows the first channel of data to pass through, and the result calculated by the computing unit at this time is PPL.

[0080] As a further aspect of the present invention, the multi-mode encoding and decoding hardware implementation method further includes mode three, which is used to calculate P' and PPL, with the first input data being the newly written data D' and the second input data being the new data D'; the method for calculating the P' data stream in mode three includes:

[0081] The first data distribution module distributes the first input data to the data selector;

[0082] The mode control parameters are configured to allow the second data channel to pass through;

[0083] The verification control module does not allow old verification P to participate in the calculation;

[0084] The data selector allows the second channel data to pass through, and then allows the first channel data to pass through. At this time, the result calculated by the computing unit is P'.

[0085] The method for calculating the PPL data stream in Mode 3 includes:

[0086] The mode control parameters are configured to allow the second data channel to pass through;

[0087] The verification control module does not allow old verification P to participate in the calculation;

[0088] The data selector allows the second channel data to pass through, and the result calculated by the computing unit at this time is PPL.

[0089] As a further aspect of the present invention, the multi-mode encoding and decoding hardware implementation method further includes two computing engines, and the input data of the computing engines are all controlled by the first data distribution module and the second data distribution module.

[0090] The RAID5 algorithm uses a first computing engine, while the first data distribution module and the second data distribution module only distribute data to the first computing engine.

[0091] The RAID6 algorithm uses a first computing engine and a second computing engine, and a first data distribution module and a second data distribution module distribute data to the first computing engine and the second computing engine.

[0092] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed, implement any of the above-described multi-mode encoding / decoding hardware implementation methods according to the present invention.

[0093] In another aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, performs any of the above-described multi-mode encoding / decoding hardware implementation methods according to the present invention.

[0094] This invention has at least the following beneficial technical effects: It proposes a multi-mode encoding / decoding hardware implementation system, method, storage medium, and device. This invention uses a single computing engine to implement three write modes. Simultaneously, it employs computing engine multiplexing to implement both RAID5 and RAID6 algorithms in a single hardware component, significantly improving hardware resource utilization and substantially reducing the hardware circuit area. Attached Figure Description

[0095] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0096] In the diagram:

[0097] Figure 1 The diagram shows the hardware architecture of the three write modes of existing RAID5;

[0098] Figure 2 A hardware architecture diagram supporting three modes is shown in an embodiment of the multi-mode encoding and decoding hardware implementation method according to the present invention;

[0099] Figure 3 A flowchart illustrating the implementation of Mode 1 in an embodiment of the multi-mode encoding / decoding hardware implementation method according to the present invention is shown;

[0100] Figure 4 A flowchart illustrating the calculation of P' for mode two is shown in an embodiment of the multi-mode codec hardware implementation system according to the present invention;

[0101] Figure 5 A flowchart illustrating the PPL calculation for Mode 2 is shown in an embodiment of the multi-mode codec hardware implementation system according to the present invention.

[0102] Figure 6 A flowchart illustrating the calculation of P' for mode 3 is shown in an embodiment of the multi-mode codec hardware implementation system according to the present invention;

[0103] Figure 7 A flowchart illustrating the PPL calculation for Mode 3 is shown in an embodiment of the multi-mode codec hardware implementation system according to the present invention.

[0104] Figure 8 A hardware architecture diagram supporting RAID5 and RAID6 is shown in an embodiment of the multi-mode codec hardware implementation system according to the present invention;

[0105] Figure 9 A schematic diagram illustrating an embodiment of a computer-readable storage medium for implementing a hardware method for multi-mode encoding and decoding according to the present invention is shown;

[0106] Figure 10 A schematic diagram of the hardware structure of an embodiment of a computer device for implementing a multi-mode codec hardware implementation method according to the present invention is shown. Detailed Implementation

[0107] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0108] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.

[0109] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0110] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0111] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0112] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0113] The current method for implementing these three modes involves implementing a separate computing engine for each mode. This results in a large number of hardware circuit modules that need to be designed, consuming significant hardware resources. For example, supporting the three write modes of RAID5 requires designing three different computing engine circuits; supporting the three write modes of RAID6 requires six computing engine circuits; and supporting both RAID5 and RAID6 requires a total of nine computing engine circuits. When using one or more of the computing engines, the others may be in an "idle" state, leading to low hardware utilization.

[0114] In view of this, the design of independent circuits for different RAID algorithms and write modes has problems such as high hardware resource consumption and large circuit area. This invention starts from improving hardware reusability. The purpose of this invention is to propose a multi-mode encoding and decoding hardware implementation system, method, storage medium and device that supports RAID5 and RAID6 algorithms and different write modes, which can greatly improve the utilization of hardware resources and reduce the hardware circuit area.

[0115] Therefore, in a first aspect, the present invention provides a multi-mode encoding and decoding hardware implementation system, wherein the system includes a first data distribution module, a mode control module, a second data distribution module, a data selector, and a verification control module.

[0116] The first data distribution module is used to distribute the module input data according to the first data distribution control parameters;

[0117] The mode control module has two modes: controlling the XOR operation of the first data channel and the second data channel, or controlling the passage of the second data channel.

[0118] The second data distribution module is used to distribute the data output by the mode control module according to the second data distribution control parameters;

[0119] The data selector is used to select one of the two input data streams to pass through;

[0120] The verification control module is used to control whether the old verification P or Q is included in the calculation.

[0121] In some embodiments, the verification control module and the data selector are located within the computing engine, and the verification control module and the data selector are also connected to the computing unit within the computing engine.

[0122] It should be noted that although several modules or units of the device for performing actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0123] A second aspect of the present invention provides a hardware implementation method for multi-mode encoding and decoding. Figure 2 A hardware architecture diagram supporting three modes is shown, representing an embodiment of the multi-mode codec hardware implementation method according to the present invention. Figure 2 In the illustrated embodiment, the method includes:

[0124] Step S10: The first data distribution control module distributes the first input data to the data selectors or mode control modules of different computing engines according to the first data distribution control parameters;

[0125] Step S20: The mode control module controls the XOR operation of the first data channel and the second data channel, or controls the passage of the second data channel; the second data distribution control module distributes the output data of the mode control module to the data selectors of different computing engines according to the second data distribution control parameters.

[0126] Step S30: Distribute the output data of the mode control module to the data selectors of different computing engines based on the second data distribution control parameters;

[0127] Step S40: The verification control module controls whether the old verification P or Q participates in the calculation, and the calculation unit performs the calculation based on the old verification and the output data from the data selector.

[0128] In summary, to address the aforementioned problems in the existing technology, the embodiments of the present invention employ three write modes that share certain similarities in their hardware architecture, namely, all requiring computational verification or PPL calculation. The computational unit hardware circuits for computational verification and PPL calculation are identical. Therefore, a scheme can be designed to reuse these identical circuits, and other differences can be switched by adding a control module, achieving the goal of implementing three different modes with a single hardware component.

[0129] In some embodiments, the steps described can achieve three modes.

[0130] like Figure 2 As shown in the diagram, the hardware architecture includes four data flow control modules, whose functions are illustrated in the table below. By configuring these control modules, different modes of functionality can be achieved using the same hardware circuit.

[0131] In some embodiments, RAID5 is used as an example to describe in detail how to implement the functions of different modes.

[0132] In this embodiment, mode one only requires calculating the validation of the new input data, and its implementation is as follows:

[0133] Calculate the checksum P' or perform decoding operations to calculate Dx.

[0134] The first data distribution module is used to distribute the module input data according to the first data distribution control parameters;

[0135] The first input data is the new data of the input data;

[0136] The second input data was not used; there is no input data.

[0137] like Figure 3 As shown, Mode 1 requires calculating the checksum P' or performing decoding operations to calculate Dx. The first input data is new data. The second input data is unused, with no input data. Its data stream is as follows: Figure 3 As indicated by the solid arrows, the control methods of each control module are as follows:

[0138] In some embodiments, in Mode 1, the first data distribution module only distributes the first input data to the data selector, and the control parameters of the data selector are set to select the first channel data to pass through.

[0139] The verification control module operates in two ways: when calculating P', the old verification P is not allowed to participate in the calculation; when decoding, the old verification P is allowed to participate in the calculation.

[0140] The input data is given to the computing unit for calculation, and the calculation result is the result of encoding or decoding.

[0141] In some embodiments, mode two is used to calculate P' and PPL, the first input data is the modified data D, the second input data is the new data D', and the data stream for calculating P' in mode two is as follows: Figure 4 As shown by the solid arrow in the middle. The method for calculating the P' data stream in Mode 2 includes:

[0142] The first data distribution module distributes the first input data to the first control mode;

[0143] The mode control parameter is configured to use an XOR operation;

[0144] The verification control module allows P to participate in the calculation;

[0145] The data selector allows the second channel data to pass through, and the result calculated by the computing unit is P'.

[0146] In some embodiments, Mode 2 calculates the PPL data stream as follows: Figure 5 As shown by the solid arrow, the method for calculating the PPL data stream in Mode 2 includes:

[0147] The first data distribution module distributes the first input data to the data selector;

[0148] The verification control module allows P to participate in the calculation;

[0149] The data selector allows the first channel of data to pass through, and the result calculated by the computing unit at this time is PPL.

[0150] In some embodiments, mode three is used to calculate P' and PPL, with the first input data being new data D' and the second input data being unmodified data D. The data stream for calculating P' in mode three is as follows: Figure 6As shown by the solid arrow, the method for calculating the P' data stream in Mode 2 includes:

[0151] The first data distribution module distributes the first input data to the data selector;

[0152] The mode control parameters are configured to allow the second data stream to pass through;

[0153] The verification control module does not allow old verification P to participate in the calculation;

[0154] The data selector first allows the second channel data to pass through, and then allows the first channel data to pass through. At this time, the calculation unit calculates the result as P'.

[0155] In some embodiments, mode 3 calculates the PPL data stream as follows: Figure 7 As shown by the solid arrow, the method for calculating the PPL data stream in Mode 3 includes:

[0156] The mode control parameters are configured to allow the second data stream to pass through;

[0157] The verification control module does not allow old verification P to participate in the calculation;

[0158] The data selector allows the second channel data to pass through, and the result calculated by the computing unit is PPL.

[0159] The above method allows for the implementation of three different modes using a single hardware circuit.

[0160] The parity calculation engines for RAID 5 and RAID 6 algorithms are the same; RAID 5 requires calculating one parity, while RAID 6 requires calculating two. Therefore, hardware circuits supporting RAID 6 can also implement RAID 5. Thus, a circuit with a maximum of two calculation engines can be designed to implement RAID 5 and RAID 6.

[0161] In some embodiments, the multi-mode codec hardware implementation method further includes two computing engines, the input data of which are all controlled by the first data distribution module and the second data distribution module. For example... Figure 8 As shown in the figure, there are two computing engines. The input data of the computing engines is controlled by the first data distribution module and the second data distribution module.

[0162] In the RAID5 algorithm, a first computing engine is used, and the first data distribution module and the second data distribution module only distribute data to the first computing engine; in the RAID6 algorithm, a first computing engine and a second computing engine are used, and the first data distribution module and the second data distribution module distribute data to the first computing engine and the second computing engine.

[0163] Reusing compute engines can effectively reduce the waste of hardware resources. Traditional methods of implementing RAID5 and RAID6 require a total of 3 compute engines. Using compute engine reuse only requires 2 compute engines, saving one-third of the resources.

[0164] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0165] A third aspect of the present invention also provides a computer-readable storage medium. Figure 9 A schematic diagram of a computer-readable storage medium illustrating a multi-mode codec hardware implementation method according to an embodiment of the present invention is shown. Figure 9 As shown, the computer-readable storage medium 300 stores computer program instructions 310, which can be executed by a processor. When executed, the computer program instructions 310 implement the method of any of the above embodiments.

[0166] It should be understood that, where there is no conflict, all the embodiments, features and advantages described above for the multi-mode codec hardware implementation method according to the present invention are equally applicable to the multi-mode codec hardware implementation system and storage medium according to the present invention.

[0167] A fourth aspect of the present invention also provides a computer device 400, including a memory 420 and a processor 410, wherein the memory stores a computer program, which, when executed by the processor, implements the method of any of the above embodiments.

[0168] like Figure 10 The diagram shown is a hardware structure schematic of an embodiment of a computer device for implementing a multi-mode encoding / decoding hardware method provided by the present invention. Figure 10 Taking the computer device 400 shown as an example, this computer device includes a processor 410 and a memory 420, and may also include an input device 430 and an output device 440. The processor 410, memory 420, input device 430, and output device 440 can be connected via a bus or other means. Figure 10Taking a bus connection as an example, input device 430 can receive input digital or character information and generate signal inputs related to the multi-mode codec hardware implementation. Output device 440 may include display devices such as a display screen.

[0169] Memory 420, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the resource monitoring method in this embodiment. Memory 420 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created by the use of the resource monitoring method, etc. In addition, memory 420 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 420 may optionally include memory remotely located relative to processor 410, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0170] The processor 410 executes various server functions and data processing by running non-volatile software programs, instructions, and modules stored in the memory 420, thereby implementing the resource monitoring method of the above method embodiment.

[0171] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0172] Finally, it should be noted that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0173] The various exemplary logic blocks, modules, and circuits described herein can be implemented or performed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and / or any other such configuration.

[0174] This invention improves hardware utilization and reduces circuit area by adding a data flow control module to reuse the computing engines of RAID5 and RAID6 algorithms. By using data flow control to reuse hardware, a single computing engine can simultaneously implement three write modes. Furthermore, by using data flow control to reuse hardware, a single hardware circuit can implement both RAID5 and RAID6 algorithms.

[0175] In some embodiments of the present invention, a data flow control module is added to the circuit to improve the reusability of the hardware circuit, thereby increasing the complexity of circuit control. On the other hand, using one circuit to implement the functions of multiple independent circuits allows for the implementation of the functions of a single circuit by modifying control parameters, which is useful in special scenarios where the functions of multiple independent circuits need to be used simultaneously. Furthermore, to address the performance degradation caused by the current implementation's serial execution capability, a parallel execution approach can be adopted to improve performance.

[0176] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0177] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0178] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A hardware implementation system for multi-mode encoding and decoding, characterized in that, The system includes a first data distribution module, a mode control module, a second data distribution module, a data selector, and a verification control module; The first data distribution module is used to distribute the module input data according to the first data distribution control parameters; The mode control module has two modes: controlling the XOR operation of the first data channel and the second data channel, or controlling the passage of the second data channel. The second data distribution module is used to distribute the data output by the mode control module according to the second data distribution control parameters; The data selector is used to select one of the two input data streams to pass through; The verification control module is used to control whether the old verification P or Q is included in the calculation; The distribution of module input data according to the first data distribution control parameters includes: the first data distribution control module distributing the first input data to the data selectors or mode control modules of different computing engines according to the first data distribution control parameters; the first input data is new data of input data; the first input data is modified data D; the first input data is newly written data D′; Controlling the XOR operation of the first data channel and the second data channel, or controlling the passage of the second data channel, includes: the first data channel being the first input data and the second data channel being the second input data; the mode control parameter is configured to perform an XOR operation, the first input data being the modified data D and the second input data being the new data D′; the mode control parameter is configured to allow the passage of the second data channel, the first input data being the new data D′ and the second input data being the unmodified data D. The two inputs include: a first data distribution control module that distributes the first input data to the data selectors of different computing engines according to the first data distribution control parameters; and a second distribution control module that distributes the output data of the mode control module to the data selectors of different computing engines according to the second data distribution control parameters.

2. The multi-mode encoding / decoding hardware implementation system according to claim 1, characterized in that, The verification control module and data selector are located within the computing engine, and are also connected to the computing units within the computing engine.

3. A hardware implementation method for multi-mode encoding and decoding, characterized in that, Based on the multi-mode encoding / decoding hardware implementation system as described in any one of claims 1-2, the method includes the following steps: The first data distribution control module distributes the first input data to the data selectors or mode control modules of different computing engines according to the first data distribution control parameters. The mode control module controls the XOR operation of the first and second data channels, or controls the passage of the second data channel; Based on the second data distribution control parameters, the mode control module outputs data to data selectors for different computing engines; The verification control module controls whether the old verification P or Q is included in the calculation, and the calculation unit calculates based on the old verification and the output data from the data selector; The first input data includes: new data for input, modified data D, and newly written data D′; Controlling the XOR operation of the first data channel and the second data channel, or controlling the passage of the second data channel, includes: the first data channel being the first input data and the second data channel being the second input data; the mode control parameter is configured to perform an XOR operation, the first input data being the modified data D and the second input data being the new data D′; the mode control parameter is configured to allow the passage of the second data channel, the first input data being the new data D′ and the second input data being the unmodified data D.

4. The hardware implementation method for multi-mode encoding and decoding according to claim 3, characterized in that, By implementing the steps described above, Mode 1 only requires calculating validation on the new input data, including: Calculate the checksum P' or perform decoding operations to calculate Dx; The first data distribution module is used to distribute the module input data according to the first data distribution control parameters; The first input data is the new data of the input data; The second input data was not used; there is no input data. Where Dx is used to represent the decoding correlation.

5. The multi-mode encoding / decoding hardware implementation method according to claim 4, characterized in that, In Mode 1, the first data distribution module only distributes the first input data to the data selector, and the control parameters of the data selector are set to select the first channel data to pass through; The verification control module operates in two ways: when calculating P', the old verification P is not allowed to participate in the calculation; when decoding, the old verification P is allowed to participate in the calculation. The input data is given to the computing unit for calculation, and the calculation result is the result of encoding or decoding.

6. The hardware implementation method for multi-mode encoding and decoding according to claim 3, characterized in that, Through the aforementioned steps, Mode 2 is implemented for calculating P' and PPL. The first input data is the modified data D, and the second input data is the new data D'. The method for calculating the P' data stream in Mode 2 includes: The first data distribution module distributes the first input data to the first control mode; The mode control parameter is configured to use an XOR operation; The verification control module allows P to participate in the calculation; The data selector allows the second channel data to pass through, and the result calculated by the computing unit is P'. PPL is used to represent a partial parity log.

7. The hardware implementation method for multi-mode encoding and decoding according to claim 6, characterized in that, The method for calculating the PPL data stream in Mode 2 includes: The first data distribution module distributes the first input data to the data selector; The verification control module allows P to participate in the calculation; The data selector allows the first channel of data to pass through, and the result calculated by the computing unit at this time is PPL.

8. The hardware implementation method for multi-mode encoding and decoding according to claim 3, characterized in that, Through the aforementioned steps, Mode 3 is implemented for calculating P' and PPL. The first input data is the new data D', and the second input data is the unmodified data D. The method for calculating the P' data stream in Mode 3 includes: The first data distribution module distributes the first input data to the data selector; The mode control parameters are configured to allow the second data stream to pass through; The verification control module does not allow old verification P to participate in the calculation; The data selector first allows the second channel data to pass through, and then allows the first channel data to pass through. At this time, the calculation unit calculates the result as P'.

9. The hardware implementation method for multi-mode encoding and decoding according to claim 8, characterized in that, The method for calculating the PPL data stream in Mode 3 includes: The mode control parameters are configured to allow the second data stream to pass through; The verification control module does not allow old verification P to participate in the calculation; The data selector allows the second channel data to pass through, and the result calculated by the computing unit is PPL.

10. A computer-readable storage medium, characterized in that, The system stores computer program instructions, which, when executed, implement the multi-mode encoding / decoding hardware implementation method as described in any one of claims 3-9.

11. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, which, when executed by the processor, performs the multi-mode encoding / decoding hardware implementation method as described in any one of claims 3-9.

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