A method, system, device, and storage medium for dynamic data prefetching in a cache based on a local algorithm.

Abstract

This invention relates to a method, system, device, and storage medium for dynamic data prefetching of a high-speed cache based on a local algorithm. The prefetching method includes: setting a history table; reading the history table to determine the cache miss type; cache miss types are categorized as transitional, repetitive, and skipped; calculating the prefetch address and the number of memory lines; initiating a prefetch request to the bus; and adjusting the history table based on the hit rate of the prefetched data group. The data prefetching strategy of this invention can effectively prefetch data to fill multi-level caches without affecting existing prefetching strategies, thus improving prefetching accuracy.

Description

Technical Field

[0001] This invention relates to a method, system, device, and storage medium for dynamic data prefetching in a cache based on a local algorithm, belonging to the field of integrated circuits. Background Technology

[0002] A cache is a higher-level storage unit in a computer's memory structure, acting as a bridge between main memory and the Central Processing Unit (CPU). The application of caching technology effectively addresses the "memory wall" limitation on processor performance. Modern processors, through their multi-level cache hierarchical structure, have significantly reduced cache miss rates. However, the access speed difference between the cache and main memory remains substantial. Therefore, when a cache miss occurs, the CPU still incurs a significant cost in retrieving the cache line from main memory.

[0003] Therefore, most modern processors use data prefetching technology to predict future memory access needs and send prefetch requests to the corresponding memory lines before the CPU actually accesses the cache, thus prefetching the memory line data into the cache in advance and improving the cache hit rate.

[0004] Data prefetching leverages the temporal and spatial locality of memory in computer programs to improve cache hit rates. Data prefetched from memory lines replaces existing cache lines. If a prefetch address is mispredicted, not only will the prefetched data be invalidated, but previously useful cache lines will also be replaced, resulting in performance loss. Most existing data prefetching strategies do not distinguish between the types of cache misses and directly prefetch the next memory line after the invalid address. While this strategy can improve cache hit rates, it has a high probability of prefetching errors. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a high-speed cache dynamic data prefetching method based on a local algorithm. This method is based on a local algorithm, classifies cache misses into three types, calculates the data prefetch address for different types of misses, proposes a high-precision data prefetching strategy, and improves the hit rate of prefetched data.

[0006] Terminology Explanation:

[0007] 1. Cache: A type of memory located between the CPU and main memory. It is faster than main memory but has a relatively small storage space.

[0008] 2. Cache hit: When the CPU issues an access request, it first checks whether the required data is in the cache. If it is, it is called a cache hit.

[0009] 3. Cache invalidation: When the CPU issues an access request but fails to find the corresponding data in the cache, it is called cache invalidation.

[0010] 4. Cache line: Data information stored in memory in blocks or lines is called a cache line.

[0011] 5. Prefetching: When a cache miss occurs, the CPU can only request data from the next lower level of storage. However, the access speed of the lower level of storage (the farther away from the CPU) is slower. The prefetching technique can extract the local data needed when a cache miss occurs into the cache line in advance for the CPU to select.

[0012] 6. Temporal locality: When a program accesses memory data in a cache line, it will access that data again or even multiple times in the following period of time.

[0013] 7. Spatial locality: When a program accesses memory data in a cache line, it is very likely to access the adjacent cache line the next time.

[0014] 8. Local Algorithm: A method for calculating the target address for data prefetching based on cache invalidation type.

[0015] 9. Step size: The difference between the current cache invalidation address and the previous cache invalidation address.

[0016] The technical solution of this invention is as follows:

[0017] A high-speed cache dynamic data prefetching method based on a local algorithm, the method being applied to a cache, specifically including:

[0018] S1, Build a history table, which is used to record the address of the instruction that has been cached invalidated;

[0019] S2, read the history table, calculate the prefetch step size, and determine the cache invalidation type;

[0020] S3 uses a local algorithm to calculate the address of the prefetched data, stores the prefetch address in the local address table, and then sends a prefetch request to the main memory via the bus.

[0021] S4 adjusts the historical record table based on the hit rate of the prefetched data group, controls the replacement rule of the historical record table, and controls the prefetching stop.

[0022] According to a preferred embodiment of the present invention, the cache is a multi-level cache, and each level of the cache is a multi-way group-connected structure, each way containing multiple cache lines, wherein the cache line includes at least a tag bit, a data bit, and a flag bit, and the flag bit includes at least a cache valid bit and a write dirty bit.

[0023] According to a preferred embodiment of the present invention, in step S1, when a cache miss occurs, the miss instruction address is stored in a history table, thereby constructing a history table; the history table includes n entries, each entry including 1 valid bit, 2 type bits, x label bits and miss instruction address bits;

[0024] The valid bit includes 0 and 1. When the valid bit is 1, it means that the entry is valid and can be selected and read by the read history table action in step S2. When the valid bit is 0, it means that the entry is invalid and the entry is waiting to be replaced by other instruction addresses to be saved. The valid bit is 1 for all three cache miss types after initialization. When a prefetch miss occurs, the valid bit changes from 1 to 0 and waits to be replaced.

[0025] The type bit includes 01, 10 and 11. Type bit 01 represents that the cache miss type is transitional, type bit 10 represents that the cache miss type is skipped, and type bit 11 represents that the cache miss type is repeated.

[0026] The label x is related to the number of entries n in the historical record table, and the label x satisfies: 2 x-1 <n≤2 x And n≥3, x≥2; x bits form label C; for example, if x=2, then the label width is 2, and the value range of label C is: 00, 01, 10, 11.

[0027] According to a preferred embodiment of the present invention, in step S1, a counter is set to record the label of each entry. The label represents the time order in which the address that has experienced a cache miss is stored in the history record table. A count value of 0 indicates that the instruction address in the entry was recorded earliest in the history record table. When the history record table is full, the historical instruction address in the table is replaced according to the replacement rule.

[0028] The replacement rule is as follows: when there is an invalid entry, replace the entry with a valid bit of 0 and a smaller label value. Assuming the label of the current entry to be replaced is r, then update it in order as follows: r = n + 1, other entry labels t = t - 1, r < t ≤ (n + 1);

[0029] If all entries are valid, the entry with the earliest recorded instruction address is replaced. Assuming the earliest recorded address entry is labeled r, the entries are updated sequentially as follows: r = n + 1, and the other entries are labeled t = t - 1 (0 < t ≤ (n + 1)). This replacement rule can promptly replace invalid entries and protects entries recently written to the history table from being replaced.

[0030] According to a preferred embodiment of the present invention, in step S2, the historical record table is read, the prefetch step size is calculated, and the cache invalidation type is determined; the specific process is as follows:

[0031] S2-1, Read the history table and determine whether the cache-invalidated address hits the history table. If it hits and the table entry is valid, jump to step S4 and return the corresponding data of the prefetched data group; if it does not hit or the table entry is invalid after the hit, jump to step S2-2.

[0032] S2-2, Read only the three cache invalidation addresses of the latest written history table, calculate the change value of the step size, and determine the relationship of the three cache invalidation addresses by calculating the step size;

[0033] S2-3, assuming the addresses of the three most recent instructions written to the history table from oldest to most recent are a, ... i-2 a i-1 a i ;

[0034] S2-4, let step size k1 = a i -a i-1 Step size k0 = a i-1 -a i-2 Determine the relationship between the two step sizes k1 and k0.

[0035] If both k1 and k0 are 0, then the cache invalidation type is determined to be duplicate.

[0036] If k1 and k0 are both equal and not 0, then the cache invalidation type is determined to be skip type.

[0037] If k1 and k0 are not equal, but one of them has a step size of 0, then the cache invalidation type is determined to be transitional.

[0038] If k1 and k0 are not equal and neither is 0, then no data prefetching is performed; and the valid position of the entry containing a2 is set to 0.

[0039] S2-5, for repeated cache misses, one cache line is prefetched from the bus;

[0040] S2-6, skip cache miss, prefetches three cache lines to the bus at a time;

[0041] S2-7, Transitional cache invalidation prefetches two cache lines to the bus at a time;

[0042] S2-8: After determining the cache invalidation type, record the type in the type field of the history table;

[0043] S2-9: Save the step size and cache invalidation type and send them to step S3, preparing to use the local algorithm to calculate the prefetch address.

[0044] According to a preferred embodiment of the present invention, in step S3, the address of the prefetched data is calculated using a local algorithm, the prefetch address is stored in a local address table, and then a prefetch request is initiated to the main memory via the bus; the specific process is as follows:

[0045] S3-1, Obtain the failure type signal and step size;

[0046] S3-2. When the step size does not span a cache line, there may be a situation where the prefetched data is the data of the current invalid cache line. In this case, the step size needs to be set to be equal to the highest bit of the step size plus 1.

[0047] S3-3, If the failure type is repetitive, the address of the data to be prefetched in memory is a. i If i = C, the instruction is marked as prefetched and will continue to be prefetched until the confidence level is 0.

[0048] S3-4, If the failure type is skip type, the addresses of the three memory rows to be prefetched are a i +j*k1, i=C, j=1, 2, 3; these three instructions are marked as prefetched and will continue to be prefetched until the confidence level is 0.

[0049] S3-5, if the cache invalidation type is transitional, the addresses of the two memory lines to be prefetched are a i +j*(k1+k0), i=C, j=1,2, mark these two instructions as prefetch, and continue prefetching until the confidence level is 0 and stop prefetching;

[0050] S3-6, after the address is obtained, it is stored in the local address table, and a data prefetch request is sent to the main memory via the bus.

[0051] According to a preferred embodiment of the present invention, in step S4, the historical record table is adjusted based on the hit rate of the prefetched data group, the replacement rule of the historical record table is controlled, and the prefetching is stopped; the specific process is as follows:

[0052] S4-1, the confidence level ranges from 00, 01, 10, to 11, with all types initially set to 10. The confidence levels, from lowest to highest, are 00, 01, 10, and 11. 00 is the minimum value, indicating that data previously prefetched due to a cache miss can no longer be retrieved. In other words, data that would have been needed in the previous cache miss is no longer required. It's becoming increasingly useless, and the entries in this historical record table can be cleared.

[0053] S4-2, waiting for data to be prefetched from main memory and placed into the prefetch data group;

[0054] S4-3, If the instruction address hits the prefetch data group, a prefetch hit signal is generated, the cache is refilled from the prefetch data group, the corresponding type confidence is incremented by 1, and then the process returns to step S3 to calculate the address of the prefetch data and continue to perform prefetching.

[0055] S4-4, if the instruction address does not hit the prefetch data group, decrease the confidence level by 1; then return to step S3 to calculate the instruction address for prefetching data; when the confidence level decreases to 00, stop prefetching and notify the history table to set the valid position of the instruction address to 0.

[0056] A high-speed cache dynamic data prefetching system based on a local algorithm includes a history record table construction module, a prefetch type discrimination module, a prefetch address storage module, and a control prefetching module connected in sequence.

[0057] The historical record table construction module is used to implement step S1; the prefetch type discrimination module is used to implement step S2; the prefetch address storage module is used to implement step S2; and the control prefetch module is used to implement step S4.

[0058] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of a cache dynamic data prefetching method based on a local algorithm.

[0059] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of a cache dynamic data prefetching method based on a local algorithm.

[0060] The beneficial effects of this invention are as follows:

[0061] 1. The present invention adopts a high-speed cache dynamic data prefetching method based on local algorithm, that is, the prefetch address is calculated by local algorithm. This algorithm can better utilize the spatial locality and temporal locality of program access to data and improve the hit rate.

[0062] 2. The present invention has a wide range of applications and can support data prefetching in multi-level caching.

[0063] 3. The local algorithm of this invention has low complexity and low hardware and software implementation overhead.

[0064] 4. The data prefetching strategy of the present invention can effectively prefetch data to fill multi-level caches without affecting existing prefetching strategies, thereby improving the accuracy of prefetching. Attached Figure Description

[0065] Figure 1 This is a schematic diagram of the logical structure of a high-speed cache dynamic data prefetching method based on a local algorithm according to the present invention.

[0066] Figure 2 This is a schematic diagram illustrating the steps of a high-speed cache dynamic data prefetching method based on a local algorithm according to the present invention. Detailed Implementation

[0067] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0068] Example 1

[0069] A high-speed cache dynamic data prefetching method based on a local algorithm, such as Figure 1 and Figure 2 As shown, the steps include:

[0070] S1, Build a history table, which is used to record the address of the instruction that has been cached invalidated;

[0071] The cache is a multi-level cache, and each level of the cache is a multi-way set-connected structure. Each way contains multiple cache lines. Each cache line includes at least a tag bit, a data bit, and a flag bit. The flag bit includes at least a cache valid bit and a write dirty bit.

[0072] In step S1, when a cache miss occurs, the miss instruction address is stored in the history table, thereby constructing the history table; the history table includes n entries, each entry including 1 valid bit, 2 type bits, x label bits and miss instruction address bits;

[0073] The valid bit includes 0 and 1. When the valid bit is 1, it means that the entry is valid and can be selected and read by the read history table action in step S2. When the valid bit is 0, it means that the entry is invalid and the entry is waiting to be replaced by other instruction addresses to be saved. The valid bit is 1 for all three cache miss types after initialization. When a prefetch miss occurs, the valid bit changes from 1 to 0 and waits to be replaced.

[0074] The type bit includes 01, 10 and 11. Type bit 01 represents that the cache miss type is transitional, type bit 10 represents that the cache miss type is skipped, and type bit 11 represents that the cache miss type is repeated.

[0075] The label x is related to the number of entries n in the historical record table, and the label x satisfies: 2 x-1 <n≤2 x And n≥3, x≥2; x bits form label C; for example, if x=2, then the label width is 2, and the value range of label C is: 00, 01, 10, 11.

[0076] In step S1, a counter is set to record the label of each entry. The label represents the time order in which the address that has experienced a cache miss is stored in the history table. A count value of 0 indicates that the instruction address in that entry was recorded earliest in the history table. When the history table is full, the historical instruction address in the table is replaced according to the replacement rule.

[0077] The replacement rule is as follows: when there is an invalid entry, replace the entry with a valid bit of 0 and a smaller label value. Assuming the label of the current entry to be replaced is r, then update it in order as follows: r = n + 1, other entry labels t = t - 1, r < t ≤ (n + 1);

[0078] If all entries are valid, the entry with the earliest recorded instruction address is replaced. Assuming the earliest recorded address entry is labeled r, the entries are updated sequentially as follows: r = n + 1, and the other entries are labeled t = t - 1 (0 < t ≤ (n + 1)). This replacement rule can promptly replace invalid entries and protects entries recently written to the history table from being replaced.

[0079] S2, read the historical record table, calculate the prefetch step size, and determine the cache invalidation type; the specific process is as follows:

[0080] S2-1, Read the history table and determine whether the cache-invalidated address hits the history table. If it hits and the table entry is valid, jump to step S4 and return the corresponding data of the prefetched data group; if it does not hit or the table entry is invalid after the hit, jump to step S2-2.

[0081] S2-2, Read only the three cache invalidation addresses of the latest written history table, calculate the change value of the step size, and determine the relationship of the three cache invalidation addresses by calculating the step size;

[0082] S2-3, assuming the addresses of the three most recent instructions written to the history table from oldest to most recent are a, ... i-2 a i-1 a i ;

[0083] S2-4, let step size k1 = a i -a i-1 Step size k0 = a i-1 -a i-2 Determine the relationship between the two step sizes k1 and k0.

[0084] If both k1 and k0 are 0, then the cache invalidation type is determined to be duplicate.

[0085] If k1 and k0 are both equal and not 0, then the cache invalidation type is determined to be skip type.

[0086] If k1 and k0 are not equal, but one of them has a step size of 0, then the cache invalidation type is determined to be transitional.

[0087] If k1 and k0 are not equal and neither is 0, then no data prefetching is performed; and the valid position of the entry containing a2 is set to 0.

[0088] S2-5, for repeated cache misses, one cache line is prefetched from the bus;

[0089] S2-6, skip cache miss, prefetches three cache lines to the bus at a time;

[0090] S2-7, Transitional cache invalidation prefetches two cache lines to the bus at a time;

[0091] S2-8: After determining the cache invalidation type, record the type in the type field of the history table;

[0092] S2-9: Save the step size and cache invalidation type and send them to step S3, preparing to use the local algorithm to calculate the prefetch address.

[0093] S3 calculates the address of the prefetched data using a local algorithm, stores the prefetch address in the local address table, and then sends a prefetch request to the main memory via the bus; the specific process is as follows:

[0094] S3-1, Obtain the failure type signal and step size;

[0095] S3-2. When the step size does not span a cache line, there may be a situation where the prefetched data is the data of the current invalid cache line. In this case, the step size needs to be set to be equal to the highest bit of the step size plus 1.

[0096] S3-3, If the failure type is repetitive, the address of the data to be prefetched in memory is a. i If i = C, the instruction is marked as prefetched and will continue to be prefetched until the confidence level is 0.

[0097] S3-4, If the failure type is skip type, the addresses of the three memory rows to be prefetched are a i +j*k1, i=C, j=1, 2, 3; these three instructions are marked as prefetched and will continue to be prefetched until the confidence level is 0.

[0098] S3-5, if the cache invalidation type is transitional, the addresses of the two memory lines to be prefetched are a i +j*(k1+k0), i=C, j=1,2, mark these two instructions as prefetch, and continue prefetching until the confidence level is 0 and stop prefetching;

[0099] S3-6, after the address is obtained, it is stored in the local address table, and a data prefetch request is sent to the main memory via the bus.

[0100] S4, adjust the historical record table based on the hit rate of the prefetched data group, control the replacement rule of the historical record table, and control the prefetching stop. The specific process is as follows:

[0101] S4-1, the confidence level ranges from 00, 01, 10, to 11, with all types initially set to 10. The confidence levels, from lowest to highest, are 00, 01, 10, and 11. 00 is the minimum value, indicating that data previously prefetched due to a cache miss can no longer be retrieved. In other words, data that would have been needed in the previous cache miss is no longer required. It's becoming increasingly useless, and the entries in this historical record table can be cleared.

[0102] S4-2, waiting for data to be prefetched from main memory and placed into the prefetch data group;

[0103] S4-3, If the instruction address hits the prefetch data group, a prefetch hit signal is generated, the cache is refilled from the prefetch data group, the corresponding type confidence is incremented by 1, and then the process returns to step S3 to calculate the address of the prefetch data and continue to perform prefetching.

[0104] S4-4, if the instruction address does not hit the prefetch data group, decrease the confidence level by 1; then return to step S3 to calculate the instruction address for prefetching data; when the confidence level decreases to 00, stop prefetching and notify the history table to set the valid position of the instruction address to 0.

[0105] Example 2

[0106] A cache dynamic data prefetching system based on a local algorithm is provided to implement a cache dynamic data prefetching method based on a local algorithm provided in Embodiment 1. The system includes a history record table construction module, a prefetch type discrimination module, a prefetch address storage module, and a control prefetching module connected in sequence.

[0107] The historical record table construction module is used to implement step S1; the prefetch type discrimination module is used to implement step S2; the prefetch address storage module is used to implement step S2; and the control prefetch module is used to implement step S4.

[0108] Example 3

[0109] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the cache dynamic data prefetching method based on a local algorithm provided in Embodiment 1.

[0110] Example 4

[0111] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the cache dynamic data prefetching method based on a local algorithm provided in Embodiment 1.

Claims

1. A high-speed cache dynamic data prefetching method based on a local algorithm, characterized in that, The method is applied to caching and specifically includes: S1, Build a history table, which is used to record the address of the instruction that has been cached invalidated; S2, read the historical record table, calculate the prefetch step size, and determine the cache invalidation type; the specific process is as follows: S2-1, Read the history table and determine whether the cache-invalidated address hits the history table. If it hits and the table entry is valid, jump to step S4 and return the corresponding data of the prefetched data group; if it does not hit or the table entry is invalid after the hit, jump to step S2-2. S2-2, Read only the three cache invalidation addresses of the latest written history table, calculate the change value of the step size, and determine the relationship of the three cache invalidation addresses by calculating the step size; S2-3, assuming the addresses of the three most recent instructions written to the history table from oldest to most recent are a, ... i-2 a i-1 a i ; S2-4, let step size k1 = a i -a i-1 Step size k0 = a i-1 -a i-2 Determine the relationship between the two step sizes k1 and k0. If both k1 and k0 are 0, then the cache invalidation type is determined to be duplicate. If k1 and k0 are both equal and not 0, then the cache invalidation type is determined to be skip type. If k1 and k0 are not equal, but one of them has a step size of 0, then the cache invalidation type is determined to be transitional. If k1 and k0 are not equal and neither is 0, then no data prefetching is performed; and the valid position of the entry containing a2 is set to 0. S2-5, for repeated cache misses, one cache line is prefetched from the bus; S2-6, skip cache miss, prefetches three cache lines to the bus at a time; S2-7, Transitional cache invalidation prefetches two cache lines to the bus at a time; S2-8: After determining the cache invalidation type, record the type in the type field of the history table; S2-9, Save the step size and cache invalidation type and send them to step S3, in preparation for calculating the prefetch address using the local algorithm; S3 uses a local algorithm to calculate the address of the prefetched data, stores the prefetch address in the local address table, and then sends a prefetch request to the main memory via the bus. S4 adjusts the historical record table based on the hit rate of the prefetched data group, controls the replacement rule of the historical record table, and controls the prefetching stop.

2. The method for dynamic data prefetching of a cache based on a local algorithm according to claim 1, characterized in that, The cache is a multi-level cache, and each level of the cache is a multi-way set-connected structure. Each way contains multiple cache lines. Each cache line includes at least a tag bit, a data bit, and a flag bit. The flag bit includes at least a cache valid bit and a write dirty bit.

3. The method for dynamic data prefetching of a cache based on a local algorithm according to claim 1, characterized in that, In step S1, when a cache miss occurs, the miss instruction address is stored in the history table, thereby constructing the history table; the history table includes n entries, each entry including 1 valid bit, 2 type bits, x label bits and miss instruction address bits; The valid bit includes 0 and 1. When the valid bit is 1, it means that the entry is valid and can be selected and read by the read history table action in step S2. When the valid bit is 0, it means that the entry is invalid and the entry is waiting to be replaced by other instruction addresses to be saved. The valid bit is 1 for all three cache miss types after initialization. When a prefetch miss occurs, the valid bit changes from 1 to 0 and waits to be replaced. The type bit includes 01, 10 and 11. Type bit 01 represents that the cache miss type is transitional, type bit 10 represents that the cache miss type is skipped, and type bit 11 represents that the cache miss type is repeated. The label x satisfies: 2 x-1 <n≤2 x And n≥3, x≥2; the x-position labels form the label C.

4. The method for dynamic data prefetching of a cache based on a local algorithm according to claim 1, characterized in that, In step S1, a counter is set to record the label of each entry. The label represents the time order in which the address that has experienced a cache miss is stored in the history table. A count value of 0 indicates that the instruction address in that entry was recorded earliest in the history table. When the history table is full, the historical instruction address in the table is replaced according to the replacement rule. The replacement rule is as follows: when there is an invalid entry, replace the entry with a valid bit of 0 and a smaller label value; if all entries are valid, replace the entry that records the earliest instruction address.

5. The method for dynamic data prefetching of a cache based on a local algorithm according to claim 1, characterized in that, In step S3, the address of the prefetched data is calculated using a local algorithm, the prefetch address is stored in the local address table, and then a prefetch request is sent to the main memory via the bus; the specific process is as follows: S3-1, Obtain the failure type signal and step size; S3-2, when the step size does not span a cache line, set the step size to be equal to the highest bit of the step size plus 1; S3-3, If the failure type is repetitive, the address of the data to be prefetched in memory is a. i If i = C, the instruction is marked as prefetched and will continue to be prefetched until the confidence level is 0. S3-4, If the failure type is skip type, the addresses of the three memory rows to be prefetched are a i +j*k1, i=C, j=1, 2, 3; these three instructions are marked as prefetched and will continue to be prefetched until the confidence level is 0. S3-5, if the cache invalidation type is transitional, the addresses of the two memory lines to be prefetched are a i +j*(k1 +k0), i=C, j=1,2, mark these two instructions as prefetch, and continue prefetching until the confidence level is 0 and stop prefetching; S3-6, after the address is obtained, it is stored in the local address table, and a data prefetch request is sent to the main memory via the bus.

6. The method for dynamic data prefetching of a cache based on a local algorithm according to claim 1, characterized in that, In step S4, the historical record table is adjusted based on the hit rate of the prefetched data group, the replacement rule of the historical record table is controlled, and the prefetching is stopped; the specific process is as follows: S4-1, the confidence level ranges from 00, 01, 10, to 11, and the initial confidence level for all types is set to 10; S4-2, waiting for data to be prefetched from main memory and placed into the prefetch data group; S4-3, If the instruction address hits the prefetch data group, a prefetch hit signal is generated, the cache is refilled from the prefetch data group, the corresponding type confidence is incremented by 1, and then the process returns to step S3 to calculate the address of the prefetch data and continue to perform prefetching. S4-4, if the instruction address does not hit the prefetch data group, decrease the confidence level by 1; then return to step S3 to calculate the instruction address for prefetching data; when the confidence level decreases to 00, stop prefetching and notify the history table to set the valid position of the instruction address to 0.

7. A high-speed cache dynamic data prefetching system based on a local algorithm, characterized in that, A method for implementing a high-speed cache dynamic data prefetching method based on a local algorithm as described in any one of claims 1-6 includes a history record table construction module, a prefetch type discrimination module, a prefetch address storage module, and a control prefetch module connected in sequence. The historical record table construction module is used to implement step S1; the prefetch type discrimination module is used to implement step S2; the prefetch address storage module is used to implement step S2; and the control prefetch module is used to implement step S4.

8. A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the cache dynamic data prefetching method based on a local algorithm as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the cache dynamic data prefetching method based on a local algorithm as described in any one of claims 1-6.

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