Initialization system and method for system-on-chip simulation
By implementing a parallel initialization system and method, the problem of excessive module initialization time in on-chip system simulation was solved, resulting in reduced simulation time and improved efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- OLED IC MICROELECTRONICS BEIJING CO LTD
- Filing Date
- 2022-08-24
- Publication Date
- 2026-06-19
Smart Images
Figure CN115392162B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to an initialization system and method for on-chip system simulation. Background Technology
[0002] System on Chip, or SoC for short, is, in a narrow sense, the chip integration of the core of an information system, integrating key system components onto a single chip. In a broader sense, SoC is a micro-miniature system. In recent years, as the scale and complexity of SoCs have increased, the corresponding logic design and verification have become increasingly complex. In related technologies, SoC simulation is usually required. In a single simulation, the initialization of each module in the SoC usually adopts a serial initialization method, with nearly half of the time consumed in the initialization of each module. Due to the excessive initialization time, the simulation time is too long, thereby reducing the simulation efficiency. Summary of the Invention
[0003] The purpose of this invention is to provide an initialization system and method for on-chip system simulation, so as to reduce initialization time, thereby reducing simulation time and improving simulation efficiency.
[0004] This invention provides an initialization system for simulation of a system-on-a-chip (SoC). The SoC includes multiple functional modules. The initialization system includes: an address decoding module, a queue maintenance module, and a driver logic module, which are sequentially connected by communication. The queue maintenance module includes a queue maintenance submodule corresponding to each functional module. The driver logic module includes a driver logic submodule corresponding to each functional module.
[0005] The address decoding module is used to parse the address information and initialization commands for at least one functional module from the acquired underlying read and write functions; based on the address information of each functional module, each initialization command is sent to the corresponding queue maintenance submodule for caching.
[0006] The driver logic submodule corresponding to each functional module is used to obtain the initialization command from the queue maintenance submodule corresponding to that functional module and send it to the corresponding functional module so that the functional module can perform initialization according to the initialization command.
[0007] Furthermore, each initialization command includes a read command and / or a write command; each queue maintenance submodule includes a read queue and a write queue; the address decoding module is also used to send the read command of each functional module to the corresponding read queue, and / or send the write command of each functional module to the corresponding write queue, based on the address information of each functional module in at least one functional module.
[0008] Furthermore, the system also includes: a low-level read / write function modification module; the low-level read / write function modification module is used to receive modification instructions for the low-level read / write functions, so as to modify the low-level read / write functions and obtain the modified low-level read / write functions.
[0009] Furthermore, the address decoding module is also used to obtain the modified underlying read / write function after sending the initialization command of each functional module in at least one functional module to the corresponding queue maintenance submodule. The modified underlying read / write function is used as the new underlying read / write function, and the steps of parsing the address information and initialization command for at least one functional module from the obtained underlying read / write function are repeated until each initialization command is sent to the corresponding queue maintenance submodule for caching.
[0010] Furthermore, the address decoding module is also used to activate the queue maintenance submodule corresponding to the specified functional module if the specified address information in at least one of the parsed address information indicates that the specified functional module corresponding to it is accessed for the first time, and the queue maintenance submodule corresponding to the specified functional module is empty.
[0011] Furthermore, the driver logic submodule corresponding to each functional module is pre-bound to the bus interface of each functional module; the driver logic submodule corresponding to each functional module is also used to obtain the initialization command from the queue maintenance submodule corresponding to the functional module, and use the general bus transmission method to call the preset DPI function to send the initialization command to the corresponding functional module through the bus interface of the functional module.
[0012] Furthermore, the chip architecture of the system-on-a-chip uses the same bus protocol.
[0013] Furthermore, the underlying read / write functions are obtained by integrating preset initialization functions and preset register interface functions.
[0014] This invention provides an initialization method for on-chip system simulation. The method includes: an address decoding module parsing address information and initialization commands for at least one functional module from the acquired underlying read / write functions; sending each initialization command to a corresponding queue maintenance submodule for caching based on the address information of each functional module; and the driver logic submodule corresponding to each functional module obtaining the initialization command from the queue maintenance submodule corresponding to that functional module and sending it to the corresponding functional module so that the functional module performs initialization according to the initialization command.
[0015] Furthermore, each initialization command includes a read command and a write command; each queue maintenance submodule includes a read queue and a write queue; the method also includes: the address decoding module sends the read command of each functional module to the corresponding read queue and the write command of each functional module to the corresponding write queue according to the address information of each functional module.
[0016] This invention provides an initialization system and method for on-chip system simulation. An address decoding module parses address information and initialization commands for at least one functional module from acquired low-level read / write functions. Based on the address information of each functional module, each initialization command is sent to a corresponding queue maintenance submodule for caching. A driver logic submodule for each functional module retrieves the initialization command from its corresponding queue maintenance submodule and sends it to the corresponding functional module, enabling the module to initialize according to the command. This system sets up a corresponding queue maintenance submodule and driver logic submodule for each functional module. After the address decoding module parses the address information and initialization commands for at least one functional module, it can process each initialization command in parallel, performing parallel initialization of the corresponding functional modules through their respective queue maintenance submodules and driver logic submodules. This parallel initialization method reduces initialization and simulation time, improving simulation efficiency. Attached Figure Description
[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This invention provides a schematic diagram of the structure of an initialization system in system-on-a-chip simulation.
[0019] Figure 2 This is another schematic diagram of the initialization system in on-chip system simulation provided by an embodiment of the present invention;
[0020] Figure 3 This is a schematic diagram of the structure of a queue maintenance module provided in an embodiment of the present invention;
[0021] Figure 4 A schematic diagram of the structure of a driving logic module provided in an embodiment of the present invention;
[0022] Figure 5This is a schematic diagram of the structure of an address decoding module provided in an embodiment of the present invention. Detailed Implementation
[0023] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0024] System on Chip, or SoC for short, is a microprocessor integrated into a single chip. In a narrow sense, it refers to the integration of the core components of an information system onto a single chip. In a broader sense, SoC is a miniature system; if the central processing unit (CPU) is the brain, then SoC is a system that includes the brain, heart, eyes, and hands. The academic community, both domestically and internationally, generally defines SoC as integrating a microprocessor, analog IP cores, digital IP cores, and memory (or off-chip memory control interfaces) onto a single chip. It is typically a customer-customized or application-specific standard product.
[0025] In recent years, with the increasing scale and complexity of SoCs, the corresponding logic design and verification have become increasingly complex, and excessive simulation time has become a bottleneck in verification work. Although we now have increasingly powerful server computing capabilities, they still cannot meet the requirements of rapid iteration of simulation time in project plans. Typically, in a single simulation, nearly half of the time is consumed in the initialization of various modules. Module initialization is a fairly common process for different tests, and if the simulation time for module initialization can be reduced, almost all tests will benefit. Existing methods for accelerating module initialization include backdoor initialization and save & restore techniques, both of which have certain drawbacks and limitations. Backdoor initialization does not include the stimulation and response on the bus during the initialization process, and cannot meet the coverage requirements; save & restore has very high requirements for simulation software and environment, and due to the immaturity of this technology, it is easy to introduce new tooling problems, leading to simulation failure. Furthermore, existing initialization methods usually use serial initialization, which results in excessive initialization time, leading to excessive simulation time and thus reducing simulation efficiency.
[0026] Based on this, embodiments of the present invention provide an initialization system and method for on-chip system simulation. This technology can be applied to scenarios that require system initialization, especially to on-chip system initialization scenarios.
[0027] To facilitate understanding of this embodiment, a detailed description of an initialization system for on-chip system simulation disclosed in this embodiment of the invention will be provided first; the on-chip system includes multiple functional modules; such as Figure 1 As shown, the initialization system includes: an address decoding module 10, a queue maintenance module 11, and a driver logic module 12, which are connected in sequence. The queue maintenance module 11 includes a queue maintenance submodule 110 corresponding to each functional module. The driver logic module 12 includes a driver logic submodule 120 corresponding to each functional module. The address decoding module 10 is used to parse the address information and initialization command for at least one functional module from the acquired underlying read / write functions. Based on the address information of each functional module, it sends each initialization command to the corresponding queue maintenance submodule 110 for caching. The driver logic submodule 120 corresponding to each functional module is used to obtain the initialization command from the queue maintenance submodule 110 corresponding to that functional module and send it to the corresponding functional module so that the functional module initializes according to the initialization command.
[0028] In actual implementation, the system-on-a-chip usually integrates multiple functional modules. The queue maintenance module 11 of the initialization system is configured with a corresponding queue maintenance submodule 110 for each functional module, and the drive logic module 12 is configured with a corresponding drive logic submodule 120 for each functional module.
[0029] When the on-chip system needs to be initialized, the address decoding module 10 can call the underlying read / write function. This underlying read / write function usually carries the address information of one or more functional modules that need to be initialized and the corresponding initialization commands. The address decoding module 10 can parse these address information and initialization commands, map each parsed address information to a specific functional module, and send the corresponding initialization commands to the queue maintenance submodule 110 corresponding to each functional module that needs to be initialized for caching. The initialization commands cached in each queue maintenance submodule 110 are sent to the corresponding functional module's driver logic submodule 120 according to the first-in-first-out logic. The driver logic submodule 120 sends each initialization command to the functional module that needs to be initialized, so that each functional module that needs to be initialized can complete the initialization according to the received initialization commands.
[0030] For example, a system-on-a-chip (SoC) includes functional modules A, B, and C. The address decoding module parses the address information and corresponding initialization command A of functional module A, as well as the address information and corresponding initialization command B of functional module B, from the underlying read / write functions. This indicates that functional modules A and B need to be initialized. Initialization command A can be sent to the queue maintenance submodule A corresponding to functional module A, and initialization command B can be sent to the queue maintenance submodule B corresponding to functional module B. The driver logic submodule A corresponding to functional module A can retrieve initialization command A from the queue maintenance submodule A and send it to functional module A, enabling functional module A to initialize according to initialization command A. Simultaneously, the driver logic submodule B corresponding to functional module B can retrieve initialization command B from the queue maintenance submodule B and send it to functional module B, enabling functional module B to initialize according to initialization command B. In other words, the initialization operations for functional modules A and B can be executed in parallel.
[0031] The aforementioned initialization system in on-chip system simulation uses an address decoding module to parse address information and initialization commands for at least one functional module from the acquired low-level read / write functions. Based on the address information of each functional module, each initialization command is sent to its corresponding queue maintenance submodule for caching. The driver logic submodule for each functional module retrieves the initialization command from its corresponding queue maintenance submodule and sends it to the corresponding functional module, enabling it to initialize accordingly. This system sets up a corresponding queue maintenance submodule and driver logic submodule for each functional module. After the address decoding module parses the address information and initialization commands for at least one functional module, it can process each initialization command in parallel, performing parallel initialization of the corresponding functional modules through their respective queue maintenance submodules and driver logic submodules. This parallel initialization method reduces initialization and simulation time, improving simulation efficiency.
[0032] Furthermore, each initialization command includes a read command and / or a write command; each queue maintenance submodule includes a read queue and a write queue; the address decoding module is also used to send the read command of each functional module to the corresponding read queue, and / or send the write command of each functional module to the corresponding write queue, based on the address information of each functional module in at least one functional module.
[0033] See Figure 2The diagram shows another architecture for the initialization system of an on-chip system. The queue maintenance module is the core of the entire design, playing a crucial role in the system architecture. On one hand, the queue maintenance module records / caches / maintains various read and write commands received from the address decoding module; on the other hand, it sends the corresponding read and write commands to the driver logic module when certain conditions are met. To support parallel initialization of multiple modules, each functional module in the on-chip system has its own dedicated queue, and each functional module's queue contains independent read and write queues, such as... Figure 3 The diagram shows the structure of a queue maintenance module.
[0034] Specifically, initializing a functional module can involve reading messages from or writing messages to that module. Therefore, each parsed initialization command may contain only read commands, only write commands, or both. The configuration can be tailored to the specific initialization requirements. Each queue maintenance submodule will have read and write queues. Read commands from the initialization commands are sent to the corresponding read queue via the read queue interface, and write commands are sent to the corresponding write queue via the write queue interface. In this embodiment, decoding the address mapping relationship is typically generated automatically using a script based on the register documentation. Manual coding is used only in rare cases. The advantage of using a script is its speed and reduced error rate.
[0035] Furthermore, the system also includes: a low-level read / write function modification module; the low-level read / write function modification module is used to receive modification instructions for the low-level read / write functions, so as to modify the low-level read / write functions and obtain the modified low-level read / write functions.
[0036] In actual implementation, users can modify the underlying read and write functions through the underlying read and write function modification module to modify the address information and initialization commands of the functional modules that need to be initialized.
[0037] Furthermore, the address decoding module is also used to obtain the modified underlying read / write function after sending the initialization command of each functional module in at least one functional module to the corresponding queue maintenance submodule. The modified underlying read / write function is used as the new underlying read / write function, and the steps of parsing the address information and initialization command for at least one functional module from the obtained underlying read / write function are repeated until each initialization command is sent to the corresponding queue maintenance submodule for caching.
[0038] In some complex systems, multiple different low-level read / write functions may need to be called. After the address decoding module sends the initialization commands of a portion of the functional modules corresponding to the current low-level read / write function to their respective queue maintenance submodules, the user can modify the current low-level read / write function through the low-level read / write function modification module to handle the parallel initialization of another portion of the functional modules. For example, the address decoding module parses the address information and initialization command of functional module A from the current low-level read / write function. After sending the address information and initialization command to the queue maintenance submodule A corresponding to functional module A, the user can modify the current low-level read / write function, such as changing the carried address information to the address information of functional module B and the corresponding initialization command to the initialization command corresponding to functional module B, to initialize functional module B. The user can start the initialization process of functional module B without waiting for the actual initialization of functional module A to be completed, thus realizing the parallel initialization of functional modules A and B. Since serial processing is not required, the initialization time is reduced.
[0039] Furthermore, the address decoding module is also used to activate the queue maintenance submodule corresponding to the specified functional module if the specified address information in at least one of the parsed address information indicates that the specified functional module corresponding to it is accessed for the first time, and the queue maintenance submodule corresponding to the specified functional module is empty.
[0040] The specified address information mentioned above can be any address information from at least one address information. In actual implementation, considering the impact of multiple queue maintenance submodules on simulation performance, the queue maintenance logic of the queue maintenance submodules corresponding to each functional module is not enabled by default. The corresponding queue maintenance submodule is only activated and enters the corresponding enabled state when the functional module is accessed for the first time. Usually, when a functional module is accessed for the first time, its corresponding queue maintenance submodule is empty. After the queue maintenance submodule is activated, if it is empty again during subsequent initialization, it does not need to be reactivated since the queue maintenance submodule has already been activated. Generally, in a single test, only some functional modules are accessed. Therefore, dynamically controlling the activation of queue maintenance submodules can greatly save simulation resources and improve simulation speed.
[0041] Furthermore, the driver logic submodule corresponding to each functional module is pre-bound to the bus interface of each functional module; the driver logic submodule corresponding to each functional module is also used to obtain the initialization command from the queue maintenance submodule corresponding to the functional module, and use a general bus transmission method to call the preset DPI (Direct Program Interface) function to send the initialization command to the corresponding functional module through the bus interface of the functional module.
[0042] In the on-chip system, the driver logic submodule corresponding to each functional module is pre-bound to the bus interface of the corresponding functional module. The read queue corresponds to a read bus, and the write queue corresponds to a write bus. This can be based on SystemC code and uses DPI functions as an interface to access the System Verilog language, thereby realizing the interaction between software initialization code and hardware bus behavior. The driver logic module is the last part of this system structure; it is the output terminal and also the interface between SystemC and System Verilog. Through multiple DPI functions, it maps software behavior to hardware simulation. By driving general-purpose buses, such as APB (Advanced Peripheral Bus), AHB (Advanced High Performance Bus), and OCP (Open Core Protocol), it simulates bus access behavior, sending read and write operations to the simulated bus, thereby realizing register and memory read and write operations and completing the initialization tasks of the relevant functional modules, such as... Figure 4 The diagram shows a structural schematic of a drive logic module. It adopts a general bus transmission method, calls a preset DPI function, and sends the initialization command to the corresponding sub-module through the general bus interface of each sub-module (corresponding to the above functional module).
[0043] Furthermore, the chip architecture of the system-on-a-chip uses the same bus protocol.
[0044] Specifically, this embodiment can verify various system-on-a-chip chips, such as ARM (a processor), RISC-V (a processor), MIPS (a processor), etc. Different processors often correspond to different bus protocols, but the bus protocols within the same chip are unified. Therefore, this embodiment only needs to adjust the parts related to the bus protocol to support system-on-a-chip based on different processors, and has high versatility.
[0045] Furthermore, the underlying read / write functions are obtained by integrating preset initialization functions and preset register interface functions.
[0046] See Figure 5The diagram illustrates the structure of an address decoding module. There may be one initialization function, but typically multiple register interface functions. The initialization function and preset register interface functions are integrated to obtain the underlying read / write functions. The address decoding module maps the parsed address information to specific functional modules and activates the access queue of the corresponding functional modules. In the initialization code, developers call different functions to access registers, thereby initializing the corresponding functional modules. In some complex systems, there may be multiple different register access functions, and different functional modules and developers may use different functions. If fast parallel access is achieved by modifying these functions, on the one hand, the number of functions that need to be modified is enormous; on the other hand, different functions need to be analyzed, consuming additional time and introducing more risks. This embodiment, without changing any code at the top level, selects different branches within the general read / write functions and integrates them to obtain the underlying read / write functions. If parallel initialization is required, the new method in this solution can be used; if parallel initialization is not possible, the original method in related technologies can be used. Furthermore, this solution can directly modify the underlying read / write functions without modifying the upper-level initialization functions and various register interface functions, achieving fast parallel initialization.
[0047] In a single on-chip system, the register initialization interface for each functional module is typically the same, such as APB, AHB, AXI (Advanced eXtensible Interface), OCP, etc. A universal standard bus protocol makes it possible to reuse functional components; that is, to attach the same driver component to different functional modules. These driver components follow the same standard bus protocol and can smoothly interact with different modules. In other words, for each different functional module in the on-chip system, developers only need to prepare one driver component that conforms to a universal standard bus protocol, and connect it to different functional modules through reuse to complete the initialization task. This method greatly reduces the development difficulty and the probability of errors.
[0048] On the other hand, during the on-chip system initialization process, the initialization processes of some functional modules are dependent, meaning there are requirements regarding the initialization order of different functional modules. For these functional modules, a serial initialization process must be followed. However, for most functional modules, especially those with unrelated functions, the initialization order is not required. For these functional modules, the parallel initialization method described in this embodiment can be used. In related technologies, since all initialization operations are issued by the processor, and the processor initializes each module sequentially by running code (C language or assembly language, etc.), this greatly limits the initialization speed and reduces simulation performance. This solution bypasses the limitation that all initialization operations are issued serially from the processor port by directly applying stimuli to the bus ports of different driver components, thus achieving fast parallel initialization of different modules.
[0049] Unlike the Universal Verification Component (UVC) or Verification Intellectual Property (VIP, used for connecting and checking protocol standards and interfaces) in typical verification environments, this scheme still derives its stimulus from the original processor code. Parallel calls are implemented through SystemC code, enabling rapid parallel initialization of various functional modules. No code was rewritten or converted from C to other languages throughout the process. The code for initializing each functional module is typically complex and maintained by multiple people; therefore, reusing this code saves significant time and resources, reduces the probability of errors, and closely approximates the actual initialization process. Simultaneously, the hardware paths from the bus ports of each functional module to their internal components are fully preserved, allowing for thorough verification of this logic. This scheme uses a simple and fast method to convert serial initialization into parallel initialization while preserving some bus behavior, thus simultaneously meeting the speed and quality requirements of simulation verification.
[0050] This invention provides an initialization method for on-chip system simulation. The method includes: an address decoding module parsing address information and initialization commands for at least one functional module from the acquired underlying read / write functions; sending each initialization command to a corresponding queue maintenance submodule for caching based on the address information of each functional module; and the driver logic submodule corresponding to each functional module obtaining the initialization command from the queue maintenance submodule corresponding to that functional module and sending it to the corresponding functional module so that the functional module performs initialization according to the initialization command.
[0051] The initialization method described above for on-chip system simulation differs from the traditional serial initialization process. In this method, sub-initialization tasks on different modules are executed in parallel. Furthermore, this parallel initialization logic is based on the original serial initialization logic, and through simple transformation, it retains reusable logic to the greatest extent possible, requiring minimal additional logic. From a performance perspective, the more complex the on-chip system and the more functional modules that can be initialized in parallel, the higher the proportion of simulation time saved by this method, and the better the effect.
[0052] Furthermore, each initialization command includes a read command and a write command; each queue maintenance submodule includes a read queue and a write queue; the method also includes: the address decoding module sends the read command of each functional module to the corresponding read queue and the write command of each functional module to the corresponding write queue according to the address information of each functional module.
[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. An initialization system for system-on-chip simulation, characterized by, The system-on-a-chip includes multiple functional modules; the initialization system includes: an address decoding module, a queue maintenance module, and a driver logic module that are sequentially connected in communication; wherein, the queue maintenance module includes a queue maintenance sub-module corresponding to each functional module; the driver logic module includes a driver logic sub-module corresponding to each functional module; The address decoding module is used to parse the address information and initialization command for at least one functional module from the acquired underlying read and write functions; according to the address information of each of the at least one functional module, each initialization command is sent to the corresponding queue maintenance submodule for caching. The driving logic submodule corresponding to each of the functional modules is used to obtain the initialization command from the queue maintenance submodule corresponding to that functional module and send it to the corresponding functional module so that the functional module performs initialization according to the initialization command; The system also includes: a module for modifying underlying read / write functions; The underlying read / write function modification module is used to receive modification instructions for the underlying read / write function, modify the underlying read / write function, and obtain the modified underlying read / write function. The address decoding module is further configured to, after sending the initialization command of each functional module in the at least one functional module to the corresponding queue maintenance submodule, obtain the modified underlying read / write function, use the modified underlying read / write function as the new underlying read / write function, and repeatedly execute the step of parsing the address information and initialization command for the at least one functional module from the obtained underlying read / write function, until each initialization command is sent to the corresponding queue maintenance submodule for caching.
2. The system according to claim 1, characterized in that, Each of the initialization commands includes a read command and / or a write command; each of the queue maintenance submodules includes a read queue and a write queue; The address decoding module is further configured to send the read command of each functional module to the corresponding read queue and / or send the write command of each functional module to the corresponding write queue based on the address information of each functional module in the at least one functional module.
3. The system according to claim 1, characterized in that, The address decoding module is further configured to activate the queue maintenance submodule corresponding to the specified function module if the specified address information in at least one parsed address information indicates that the specified function module corresponding to it is accessed for the first time, and the queue maintenance submodule corresponding to the specified function module is empty.
4. The system according to claim 1, characterized in that, The driving logic submodule corresponding to each of the functional modules is pre-bound to the bus interface of each of the functional modules; The driving logic submodule corresponding to each of the functional modules is further configured to obtain the initialization command from the queue maintenance submodule corresponding to the functional module, and send the initialization command to the corresponding functional module through the bus interface of the functional module by calling the preset DPI function using a general bus transmission method.
5. The system of claim 1, wherein, The chip architecture of the system-on-a-chip uses the same bus protocol.
6. The system of claim 1, wherein, The underlying read / write functions are obtained by integrating preset initialization functions and preset register interface functions.
7. A method for initialization in system-on-chip simulation, the method comprising: The method includes: The address decoding module parses the address information and initialization commands for at least one functional module from the acquired underlying read and write functions; based on the address information of each of the at least one functional module, it sends each initialization command to the corresponding queue maintenance submodule for caching; The driving logic submodule corresponding to each functional module obtains the initialization command from the queue maintenance submodule corresponding to that functional module and sends it to the corresponding functional module so that the functional module performs initialization according to the initialization command; The underlying read / write function modification module receives modification instructions for the underlying read / write function to modify the underlying read / write function and obtain the modified underlying read / write function. After the address decoding module sends the initialization command of each functional module in the at least one functional module to the corresponding queue maintenance submodule, it obtains the modified underlying read / write function, uses the modified underlying read / write function as the new underlying read / write function, and repeatedly executes the step of parsing the address information and initialization command for the at least one functional module from the obtained underlying read / write function until each initialization command is sent to the corresponding queue maintenance submodule for caching.
8. The method of claim 7, wherein, Each initialization command includes a read command and a write command; each queue maintenance submodule includes a read queue and a write queue; the method further includes: The address decoding module sends the read command of each functional module to the corresponding read queue and the write command of each functional module to the corresponding write queue according to the address information of each functional module.