A circuit design segmentation method and device

Abstract

The present application provides a method and device for segmenting a circuit design. Before segmenting the circuit design, a pre-processing step is added, including: first calculating the arrival time of each node, then determining the critical path, and then increasing the weight value of each connection on the critical path based on the delay constraint information; at the same time, converting the circuit design into a topology diagram and determining the level of each node, and then removing cross-layer connections with too large a level difference. Through the above pre-segmentation, higher weight values ​​are assigned to the connections in the paths with larger delays and the connections that easily cause the same path to be cut repeatedly, or they are deleted to prevent them from being cut, so that when the circuit is segmented next, the cutting of the paths with larger delays and the repeated cutting of the same path can be avoided as much as possible, thereby effectively reducing or even eliminating the problem of increased overall circuit delay caused by improper cutting, so that the operating speed of the system is significantly improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method and device for segmenting a circuit design. Background Art

[0002] Before a chip goes into production, a prototyping system based on an FPGA (Field Programmable Gate Array) is typically used to perform logic verification on the chip design. With the rapid advancement of technology, the integration and complexity of chips are constantly increasing. To address the conflict between chip design scale and the logic capacity of a single FPGA, multiple FPGAs can be interconnected via interconnects to form a networked system, enabling the loading and verification of the entire chip design. In this scenario, large circuit designs, such as chips, need to be segmented (or partitioned).

[0003] While implementing this solution, the inventors discovered that the latency of signal transmission between FPGAs is significantly greater than the latency of signal transmission within an FPGA. Consequently, segmenting circuit designs, such as chips, often introduces new problems that were not present in the original design. The industry continues to face the challenge of figuring out how to segment circuits in a way that more efficiently and accurately reflects the functionality of the original design.

[0004] In the prior art, when chip design is segmented, the delay of the entire path is often not taken into consideration. For example, the delay of the path with the longest delay may be made longer, resulting in a longer delay for the entire system, which reduces the overall system frequency and thus reduces system performance. Summary of the Invention

[0005] The present application provides a circuit design segmentation method and device to solve the technical problem of increased overall delay of the circuit system due to improper segmentation.

[0006] According to a first aspect of an embodiment of the present application, a circuit design segmentation method is provided, the method comprising:

[0007] Obtaining circuit design information according to a design file corresponding to the circuit design, the circuit design information including node interconnection information, delay constraint information, and internal delay of each node, wherein the node interconnection information includes a connection relationship between nodes and a delay value of a connection between nodes, the internal delay of a node is a delay value of a signal from an input port to an output port of the node, and the delay constraint information includes an upper limit of a delay value between nodes;

[0008] Calculate the arrival time of each node, where the arrival time of each node is the maximum delay from the starting node to the current node;

[0009] Determine a critical path, wherein the critical path is a path starting from a start node and ending at an end node, and a path delay value of the critical path is equal to an arrival time at the end node;

[0010] According to the delay constraint information, the weight value of each link on the critical path is increased according to a preset strategy, wherein the weight value of the link is inversely correlated with the probability of the link being cut during segmentation;

[0011] Converting the circuit design into a topology graph and determining the level of each node, wherein the starting node is the first level;

[0012] Remove cross-layer connections, where the difference in level between two nodes connected by the cross-layer connection is greater than a preset value;

[0013] The circuit design after the above processing is divided according to a preset process.

[0014] Optionally, before calculating the arrival time of each node, the method further includes:

[0015] determining whether there is a loop path in the circuit design;

[0016] If a circular path exists, cut the circular path from the data terminal of the flip-flop device.

[0017] Optionally, obtain the internal latency of each node, including:

[0018] If the node is a combinational logic node, the maximum delay value of all paths within the node is used as the internal delay of the node.

[0019] If this node is sequential logic, the period of the clock domain where this node is located is used as the internal delay of this node.

[0020] Optionally, calculate the arrival time for each node, including:

[0021] Calculate the path delay value of each path from the starting node to the current node;

[0022] The maximum path delay value is selected as the arrival time of this node.

[0023] Optionally, the circuit design information further includes pre-allocation information, where the pre-allocation information is used to indicate pre-allocated nodes, where the pre-allocated nodes are nodes that have been pre-bound to the FPGA board before segmentation.

[0024] Calculate the path delay value of each path from the starting node to the current node, including:

[0025] When the path includes pre-assigned nodes, the path delay value is further added with a corresponding number of group delays, where the group delay is the delay of transmitting signals through interconnection lines between FPGAs.

[0026] Before determining the critical path, the method further includes:

[0027] Determining whether there is a node to be merged, wherein the node to be merged is connected to multiple pre-assigned nodes on the same FPGA; if the node to be merged exists, binding the node to be merged to the same FPGA;

[0028] The starting node is bound to the FPGA where the pre-allocated node closest to it is located, and the ending node is bound to the FPGA where the pre-allocated node closest to it is located, where the closest node means the node with the least number of nodes in between.

[0029] Optionally, before increasing the weight value of each link on the critical path, the method further includes:

[0030] According to the arrival time of the nodes, it is determined whether the upper limit of the delay value between the nodes in the delay constraint information is less than the difference in the arrival time between the nodes, and if it is less than the difference, the method is exited.

[0031] Optionally, the preset strategy includes:

[0032] Determine the maximum number of times the critical path can be cut based on the upper limit of the delay value between the nodes at both ends of the critical path, the difference in arrival time between the nodes at both ends, and the group delay, where the group delay is the delay in transmitting signals through the interconnection lines between the FPGAs;

[0033] According to the maximum number of times and the number of links included in the critical path, the probability of each link in the critical path being cut is determined, and the weight value of each link is increased according to the probability.

[0034] Optionally, converting the circuit design into a topology diagram and determining the hierarchy of each node includes:

[0035] Starting from the starting node, along the longest path, the topology structure is divided into levels according to the principle that the first level is the starting node and the level increases by 1 for each node passed;

[0036] The level of each node is determined by the number of nodes between each node and the starting node.

[0037] According to a second aspect of an embodiment of the present application, a circuit design segmentation device is provided, the device comprising:

[0038] a circuit design information acquisition module, configured to acquire circuit design information based on a design file corresponding to the circuit design, the circuit design information including node interconnection information, delay constraint information, and internal delay of each node, wherein the node interconnection information includes the connection relationship between nodes and the delay value of the connection between nodes, the internal delay of a node is the delay value of a signal from a node input port to an output port, and the delay constraint information includes an upper limit on the delay value between nodes;

[0039] The splitting preprocessing module is configured to: calculate the arrival time of each node, wherein the arrival time of each node is the maximum delay from the starting node to the current node; determine a critical path, wherein the critical path is a path starting from the starting node and ending at the ending node, and the path delay value of the critical path is equal to the arrival time of the ending node; increase the weight value of each link on the critical path according to a preset strategy based on the delay constraint information, wherein the weight value of the link is inversely correlated with the probability of the link being cut during splitting; convert the circuit design into a topological graph and determine the level of each node, wherein the starting node is the first level; remove cross-layer links, wherein the difference between the levels of the two nodes connected by the cross-layer link is greater than a preset value;

[0040] The segmentation module is used to segment the circuit design processed by the segmentation pre-processing module according to a preset process.

[0041] Optionally, the segmentation preprocessing module is further used to:

[0042] Before calculating the arrival time of each node, it is determined whether there is a loop path in the circuit design. If there is a loop path, the loop path is cut off from the data end of the trigger device.

[0043] Optionally, the circuit design information acquisition module is specifically configured to:

[0044] If the node is combinational logic, the maximum delay value of all paths within the node is used as the internal delay of the node. If the node is sequential logic, the period of the clock domain in which the node is located is used as the internal delay of the node.

[0045] Optionally, when calculating the arrival time of each node, the segmentation preprocessing module is specifically used to:

[0046] Calculate the path delay value of each path from the starting node to the current node, and select the largest path delay value as the arrival time of the current node.

[0047] Optionally, the circuit design information further includes pre-allocation information, where the pre-allocation information is used to indicate pre-allocated nodes, where the pre-allocated nodes are nodes that have been pre-bound to the FPGA board before segmentation.

[0048] When the path includes pre-assigned nodes, the segmentation pre-processing module also adds a corresponding number of group delays when calculating the path delay value, where the group delay is the delay of transmitting signals through interconnection lines between FPGAs.

[0049] The segmentation preprocessing module is further configured to: before determining the critical path, determine whether there is a node to be merged, wherein the node to be merged is connected to multiple pre-allocated nodes on the same FPGA; if the node to be merged exists, bind the node to be merged to the same FPGA; bind the starting node to the FPGA on which the pre-allocated node closest to it is located, and bind the ending node to the FPGA on which the pre-allocated node closest to it is located, wherein the term "closest" means the node with the least number of nodes in between.

[0050] Optionally, the segmentation preprocessing module is further used to:

[0051] Before increasing the weight value of each link on the critical path, it is determined whether the upper limit of the delay value between nodes in the delay constraint information is less than the difference in the arrival time between nodes based on the arrival time of the nodes. If so, the processing is terminated.

[0052] Optionally, the preset strategy includes:

[0053] Determine the maximum number of times the critical path can be cut based on the upper limit of the delay value between the nodes at both ends of the critical path, the difference in arrival time between the nodes at both ends, and the group delay, where the group delay is the delay in transmitting signals through the interconnection lines between the FPGAs;

[0054] According to the maximum number of times and the number of links included in the critical path, the probability of each link in the critical path being cut is determined, and the weight value of each link is increased according to the probability.

[0055] Optionally, when converting the circuit design into a topology graph and determining the level of each node, the segmentation pre-processing module is specifically configured to:

[0056] Starting from the starting node, along the longest path, the topology structure is divided into levels according to the principle that the first level is the starting node and the level increases by 1 for each node passed; the level of each node is determined by the number of nodes between each node and the starting node.

[0057] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0058] In an embodiment of the present application, a preprocessing step is added before segmenting a circuit design, such as a chip. The steps include: first calculating the arrival time of each node, then determining all critical paths, and then increasing the weight of each connection on the critical path according to a preset strategy based on the delay constraint information. Simultaneously, the circuit design is converted into a topology graph and the level of each node is determined. Cross-level connections are then removed, where the difference in level between the two nodes connected by a cross-level connection is greater than a preset value β. After this preprocessing, the circuit design is segmented according to the preset process.

[0059] Through the above pre-segmentation preprocessing, the connections in the paths with larger delays and the connections that easily cause the same path to be repeatedly cut are given higher weight values ​​or deleted to prevent them from being cut. Therefore, when the circuit is segmented next, the cutting of paths with larger delays and the repeated cutting of the same path can be avoided as much as possible. This can effectively reduce or even eliminate the problem of increased overall circuit delay caused by improper cutting, and significantly improve the system's operating speed.

[0060] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following briefly introduces the drawings required for the embodiments or the prior art description. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without inventive work. In addition, these introductions do not constitute a limitation of the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0062] Figure 1 It is a schematic diagram of a scene where nodes are connected;

[0063] Figure 2 This is a schematic diagram of the data output after passing through m1, m2, and m3;

[0064] Figure 3 This is another schematic diagram of a node connection scenario;

[0065] Figure 4 is a schematic flow chart of a circuit design segmentation method provided in an embodiment of the present application;

[0066] Figure 5 This is a schematic diagram of level division in an embodiment of the present application;

[0067] Figure 6 is a schematic diagram of cutting a circular path in an embodiment of the present application;

[0068] Figure 7 This is a schematic diagram of node connections with fixed nodes in an embodiment of the present application;

[0069] Figure 8 The overall flow chart of the segmentation process provided in the embodiment of the present application;

[0070] Figure 9 This is a schematic diagram of a circuit segmentation device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the drawings in the embodiments of the present application. When referring to the drawings, unless otherwise specified, the same numbers in different drawings represent the same or similar elements. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments, or the embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0072] When the terms "first", "second", "third", etc. appear in the specification, claims, and above-mentioned drawings of the embodiments of the present application, they are used to distinguish different objects, rather than to limit a specific order. In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way.

[0073] To facilitate understanding, the following briefly introduces the terms and other related concepts involved in the embodiments of this application:

[0074] Node: In circuit design such as chips, a node is a module in the circuit design.

[0075] Start node: A node that has only output and no input.

[0076] Sink node: A node that has only input and no output.

[0077] Fixed node: A node that has been pre-assigned (or bound) to certain FPGAs before segmentation.

[0078] Net: A line connecting two adjacent nodes is called a net, and in this article it is also called a net. Each net has a corresponding delay value.

[0079] Path: A series of connected lines and nodes on them constitutes a path. The path delay of a path is the sum of the delay of all lines on the path and the internal delay of all nodes on the path.

[0080] Group delay: Group delay is the delay in transmitting signals on interconnect lines between FPGAs.

[0081] Large circuit designs, such as chips, require multiple interconnected FPGAs to accommodate and verify them. FPGA prototyping systems support partitioning of large designs. However, the signal latency of interconnects between FPGAs is much greater than the latency of signals within the FPGA itself. Therefore, partitioning often introduces new issues that were not present in the original design. Finding partitioning that more efficiently and accurately reflects the functionality of the original design has been a persistent challenge for the industry.

[0082] Many types of delay exist within user-designed logic and partition groups, with different logic units employing varying delay values. The inventors believe that to achieve optimal partitioning results for circuit designs, partitioning tools must consider minimum or user-specified timing constraints (critical paths, minimum-maximum delays, and so on). Lower overall delay values ​​translate to higher overall system efficiency, so the goal is to minimize data path latency expectations during the partitioning process.

[0083] In the prior art, when segmenting chip designs, the latency of the entire path is often not considered. For example, the latency of the path with the longest latency may be increased, resulting in a longer latency for the entire system, which in turn reduces the overall system frequency and significantly degrades system performance. The following are two common scenarios of improper segmentation discovered by the inventors during the implementation of this application:

[0084] Scenario 1:

[0085] See also Figure 1 and Figure 2 shown. Figure 1 A schematic diagram of a node connection scenario. Figure 1 There are multiple paths for signal transmission between midpoint nodes g0 and g1. The paths passing through m1, m2, and m3 are called r1, r2, and r3 respectively. Figure 2 This is a schematic diagram of the data output after passing through m1, m2, and m3. Figure 2In the figure, data1 represents the data transmitted by path r1 at the first moment, and data1' represents the data transmitted by path r1 at the second moment. That is, data1 and data1' respectively represent the data transmitted by the same path at different time periods. The same is true for data2, data2', data3, and data3' in the figure. Figure 2 As can be seen from the figure, the data signal output through m2 has the longest delay. If path r2 is cut, the signal on path r2 needs to be transmitted across two different FPGA boards, which will cause the delay of r2, which originally has the longest delay, to become even longer, resulting in longer delay for the entire system and lower system efficiency.

[0086] Scenario 2:

[0087] See also Figure 3 shown. Figure 3 This is a schematic diagram of another node connection scenario. Figure 3 In the figure, cut1 and cut2 represent different cutting methods. Figure 3 As can be seen in the figure, if the cut method is used, nodes g2, g3, and g4 will be on one FPGA, and the other nodes (g0, g1, g5, g6, g7, and g8) will be on another FPGA. However, if the cut method is used, g0, g1, g2, g6, and g8 will be on one FPGA, and the other nodes will be on another FPGA. Cut 1 cuts the path g0→g2→g3→g4→g5 twice, causing the signal on this path to cross the board twice. This means that the delay is doubled by the group delay, which affects the overall system speed by double the group delay. While cut 2 cuts more paths, each path is cut only once, affecting the overall system speed by only a single group delay.

[0088] There are multiple paths in the user design, and the delay of each path is different. Through the above analysis, the inventors found that in the process of segmenting the circuit design, the current segmentation scheme does not consider how to avoid cutting paths with longer delays as much as possible, and how to avoid repeatedly cutting the same path as much as possible.

[0089] Figure 4 This is a schematic flow chart of a circuit design segmentation method provided in an embodiment of the present application. The method can be applied to scenarios such as prototype verification systems.

[0090] See also Figure 4 As shown, the method may include:

[0091] In step S401, circuit design information is obtained based on the design file corresponding to the circuit design, where the circuit design information includes node interconnection information, delay constraint information, and the internal delay of each node. The node interconnection information includes the connection relationship between nodes and the delay value of the connection between nodes. The internal delay of the node is the delay value of the signal from the node input port to the output port, and the delay constraint information includes the upper limit of the delay value between nodes.

[0092] By reading the user's design file and performing syntax parsing, a lot of information can be obtained, such as the node interconnection information and delay constraint information mentioned above.

[0093] Based on the design file, we can further obtain the internal delay of each node, as an example:

[0094] If the node is sequential logic, the period of the clock domain where the node is located is used as the internal delay of the node;

[0095] If the node is a combinational logic node, the maximum delay value of all paths within the node is used as the internal delay of the node.

[0096] In other words, for a combinational logic node, if there are many paths within the node and each path has an alternative delay value, for example, if there are three delay values ​​(min delay, typical delay, and max delay), then the largest value among these delay values ​​is selected as the internal delay of this node.

[0097] This embodiment does not limit how to determine the internal delay of a node. Those skilled in the art can make their own choices and designs based on different needs and scenarios. These choices and designs that can be used here do not deviate from the spirit and scope of protection of this application.

[0098] In step S402, the arrival time of each node is calculated, where the arrival time of each node is the maximum delay from the starting node to the current node.

[0099] As an example, in this embodiment or certain other embodiments of the present application, calculating the arrival time of each node may specifically include:

[0100] Calculate the path delay value of each path from the starting node to the current node;

[0101] The maximum path delay value is selected as the arrival time of this node.

[0102] In other words, the arrival time of each node is the delay from the starting node (a node with only output and no input) to the current node. If there are multiple paths from the starting node to the current node, the path with the largest delay is used as the arrival time of the current node.

[0103] When calculating path delay, "to this node" can be considered to include the internal delay of this node. In other embodiments, the definition of path delay calculation can be designed differently based on different situations or needs, and this embodiment does not limit this. Furthermore, the starting node generally receives signals directly, so the internal delay of the starting node can usually be considered to be zero.

[0104] In step S403, a critical path is determined, wherein the critical path is a path whose starting point is a source node and whose end point is a sink node, and the path delay value of the critical path is equal to the arrival time of the sink node.

[0105] Starting from a sink node (a node without any load nodes, also known as an end node, with only input and no output), find a path whose path delay is exactly equal to the arrival time of the sink node. Typically, the number of critical paths is equal to the number of sink nodes, that is, there are as many critical paths as there are sink nodes.

[0106] In step S404, the weight of each link on the critical path is increased according to the delay constraint information and a preset strategy, wherein the weight of a link is inversely correlated with the probability of the link being cut during segmentation.

[0107] Delay constraint information indicates the upper limit of delay between nodes and is pre-set by the user in the design file. Of course, in practice, the user may not set upper limits for delay between all two nodes in the delay constraint information. Instead, the user may set upper limits for delay between some nodes. For example, the delay constraint information may include upper limits for delay between the starting node and another node (i.e., one end is the starting node and the other end is another node). This embodiment does not limit the specific delay limits between which nodes are included in the delay constraint information.

[0108] The weight of the connection (net) will affect the segmentation. Specifically, the weight of the net is inversely correlated with the probability of the net being cut during segmentation. In other words, the larger the weight of the net, the less likely it is to be cut during segmentation.

[0109] After determining the critical path, in order to avoid the critical path being cut, the net on the critical path can be given a higher weight value, that is, the original weight value of the connection on the critical path can be increased.

[0110] As for how much the weight of each connection is increased, it can be determined based on the specific scenario. This embodiment does not need to limit the specific increase in the weight of each connection. One of the contributions of this application is to point out the method of first determining the critical path and then increasing the weight of the connections on the critical path. As for how to increase the weight value specifically and how much to increase it, this embodiment does not limit it. Those skilled in the art can make their own choices and designs based on different needs and different scenarios. These choices and designs that can be used here do not deviate from the spirit and scope of protection of this application.

[0111] Here is an example of increasing the weight value:

[0112] As an example, the preset strategy may specifically include:

[0113] Determine the maximum number of times the critical path can be cut based on the upper limit of the delay between the two end nodes of the critical path, the difference in arrival time between the two end nodes, and the group delay, where the group delay is the delay in transmitting signals on the interconnection lines between FPGAs;

[0114] According to the maximum number of times and the number of links included in the critical path, the probability of each link in the critical path being cut is determined, and the weight value of each link is increased according to the probability.

[0115] For example, suppose g0 and g1 are nodes at the two ends of a critical path. The value obtained by subtracting the arrival time of g0 from the arrival time of g1 (i.e., the difference in arrival time between the two nodes) is 50ns. The delay constraint information shows that the upper limit of the delay between g0 and g1 is set to 100ns. The added delay across the FPGA (i.e., group delay) is also known to be 20ns. The maximum number of times the critical path between g0 and g1 can be cut (rounded) is:

[0116] (100-50) / 20 = 2

[0117] Assume that if the number of nets on critical path 1 is 15, the maximum probability of each net being cut is 2 / 15; if the number of nets on critical path 2 is 10, the maximum probability of each net being cut is 2 / 10; if the number of nets on critical path 3 is 5, the maximum probability of each net being cut is 2 / 5. It can be seen that the net on critical path 1 has the lowest probability of being cut, so it will be given a higher weight. Then we have:

[0118] The weight of the net on path1 > the weight of the net on path2 > the weight of the net on path3 > the weight of the normal net.

[0119] Of course, the above calculation is only an example. This embodiment does not limit how to determine the probability of each link in the critical path being cut based on the maximum number of times and the number of links contained in the critical path, and how to increase the weight value of each link based on the probability. Those skilled in the art can make their own choices and designs based on different needs and different scenarios. These choices and designs that can be used here do not deviate from the spirit and protection scope of this application.

[0120] In step S405 , the circuit design is converted into a topology diagram and the level of each node is determined, wherein the starting node is the first layer, ie, level=1.

[0121] As an example, in this embodiment or certain other embodiments of the present application, converting the circuit design into a topology diagram and determining the hierarchical level of each node may include:

[0122] Starting from the starting node, along the longest path, the topology structure is divided into levels according to the principle that the level of the starting node = 1 and the level increases by 1 for each node passed;

[0123] The level of each node is determined by the number of nodes between each node and the starting node.

[0124] For example, you can refer to Figure 5 As shown, Figure 5 This is a schematic diagram of the level division in the embodiment of the present application. Figure 5 There are two starting nodes g0 and g1, and one ending node g5. There are also nodes g6, g7, g8, etc. in the figure. The longest path is g0→g2→g3→g4→g5. Taking the longest path as the basis and setting the level of g0=1, 5 levels can be divided, such as Figure 5 shown.

[0125] In step S406 , cross-level links are removed, where the difference between the levels of two nodes connected by the cross-level link is greater than a preset value β.

[0126] Continue with Figure 5 For example, assuming the preset value β=3, the levels of g0 and g5 are 1 and 5 respectively, and the level difference of the line g0→g5 directly connecting g0 and g5 is |level5-level1|=4, which is greater than β. Then the line g0→g5 is a cross-level line and needs to be removed to ensure that g0 and g5 are not merged together separately during the clustering process.

[0127] G0 and G5 are far apart (the level difference is 4). During the segmentation process, clustering should be avoided. This is because if G0 and G5 are clustered together, G2, G3, and G4 will be clustered together, causing signal transmission and return, resulting in unnecessary delays. The presence of a net directly connecting G0 and G5 can easily cause G0 and G5 to be clustered together, so this net should be removed in advance.

[0128] In step S407, the circuit design after the above processing is segmented according to a preset process, that is, the circuit design with increased connection weights on critical paths and removed cross-layer connections is segmented according to a preset process.

[0129] After the two preprocessing steps mentioned above (increasing the weight of connections on critical paths and removing cross-level paths), segmentation can reduce or even avoid cutting paths with large delays or repeatedly cutting the same path.

[0130] After preprocessing, the specific segmentation process is not limited in this embodiment, and an existing segmentation process can be used as a preset process. For example, the segmentation process may include:

[0131] Clustering: Merge some nodes to reduce the order of magnitude of segmentation.

[0132] Initial segmentation: During the segmentation process, the net with smaller weight is prioritized.

[0133] Refinement: Restore the nodes merged during the clustering process. During the restoration process, try to move the restored nodes to another FPGA. If this reduces the overall latency, move the node. Moving nodes that do not affect the latency value can achieve more balanced utilization of FPGA resources.

[0134] For further optimization, some situations are explained below:

[0135] i) In some cases, a loop path may exist in the circuit. The existence of the loop path may cause the calculation delay to fall into an infinite loop. Therefore, in this embodiment or certain other embodiments of the present application, before calculating the arrival time of each node, the method may further include:

[0136] determining whether there is a loop path in the circuit design;

[0137] If a loop exists, cut the loop from the data terminal of the flip-flop device. For example, cut the loop from the D terminal of the FF attribute node.

[0138] As an example, you can refer to Figure 6 As shown, Figure 6 It is a schematic diagram of cutting a circular path in an embodiment of the present application. Figure 6 The middle cloud type represents a combinational logic circuit. Figure 6 In the diagram, C represents the clk terminal of the flip-flop, and Q represents the output terminal of the flip-flop. It is easy to see that there is a circular path in the diagram. The circular path needs to be cut from the D terminal of the node with the attribute FF, as shown by the diagonal line in the diagram. FF is the flip-flop.

[0139] ii) In some cases, users pre-allocate some nodes in the design file, that is, pre-allocate or bind these nodes to certain FPGAs in advance. Such nodes are called fixed nodes. For example, refer to Figure 7 As shown, Figure 7 This is a schematic diagram of node connections with fixed nodes in the embodiment of the present application. Figure 3 、 Figure 5 similar, Figure 7 There are multiple nodes such as g0, g1, ..., g7, g8, etc. Figure 7 Midpoints g2, g3, and g4 are pre-assigned to plates F1, F2, and F3, respectively.

[0140] Therefore, in this embodiment or certain other embodiments of the present application, the circuit design information may further include pre-allocation information, and the pre-allocation information is used to indicate a pre-allocated node fixed node, which is a node that has been pre-bound to the FPGA board before segmentation.

[0141] Fixed nodes affect path delays, namely:

[0142] Calculate the path delay value of each path from the starting node to the current node, including:

[0143] When the path includes pre-assigned nodes, the path delay value is further added with a corresponding number of group delays, where the group delay is the delay of transmitting signals by interconnection lines between FPGAs.

[0144] As an example, you can refer to Figure 7 As shown, nodes g2, g3, and g4 are pre-assigned to boards F1, F2, and F3, respectively. For g3, its arrival time is the sum of the internal delay of all nodes on the path from g0 to g3, the delay of all nets, and the group delay. This is because g2 and g3 are located on F1 and F2, respectively, which means there must be a group delay between g2 and g3.

[0145] For g4, its arrival time is the internal delay of all nodes on the path from g0 to g4 + the delay of all nets + the group delay × 2. This is because there must be group delay between g2 and g3 and between g3 and g4, so it is double the group delay.

[0146] For g5, its arrival time is the internal delay of all nodes on the path g0 → g2 → g3 → g4 → g5 + the delay of all nets + the group delay × 2. Because it is currently uncertain whether g4 and g5 will be cut, they are treated as not cut, resulting in a delay of 2 times the group delay instead of 3 times.

[0147] Fixed node also affects whether to pre-merge nodes, namely:

[0148] Before determining the critical path, the method may further include:

[0149] Determine whether there is a node to be merged, where the node to be merged is connected to multiple pre-assigned nodes on the same FPGA; if the node to be merged exists, bind the node to be merged to the same FPGA. The multiple nodes may be at least one node.

[0150] The starting node is bound to the FPGA where the pre-allocated node closest to it is located, and the ending node is bound to the FPGA where the pre-allocated node closest to it is located, where the closest node means the node with the least number of nodes in between.

[0151] In other words, the starting node may be directly or indirectly connected to multiple pre-assigned nodes. Among these pre-assigned nodes, the pre-assigned node with the fewest nodes between it and the starting node is the pre-assigned node closest to the starting node. The starting node is then bound to the FPGA on which the pre-assigned node closest to the starting node resides. Similarly, the ending node is bound to the FPGA on which the pre-assigned node closest to the ending node resides.

[0152] iii) In some cases, the user-defined delay constraint information may be unreasonable. In this case:

[0153] Before increasing the weight value of each link on the critical path, the method further includes:

[0154] Based on the arrival times of the nodes, a determination is made as to whether the upper limit of the delay between nodes in the delay constraint information is less than the difference in the arrival times between the nodes. If so, the method exits. In other words, based on the arrival times of the nodes, a determination is made as to whether the upper limit of the delay between nodes in the delay constraint information is reasonable. If not, the method exits.

[0155] This is because the upper limit of the delay between nodes in the delay constraint information is user-defined, i.e., the user's requirements. If, during the segmentation preprocessing process, the difference in arrival time between two nodes is found to exceed the upper limit of the delay constraint information, the current segmentation method cannot meet the user's requirements. The user-defined delay constraint may be unreasonable, and the process cannot proceed further, so the process must be exited. Furthermore, upon exiting, the user can be prompted with the relevant nodes where the problem occurred, so that the user can review them.

[0156] In this embodiment, through pre-processing before segmentation, the connections in the paths with larger delays and the connections that easily cause the same path to be repeatedly cut are given higher weight values ​​or deleted to prevent them from being cut. Therefore, when the circuit is segmented next, the paths with larger delays can be avoided as much as possible and the same path can be avoided from being cut repeatedly. This can effectively reduce or even eliminate the problem of increased overall circuit delay caused by improper cutting, thereby significantly improving the system's operating speed.

[0157] The present application scheme will be further described below in conjunction with specific application scenarios. Of course, the following application scenarios are only exemplary and can also be applied to other application scenarios in actual applications.

[0158] Figure 8 The overall flow chart of the segmentation process provided in the embodiment of the present application may include the following steps:

[0159] 1) Input. This means reading the user's design and parsing it. For example, the following information can be generated:

[0160] Node information: This includes the number of various resources occupied by each node (such as PIO, INT, LUT, FF, BUFG, BUFT, CMT, BRAM.DSP, PPC, etc.), whether it has FF attributes and clk attributes, etc.

[0161] Internal delay information for each node: the delay of a signal from the input port to the output port of the node. For example, each delay information piece contains three values ​​(min delay, typical delay, and maximum delay).

[0162] Pre-allocation information: This refers to the information that the user uses to fix a node on a certain FPGA board in advance.

[0163] Node interconnection information: includes the connection relationship between nodes and the net delay value between two nodes.

[0164] FPGA board resource information: that is, the number of resources contained in each FPGA board.

[0165] Delay constraint information: Users can set an upper limit on the delay between nodes, that is, specify that the delay between two nodes cannot exceed a certain value.

[0166] 2) Preprocessing. Depending on the specific situation, multiple preprocessing steps may be included, for example:

[0167] Determine whether a circular path exists: If so, cut the circular path from the D end of the FF attribute node.

[0168] Calculate the internal delay of each node: If the node is combinational logic, the maximum delay of all paths within the node is used as the internal delay of the node. If the node is sequential logic, the period of the clock domain in which the node is located is used as the internal delay of the node.

[0169] Calculate each node's arrival time: The delay from the starting node to each node is used as the arrival time. If the path is split by a fixed node, the corresponding group delay is added (the group delay is added to the next node along the signal transmission direction). If multiple paths exist from the starting node to the node, the path with the longest overall delay is used as the node's arrival time.

[0170] Pre-merge some nodes: If a node is connected to multiple fixed nodes on the same FPGA, place the node on that FPGA as well. Place the starting node on the FPGA of the closest fixed node. Place the ending node on the FPGA of the closest fixed node.

[0171] Determine the critical path: Starting from the sink node (the node without any load nodes, that is, the end node), find a path such that the sum of the delays of this path is exactly equal to the arrival time of this sink node.

[0172] Determine whether the delay constraint information provided by the user is reasonable: Determine whether the constraint delay value of the critical path provided by the user is reasonable. If not, exit.

[0173] Assign higher weights to nets on the critical path: Assign higher weights to nets on the critical path based on the critical path delay value set by the user.

[0174] Remove cross-level nets: First, convert the designed circuit diagram into a topological diagram. Take the starting node as level 1. Along the longest path, the level increases by 1 for each node passed. At the same time, set a parameter β=3. When a net connects two nodes A and B, and |levelA-levelB|>β, remove the net to ensure that A and B are not merged together separately during the clustering process.

[0175] 3) Clustering: Merge some nodes to reduce the order of magnitude of segmentation.

[0176] 4) Initial segmentation: During the segmentation process, the net with smaller weight is prioritized.

[0177] 5) Refinement: Restore the nodes merged during the clustering process. During the restoration process, try to move the restored nodes to another FPGA. If this reduces the overall latency, move the node. Moving nodes that do not affect the latency value can achieve more balanced utilization of FPGA resources.

[0178] In this embodiment, through pre-processing before segmentation, the connections in the paths with larger delays and the connections that easily cause the same path to be repeatedly cut are given higher weight values ​​or deleted to prevent them from being cut. Therefore, when the circuit is segmented next, the paths with larger delays can be avoided as much as possible and the same path can be avoided from being cut repeatedly. This can effectively reduce or even eliminate the problem of increased overall circuit delay caused by improper cutting, thereby significantly improving the system's operating speed.

[0179] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0180] Figure 9 Schematic diagram of a circuit design segmentation device provided in an embodiment of the present application. The device can be applied to scenarios such as prototype verification systems.

[0181] See also Figure 9 As shown, the device may include:

[0182] The circuit design information acquisition module 901 is used to obtain circuit design information based on the design file corresponding to the circuit design. The circuit design information includes node interconnection information, delay constraint information, and the internal delay of each node. The node interconnection information includes the connection relationship between nodes and the delay value of the connection between nodes. The internal delay of the node is the delay value of the signal from the node input port to the output port. The delay constraint information includes the upper limit of the delay value between nodes.

[0183] The segmentation preprocessing module 902 is used to: calculate the arrival time of each node, wherein the arrival time of each node is the maximum delay from the starting node to the current node; determine the critical path, wherein the critical path is a path with the starting point being the starting node and the end point being the ending node, and the path delay value of the critical path is equal to the arrival time of the ending node; based on the delay constraint information, increase the weight value of each connection on the critical path according to a preset strategy, wherein the weight value of the connection is inversely correlated with the probability of the connection being cut during segmentation; convert the circuit design into a topological diagram and determine the level of each node, wherein the starting node is the first level; remove cross-layer connections, wherein the difference between the levels of the two nodes connected by the cross-layer connection is greater than a preset value.

[0184] The segmentation module 903 is configured to segment the circuit design processed by the segmentation pre-processing module according to a preset process.

[0185] In some cases, a loop path may exist in the circuit. The existence of the loop path may cause the calculation delay to fall into an infinite loop. Therefore, in this embodiment or certain other embodiments of the present application, the segmentation preprocessing module may also be used to:

[0186] Before calculating the arrival time of each node, it is determined whether there is a loop path in the circuit design. If there is a loop path, the loop path is cut off from the data end of the trigger device.

[0187] In this embodiment or certain other embodiments of the present application, the circuit design information acquisition module may be used to obtain the internal delay of each node by:

[0188] If the node is combinational logic, the maximum delay value of all paths within the node is used as the internal delay of the node. If the node is sequential logic, the period of the clock domain in which the node is located is used as the internal delay of the node.

[0189] In this embodiment or certain other embodiments of the present application, when calculating the arrival time of each node, the segmentation pre-processing module may be specifically used to:

[0190] Calculate the path delay value of each path from the starting node to the current node, and select the largest path delay value as the arrival time of the current node.

[0191] In other words, the arrival time of each node is the delay from the starting node (a node with only output and no input) to the current node. If there are multiple paths from the starting node to the current node, the path with the largest delay is used as the arrival time of the current node.

[0192] In some cases, the user may pre-allocate some nodes in the design file, that is, pre-allocate or bind these nodes to certain FPGAs in advance. Such nodes are called fixed nodes. Therefore, in this embodiment or certain other embodiments of the present application, the circuit design information may further include pre-allocation information, and the pre-allocated information is used to indicate the pre-allocated nodes. The pre-allocated nodes are nodes that have been pre-bound to the FPGA board before segmentation.

[0193] When the path includes pre-assigned nodes, the segmentation pre-processing module also adds a corresponding number of group delays when calculating the path delay value, where the group delay is the delay of transmitting signals through interconnection lines between FPGAs.

[0194] In this embodiment or certain other embodiments of the present application, the circuit design information may further include pre-allocation information, where the pre-allocation information is used to indicate a pre-allocated node, where the pre-allocated node is a node that has been pre-bound to the FPGA board before segmentation.

[0195] Accordingly, the segmentation preprocessing module can also be used to: before determining the critical path, determine whether there is a node to be merged, wherein the node to be merged is connected to multiple pre-allocated nodes on the same FPGA; if the node to be merged exists, bind the node to be merged to the same FPGA; bind the starting node to the FPGA where the pre-allocated node closest to it is located, and bind the ending node to the FPGA where the pre-allocated node closest to it is located, wherein the "closest" means the node with the least number of nodes in between.

[0196] In other words, the starting node may be directly or indirectly connected to multiple pre-assigned nodes. Among these pre-assigned nodes, the pre-assigned node with the fewest nodes between it and the starting node is the pre-assigned node closest to the starting node. The starting node is then bound to the FPGA on which the pre-assigned node closest to the starting node resides. Similarly, the ending node is bound to the FPGA on which the pre-assigned node closest to the ending node resides.

[0197] In this embodiment or certain other embodiments of the present application, the segmentation preprocessing module may also be used to:

[0198] Before increasing the weight value of each link on the critical path, it is determined whether the upper limit of the delay value between nodes in the delay constraint information is less than the difference in the arrival time between nodes based on the arrival time of the nodes. If so, the processing is terminated.

[0199] In this embodiment or certain other embodiments of the present application, the preset strategy may specifically include:

[0200] Determine the maximum number of times the critical path can be cut based on the upper limit of the delay value between the nodes at both ends of the critical path, the difference in arrival time between the nodes at both ends, and the group delay, where the group delay is the delay in transmitting signals through the interconnection lines between the FPGAs;

[0201] According to the maximum number of times and the number of links included in the critical path, the probability of each link in the critical path being cut is determined, and the weight value of each link is increased according to the probability.

[0202] In this embodiment or certain other embodiments of the present application, when converting the circuit design into a topology graph and determining the level of each node, the segmentation pre-processing module may be specifically used to:

[0203] Starting from the starting node, along the longest path, the topology structure is divided into levels according to the principle that the first level is the starting node and the level increases by 1 for each node passed; the level of each node is determined by the number of nodes between each node and the starting node.

[0204] In this embodiment, through pre-processing before segmentation, the connections in the paths with larger delays and the connections that easily cause the same path to be repeatedly cut are given higher weight values ​​or deleted to prevent them from being cut. Therefore, when the circuit is segmented next, the paths with larger delays can be avoided as much as possible and the same path can be avoided from being cut repeatedly. This can effectively reduce or even eliminate the problem of increased overall circuit delay caused by improper cutting, thereby significantly improving the system's operating speed.

[0205] Regarding the apparatus in the above embodiments, the specific manner in which each unit or module performs operations has been described in detail in the embodiments of the relevant methods and will not be repeated here. In this application, the names of the above units or modules do not limit the units or modules themselves. In actual implementation, these units or modules may appear with other names. As long as the functions of each unit or module are similar to those of the present application, they are all within the scope of the claims of this application and their equivalents.

[0206] The above description is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of the technical content disclosed above without departing from the scope of the technical solution of the present application. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the technical solution of the present application, within the spirit and principles of the technical solution of the present application, without departing from the content of the technical solution of the present application, shall still fall within the scope of protection of the technical solution of the present application.

[0207] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the solutions disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present invention are indicated by the appended claims.

[0208] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A circuit design segmentation method, characterized in that: The method comprises: Obtaining circuit design information according to a design file corresponding to the circuit design, the circuit design information including node interconnection information, delay constraint information, and internal delay of each node, wherein the node interconnection information includes a connection relationship between nodes and a delay value of a connection between nodes, the internal delay of a node is a delay value of a signal from an input port to an output port of the node, and the delay constraint information includes an upper limit of a delay value between nodes; Calculate the arrival time of each node, where the arrival time of each node is the maximum delay from the starting node to the current node; Determine a critical path, wherein the critical path is a path starting from a start node and ending at an end node, and a path delay value of the critical path is equal to an arrival time at the end node; According to the delay constraint information, the weight value of each link on the critical path is increased according to a preset strategy, wherein the weight value of the link is inversely correlated with the probability of the link being cut during segmentation; Converting the circuit design into a topology graph and determining the level of each node, wherein the starting node is the first level; Remove cross-layer connections, where the difference in level between two nodes connected by the cross-layer connection is greater than a preset value; The circuit design after the above processing is divided according to a preset process.

2. The method according to claim 1, characterized in that Before calculating the arrival time of each node, the method further includes: determining whether there is a loop path in the circuit design; If a circular path exists, cut the circular path from the data terminal of the flip-flop device.

3. The method according to claim 1, characterized in that Get the internal latency of each node, including: If the node is a combinational logic node, the maximum delay value of all paths within the node is used as the internal delay of the node. If this node is sequential logic, the period of the clock domain where this node is located is used as the internal delay of this node.

4. The method according to claim 1, wherein Calculate the arrival time of each node, including: Calculate the path delay value of each path from the starting node to the current node; The maximum path delay value is selected as the arrival time of this node.

5. The method according to claim 4, characterized in that The circuit design information also includes pre-allocation information, where the pre-allocation information is used to indicate pre-allocated nodes, where the pre-allocated nodes are nodes that have been pre-bound to the FPGA board before segmentation. Calculate the path delay value of each path from the starting node to the current node, including: When the path includes pre-assigned nodes, the path delay value is further added with a corresponding number of group delays, where the group delay is the delay of transmitting signals through interconnection lines between FPGAs.

6. The method according to claim 1, characterized in that The circuit design information also includes pre-allocation information, where the pre-allocation information is used to indicate pre-allocated nodes, where the pre-allocated nodes are nodes that have been pre-bound to the FPGA board before segmentation. Before determining the critical path, the method further includes: Determining whether there is a node to be merged, wherein the node to be merged is connected to multiple pre-assigned nodes on the same FPGA; if the node to be merged exists, binding the node to be merged to the same FPGA; The starting node is bound to the FPGA where the pre-allocated node closest to it is located, and the ending node is bound to the FPGA where the pre-allocated node closest to it is located, where the closest node means the node with the least number of nodes in between.

7. The method according to claim 1, characterized in that Before increasing the weight value of each link on the critical path, the method further includes: According to the arrival time of the nodes, it is determined whether the upper limit of the delay value between the nodes in the delay constraint information is less than the difference in the arrival time between the nodes, and if it is less than the difference, the method is exited.

8. The method according to claim 1, characterized in that The preset strategies include: Determine the maximum number of times the critical path can be cut based on the upper limit of the delay value between the nodes at both ends of the critical path, the difference in arrival time between the nodes at both ends, and the group delay, where the group delay is the delay in transmitting signals through the interconnection lines between the FPGAs; According to the maximum number of times and the number of links included in the critical path, the probability of each link in the critical path being cut is determined, and the weight value of each link is increased according to the probability.

9. The method according to claim 1, characterized in that Convert the circuit design into a topology diagram and determine the hierarchy of each node, including: Starting from the starting node, along the longest path, the topology structure is divided into levels according to the principle that the first level is the starting node and the level increases by 1 for each node passed; The level of each node is determined by the number of nodes between each node and the starting node.

10. A circuit design segmentation device, characterized in that: The device comprises: a circuit design information acquisition module, configured to acquire circuit design information based on a design file corresponding to the circuit design, the circuit design information including node interconnection information, delay constraint information, and internal delay of each node, wherein the node interconnection information includes the connection relationship between nodes and the delay value of the connection between nodes, the internal delay of a node is the delay value of a signal from a node input port to an output port, and the delay constraint information includes an upper limit on the delay value between nodes; The splitting preprocessing module is configured to: calculate the arrival time of each node, wherein the arrival time of each node is the maximum delay from the starting node to the current node; determine a critical path, wherein the critical path is a path starting from the starting node and ending at the ending node, and the path delay value of the critical path is equal to the arrival time of the ending node; increase the weight value of each link on the critical path according to a preset strategy based on the delay constraint information, wherein the weight value of the link is inversely correlated with the probability of the link being cut during splitting; convert the circuit design into a topological graph and determine the level of each node, wherein the starting node is the first level; remove cross-layer links, wherein the difference between the levels of the two nodes connected by the cross-layer link is greater than a preset value; The segmentation module is used to segment the circuit design processed by the segmentation pre-processing module according to a preset process.

11. The device according to claim 10, characterized in that The segmentation preprocessing module is further used for: Before calculating the arrival time of each node, it is determined whether there is a loop path in the circuit design. If there is a loop path, the loop path is cut off from the data end of the trigger device.

12. The device according to claim 10, characterized in that When obtaining the internal delay of each node, the circuit design information acquisition module is specifically used to: If the node is combinational logic, the maximum delay value of all paths within the node is used as the internal delay of the node. If the node is sequential logic, the period of the clock domain in which the node is located is used as the internal delay of the node.

13. The device according to claim 10, characterized in that When calculating the arrival time of each node, the segmentation preprocessing module is specifically used to: Calculate the path delay value of each path from the starting node to the current node, and select the largest path delay value as the arrival time of the current node.

14. The device according to claim 13, characterized in that The circuit design information also includes pre-allocation information, where the pre-allocation information is used to indicate pre-allocated nodes, where the pre-allocated nodes are nodes that have been pre-bound to the FPGA board before segmentation. When the path includes pre-assigned nodes, the segmentation pre-processing module also adds a corresponding number of group delays when calculating the path delay value, where the group delay is the delay of transmitting signals through interconnection lines between FPGAs.

15. The device according to claim 10, characterized in that The circuit design information also includes pre-allocation information, where the pre-allocation information is used to indicate pre-allocated nodes, where the pre-allocated nodes are nodes that have been pre-bound to the FPGA board before segmentation. The segmentation preprocessing module is further configured to: before determining the critical path, determine whether there is a node to be merged, wherein the node to be merged is connected to multiple pre-allocated nodes on the same FPGA; if the node to be merged exists, bind the node to be merged to the same FPGA; bind the starting node to the FPGA on which the pre-allocated node closest to it is located, and bind the ending node to the FPGA on which the pre-allocated node closest to it is located, wherein the term "closest" means the node with the least number of nodes in between.

16. The device according to claim 10, characterized in that The segmentation preprocessing module is further used for: Before increasing the weight value of each link on the critical path, it is determined whether the upper limit of the delay value between nodes in the delay constraint information is less than the difference in the arrival time between nodes based on the arrival time of the nodes. If so, the processing is terminated.

17. The device according to claim 10, characterized in that The preset strategies include: Determine the maximum number of times the critical path can be cut based on the upper limit of the delay value between the nodes at both ends of the critical path, the difference in arrival time between the nodes at both ends, and the group delay, where the group delay is the delay in transmitting signals through the interconnection lines between the FPGAs; According to the maximum number of times and the number of links included in the critical path, the probability of each link in the critical path being cut is determined, and the weight value of each link is increased according to the probability.

18. The device according to claim 10, characterized in that When converting the circuit design into a topology diagram and determining the level of each node, the segmentation pre-processing module is specifically used to: Starting from the starting node, along the longest path, the topology structure is divided into levels according to the principle that the first level is the starting node and the level increases by 1 for each node passed; the level of each node is determined by the number of nodes between each node and the starting node.

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