Novel escape routing method based on linear programming

Abstract

The application proposes a new escape routing method based on linear programming, which is used for the wiring design of printed circuit board, and comprises the following steps: step S1, equivalent the nonlinear problem of escape routing to linear programming problem, and establish network flow model; step S2, describe each constraint of the wiring rule as the constraint condition of the linear programming, so as to realize the conversion of the nonlinear problem to linear problem solution; step S3, determine the main obstacle point of the congestion part, re-describe the path selection problem of the point as ILP problem with linear constraint, and then locally optimize and solve; step S4, repeatedly iterate the LP solution of linear programming to judge congestion and ILP local optimization, so as to realize the legalization of overall wiring, that is, keep the path of the optimized point, continue to alternately use linear programming solution and local heuristic optimization for the remaining points, until the wiring area no longer appears congestion; the application greatly improves the wiring efficiency and reduces the cost consumption under the condition of meeting the signal integrity and stability constraint.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of large-scale electronic design automation, in particular to a new escape routing method based on linear programming. BACKGROUND

[0002] With the development of integrated circuit scale, electronic products are more functional and complex, which leads to a great increase in the number of pins of printed circuit boards (PCB). Under the constraints of signal integrity and stability, EDA automatic routing tools can find a reasonable routing scheme in a tedious and complex circuit with high efficiency, greatly reducing the consumption of manpower and cost. In addition, a well-designed circuit also needs to be routed to be implemented and verified. Therefore, how to route is a crucial link in PCB design, and the routing scheme will directly affect the performance of the entire circuit system.

[0003] The problem of PCB escape routing is different from that of general routing. General routing is mostly connecting a pin to another pin (pin to pin), that is, point-to-point connection, while escape routing is point-to-edge connection, which is connecting a pin to the edge boundary of a specific bus. There are three main escape routing methods: network flow, negotiated congestion, and bound routing. This paper uses network flow modeling to design linear programming constraints so that the routing problem can find the optimal solution within the flow limiting step of the equation.

[0004] The existing method of using linear programming to solve ordered escape has the following problems: using integer linear programming method to solve, which limits the variables to integers, which may lead to time violation or routing failure. Therefore, in order to get a better legalization result, it is worth considering to consider this legalization problem from a more global perspective and design a corresponding efficient algorithm with a certain theoretical basis. SUMMARY

[0005] The present application proposes a new escape routing method based on linear programming, which combines global LP solving and local heuristic optimization, greatly improves the routing efficiency and reduces the cost consumption under the constraints of signal integrity and stability.

[0006] The present application adopts the following technical solutions.

[0007] The new escape routing method based on linear programming is used for the routing design of printed circuit boards, including the following steps:

[0008] Step S1, equivalent the nonlinear problem of escape routing to a linear programming problem, and establish a corresponding network flow model;

[0009] Step S2, each constraint of the routing rule is described as a constraint condition of the linear programming, so as to realize the conversion of the nonlinear problem into the linear problem for solving;

[0010] Step S3, the main obstacle point of the congestion part is determined, the path selection problem of the point is re-described as an ILP problem with linear constraints, and then is locally optimized and solved;

[0011] Step S4, the LP solution of the linear programming and the ILP local optimization are repeatedly iterated to realize the legalization of the overall routing, that is, the path of the optimized point is reserved, and the linear programming solution and the local heuristic optimization are continuously alternately used for the remaining points until no congestion occurs in the routing area.

[0012] In step S1, the routing design mapping method is:

[0013] Three types of points are added during mapping, that is, one center tile is added between every four pins, one imaginary node is added between every two pins, and corresponding boundary points are added to the escape boundary;

[0014] After mapping is completed, according to the routing rule, four kinds of routing modes are formed between the points, and the line length cost is set, which is expressed by the formula as:

[0015]

[0016] Wherein, V represents all vertex sets of the routing area, V t represents the center tile set, V e represents the escape pin point set, V i represents the added imaginary node set, V b represents the boundary point set; E represents all edge sets in the routing area, e wv represents the edge from w to v, IE v represents all incoming edge sets of vertex v, OE v represents all outgoing edge sets of vertex υ; represents the ith escape pin, represents the ith boundary pin. The above formula shows that in order to meet the cost minimization, the cost from the escape pin point to the boundary or the imaginary node is 0.5, the cost from the imaginary node to the boundary or other imaginary nodes is 1, and the cost of others is 0.

[0017] The various constraints of the routing rule in step S2 include order, non-crossing, and capacity restrictions; the method of step S2 is as follows:

[0018] According to the distribution mode of the line length cost of each edge of the routing, the basic objective function of the linear programming problem is described as:

[0019]

[0020] where c(e) represents the cost of the edge occupied, is 1 or 0, representing whether the edge is selected or not;

[0021] The constraint conditions of the linear programming problem of the routing method are as follows:

[0022] Constraint condition a, the escape pin point as the source point of the flow, only allows to route outward, for the pin i, there is a formula:

[0023]

[0024] where L represents the number of pin points;

[0025] Constraint condition b, the transit node containing the bidirectional edge of the service routing, must ensure the outflow and inflow conservation of the flow, the transit node includes the center tile point and the virtual node, and is expressed by a formula:

[0026]

[0027] Constraint condition c, the sink point is located at the boundary, and there is only one, and satisfies:

[0028]

[0029] Constraint condition d, for the PCB routing, the corresponding capacity constraint must be set, for the routing area with a capacity of 1, there is a formula:

[0030]

[0031] where the first formula constrains the center tile point, the second formula constrains the virtual node, in addition, for the case of capacity increase, the formula also meets the condition, only need to change the constraint condition to less than or equal to the capacity;

[0032] Constraint condition e, the OER routing prohibits the crossing of the routing, in the network flow mapping, the crossing can only occur at the center tile, two binary variables representing the vertical direction are introduced at the tile, and there is a formula:

[0033]

[0034] where w1, w2, w3, and w4 represent the west, north, east, and south four directions of the vertex w, r wi represents the variable of the center tile point at the number w of the pin point i, represents the horizontal direction, represents the vertical direction; the non-crossing is converted into the constraint condition of the linear programming, that is:

[0035]

[0036] Constraint f, order, that is, the internal pins of the circuit board wiring must escape according to the given pin order, after the internal pin is connected to the component boundary, the external connection does not limit the capacity, connected to the same sink, expressed in formula as:

[0037]

[0038] Wherein, Indicates that in the case of consistent target sink, pin i+1 will always be more than pin i to select a part of the external boundary point connection, realize order;

[0039] Constraint g. Relax the above linear constraint condition by a preset proportion, so as to facilitate the routing of the subsequent main obstacle point;

[0040] For the path congestion caused by the simultaneous selection of multiple pins to escape from the same boundary point in some areas, a local optimization method is used to adjust the result.

[0041] The method of step S3 is a local heuristic optimization, specifically:

[0042] When the linear programming LP wiring initial result is known, including a part of complete wiring path, a part of congestion area with pin wiring intersection:

[0043] Step a, establish an ILP model for the current congestion area, determine the main obstacle point from the congestion area, add non-intersection and order linear constraints to the known path of the point and solve;

[0044] Step b, judge whether the path congestion condition is solved, if yes, return to the next step, otherwise continue to solve the path of other points in the region;

[0045] Step c, repeat iteration until there is no congestion in the region, return to execute new linear programming LP.

[0046] The method of step S4 is specifically:

[0047] Method a, reset all wiring paths except the main obstacle point;

[0048] Method b, remove the optimized main obstacle point, continue to solve the global iteration LP, judge the wiring path congestion condition, if there is congestion, locally optimize to solve the congestion, until the wiring is completed.

[0049] The present application provides a method for solving large-scale integrated circuit ordered escape routing (OER) problem by combining global LP solution and local heuristic optimization, which has the advantages of:

[0050] (1) the present application proposes to use linear programming for escape routing, solves the problem that traditional integer linear programming cannot directly solve large-scale circuits, helps to reduce the computational complexity and save time cost;

[0051] (2) the present application uses integer linear programming method to select feasible solution from known congestion path, effectively reduces the solution scale;

[0052] (3) the present application innovatively combines linear programming solution and local heuristic optimization effectively, considers the legalization problem from a more global perspective, and designs a corresponding efficient algorithm with certain theoretical basis, and obtains better legalization result.

[0053] The present application uses a fast and theoretically based algorithm to solve the ordered escape routing problem of larger scale, thereby improving the wiring effect of the circuit and saving effective time, which is beneficial to expand to larger wiring area, improve the quality of wiring scheme, and is easy to implement. BRIEF DESCRIPTION OF DRAWINGS

[0054] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0055] The accompanying drawings are schematic diagrams of the flow of the present application; Figure 1 The accompanying drawings are schematic diagrams of the flow of the present application;

[0056] Figure 2 The accompanying drawings are schematic diagrams of the flow of the present application;

[0057] The accompanying drawings are schematic diagrams of the flow of the present application; Figure 3 The accompanying drawings are schematic diagrams of the flow of the present application. DETAILED DESCRIPTION

[0058] As shown in the figure, the new escape routing method based on linear programming is used for the wiring design of printed circuit board, including the following steps:

[0059] Step S1, the nonlinear problem of escape routing is equivalent to a linear programming problem, and a corresponding network flow model is established;

[0060] Step S2, each constraint of the wiring rule is described as a constraint condition of the linear programming, so as to realize the conversion of the nonlinear problem into the linear problem for solving;

[0061] Step S3, the main obstacle point of the congestion part is determined, the path selection problem of the point is re-described as an ILP problem with linear constraints, and then locally optimized and solved;

[0062] ​Step S4, the LP solving and the ILP local optimization are iterated repeatedly to judge congestion and to realize overall routing legalization, i.e. the path of the optimized point is reserved, and the linear programming solving and the local heuristic optimization are continued to be alternately used for the remaining points until no congestion appears in the routing area.

[0063] In step S1, the routing design layout method is as follows:

[0064] Three types of points are added during the layout, i.e. a center tile is added in the middle of every four pins, an imaginary node is added between every two pins, and a corresponding boundary point is added at the escape boundary;

[0065] After the layout is completed, according to the routing rules, four types of routing are formed between the points, and the line length cost is set, which is expressed by the formula as follows:

[0066]

[0067] Wherein, V represents the set of all vertices in the routing area, V t represents the set of center tiles, V e represents the set of escape pin points, V i represents the set of added imaginary nodes, V b represents the set of boundary points; E represents the set of all edges in the routing area, e wv represents the edge from w to v, IE v represents the set of all incoming edges of vertex v, OE v represents the set of all outgoing edges of vertex v; represents the i-th escape pin, represents the i-th boundary pin. The above formula shows that in order to meet the cost minimization, the cost from the escape pin point to the boundary or the imaginary node is 0.5, the cost from the imaginary node to the boundary or other imaginary node is 1, and the cost of others is 0.

[0068] The constraints of the routing rules in step S2 include order, non-crossing, and capacity limitations; the method of step S2 is as follows:

[0069] According to the distribution mode of the line length cost of each edge of the routing, the basic objective function of the linear programming problem is described as follows:

[0070]

[0071] Wherein c(e) represents the cost of the occupied edge, is 1 or 0, representing whether the edge is selected or not;

[0072] The constraint conditions of the linear programming problem of the routing method are as follows:

[0073] Constraint a, the escape pin point as the source point of the flow, only allows to wire outward, for pin i, there is a formula:

[0074]

[0075] Wherein, L represents the number of pin points;

[0076] Constraint b, the transit node containing bidirectional edges of the service wire, must ensure the flow out and flow in conservation, the transit node includes the center tile point and the virtual node, and is expressed by a formula as:

[0077]

[0078] Constraint c, the sink point is located at the boundary, and there is only one, and satisfies:

[0079]

[0080] Constraint d, for the PCB wiring, the corresponding capacity constraint must be set, for the wiring area with a capacity of 1, there is a formula:

[0081]

[0082] Wherein, the first formula constrains the center tile point, the second formula constrains the virtual node, in addition, for the case of capacity increase, the formula also meets the condition, only need to change the constraint condition to less than or equal to the capacity;

[0083] Constraint e, the OER wiring prohibits the crossing of the wire, in the network flow mapping, the crossing can only occur at the center tile, two binary variables representing the vertical direction are introduced at the tile, and there is a formula:

[0084]

[0085] Wherein w1, w2, w3, w4 represent the west, north, east and south four directions of vertex w, r wi Represents the variable at the center tile point of pin point i with number w, Represents the horizontal direction, Represents the vertical direction; the non-crossing is converted into the constraint condition of linear programming, that is:

[0086]

[0087] Constraint f, order, that is, the internal pins of the circuit board wiring must escape according to the given pin order, after the internal pins are connected to the component boundary, the external connection is not limited in capacity, and is connected to the same sink point, which is expressed by a formula as:

[0088]

[0089] wherein, It means that in the case of the target sink consistent, pin i+1 will always be more than pin i to select a part of the outer boundary point line, to achieve order;

[0090] Constraint g. Relax the above linear constraints by a preset proportion to facilitate the subsequent routing of the main obstacle points;

[0091] For the path congestion caused by multiple pins selecting the same boundary point escape in some areas at the same time, a local optimization method is used to adjust the results.

[0092] The method of step S3 is a local heuristic optimization, specifically:

[0093] When the initial result of linear programming LP routing is known, including a part of complete routing path and a part of congestion area with pin crossing:

[0094] Step a, establish an ILP model for the current congestion area, determine the main obstacle point from the congestion area, add non-crossing and ordered linear constraints to the known path of the point and solve it;

[0095] Step b, judge whether the path congestion is solved, if yes, return to the next step, otherwise continue to solve the path of other points in the area;

[0096] Step c, repeat until there is no congestion in the area, return to execute new linear programming LP.

[0097] The method of step S4 is specifically:

[0098] Method a, reset all routing paths except the main obstacle point;

[0099] Method b, remove the optimized main obstacle point, continue to solve the global iteration LP, judge the congestion of the routing path, if there is congestion, locally optimize to resolve the congestion, until the routing is completed.

Claims

1. An escape routing method based on linear programming for printed circuit board routing design, characterized in that: Includes the following steps; Step S1: Equivalent the nonlinear problem of escape routing to a linear programming problem and establish the corresponding network flow model; Step S2: Describe each constraint of the wiring rule as a constraint condition of the linear programming problem, thereby transforming the nonlinear problem into a linear problem for solution. Step S3: Identify the main obstacle points in the congested section, reformulate the path selection problem at these points as an ILP problem with linear constraints, and then solve it using local optimization. Step S4: Iterate through the linear programming LP solution to determine congestion and ILP local optimization to achieve overall routing legality. That is: retain the path of the optimized point, and continue to use linear programming solution and local heuristic optimization alternately for the remaining points until there is no more congestion in the routing area. In step S1, the wiring design diagram method is as follows: Three types of points are added during the graph construction: first, a central tile is added between every four pins; second, an imaginary node is added between every two pins; and third, corresponding boundary points are added at the escape boundary. After the layout is completed, according to the routing rules, four routing methods are formed between points, and the cost of each routing method is set, which can be expressed by the following formula: Among them, V t V represents the central tile set. b V represents the set of boundary points. e V represents the escape pin set. i e represents the set of hypothetical nodes to be added. wv This represents the edge pointing from w to v. The above formula shows that, in order to minimize costs, the cost from the escape pin point to the boundary or a hypothetical node is 0.5, the cost from the hypothetical node to the boundary or other hypothetical nodes is 1, and the cost for others is 0.

2. The escape routing method based on linear programming according to claim 1, characterized in that: The constraints of the routing rules in step S2 include ordering, non-crossing, and capacity limitations; the method for step S2 is as follows: Based on the allocation of cost across the wiring edges, the basic objective function of the linear programming problem can be described as follows: Where c(e) represents the cost of the edge occupied. A value of 1 or 0 indicates whether the edge is selected; The constraints for the linear programming problem of the wiring method are as follows: Constraint a: The escape pin point, as the source point of the current, is only allowed to route outwards. For pin i, the formula is: Where L represents the number of pins; IE v OE represents the set of all incoming edges to vertex v. v Represents the set of all outgoing edges from vertex v; Constraint b: For service paths that include transit nodes with bidirectional edges, the outflow and inflow of flow must be conserved. The transit node includes the central tile point and the hypothetical node, which can be expressed by the formula: Represents the i-th escape pin. Let represent the i-th boundary pin; V represents the set of all vertices in the routing region. Constraint c: The sink point is located on the boundary, has one and only one, and satisfies: Constraint d: Appropriate capacity constraints must be set for PCB routing. For a routing area with a capacity of 1, the formula is: Among them, V b This represents the set of boundary points; the first constraint applies to the central tile point, and the second constraint applies to the imaginary nodes. Furthermore, for cases where the capacity increases, simply change the constraint condition to be less than or equal to the capacity. Constraint e: OER routing prohibits trace crossings. In the network flow diagram, crossings can only occur at the center tile. Two binary variables representing the vertical direction are introduced at the tile, with the following formula: Where w1, w2, w3, and w4 represent the four directions of vertex w: west, north, east, and south, respectively. wi This represents the variable at the center tile point w of pin point i. Represents the horizontal direction. Representing the vertical direction; transforming non-intersecting conditions into linear programming constraints, namely: Constraint f is ordered, meaning that the internal pins of the circuit board wiring must escape in a given pin order. After the internal pins are connected to the component boundary, the external connections are not limited in capacity and are connected to the same junction. This can be expressed by the formula: in, This means that when the target sink is consistent, pin i+1 will always select a portion of the outer boundary points for connection than pin i, thus achieving order; Constraint g: Relax the above linear constraints by a preset ratio to facilitate the selection of the main obstacle points in the future. To address the path congestion caused by multiple pins simultaneously choosing the same boundary point to escape in certain areas, a local optimization method is used to adjust the results.

3. The escape routing method based on linear programming according to claim 1, characterized in that: Step S3 uses a local heuristic optimization method, specifically: When the initial results of linear programming (LP) routing are known, including a portion of the complete routing path and a portion of congested areas with pin crossings: Step a: Establish an ILP model for the current congested region, identify the main obstacle points from the congested region, add non-intersecting, ordered linear constraints to the known paths of the points, and solve them; Step b: Determine if the path congestion has been resolved. If yes, proceed to the next step; otherwise, continue to solve for the paths of other points in the region. Step c: Iterate repeatedly until there is no congestion in the region, then return to execute a new linear programming LP.

4. The escape routing method based on linear programming according to claim 1, characterized in that: The specific method for step S4 is as follows: Method a: Reset all wiring paths except for the main obstacle points; Method b: Eliminate the main obstacles after optimization, continue to solve the global iterative LP, determine the congestion of the routing path, and if congestion exists, locally optimize to resolve the congestion until the routing is completed.

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