An SRAM-based in-memory computing circuit unit

Abstract

This invention relates to an in-memory computing circuit unit based on SRAM. The unit consists of a standard 6-transistor SRAM and six additional PMOS transistors. The standard 6-transistor SRAM is used to store information, while the six additional PMOS transistors are responsible for performing single-bit multiplication and addition operations between external signals and the information stored in memory, thereby enabling high-speed and stable implementation of a single-bit neural network. This invention can accelerate the speed of single-bit neural networks and reduce their power consumption.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing circuit technology, specifically to an in-memory computing circuit unit based on SRAM. Background Technology

[0002] With the development of artificial intelligence, we are entering the era of big data. Massive amounts of data are being processed in fields such as social media, healthcare, and transportation, leading to an ever-increasing demand for high-throughput and energy-efficient computing. However, the current mainstream computer systems, employing the von Neumann architecture to separate computing and storage modules, suffer from memory and bandwidth walls, severely impacting data throughput and computational efficiency. In-memory computing architectures have become a research focus due to their potential to overcome the problems inherent in the von Neumann architecture.

[0003] Currently, researchers have proposed in-memory computing architectures with different structures and demonstrated that SRAM-based in-memory computing architectures can significantly improve energy efficiency when processing massive amounts of data, and have also achieved widespread application in neural networks, encryption, and other fields. Traditional SRAM-based in-memory computing circuit units suffer from read corruption problems when running single-bit multiply-accumulate operations in single-bit neural networks. During multiply-accumulate operations, bit lines often need to be enabled simultaneously. When bit lines are enabled simultaneously, the direct connection between storage nodes via bit lines can easily cause data flipping in memory, leading to errors in the final calculation result. Therefore, we propose an SRAM-based in-memory computing circuit unit to solve the above problems. Summary of the Invention

[0004] The purpose of this invention is to provide an SRAM-based in-memory computing circuit unit to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: an SRAM-based in-memory computing circuit unit, comprising a computing section consisting of a 6-transistor SRAM and 6 PMOS transistors, characterized in that:

[0006] The aforementioned 6-transistor SRAM includes NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, PMOS transistor P1, and PMOS transistor P2;

[0007] The computing section consisting of the six PMOS transistors includes PMOS transistors P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, and PMOS transistor P8.

[0008] in:

[0009] PMOS transistor P1 and NMOS transistor N3 form the first inverter, and PMOS transistor P2 and NMOS transistor N4 form the second inverter. These two inverters are cross-coupled to form a latch.

[0010] The drain of PMOS transistor P1 is electrically connected to the drain of NMOS transistor N3 in memory node Q, and the drain of PMOS transistor P2 is electrically connected to the drain of NMOS transistor N4 in memory node QB.

[0011] The source of PMOS transistor P1 and the source of PMOS transistor P2 are electrically connected to the power supply. The source of NMOS transistor N3 and the source of NMOS transistor N4 are electrically connected to ground.

[0012] The source of NMOS transistor N1 is electrically connected to the left column bit line BL, the gate of NMOS transistor N1 is electrically connected to the word line WL, and the drain of NMOS transistor N1 is electrically connected to the drain of NMOS transistor N3.

[0013] The source of NMOS transistor N2 is electrically connected to the right column bit line BLB, the gate of NMOS transistor N2 is electrically connected to the word line WL, and the drain of NMOS transistor N2 is electrically connected to the drain of NMOS transistor N4.

[0014] The source of PMOS transistor P3 is electrically connected to the source of PMOS transistor P4 at node R. The gate of PMOS transistor P3 is electrically connected to the drain of NMOS transistor N1. The drain of PMOS transistor P3 is electrically connected to line RBL. The gate of PMOS transistor P4 is electrically connected to the drain of NMOS transistor N2. The drain of PMOS transistor P4 is electrically connected to line RBLB.

[0015] The source of PMOS transistor P5 is electrically connected to the source of PMOS transistor P6 at node RB. The gate of PMOS transistor P5 is electrically connected to the gate of PMOS transistor P4. The drain of PMOS transistor P5 is electrically connected to line RBL. The gate of PMOS transistor P6 is electrically connected to the gate of PMOS transistor P3. The drain of PMOS transistor P6 is electrically connected to line RBLB.

[0016] The source of PMOS transistor P7 is electrically connected to the power supply, the gate of PMOS transistor P7 is electrically connected to line IL, and the drain of PMOS transistor P7 is electrically connected to node R.

[0017] The source of PMOS transistor P8 is electrically connected to the power supply, the gate of PMOS transistor P8 is electrically connected to line ILB, and the drain of PMOS transistor P8 is electrically connected to node RB.

[0018] Lines BL and BLB are used to read and write data in the standard 6-transistor SRAM. Line WL is used to control the read and write enable of the standard 6-transistor SRAM cell.

[0019] When node Q is high and node QB is low, the weight of a standard 6-transistor SRAM memory is "1". When node Q is low and node QB is high, the weight of a standard 6-transistor SRAM memory is "-1".

[0020] During multiplication and addition, the signals on line IL and line ILB are an opposite pair. When the signal on line IL is high and the signal on line ILB is low, it represents a multiplier of "1". When the signal on line IL is low and the signal on line ILB is high, it represents a multiplier of "-1".

[0021] During multiplication and addition operations, lines RBL and RBLB are used to read the result. Lines RBL and RBLB typically need to be pulled down using appropriate NMOS transistors or resistors. The voltages on line RBL and RBLB represent the result, which can be read using a sensitive amplifier or dynamic comparator. When the operation is complete, if the voltage on line RBL is greater than the voltage on line RBLB, the result is "1". When the voltage on line RBLB is greater than the voltage on line RBL, the result is "-1".

[0022] When no multiplication-addition operations are being performed, the signals on line IL and line ILB should be at a high level to turn off PMOS transistors P7 and P8, thereby reducing power consumption.

[0023] Compared with the prior art, the SRAM-based in-memory computing circuit unit implemented according to the above technical solution of the present invention avoids the problem of memory data flipping when performing multiplication and addition operations in traditional in-memory computing circuit units. It has the characteristics of high precision, good stability, low power consumption, and high speed, and can efficiently execute artificial intelligence algorithms. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an SRAM-based in-memory computing circuit unit according to the present invention.

[0025] Figure 2 This is a schematic diagram of the structure of an SRAM-based in-memory computing circuit array device according to the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Example 1

[0028] like Figure 1 As shown, this invention discloses an in-memory computing circuit unit based on SRAM. The SRAM-based in-memory computing circuit unit includes a standard 6-transistor SRAM and a computing section consisting of an additional 6 PMOS transistors. Data storage and data reading / writing are performed by the standard 6-transistor SRAM. Multiply-accumulate operations are mainly performed by the computing section consisting of the additional 6 PMOS transistors.

[0029] NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, PMOS transistor P1, and PMOS transistor P2 constitute a standard 6-transistor SRAM. PMOS transistors P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, and PMOS transistor P8 constitute an additional 6 PMOS transistors forming the computational part.

[0030] The source of PMOS transistor P1 and the source of PMOS transistor P2 are electrically connected to the power supply. The source of NMOS transistor N3 and the source of NMOS transistor N4 are electrically connected to ground.

[0031] The drains of PMOS transistor P1, NMOS transistor N3, NMOS transistor N1, PMOS transistor P2, NMOS transistor N4, PMOS transistor P3, and PMOS transistor P6 are electrically connected to each other. The drains of PMOS transistor P2, NMOS transistor N4, NMOS transistor N2, PMOS transistor P1, NMOS transistor N3, PMOS transistor P4, and PMOS transistor P5 are also electrically connected to each other.

[0032] The source of NMOS transistor N1 is electrically connected to the left column bit line BL, and the source of NMOS transistor N2 is electrically connected to the right column bit line BLB. The gate of NMOS transistor N1 and the gate of NMOS transistor N2 are electrically connected to the word line WL.

[0033] The drains of PMOS transistors P3 and P5 are electrically connected to line RBL, and the drains of PMOS transistors P4 and P6 are electrically connected to line RBLB.

[0034] The source of PMOS transistor P3, the source of PMOS transistor P4, and the drain of PMOS transistor P7 are electrically connected to node R. The source of PMOS transistor P5, the source of PMOS transistor P6, and the drain of PMOS transistor P8 are electrically connected to node RB.

[0035] The source of PMOS transistor P7 and the source of PMOS transistor P8 are electrically connected to the power supply. The gate of PMOS transistor P7 is electrically connected to line IL, and the gate of PMOS transistor P8 is electrically connected to line ILB.

[0036] Line WL is used to control the read / write enable of the SRAM cell. Lines BL and BLB are used to read and write data in a standard 6-transistor SRAM.

[0037] When node Q is high and node QB is low, the stored weight is "1". When node Q is low and node QB is high, the stored weight is "-1".

[0038] During multiplication and addition operations, the signals on line IL and line ILB are opposite. When the input multiplier is "1", the signal on line IL is high and the signal on line ILB is low. When the input multiplier is "-1", the signal on line IL is low and the signal on line ILB is high.

[0039] When the operation result is "1", line RBL is pulled up. When the operation result is "-1", line RBLB is pulled up. When the input multiplier is "1" and the storage weight is "1", PMOS transistors P5 and P8 are turned on, and line RBL is pulled up. When the input multiplier is "1" and the storage weight is "-1", PMOS transistors P6 and P8 are turned on, and line RBLB is pulled up. When the input multiplier is "-1" and the storage weight is "1", PMOS transistors P4 and P7 are turned on, and line RBLB is pulled up. When the input multiplier is "-1" and the storage weight is "-1", PMOS transistors P3 and P7 are turned on, and line RBL is pulled up.

[0040] When not performing multiplication and addition operations, in order to reduce power consumption, the signals on line IL and line ILB should be at a high level, thereby turning off PMOS transistors P7 and P8.

[0041] Example 2

[0042] like Figure 2 As shown, the present invention also provides an in-memory computing device suitable for single-bit neural networks. The device includes a 3-row, 2-column array composed of six SRAM-based in-memory computing circuit units as described in Embodiment 1, four pull-down resistors, and two sensitive amplifiers for reading the computation results.

[0043] The six embodiments described in Example 1, comprising a 3x2 array of SRAM-based in-memory computing circuit units, include unit D. <1> Unit D <2> Unit D <3> Unit D <4> Unit D <5> Unit D <6> .

[0044] BL (Boys' Love) <1> BL (Boys' Love) <2> The line BLB corresponds to the SRAM-based in-memory computing circuit unit described in Embodiment 1. <1> , line BLB <2> The line BLB corresponds to the SRAM-based in-memory computing circuit unit described in Embodiment 1. Line RBL <1> 、Line RBL <2> The line RBL corresponds to the SRAM-based in-memory computing circuit unit described in Embodiment 1. Line RBLB <1> , line RBLB <2> The corresponding line RBLB of the SRAM-based in-memory computing circuit unit described in Embodiment 1. Line WL <1> 、line WL <2> 、line WL <3> The line WL corresponds to the SRAM-based in-memory computing circuit unit described in Embodiment 1. Line IL <1> IL line <2> IL line <3> The corresponding line IL of the SRAM-based in-memory computing circuit unit described in Embodiment 1. Line ILB <1> , line ILB <2> , line ILB <3> The line ILB corresponds to the SRAM-based in-memory computing circuit unit described in Embodiment 1.

[0045] Unit D <1> Unit D <3> Unit D <5> Shared line BL <1> , line BLB <1> 、Line RBL <1> , line RBLB <1> Unit D <2> Unit D <4> Unit D <6> Shared line BL <2> , line BLB <2> 、Line RBL <2> , line RBLB <2> Unit D <1> Unit D <2> Common line IL <1> , line ILB <1> 、line WL <1> Unit D <3> Unit D <4> Common line IL <2> , line ILB <2> 、line WL <2> Unit D <5> Unit D <6> Common line IL <3> , line ILB <3> 、line WL <3> .

[0046] Unit D <1> Unit D <3> Unit D <5> The first column of the 3x2 array of SRAM-based in-memory computing circuit units described in Embodiment 1. Unit D <2> Unit D <4> Unit D <6> The second column of the 3-row, 2-column array of the six SRAM-based in-memory computing circuit units described in Embodiment 1.

[0047] Line WL <1> 、line WL <2> 、line WL <3> Used to control the read / write enable of the aforementioned in-memory computing circuit unit. (Line BL) <1> , line BLB <1> BL (Boys' Love) <2> , line BLB <2> Used to read and write the weights stored in the in-memory computing circuit unit. (IL) <1> , line ILB <1> IL line <2> , line ILB <2> IL line <3> , line ILB <3> Used to input signals. When line IL <1> The voltage signal on the line is high level, ILB <1> When the voltage signal on line IL is low, it means the input signal for the first row is "1". <1> The voltage signal on the line is low level, ILB <1> A high voltage signal on the line indicates that the input signal for the first row is "-1". When line IL... <2> The voltage signal on the line is high level, ILB <2> When the voltage signal on line IL is low, it means the input signal for the second row is "1". <2> The voltage signal on the line is low level, ILB <2> A high voltage signal on line IL indicates that the input signal for the second row is "-1". <3> The voltage signal on the line is high level, ILB <3> The voltage signal on line IL is low, indicating that the input signal of the third row is "1". <3> The voltage signal on the line is low level, ILB <3> The voltage signal on the line is high, which means the input signal for the third line is "-1".

[0048] When unit D <1> When the result of the operation is "1", unit D <1> Line RBL <1> The voltage is pulled up on the unit D. <1> When the result of the operation is "-1", unit D <1> RBLB line <1> The voltage on cell D is pulled up. <2> When the result of the operation is "1", unit D <2> Line RBL <2> The voltage is pulled up on the unit D. <2> When the result of the operation is "-1", unit D <2> RBLB line <2> The voltage on cell D is pulled up. <3> When the result of the operation is "1", unit D <3> Line RBL <1> The voltage is pulled up on the unit D. <3> When the result of the operation is "-1", unit D <3> RBLB line <1> The voltage on cell D is pulled up. <4> When the result of the operation is "1", unit D <4> Line RBL <2> The voltage is pulled up on the unit D. <4> When the result of the operation is "-1", unit D <4> RBLB line <2> The voltage on cell D is pulled up. <5> When the result of the operation is "1", unit D <5> Line RBL <1> The voltage is pulled up on the unit D. <5> When the result of the operation is "-1", unit D <5> RBLB line <1> The voltage on cell D is pulled up. <6> When the result of the operation is "1", unit D <6> Line RBL <2> The voltage is pulled up on the unit D. <6> When the result of the operation is "-1", unit D <6> Line RBLB <2> The voltage is pulled up.

[0049] The four pull-down resistors mentioned include resistor R <1> Resistance R <2> Resistance R <3> Resistance R <4> Pull-down resistor R <1> Line RBL <1> Pull-down, pull-down resistor R <2> Line RBLB <1> Pull-down, pull-down resistor R <3> Line RBL <2> Pull-down, pull-down resistor R <4> Line RBLB <2> drop down.

[0050] The two sensitive amplifiers mentioned above have outputs of line OUT respectively. <1> Voltage signal on line OUT <2> The voltage signal on the output. OUT <1> The result is obtained by the sensitivity amplifier comparison line RBL <1> Voltage on line RBLB <1> The voltage on the line RBL is obtained. <1> The voltage on line RBLB is greater than the voltage on line RBLB. <1> When the voltage is OUT, line OUT <1> A high voltage signal on the line indicates a "1" output from the first column of the array. When line RBLB... <1> The voltage on the line is greater than that of line RBL <1> When the voltage is OUT, line OUT <1> A low voltage signal indicates a -1 output value for the first column of the array. Output OUT <2> The result is obtained by the sensitivity amplifier comparison line RBL <2> Voltage on line RBLB <2> The voltage on the line RBL is obtained. <2> The voltage on line RBLB is greater than the voltage on line RBLB. <2> When the voltage is OUT, line OUT <2> A high voltage signal on the line indicates a "1" output from the second column of the array. When line RBLB... <2> The voltage on the line is greater than that of line RBL <2> When the voltage is OUT, line OUT <2> The voltage signal on the array is low, which means the output result of the second column of the array is "-1".

[0051] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An SRAM-based computing-in-memory circuit unit, comprising a 6-transistor SRAM and a 6-PMOS computing part, characterized in that: the 6-transistor SRAM comprises NMOS transistors N1, N2, N3, N4, PMOS transistors P1 and P2; the 6-PMOS computing part comprises PMOS transistors P3, P4, P5, P6, P7 and P8; wherein: the PMOS transistor P1 and the NMOS transistor N3 constitute a first inverter, the PMOS transistor P2 and the NMOS transistor N4 constitute a second inverter, and the two inverters are cross-coupled to form a latch; the drain of the PMOS transistor P1 and the drain of the NMOS transistor N3 are electrically connected to a storage node Q, and the drain of the PMOS transistor P2 and the drain of the NMOS transistor N4 are electrically connected to a storage node QB; the source of the PMOS transistor P1 and the source of the PMOS transistor P2 are electrically connected to a power supply, and the source of the NMOS transistor N3 and the source of the NMOS transistor N4 are electrically connected to ground; the source of the NMOS transistor N1 is electrically connected to a left column bit line BL, the gate of the NMOS transistor N1 is electrically connected to a word line WL, and the drain of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N3; the source of the NMOS transistor N2 is electrically connected to a right column bit line BLB, the gate of the NMOS transistor N2 is electrically connected to the word line WL, and the drain of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N4; the source of the PMOS transistor P3 and the source of the PMOS transistor P4 are electrically connected to a node R, the gate of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N1, the drain of the PMOS transistor P3 is electrically connected to a line RBL, the gate of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2, and the drain of the PMOS transistor P4 is electrically connected to a line RBLB; the source of the PMOS transistor P5 and the source of the PMOS transistor P6 are electrically connected to a node RB, the gate of the PMOS transistor P5 is electrically connected to the gate of the PMOS transistor P4, the drain of the PMOS transistor P5 is electrically connected to the line RBL, the gate of the PMOS transistor P6 is electrically connected to the gate of the PMOS transistor P3, and the drain of the PMOS transistor P6 is electrically connected to the line RBLB; the source of the PMOS transistor P7 is electrically connected to a power supply, the gate of the PMOS transistor P7 is electrically connected to a line IL, and the drain of the PMOS transistor P7 is electrically connected to the node R; the source of the PMOS transistor P8 is electrically connected to the power supply, the gate of the PMOS transistor P8 is electrically connected to a line ILB, and the drain of the PMOS transistor P8 is electrically connected to the node RB. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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