Memory device, method of manufacturing the same, and electronic device including the memory device

Abstract

A memory device, a manufacturing method thereof, and an electronic device including the memory device are disclosed. According to embodiments, the memory device can include: a plurality of cell active layers vertically stacked on a substrate, each cell active layer including a lower source / drain region and an upper source / drain region disposed at different vertical heights in the cell active layer, and a channel region between the lower source / drain region and the upper source / drain region; a gate stack vertically extending on the substrate with respect to the substrate to pass through the plurality of cell active layers, wherein the gate stack includes a gate conductor layer and a storage functional layer disposed between the gate conductor layer and the cell active layers, defining a memory cell at an intersection of the gate stack and each cell active layer; and a conductive metal layer disposed on at least one of a lower surface and an upper surface of each cell active layer.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically to memory devices, methods of manufacturing the same, and electronic devices including memory devices. Background Technology

[0002] In horizontal devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), the source, gate, and drain are arranged in a direction generally parallel to the substrate surface. Due to this arrangement, horizontal devices are not easily miniaturized further. In contrast, in vertical devices, the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical devices are easier to miniaturize than horizontal devices. Furthermore, vertical devices are easier to stack on top of each other, making them suitable for three-dimensional (3D) structures.

[0003] However, it is difficult to embed metal conductive lines in 3D structures, especially when using monocrystalline silicon material in the channel to suppress the increase in resistance. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is at least in part to provide a storage device with improved performance, a method of manufacturing the same, and an electronic device including the storage device.

[0005] According to one aspect of this disclosure, a memory device is provided, comprising: a plurality of cell active layers vertically stacked on a substrate, each cell active layer including a lower source / drain region and an upper source / drain region disposed at different vertical heights in the cell active layer, and a channel region between the lower source / drain region and the upper source / drain region; a gate stack extending vertically relative to the substrate to pass through the plurality of cell active layers on the substrate, wherein the gate stack includes a gate conductor layer and a memory function layer disposed between the gate conductor layer and the cell active layers, defining a memory cell at the intersection of the gate stack and each cell active layer; and a conductive metal layer disposed on at least one of the lower surface and the upper surface of each cell active layer.

[0006] According to another aspect of this disclosure, a method of manufacturing a memory device is provided, comprising: forming a stack of a plurality of cell active layers and a plurality of sacrificial layers on a substrate, each cell active layer having a sacrificial layer at least on one side; forming a processing channel extending vertically relative to the substrate through the stack; removing the sacrificial layers via the processing channel; forming conductive metal layers on the lower and / or upper surfaces of each cell active layer exposed therefrom in the space released due to the removal of the sacrificial layers via the processing channel, and forming isolation layers electrically isolating the conductive metal layers from each other; and forming a gate stack in the processing channel, the gate stack including a gate conductor layer and a memory function layer disposed between the gate conductor layer and the cell active layers, defining a memory cell at the intersection of the gate stack and the cell active layers.

[0007] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned storage device.

[0008] According to embodiments of this disclosure, a conductive metal layer can be provided as a bit line / source line connection to reduce resistance. Additionally, stacks of single-crystal materials can be used as building blocks to construct three-dimensional (3D) memory devices. Therefore, when multiple memory cells are stacked on top of each other, the increase in resistance can be suppressed. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figures 1 to 13(c) A schematic diagram of some stages in the process of manufacturing a storage device according to an embodiment of the present disclosure is shown;

[0011] Figure 14 An equivalent circuit diagram of a storage device according to an embodiment of the present disclosure is shown schematically;

[0012] Figures 15 to 18 A schematic diagram of some stages in the process of manufacturing a storage device according to another embodiment of the present disclosure is shown;

[0013] Figures 19 to 21 A schematic diagram of some stages in the process of manufacturing a storage device according to another embodiment of the present disclosure is shown;

[0014] Figure 22 An equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure is shown schematically.

[0015] in, Figure 2(a) , 10(a) Figure 13(a) is a top view. Figure 2(a) shows the positions of lines AA′ and BB′.

[0016] Figure 1 , 2(b) Sections 3 to 9, 10(b), 11(a), 12(a), 13(b), and 15 to 21 are cross-sectional views along line AA′.

[0017] Figure 10(c) , 11(b) Figures 12(b) and 13(c) are cross-sectional views along line BB′.

[0018] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0019] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0020] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0021] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0022] The memory device according to embodiments of this disclosure is based on a vertical device. The vertical device may include an active region disposed on a substrate in a vertical direction (generally perpendicular to the substrate surface), including source / drain regions disposed at different vertical heights (e.g., at the top and bottom ends respectively) and a channel region located between the source / drain regions. A conductive path can be formed between the source / drain regions through the channel region. In the active region, the source / drain regions and the channel region may be defined, for example, by doping concentration.

[0023] According to embodiments of this disclosure, the active region can be defined by a unit active layer on a substrate. For example, the unit active layer can be a semiconductor material layer, where source / drain regions can be formed at opposite ends in the vertical direction by doping (e.g., diffusion doping described below), and a channel region can be formed in the middle of the semiconductor material layer in the vertical direction. Alternatively, the unit active layer can be a stack of source / drain layers, a channel layer, and source / drain layers, where the source / drain layers can be in-situ doped during growth to form source / drain regions. A gate stack can extend through the unit active layer, so that the active region can surround the outer periphery of the gate stack. Here, the gate stack can include at least one of a storage functional layer, such as a charge trapping material or a ferroelectric material, to realize a storage function. Thus, the gate stack cooperates with the opposite active region to define a memory cell. Here, the memory cell can be a flash memory cell.

[0024] Multiple gate stacks can be configured to extend through the cell active layer, thereby defining multiple memory cells at the intersections of these gate stacks and the cell active layer. These memory cells are arranged in an array (e.g., typically a two-dimensional array arranged in rows and columns) in the plane containing the cell active layer, corresponding to the multiple gate stacks.

[0025] Due to the ease of stacking vertical devices, the memory devices according to embodiments of this disclosure can be three-dimensional (3D) arrays. Specifically, a plurality of such cell active layers can be arranged in the vertical direction. The gate stack can extend vertically through these plurality of cell active layers. Thus, for a single gate stack, it intersects with the plurality of cell active layers stacked in the vertical direction to define a plurality of memory cells stacked in the vertical direction.

[0026] In NOR ("NOR") type memory devices, each memory cell can be connected to a common source line. Given this configuration, to save wiring, two adjacent memory cells can share the same source line connection in the vertical direction. For example, for these two adjacent memory cells, their respective source / drain regions at their near ends (i.e., the ends where the two memory cells are close to each other) can serve as source regions and are therefore electrically connected to the source line, for example, through a common contact; their respective source / drain regions at their far ends (i.e., the ends where the two memory cells are far from each other) can serve as drain regions and can be connected to different bit lines respectively.

[0027] The single-cell active layer can be formed by epitaxial growth and can be a single-crystal semiconductor material. Compared to conventional processes that form multiple gate stacks stacked on top of each other and then form vertical active regions through these gate stacks, it is easier to form single-crystal active regions (especially channel regions).

[0028] The active layer can be doped in situ during growth, which can define the doping characteristics in the channel region. Furthermore, doping in the source / drain regions can be formed through diffusion. For example, solid-phase dopant source layers can be placed at opposite ends of each active layer, and the dopant in the solid-phase dopant source layers can be driven into the active layer to form source / drain regions. Thus, the doping distribution in the source / drain regions and the channel region can be adjusted independently, and steep high-doping sources / drain regions can be formed.

[0029] A conductive metal layer may be disposed on at least one of the lower and upper surfaces of a cell active layer, which helps to reduce resistance. When conductive metal layers are disposed on both the lower and upper surfaces of a cell active layer, one can be used as a bit line (BL) connection, and the other as a source line (SL) connection. Alternatively, when a conductive metal layer is disposed on one of the lower and upper surfaces of a cell active layer (while no conductive metal layer is disposed on the other surface), the conductive metal layer can be used as either a BL connection or an SL connection.

[0030] Such vertical memory devices can be manufactured, for example, as follows. Specifically, a stack of multiple active cell layers and multiple sacrificial layers can be formed on a substrate, such that each active cell layer has a sacrificial layer on at least one side (upper and / or lower). For example, the active cell layers and sacrificial layers can be alternately arranged, or a sacrificial layer can be provided between every two active cell layers. The active cell layers and sacrificial layers can be provided by epitaxial growth. The sacrificial layer can then be replaced with an isolation layer (in particular, a structure in which a conductive metal layer sandwiches an isolation layer). In addition, in-situ doping can be performed during epitaxial growth to achieve the desired doping polarity and doping concentration.

[0031] Processing channels can be formed that extend vertically relative to the substrate through each unit active layer. Within these processing channels, the sidewalls of the sacrificial layer can be exposed, allowing it to be replaced with a structure consisting of a conductive metal layer sandwiching an isolation layer. For example, a support layer can be formed in a portion of the processing channels to support the stack when the sacrificial layer is replaced. The sacrificial layer can be removed via the remaining processing channels, for example, through selective etching. In the space freed up by the removal of the sacrificial layer, conductive metal layers and isolation layers can be formed, for example, by deposition followed by etching back.

[0032] According to other embodiments, the sacrificial layer can be replaced with a solid-state doped source layer first. Annealing can be used to drive the dopant from the solid-state doped source layer into opposite ends of the cell active layer to form source / drain regions. Subsequently, the solid-state doped source layer can be replaced with a structure consisting of a conductive metal layer sandwiching an isolation layer. Additionally, a gate stack can be formed in the fabrication channel.

[0033] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, conductive materials for forming electrodes, interconnect structures, etc.) but also etching selectivity. In the following description, the desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etching selectivity relative to other layers exposed to the same etching formulation.

[0034] Figures 1 to 13(c) A schematic diagram of some stages in the process of manufacturing a storage device according to an embodiment of the present disclosure is shown.

[0035] like Figure 1As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. In the following description, for ease of explanation, a bulk Si substrate, such as a Si wafer, will be used as an example.

[0036] On substrate 1001, a memory device, such as NOR or AND flash memory, can be formed as described below. The memory cell in the memory device can be an n-type device or a p-type device. Here, an n-type memory cell is described as an example, for which a p-type well can be formed in substrate 1001. Therefore, the following description, particularly regarding the doping type, is directed towards the formation of an n-type device. However, this disclosure is not limited thereto.

[0037] On the substrate 1001, a sacrificial layer 10031 for defining an isolation layer and a cell active layer 10051 for defining an active region of a memory cell can be formed, for example, by epitaxial growth.

[0038] The layers grown on the substrate 1001 can be single-crystal semiconductor layers. Because these layers are grown or doped separately, they can have crystal interfaces or doping concentration interfaces with each other.

[0039] The sacrificial layer 10031 can then be replaced with an isolation layer for electrical isolation, the thickness of which can correspond to the desired thickness of the isolation layer, for example, about 10 nm to 50 nm. According to embodiments of this disclosure, the sacrificial layer 10031 can also be used to define the location of bit line / source line (BL / SL) connections. The cell active layer 10051 then defines the active region of the memory cell, the thickness of which can be, for example, about 40 nm to 200 nm.

[0040] These semiconductor layers can include various suitable semiconductor materials, such as elemental semiconductor materials like Si or Ge, compound semiconductor materials like SiGe, etc. Consider the following process of replacing the sacrificial layer 10031 with an isolation layer, where the sacrificial layer 10031 can have etch selectivity relative to the unit active layer 10051. For example, the sacrificial layer 10031 can include SiGe (the atomic percentage of Ge is, for example, about 15%-30%), and the unit active layer 10051 can include Si.

[0041] When growing the active layer 10051, in-situ doping can be performed. For example, for n-type devices, p-type doping can be performed with a doping concentration of approximately 1E17-1E19 cm⁻¹. -3 This doping can define the doping characteristics in the subsequently formed channel region to, for example, adjust the device threshold voltage (V). tThis includes controlling short-channel effects, etc. Here, the doping concentration can have a non-uniform distribution in the vertical direction to optimize device performance. For example, the concentration is relatively high in the region close to the drain region (which is later connected to the bit line) to reduce short-channel effects, while the concentration is relatively low in the region close to the source region (which is later connected to the source line) to reduce channel resistance. This can be achieved by introducing different doses of dopant at different stages of growth.

[0042] To increase integration density, multiple active cell layers can be provided. For example, active cell layers 10052, 10053, and 10054 can be provided on active cell layer 10051 through epitaxial growth, with the active cell layers spaced apart by sacrificial layers 10032, 10033, and 10034 used to define isolation layers. Although Figure 1 Only four active layers are shown in the diagram, but this disclosure is not limited thereto. Active layers 10052, 10053, and 10054 may have the same or similar thickness and / or material as active layer 10051, or they may have different thicknesses and / or materials. For ease of description only, it is assumed that each active layer has the same configuration.

[0043] On these layers formed on the substrate 1001, a hard mask layer 1015 can be disposed to facilitate patterning. For example, the hard mask layer 1015 may include a nitride (e.g., silicon nitride) with a thickness of about 50 nm to 200 nm.

[0044] Between the hard mask layer 1015 and the active cell layer 10054, a sacrificial layer 10035 for defining the isolation layer may also be provided. For details about sacrificial layers 10032 to 10035, please refer to the description of sacrificial layer 10031 above.

[0045] Therefore, on the one hand, a processing channel is needed to reach the sacrificial layer in order to replace the sacrificial layer with an isolation layer; on the other hand, it is necessary to define the area for forming the gate. According to embodiments of this disclosure, these two can be combined. Specifically, the processing channel can be used to define the gate area.

[0046] For example, such as Figure 2(a) and 2(b)As shown, photoresist 1017 can be formed on the hard mask layer 1015 and patterned by photolithography to have a series of openings that define the locations of processing channels. The openings can be of various suitable shapes, such as circles, rectangles, squares, polygons, etc., and have suitable sizes, such as diameters or side lengths of approximately 20 nm to 500 nm. Here, these openings (particularly in the cell regions) can be arranged in an array, for example, a two-dimensional array along the horizontal and vertical directions in the plane of the paper in FIG. 2(a). This array can then define an array of memory cells. Although the openings are shown in FIG. 2(a) as being formed on the substrate (including the cell regions where memory cells will subsequently be fabricated and the contact regions where contacts will subsequently be fabricated) with substantially uniform size and a generally uniform density, this disclosure is not limited thereto. The size and / or density of the openings can be varied; for example, the density of openings in the contact regions can be less than the density of openings in the cell regions to reduce the resistance in the contact regions.

[0047] like Figure 3 As shown, photoresist 1017, configured as an etching mask, is used to etch layers on substrate 1001 using anisotropic etching such as reactive ion etching (RIE) to form processing channels T. RIE can be performed in a generally vertical direction (e.g., perpendicular to the substrate surface) and can extend into substrate 1001. This leaves a series of vertical processing channels T on substrate 1001. The processing channels T in the cell region also define gate regions. Afterward, photoresist 1017 can be removed.

[0048] Currently, the sidewalls of the sacrificial layer are exposed in the processing channel T. Therefore, the sacrificial layer can be replaced with an isolation layer via the exposed sidewalls. Considering the support function for the active layers 10051 to 10054 during replacement, a support layer can be formed.

[0049] For example, such as Figure 4 As shown, a support material layer can be formed on substrate 1001 by deposition, for example, chemical vapor deposition (CVD). The support material layer can be formed in a generally conformal manner. Considering etching selectivity, especially relative to the hard mask layer 1015 (nitride in this example) and the subsequently formed isolation layer (oxide in this example), the support material layer can include, for example, SiC. The support material layer in a portion of the processing channel T can be removed, for example, by forming photoresist 1021 and selectively etching, such as RIE, in conjunction with the photoresist 1021, while retaining the support material layer in the remaining processing channels T. The remaining support material layer forms support layer 1019. In this way, on the one hand, the sacrificial layer can be replaced by the processing channel in which support layer 1019 is not formed, and on the other hand, the active cell layers 10051 to 10054 can be supported by support layer 1019 in other processing channels. Afterwards, photoresist 1021 can be removed.

[0050] The arrangement of processing channels with and without support layers 1019 can be achieved through the patterning of photoresist 1021, and for the sake of process consistency and uniformity, they can be distributed approximately evenly. Figure 4 As shown, processing channels with a support layer 1019 and processing channels without a support layer 1019 can be arranged alternately.

[0051] According to embodiments of this disclosure, diffusion doping is used for source / drain doping to achieve better doping characteristics. For this purpose, the sacrificial layer can be replaced with a solid-phase dopant source layer before forming the isolation layer.

[0052] For example, such as Figure 5 As shown, the sacrificial layers 10031 to 10035 can be removed via selective etching through processing channel T. Due to the presence of the support layer 1019, the cell active layers 10051 to 10054 can be prevented from collapsing. In the voids left by the removal of the sacrificial layers, doped material can be filled to form solid-state doped source layers 10231, 10232, 10233, 10234, and 10235 by, for example, deposition (preferably atomic layer deposition (ALD) for better control of film thickness) followed by etching back (e.g., vertical RIE). For example, the solid-state doped source layers 10231 to 10235 may comprise phosphorus (P) glass (PSG) with a phosphorus (P) content of about 0.1% to 10% (for n-type memory cells) or borosilicate glass (BSG) with a boron (B) content of about 0.1% to 10% (for p-type memory cells).

[0053] In this example, source / drain doping is achieved through a solid-phase dopant source layer rather than in-situ doping. This allows for steep high source / drain doping and can suppress cross-contamination that may result from in-situ growth during epitaxial growth.

[0054] Annealing can be performed to drive the dopant in the solid-state dopant source layer into the unit active layer. For example... Figure 6 As shown, for each of the unit active layers 10051 to 10054, the dopant in the solid-state dopant source layer at its upper and lower ends enters from the upper and lower ends respectively, thereby forming highly doped regions 10071, 10091; 10072, 10092; 10073, 10093; 10074, 10094 (e.g., approximately 1E19-1E21 cm) at its upper and lower ends. -3The source / drain regions are defined by n-type doping. Here, the diffusion depth of the dopant from the isolation layer into the unit active layer can be controlled (e.g., approximately 10 nm–50 nm) so that the middle of each unit active layer in the vertical direction can maintain relatively low doping, for example, essentially maintaining the doping polarity (e.g., p-type doping) and doping concentration (e.g., 1E17–1E19 cm⁻¹) resulting from in-situ doping during growth. -3 ), and can define the channel area.

[0055] In-situ doping can typically achieve doping concentrations below 1E20cm⁻¹. -3 According to embodiments of this disclosure, source / drain doping is performed by diffusion from a solid-phase dopant source layer, which allows for high doping levels, for example, with doping concentrations exceeding 1E20 cm⁻¹. -3 It can even reach a height of approximately 7E20-3E21cm -3 Furthermore, due to diffusion characteristics, the source / drain regions can have a doping concentration gradient that decreases vertically from the side closer to the solid-phase dopant source layer towards the side closer to the channel region.

[0056] This type of diffusion doping can achieve a steep doping concentration distribution. For example, there can be a steep abrupt change in doping concentration between the source / drain region and the channel region, such as less than about 5 nm / dec to 20 nm / dec (i.e., a drop in doping concentration of at least one order of magnitude occurs in the range of less than about 5 nm to 20 nm). This abrupt change region in the vertical direction can be called an "interface layer".

[0057] Since the solid-phase dopant diffuses into the unit active layer from each source layer with approximately the same diffusion characteristics, each source / drain region 10071, 10091; 10072, 10092; 10073, 10093; 10074, 10094 can be substantially coplanar in the lateral direction. Similarly, each channel region can be substantially coplanar in the lateral direction. In addition, as mentioned above, the channel regions can have a non-uniform distribution in the vertical direction, with a relatively high doping concentration in the source / drain regions (drain regions) closer to one side and a relatively low doping concentration in the source / drain regions (source regions) closer to the other side.

[0058] While it is advantageous to use a solid-phase doped source layer, this disclosure is not limited thereto. For example, doping of the source / drain regions can also be achieved by in-situ doping during epitaxial growth.

[0059] like Figure 7As shown, solid-state dopant source layers 10231, 10232, 10233, 10234, and 10235 can be removed by selective etching. In the spaces freed up by the removal of solid-state dopant source layers 10231, 10232, 10233, 10234, and 10235, a conductive metal layer 1053 and an isolation layer 1055 can be formed. For example, a conductive metal material such as tungsten (W) can be deposited in a generally conformal manner, followed by the deposition of a dielectric material such as an oxide to fill the released spaces and any remaining voids in the processing channels. A conductive diffusion barrier layer can also be formed before depositing the conductive metal material. The deposited dielectric and conductive metal materials (and diffusion barrier layers, if present) can be etched back, such as by a vertical RIE, to remove them from the processing channels (the released processing channels will be used for gate stacking), leaving them in the space freed up by the removal of solid dopant source layers 10231, 10232, 10233, 10234 and 10235, resulting in conductive metal layer 1053 and isolation layer 1055.

[0060] The conductive metal layer 1053 can extend on the upper and lower surfaces of each active cell layer. The portions of the conductive metal layer 1053 extending on the upper and lower surfaces of each active cell layer can then be used as the BL / SL connection for the memory cells in the corresponding active cell layer. Additionally, due to the presence of the support layer 1019, the conductive metal layer 1053 has a portion extending along the sidewall of the isolation layer 1055 adjacent to the support layer 1019 (hereinafter referred to as the "sidewall portion" for convenience), which results in electrical communication between the BL / SL connections of different active cell layers. This may be undesirable.

[0061] Therefore, such as Figure 8 As shown, the support layer 1019 can be removed by selective etching. A masking layer 1057, such as photoresist, can be formed in the processing channels where the support layer 1019 was not previously formed, exposing the processing channels where the support layer 1019 was previously formed. Thus, the sidewall portions of the conductive metal layer 1053 are exposed in these processing channels. The sidewall portions of the conductive metal layer 1053 can be selectively etched through the unmasked processing channels. Therefore, the conductive metal layer 1053 can remain on the upper and lower surfaces of each active unit layer to serve as the BL / SL connection for the corresponding active unit layer, and the BL / SL connections of different active units can be electrically isolated from each other.

[0062] After that, the masking layer 1057 can be removed.

[0063] Gate stacks can be formed in the processing channels, particularly in the processing channels of the cell area. To form a storage device, the storage function can be achieved through the gate stack. For example, the gate stack can include storage structures such as charge-trapping materials or ferroelectric materials.

[0064] like Figure 9 As shown, the memory functional layer 1025 and the gate conductor layer 1027 can be formed sequentially, for example, by deposition. The memory functional layer 1025 can be formed in a generally conformal manner, and the gate conductor layer 1027 can fill the gaps remaining in the processing channel T after the memory functional layer 1025 is formed. The formed gate conductor layer 1027 and memory functional layer 1025 can be planarized, such as by chemical mechanical polishing (CMP, for example, stopping at the hard mask layer 1015), so that the gate conductor layer 1027 and memory functional layer 1025 can remain in the processing channel T, forming a gate stack.

[0065] The storage functional layer 1025 can be based on dielectric charge trapping, ferroelectric material effects, or engineered charge storage (SONOS). For example, the storage functional layer 1025 may include a dielectric tunneling layer (e.g., an oxide layer with a thickness of about 1 nm to 5 nm, which can be formed by oxidation or ALD) - a band shift layer (e.g., a nitride layer with a thickness of about 2 nm to 10 nm, which can be formed by CVD or ALD) - an isolation layer (e.g., an oxide layer with a thickness of about 2 nm to 6 nm, which can be formed by oxidation, CVD, or ALD). This three-layer structure can result in a band structure that traps electrons or holes. Alternatively, the storage functional layer 1025 may include a ferroelectric material layer, such as HfZrO2 with a thickness of about 2 nm to 20 nm.

[0066] The gate conductor layer 1027 may include, for example, (doped, such as p-type doped in the case of an n-type device) polysilicon or a metal gate material.

[0067] like Figure 9 As shown, the gate stack (1025 / 1027) with the storage function layer is surrounded by the cell active layer. The gate stack and the cell active layer work together to define the storage cell, as... Figure 9 The dotted circle in the diagram illustrates this. The channel region can connect the source / drain regions on opposite sides, and the channel region can be controlled by the gate stack. In a single memory cell, one of the source / drain regions at the top and bottom ends serves as the source region and can be electrically connected to the source line; the other serves as the drain region and can be electrically connected to the bit line. In the case of forming a NOR-type memory device, for every two vertically adjacent memory cells, the source / drain region at the top end of the lower memory cell and the source / drain region at the bottom end of the upper memory cell can be used as source regions, thus allowing them to share the same source line connection.

[0068] The gate stack extends vertically in a columnar shape, intersecting with multiple active cell layers, thereby defining multiple memory cells stacked on top of each other in the vertical direction. Memory cells associated with a single gate stack pillar can form a memory cell string. Corresponding to the layout of the gate stack pillars (corresponding to the layout of the aforementioned processing channel T, such as a two-dimensional array), multiple such memory cell strings are arranged on the substrate, thereby forming a three-dimensional (3D) array of memory cells.

[0069] This completes the fabrication of the storage cell (in the cell area). Then, various electrical contacts can be fabricated (in the contact area) to achieve the required electrical connections.

[0070] To achieve electrical connections to the active layers of each unit, a stepped structure can be formed in the contact area. Various methods exist in the art for forming such a stepped structure. According to embodiments of this disclosure, the stepped structure can be formed, for example, as follows.

[0071] like Figure 9 As shown, the current gate stack is exposed at the surface of hard mask layer 1015. To protect the gate stack (within the cell region) during the fabrication of the stepped structure, another hard mask layer 1029 can be formed first on hard mask layer 1015, as shown below. Figure 10(a) , 10(b) As shown in 10(c). For example, the hard mask layer 1029 may include oxide. Photoresist 1031 may be formed on the hard mask layer 1029 and patterned into masking cell regions by photolithography to expose the contact region. The photoresist 1031 can be used as an etching mask to selectively etch the hard mask layer 1029, hard mask layer 1015, conductive metal layer 1053, insulating layer 1055, and gate stack by means of RIE (Residual Etching). The etching depth can be controlled so that the surface exposed by the photoresist 1031 in the contact region after etching is substantially flat. For example, the hard mask layer 1029 can be etched first; then the gate conductor layer 1027 can be etched, with the etching of the gate conductor layer 1027 stopping near the top surface of the cell active layer 10054; then, the hard mask layer 1015, the conductive metal layer 1053, and the insulating layer 1055 can be etched sequentially; after this etching, the top of the storage function layer 1025 can protrude above the top surface of the cell active layer 10054 and can be removed by RIE. This creates a step between the contact area and the cell area. Afterwards, the photoresist 1031 can be removed.

[0072] like Figure 11(a) and 11(b)As shown, a sidewall 1033 can be formed at the step between the contact area and the cell area using a spacer forming process. For example, a dielectric material, such as an oxide, can be deposited in a generally conformal manner, followed by anisotropic etching, such as a vertical RIE, of the deposited dielectric to remove the lateral extensions of the deposited dielectric, leaving only its vertical extensions, thereby forming the sidewall 1033. Here, considering that the hard mask layer 1029 also includes oxide, the etching depth of the RIE can be controlled to be substantially equal to or slightly greater than the deposition thickness of the dielectric to avoid completely removing the hard mask layer 1029. The width of the sidewall 1033 (in the horizontal direction in the figure) can be substantially equal to the deposition thickness of the dielectric. The width of the sidewall 1033 defines the size of the landing pad subsequently used to connect to the source / drain region 10094 in the cell active layer 10054.

[0073] Using the sidewall 1033 thus formed as an etching mask, selective etching such as RIE can be used to etch the conductive metal layer 1053, the source / drain regions 10094 in the cell active layer 10054, and the gate stack to expose the channel region in the cell active layer 10054. The etching depth can be controlled so that the surface exposed by the sidewall 1033 in the contact area after etching is substantially flat. For example, the conductive metal layer 1053 can be etched to expose the source / drain regions 10094, and then the source / drain regions 10094 and the gate conductor layer 1027 (e.g., Si and polysilicon, respectively; if the gate conductor layer 1027 includes a metal gate, they can be etched separately) can be etched, stopping at the channel region in the cell active layer 10054; after such etching, the top of the storage function layer 1025 can protrude above the channel region in the cell active layer 10054 and can be removed by RIE. Thus, another step is formed in the contact area between the source / drain region 10094 in the active layer 10054 of the unit and the surface exposed by the sidewall 1033.

[0074] You can combine the above methods. Figure 11(a) and 11(b) The described process involves forming sidewalls and using these sidewalls as etching masks to create multiple steps in the contact area, such as... Figure 12(a) and 12(b) As shown. These steps form a stepped structure such that for each source / drain region (the conductive metal layer on the surface is also patterned in the same way as the corresponding source / drain region) and optional trench region in the active layer of each unit that requires electrical connection, its ends protrude relatively from the region above to define the contact pads of the contact portion to that region. Figure 12(a) and 12(b) The 1035 in the diagram represents the portion of the sidewalls formed in each stage that remains after processing. Since these sidewalls 1035 and the insulating layer are both oxides, they are shown as a single unit here.

[0075] After that, the contact parts can be made.

[0076] For example, such as Figure 13(a) , 13(b) As shown in Figure 13(c), the interlayer dielectric layer 1037 can be formed by depositing oxide and planarizing it, such as with CMP. Here, since both are oxides, the previous isolation layer and sidewalls 1035 are shown as integral with the interlayer dielectric layer 1037. Then, as shown, contacts 1039 and 1041 can be formed in the interlayer dielectric layer 1037. Specifically, contacts 1039 are formed in the cell region and electrically connected to the gate conductor layer 1027 in the gate stack; contacts 1041 are formed in the contact region and electrically connected to the respective source / drain regions and optionally the channel region. The contacts 1041 in the contact region can avoid the gate stack remaining in the contact region. These contacts can be formed by etching holes in the interlayer dielectric layer 1037 and filling them with a conductive material such as a metal.

[0077] Here, contact 1039 can be electrically connected to a word line. A gate control signal can be applied to the gate conductor layer 1027 via the word line and contact 1039. Contact 1041 can be electrically connected to a source line or a bit line. More specifically, for the same memory cell, one source / drain region can be electrically connected to a bit line, while another source / drain region can be electrically connected to a source line. Due to the presence of the conductive metal layer 1053, the resistance when applying electrical signals from the bit line or source line to the corresponding source / drain region can be reduced. A contact to the channel region is also formed here. This contact can be called a body contact and can receive body bias to adjust the device threshold voltage.

[0078] Figure 14 An equivalent circuit diagram of a storage device according to an embodiment of the present disclosure is shown schematically.

[0079] exist Figure 14The example illustrates eight stacked memory cell layers (corresponding to the eight active cell layers in the previous embodiment) and three word lines WL1, WL2, and WL3 passing through these eight memory cell layers. Memory cells in each memory cell layer can be connected in parallel between corresponding bit lines / source lines. The figure schematically illustrates the bit lines / source lines BL / SL1a, BL / SL1b, BL / SL2a, BL / SL2b, BL / SL3a, BL / SL3b, BL / SL4a, BL / SL4b, BL / SL5a, BL / SL5b, BL / SL6a, BL / SL6b, BL / SL7a, BL / SL7b, BL / SL8a, and BL / SL8b for these eight memory cell layers. In each pair of bit line / source lines BL / SLia and BL / SLib (where 1 ≤ i ≤ 8), one (e.g., BL / SLia) can serve as a bit line, while the other (e.g., BL / SLib) can serve as a source line. It should be noted that the number of memory cell layers, and therefore the number of bit lines / source lines and word lines, is not limited to this. Memory cells (MCs) are located at the intersections of bit lines and word lines. Additionally, Figure 14 The optional volume connections to each memory cell are also schematically shown in dashed lines.

[0080] For illustrative purposes only, a two-dimensional array of storage cells MC is shown here. Multiple such two-dimensional arrays can be arranged in directions intersecting with this two-dimensional array (e.g., the direction perpendicular to the paper in the figure) to obtain a three-dimensional array.

[0081] Based on this configuration, NOR or AND type flash memory can be formed. As described in further detail below, in the case of NOR type flash memory, at least some of the source lines of the memory cell layers can be connected to each other.

[0082] In the above embodiments, conductive metal layers are formed on both the upper and lower surfaces of each active layer to serve as bit line / source line connections, thereby reducing resistance. However, embodiments according to this disclosure are not limited to this. For example, conductive metal layers may be formed only on the upper or lower surface.

[0083] Figures 15 to 18 A schematic diagram of a portion of the process for manufacturing a storage device according to another embodiment of the present disclosure is shown.

[0084] like Figure 15 As shown, it can be combined as described above. Figure 1The method involves forming an alternating stack of sacrificial layers and unit active layers on a substrate 1001. Here, the sacrificial layers may include first sacrificial layers 10031, 10033, and 10035 and second sacrificial layers 20032 and 20034, each having etch selectivity relative to the others. Each unit active layer 10051, 10052, 10053, 10054, and 10055 has one of the first and second sacrificial layers formed on its upper surface, and the other of the first and second sacrificial layers formed on its lower surface. For example, the first and second sacrificial layers may comprise SiGe with different Ge atomic percentages, or one of the first and second sacrificial layers may comprise SiGe and the other may comprise SiC. Furthermore, each unit active layer 10051, 10052, 10053, 10054, and 10055 may be in-situ doped during epitaxial growth to define source / drain regions. Figure 15 The dashed line schematically illustrates the doping concentration interface between the source / drain region and the channel region (this dashed line will not be shown again in the following illustrations for convenience).

[0085] Next, as described above, processing channels can be formed in the stack, and support layers 1019 can be formed in some of the processing channels to obtain, as shown below. Figure 16 The structure shown is similar. The sacrificial layer can be replaced with a structure consisting of a conductive metal layer sandwiching an insulating layer via a processing channel. However, unlike the above embodiment, the first sacrificial layers 10031, 10033, and 10035, and the second sacrificial layers 20032 and 20034 can be replaced respectively.

[0086] For example, such as Figure 17 As shown, the second sacrificial layers 20032 and 20034 can be removed by selective etching (especially relative to the first sacrificial layers 10031, 10033 and 10035), and an isolation layer 2055 can be formed in the space freed up by the removal of the second sacrificial layers 20032 and 20034 by depositing and then etching back a dielectric (e.g., oxide).

[0087] Then, as Figure 18 As shown, the first sacrificial layers 10031, 10033, and 10035 can be removed by selective etching, and in the space freed up by the removal of the first sacrificial layers 10031, 10033, and 10035, the components can be combined as described above. Figure 7 As described above, a conductive metal layer 1053 and an isolation layer 1055 are formed. Thus, for each unit active layer 10051, 10052, 10053, 10054, and 10055, the conductive metal layer 1053 may be formed only on its upper or lower surface, and an isolation layer 2055 may be formed on the other surface, without a conductive metal layer.

[0088] Subsequent processes can be carried out according to the above embodiments, such as removing the support layer, etching the sidewall portion of the conductive metal layer 1053, and forming a gate stack in the processing channel.

[0089] According to another embodiment, only one of the first sacrificial layer and the second sacrificial layer can be removed to form a conductive metal layer (with an isolation layer sandwiched in between), while the other is retained. For example, one of the first sacrificial layer and the second sacrificial layer may include SiGe, while the other may include Si or a Si layer with a pnp doping distribution or an npn doping distribution along the vertical direction (such a Si layer can form electrical isolation through a pn junction).

[0090] In the above embodiments, adjacent active layers of the cells are separated by an isolation layer. However, this disclosure is not limited thereto. According to other embodiments, some active layers of the cells may not be isolated from each other.

[0091] Figures 19 to 21 A schematic diagram of a portion of the process for manufacturing a storage device according to another embodiment of the present disclosure is shown.

[0092] like Figure 19 As shown, a stack of active and sacrificial layers can be formed on substrate 1001. Combined with the above... Figure 1 The described embodiment differs in that a sacrificial layer is set between all adjacent active unit layers. In this embodiment, a sacrificial layer can be set every two adjacent active unit layers: no sacrificial layer is set between active unit layers L1 and L2, but sacrificial layers 10031 and 10032 are set above and below their combination, respectively; no sacrificial layer is set between active unit layers L3 and L4, but sacrificial layers 10032 and 10033 are set above and below their combination, respectively.

[0093] Each active layer can define source / drain regions (and therefore channel regions between them) through in-situ doping. For example, active layer L1 may include a first source / drain region 30071, a channel region 30051, and a second source / drain region 30091, which may be formed at different stages of epitaxial growth by introducing impurities of different concentrations. Active layer L2 may include a first source / drain region 30072, a channel region 30052, and a second source / drain region 30091. Here, active layers L1 and L2 are adjacent to each other and may share the same source / drain region 30091. Similarly, active layer L3 may include a first source / drain region 30073, a channel region 30053, and a second source / drain region 30093, and active layer L4 may include a first source / drain region 30074, a channel region 30054, and a second source / drain region 30093, which may share the same source / drain region 30093.

[0094] Next, as described above, processing channels can be formed in the stack, and support layers 1019 can be formed in some of the processing channels to obtain, as shown below. Figure 20 The structure shown is similar. The sacrificial layer can be replaced with a structure consisting of a conductive metal layer sandwiched between two insulating layers via a processing channel.

[0095] Then, as Figure 21 As shown, the first sacrificial layers 10031, 10032, and 10033 can be removed by selective etching, and in the space freed up by the removal of the first sacrificial layers 10031, 10032, and 10033, the components can be combined as described above. Figure 7 As described above, a conductive metal layer 1053 and an isolation layer 1055 are formed. Thus, for each unit active layer L1, L2, L3, L4, the conductive metal layer 1053 can be formed only at its upper or lower end, and the other end can be adjacent to the adjacent unit active layer.

[0096] Subsequent processes can be carried out according to the above embodiments, such as removing the support layer, etching the sidewall portion of the conductive metal layer 1053, and forming a gate stack in the processing channel.

[0097] In this embodiment, two vertically adjacent memory cells can share the same source / drain regions and can be electrically connected to the source line together. This results in a NOR configuration.

[0098] Figure 22 An equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure is shown schematically.

[0099] exist Figure 22 The example schematically shows three word lines WL1, WL2, WL3 and eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8. However, the specific number of bit lines and word lines is not limited to this. A memory cell MC is located at the intersection of the bit lines and word lines. Figure 22 The diagram also shows four source lines SL1, SL2, SL3, and SL4. As mentioned above, adjacent memory cells in any two layers vertically can share the same source line connection. Furthermore, the source lines can be interconnected, allowing each memory cell MC to be connected to a common source line. Figure 22 The optional body connections to each memory cell are also schematically shown in dashed lines. As described below, the body connection of each memory cell can be electrically connected to the source line connection of that memory cell.

[0100] Figure 22 The extension direction of the middle bit lines WL1 to WL3 can correspond to the extension direction of the gate stack, that is, the vertical direction relative to the substrate in the aforementioned embodiment. In this direction, adjacent bit lines are isolated from each other.

[0101] For every two adjacent memory cells in the vertical direction, the source / drain regions located in the middle, namely the source / drain regions 30091 between cell active layer L1 and cell active layer L2, and the source / drain regions 30093 between cell active layer L3 and cell active layer L4, can be electrically connected to the source line via the contact portion (see 1041 in Figure 13(c)); the source / drain regions located at the upper and lower ends, namely the source / drain regions 30071 in cell active layer L1 and 30072 in cell active layer L2, the source / drain regions 30073 in cell active layer L3 and 30074 in cell active layer L4, can be electrically connected to the bit line respectively via the contact portion (see 1041 in Figure 13(c)).

[0102] Here, two vertically adjacent memory cells are configured as source / drain regions located between them, electrically connected to the source line. This reduces the number of wires required.

[0103] The storage device according to embodiments of this disclosure can be applied to various electronic devices. For example, the storage device can store various programs, applications, and data required for the operation of the electronic device. The electronic device may also include a processor that works in conjunction with the storage device. For example, the processor can operate the electronic device by running programs stored in the storage device. Such electronic devices include, for example, smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, power banks, automotive electronic devices, communication devices, or Internet of Things (IoT) devices.

[0104] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0105] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A storage device, comprising: Multiple unit active layers are vertically stacked on a substrate, each unit active layer including a lower source / drain region and an upper source / drain region disposed at different vertical heights in the unit active layer, and a channel region between the lower source / drain region and the upper source / drain region; A gate stack extending vertically relative to the substrate through the plurality of cell active layers on the substrate, wherein the gate stack includes a gate conductor layer and a storage function layer disposed between the gate conductor layer and the cell active layers, and defines a storage cell at the intersection of the gate stack and each of the cell active layers; A conductive metal layer is disposed on at least one of the lower and upper surfaces of the active layer of each unit; as well as An insulating layer between adjacent conductive metal layers in the vertical direction. The storage device further includes at least one of the following: The bottom isolation layer on the substrate is located between the plurality of unit active layers and the substrate. The bottom isolation layer has a conductive metal layer on its first surface facing the substrate and on its second surface facing the lowest unit active layer among the plurality of unit active layers. The conductive metal layer on the second surface constitutes the conductive metal layer on the lower surface of the lowest unit active layer. as well as The top isolation layer on the plurality of active unit layers has a conductive metal layer on its third surface facing the uppermost active unit layer and on its fourth surface facing away from the uppermost active unit layer. The conductive metal layer on the third surface constitutes the conductive metal layer on the upper surface of the uppermost active unit layer.

2. The storage device according to claim 1, wherein, The conductive metal layer is disposed on both the lower and upper surfaces of the active layer of the unit.

3. The storage device according to claim 1, wherein, One of the plurality of active unit layers has a conductive metal layer disposed on its lower surface, while the active unit layer adjacent to the active unit layer has a conductive metal layer disposed on its upper surface. or One of the plurality of active unit layers has a conductive metal layer disposed on its upper surface, while the active unit layer adjacent to the active unit layer has a conductive metal layer disposed on its lower surface.

4. The storage device according to claim 3, wherein, A pair of adjacent active unit layers are connected to each other, and the conductive metal layer is disposed on the lower surface of the lower active unit layer and the upper surface of the upper active unit layer in the pair of active unit layers.

5. The storage device according to claim 1, wherein, The active layer of the unit includes a single-crystal semiconductor.

6. The storage device according to claim 1, wherein, Each of the cell active layers extends in a lateral direction relative to the substrate, thereby surrounding the outer periphery of the gate stack.

7. The storage device according to claim 6, wherein, Multiple gate stacks are provided, and the multiple gate stacks are arranged in an array on the substrate. Each of the conductive metal layers extends on the upper or lower surface of the corresponding unit active layer to surround the outer periphery of the gate stack.

8. The storage device according to claim 6, wherein, The substrate includes a cell region and a contact region adjacent to the cell region, the gate stack is disposed in the cell region, and the memory device further includes: The first contact portion and the second contact portion formed in the contact area respectively to the lower source / drain region and the upper source / drain region of the active layer of each unit.

9. The storage device according to claim 1, wherein, The conductive metal layer is used as a bit line connection or a source line connection.

10. The storage device according to claim 2, wherein, The conductive metal layer on one of the lower and upper surfaces of the active layer of the unit is used as a bit line connection, while the conductive metal layer on the other of the lower and upper surfaces is used as a source line connection.

11. The storage device according to claim 4, wherein, The conductive metal layer serves as a bit line connection.

12. The storage device according to claim 1, wherein, The doping concentration in the lower source / drain region and the upper source / drain region decreases in the vertical direction toward the channel region.

13. The storage device according to claim 1, further comprising: The interface layer between the lower source / drain region and the channel region, and the interface layer between the upper source / drain region and the channel region.

14. The storage device according to claim 1, wherein, The highest doping concentration in the lower source / drain region and the upper source / drain region is greater than 1E20 cm⁻¹. -3 .

15. The storage device according to claim 1, wherein, The storage functional layer includes at least one of a charge trapping material or a ferroelectric material.

16. A method of manufacturing a storage device, comprising: A stack of multiple active unit layers and multiple sacrificial layers is disposed on a substrate, wherein each active unit layer has a sacrificial layer on at least one side; Forming processing channels that extend vertically relative to the substrate to pass through the stack; The sacrificial layer is removed via the processing channel; Through the processing channel, in the space released due to the removal of the sacrificial layer, a conductive metal layer is formed on the lower and / or upper surface of each of the unit active layers exposed therefrom, and an isolation layer is formed to electrically isolate the conductive metal layers from each other. as well as A gate stack is formed in the processing channel. The gate stack includes a gate conductor layer and a storage function layer disposed between the gate conductor layer and the cell active layer. A storage cell is defined at the intersection of the gate stack and the cell active layer. The formation of the conductive metal layer and the formation of the isolation layer include: A support layer is formed in a portion of the processing channels; Conductive metallic materials are formed in a substantially conformal manner through the remaining processing channels; Dielectric material is filled through the remaining processing channels; The dielectric material and the conductive metal material are etched back to leave them in the space, and the etched-back dielectric material forms the isolation layer; The sacrificial layer is removed from one portion of the processing channels, and a masking layer is formed in the remaining processing channels; The portion of the conductive metal material extending on the sidewall of the dielectric material is etched via the aforementioned processing channel, and the etched conductive metal material forms the conductive metal layer; and Remove the masking layer.

17. The method of claim 16, further comprising: Multiple dopant source layers containing dopants are formed in the space via the processing channel; Annealing drives the dopant from the solid-phase dopant source layer into the opposite ends of the cell active layer to define the source / drain regions; as well as The solid dopant source layer is removed via the processing channel, wherein after the solid dopant source layer is removed, the conductive metal layer is formed in the space and the isolation layer is formed.

18. The method according to claim 16, wherein, The plurality of active unit layers and the plurality of sacrificial layers are formed by epitaxial growth.

19. The method according to claim 18, wherein, The multiple active unit layers are in-situ doped during epitaxial growth.

20. The method of claim 16, wherein, In the stack, the plurality of active unit layers and the plurality of sacrificial layers are alternately arranged, or In the stack, the sacrificial layer is disposed between every two adjacent active cell layers.

21. The method according to claim 16, wherein, Forming the gate stack includes: The storage functional layer is formed on the bottom surface and sidewalls of the processing channel in a substantially conformal manner; and The gate conductor layer is filled in the processing channel in which the storage function layer is formed.

22. An electronic device comprising a storage device as claimed in any one of claims 1 to 15.

23. The electronic device according to claim 22, wherein, The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, power banks, automotive electronic devices, communication devices, or Internet of Things (IoT) devices.

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