Ferroelectric complementary switch device, fabrication method, control method, and three-dimensional memory

Abstract

A ferroelectric complementary switching device can generate an in-plane electric field in a ferroelectric layer by applying a voltage on the ferroelectric layer through a first electrode and a second electrode, change the direction of the in-plane electric field by changing the direction of the voltage, control the first crack and the second crack to separate alternatively, realize the electrical connection and electrical insulation of the first conductive layer by closing and separating the first crack, realize the electrical and electrical insulation of the second conductive layer by closing and opening the second crack, and realize the function of the ferroelectric complementary switching device. The ferroelectric complementary switching device has higher speed, lower energy consumption and smaller chip area, and the manufacturing process is simple, compatible with Fe-NAND process, low cost and high economic benefit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and in particular to a ferroelectric complementary switching device, its fabrication method, its control method, and a three-dimensional memory. Background Technology

[0002] With the development of microelectronics technology, the feature size of transistors on integrated circuits is constantly approaching physical limits. Further reduction in device size would lead to serious leakage problems. However, functional devices based on electromechanical coupling, due to their mechanical "on" and "off" characteristics, effectively avoid leakage problems in the "off" state. Furthermore, compared to traditional semiconductor devices, microelectromechanical devices (MEMS) offer advantages such as a high switching ratio, low power consumption, and simple structure and manufacturing processes. These advantages hold enormous potential and application value in developing high-density, low-power, and high-stability memories, transistors, and logic devices. Summary of the Invention

[0003] The technical problem to be solved by the embodiments of this disclosure is to provide a ferroelectric complementary switching device, a preparation method, a control method, and a three-dimensional memory.

[0004] One embodiment of this disclosure provides a ferroelectric complementary switching device, which includes:

[0005] Ferroelectric layer;

[0006] The first electrode and the second electrode are disposed on the ferroelectric layer and are independent of each other, and are used to apply voltage to the ferroelectric layer;

[0007] An interlayer insulating layer is disposed on the first electrode and the second electrode;

[0008] A first conductive layer is disposed on the interlayer insulating layer and corresponds to the first electrode;

[0009] A second conductive layer is disposed on the interlayer insulating layer and corresponds to the second electrode;

[0010] The first signal transmission terminal and the second signal transmission terminal are disposed on the first conductive layer;

[0011] The third signal transmission terminal and the fourth signal transmission terminal are disposed on the second conductive layer;

[0012] A first crack extends from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrates the first electrode, the interlayer insulating layer, and the first conductive layer between the first signal transmission end and the second signal transmission end. The first crack does not penetrate the ferroelectric layer. The first conductive layer is divided into two independent parts by the first crack. The first signal transmission end and the second signal transmission end are respectively disposed on the two independent parts of the first conductive layer divided by the first crack.

[0013] The second crack extends from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrates the second electrode, the interlayer insulating layer, and the second conductive layer between the third signal transmission end and the fourth signal transmission end. The second crack does not penetrate the ferroelectric layer. The second conductive layer is divided into two independent parts by the second crack. The third signal transmission end and the fourth signal transmission end are respectively disposed on the two independent parts of the second conductive layer divided by the second crack.

[0014] Specifically, changing the direction of the voltage applied to the ferroelectric layer controls the separation of either the first crack or the second crack.

[0015] In one embodiment, the first crack does not penetrate the ferroelectric layer, and / or the second crack does not penetrate the ferroelectric layer.

[0016] In one embodiment, the first signal transmission terminal and the second signal transmission terminal are arranged on the first conductive layer along a first transverse direction, and the first crack extends along a second transverse direction and penetrates the first conductive layer; the third signal transmission terminal and the fourth signal transmission terminal are arranged on the second conductive layer along a first transverse direction, and the second crack extends along a second transverse direction and penetrates the second conductive layer; the first transverse direction and the second transverse direction intersect.

[0017] In one embodiment, the interlayer insulating layer further covers the ferroelectric layer region between the first electrode and the second electrode.

[0018] In one embodiment, the interlayer insulation layer comprises:

[0019] A first insulating layer is disposed on the first electrode, and a first conductive layer is disposed on the first insulating layer;

[0020] A second insulating layer is disposed on the second electrode, and a second conductive layer is disposed on the second insulating layer. The first insulating layer and the second insulating layer are independent of each other.

[0021] In one embodiment, the interlayer insulating layer covers a portion of the surfaces of the first electrode and the second electrode, a first conductive terminal is provided on the surface of the first electrode not covered by the interlayer insulating layer, and a second conductive terminal is provided on the surface of the second electrode not covered by the interlayer insulating layer.

[0022] In one embodiment, the orthogonal projection of the first electrode on the ferroelectric layer overlaps the orthogonal projection of the first conductive layer on the ferroelectric layer.

[0023] In one embodiment, the orthogonal projection of the second electrode onto the ferroelectric layer overlaps the orthogonal projection of the second conductive layer onto the ferroelectric layer.

[0024] In one embodiment, the material of the first electrode is the same as the material of the first conductive layer.

[0025] In one embodiment, the material of the second electrode is the same as the material of the second conductive layer.

[0026] In one embodiment, one of the signal transmission terminals on the first conductive layer is electrically connected to one of the signal transmission terminals on the second conductive layer, forming the signal output terminal of the ferroelectric complementary switching device.

[0027] In one embodiment, the signal transmission terminal constituting the signal output terminal on the first conductive layer is closer to the second conductive layer than another signal transmission terminal on the first conductive layer, and the signal transmission terminal constituting the signal output terminal on the second conductive layer is closer to the first conductive layer than another signal transmission terminal on the second conductive layer.

[0028] This disclosure also provides a method for fabricating a ferroelectric complementary switching device, comprising:

[0029] Provide substrate;

[0030] A ferroelectric layer, a first electrode, a second electrode, an interlayer insulating layer, a first conductive layer, a second conductive layer, a first signal transmission terminal, a second signal transmission terminal, a third signal transmission terminal, and a fourth signal transmission terminal are sequentially formed on the surface of the substrate. The first conductive layer corresponds to the first electrode, the second conductive layer corresponds to the second electrode, the first signal transmission terminal and the second signal transmission terminal are disposed on the first conductive layer, and the third signal transmission terminal and the fourth signal transmission terminal are disposed on the second conductive layer.

[0031] A first crack and a second crack are formed. The first crack extends from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrates the second electrode, the interlayer insulating layer, and the first conductive layer between the first signal transmission end and the second signal transmission end. The first crack does not penetrate the ferroelectric layer. The first conductive layer is divided into two independent parts by the first crack. The first signal transmission end and the second signal transmission end are respectively disposed on the two independent parts of the first conductive layer divided by the first crack. The second crack extends from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrates the second electrode, the interlayer insulating layer, and the second conductive layer between the third signal transmission end and the fourth signal transmission end. The second crack does not penetrate the ferroelectric layer. The second conductive layer is divided into two independent parts by the second crack. The third signal transmission end and the fourth signal transmission end are respectively disposed on the two independent parts of the second conductive layer divided by the second crack.

[0032] In one embodiment, prior to the formation of the first and second cracks, the ferroelectric layer has a defined ferroelectric domain polarization direction, and the method for forming the first and second cracks includes:

[0033] A first flip voltage is applied to the ferroelectric layer via the first electrode and the second electrode to form the first crack.

[0034] A second reversal voltage is applied to the ferroelectric layer through the first electrode and the second electrode to form the second crack. The second reversal voltage has the opposite polarity to the first reversal voltage.

[0035] In one embodiment, after forming the ferroelectric layer on the substrate, the method further includes the following step: applying a polarization voltage to the ferroelectric layer so that the polarization direction of the ferroelectric domains of the ferroelectric layer is the same as the direction of the polarization voltage, thereby forming the predetermined ferroelectric domain polarization direction.

[0036] This disclosure also provides a control method for the ferroelectric complementary switching device as described above, comprising: applying a first voltage to the ferroelectric layer via the first electrode and the second electrode to control the separation of the first crack and the closure of the second crack, thereby achieving electrical insulation between the first signal transmission terminal and the second signal transmission terminal and electrical conduction between the third signal transmission terminal and the fourth signal transmission terminal; applying a second voltage to the ferroelectric layer via the first electrode and the second electrode to control the closure of the first crack and the separation of the second crack, thereby achieving electrical conduction between the first signal transmission terminal and the second signal transmission terminal and electrical insulation between the third signal transmission terminal and the fourth signal transmission terminal, wherein the first voltage and the second voltage have opposite polarities.

[0037] In one embodiment, the corresponding levels of the first voltage and the second voltage are used as input signals, and the logic circuit function is realized by setting the levels of the first signal transmission terminal and the third signal transmission terminal.

[0038] In another aspect, embodiments of this disclosure also provide a three-dimensional memory, which includes the ferroelectric complementary switching device described above.

[0039] The ferroelectric complementary switching device provided in this disclosure can apply a voltage to the ferroelectric layer through the first and second electrodes, thereby generating an in-plane electric field within the ferroelectric layer. By changing the direction of the voltage, the direction of the in-plane electric field is changed, thereby controlling the selective separation of the first crack and the second crack. The closure and separation of the first crack achieve electrical connection and electrical insulation of the first conductive layer, and the closure and separation of the second crack achieve electrical connection and electrical insulation of the second conductive layer, thus realizing the function of the ferroelectric complementary switching device. Compared with MOSFET complementary switching devices, the ferroelectric complementary switching device of this disclosure has higher speed, lower power consumption, and smaller chip area. It also has a simple manufacturing process, is compatible with Fe-NAND technology, has low cost, and high economic benefits. Furthermore, the ferroelectric-crack based ferroelectric complementary switching device has abrupt switching behavior and a high ON / OFF current ratio. In addition, the entire first and second conductive layers serve as conductive channels. At the first and second cracks, the metal contact interface (fracture surface) of the two separated parts of the first and second conductive layers has a large contact area, resulting in low contact resistance and fast signal transmission speed. Attached Figure Description

[0040] Figure 1 This is a top view schematic diagram of the ferroelectric complementary switching device provided in the first embodiment of this disclosure;

[0041] Figure 2 It is along Figure 1 A schematic diagram of the cross-section of line C-C' shown;

[0042] Figure 3 This is another top view schematic diagram of the ferroelectric complementary switching device provided in the first embodiment of this disclosure;

[0043] Figure 4 It is along Figure 3 A schematic diagram of the cross-section of line C-C' shown;

[0044] Figure 5 These are scanning electron microscope (SEM) images of the ferroelectric complementary switching device provided in the first embodiment of this disclosure when the first electrode and the second electrode are exposed, wherein (a) is an SEM image without applied voltage, (b) is an SEM image with a first voltage applied to the first electrode and the second electrode, and (c) is an SEM image with a second voltage applied to the first electrode and the second electrode.

[0045] Figure 6A This is a top view schematic diagram of the ferroelectric complementary switching device provided in the second embodiment of this disclosure;

[0046] Figure 6B It is along Figure 6A A schematic diagram of the cross-section of line C-C' shown;

[0047] Figure 7A This is a schematic diagram of a triangular cyclic voltage;

[0048] Figure 7B This is a schematic diagram of pulse cyclic voltage;

[0049] Figure 8 This is a schematic diagram of the steps in the fabrication method of the ferroelectric complementary switching device provided in the embodiments of this disclosure;

[0050] Figures 9A-9D This is a schematic diagram of the device structure formed by the main steps of the fabrication method of the ferroelectric complementary switching device provided in the embodiments of the present invention;

[0051] Figure 10 This is a schematic diagram of a logic circuit composed of ferroelectric complementary switching devices according to an embodiment of this disclosure;

[0052] Figure 11A It is to utilize Figure 10 The truth table for the logic circuit shown to implement the buffer function;

[0053] Figure 11B It is to utilize Figure 10 The truth table for the logic circuit shown implements the NOT gate function.

[0054] Figure 11C It is to utilize Figure 10 The truth table for the logic circuit shown implements the AND gate function.

[0055] Figure 11D It is to utilize Figure 10 The truth table shown illustrates the implementation of an OR gate circuit. Detailed Implementation

[0056] To make the objectives, technical means, and effects of this disclosure clearer, the embodiments will be further described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are merely some, not all, of the embodiments of this disclosure, and are not intended to limit this disclosure. All other specific embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0057] Figure 1 and Figure 3This is a top view schematic diagram of the ferroelectric complementary switching device provided in the first embodiment of this disclosure. Figure 2 It is along Figure 1 A schematic diagram of the cross-section of line C-C' shown. Figure 4 It is along Figure 3 The diagram shows a cross-section of line C-C', where... Figure 1 This is a schematic diagram showing the separation of the first crack A1 and the closure of the second crack A2. Figure 3 This is a schematic diagram showing the separation of the first crack A1 and the closure of the second crack A2.

[0058] Please see Figures 1-4 The ferroelectric complementary switching device includes a ferroelectric layer 10, a first electrode 20, a second electrode 30, an interlayer insulating layer 40, a first conductive layer 50, a second conductive layer 60, a first signal transmission terminal 70 and a second signal transmission terminal 71, a third signal transmission terminal 80 and a fourth signal transmission terminal 81.

[0059] The first electrode 20 and the second electrode 30 are disposed on the ferroelectric layer 10 and are independent of each other, used to apply voltage to the ferroelectric layer. The interlayer insulating layer 40 is disposed on the first electrode 20 and the second electrode 30. The first conductive layer 50 is disposed on the interlayer insulating layer 40 and corresponds to the first electrode 20. The second conductive layer 50 is disposed on the interlayer insulating layer 40 and corresponds to the second electrode 30. The first signal transmission terminal 70 and the second signal transmission terminal 71 are disposed on the first conductive layer 50. The third signal transmission terminal 80 and the fourth signal transmission terminal 81 are disposed on the second conductive layer 60.

[0060] The first crack A1 originates from the ferroelectric layer 10 along a direction perpendicular to the ferroelectric layer 10 (e.g., Figure 2 The first conductive layer 50 extends (in the Z direction) and penetrates the first electrode 20, the interlayer insulating layer 40, and the first signal transmission end 70 and the second signal transmission end 71. The first conductive layer 50 is divided into two independent parts by the first crack A1. The first signal transmission end 70 and the second signal transmission end 71 are respectively disposed on the two independent parts of the first conductive layer 50 divided by the first crack A1.

[0061] The second crack A2 originates from the ferroelectric layer 10 along a direction perpendicular to the ferroelectric layer 10 (e.g., Figure 2The second conductive layer 60 extends (in the Z direction) and penetrates the second electrode 30, the interlayer insulating layer 40, and the second conductive layer 60 between the third signal transmission end 80 and the fourth signal transmission end 81, and the second conductive layer 60 is separated into two independent parts by the second crack A2. The third signal transmission end 80 and the fourth signal transmission end 81 are respectively disposed on the two independent parts of the second conductive layer 60 separated by the second crack A2.

[0062] Specifically, changing the direction of the voltage applied to the ferroelectric layer 10 allows for selective separation of the first crack A1 and the second crack A2. Selective separation of the first crack A1 and the second crack A2 means that at any given time, neither the first crack A1 nor the second crack A2 can separate simultaneously; only one can separate. Similarly, at any given time, neither the first crack A1 nor the second crack A2 can close simultaneously; only one can close.

[0063] In one embodiment of this disclosure, at least one of the first crack A1 and the second crack A2 may penetrate the ferroelectric layer 10, wherein the penetration direction may include the Z direction or the Y direction. In some embodiments of this disclosure, neither the first crack A1 nor the second crack A2 may penetrate the ferroelectric layer 10, and the penetration direction may include the Z direction or the Y direction. In particular, neither the first crack A1 nor the second crack A2 penetrates the ferroelectric layer 10 in the Y direction.

[0064] In the direction perpendicular to the ferroelectric layer 10 (e.g.) Figure 2 In the Z-direction, the first electrode 20 and the second electrode 30 are located above the ferroelectric layer 10, that is, the first electrode 20 and the second electrode 30 are disposed on the upper surface of the ferroelectric layer 10. The first electrode 20 and the second electrode 30 can be metal electrodes, such as Pt, Au, Cu, or Ag. In this embodiment, the ferroelectric layer 10 is disposed on the substrate 100, the first electrode 20 and the second electrode 30 are disposed on the upper surface of the ferroelectric layer 10, and the substrate 100 is used to support the ferroelectric complementary switching device.

[0065] The first electrode 20 and the second electrode 30 are independent of each other, meaning that the first electrode 20 and the second electrode 30 are electrically insulated from each other. In one embodiment of this disclosure, the first electrode 20 and the second electrode 30 are disposed in parallel on the surface of the ferroelectric layer 10, and there is a gap between the first electrode 20 and the second electrode 30.

[0066] Furthermore, the materials of the first electrode 20 and the second electrode 30 can be intermetallic alloys, such as MnPt or FePt. The intermetallic alloy has low ductility, allowing the first crack A1 and the second crack A2 to penetrate the first electrode 20 and the second electrode 30, and further extend and penetrate the first conductive layer 50 and the second conductive layer 60.

[0067] The interlayer insulating layer 40 is located on the first electrode 20 and the second electrode 30, that is, the interlayer insulating layer 40 is formed on the first electrode 20 and the second electrode 30. The interlayer insulating layer 40 not only electrically isolates the first electrode 20 from the first conductive layer 50 and the second electrode 30 from the second conductive layer 60, but also electrically isolates the first electrode 20 from the first signal transmission terminal 70 and the second signal transmission terminal 71, and electrically isolates the second electrode 30 from the third signal transmission terminal 80 and the fourth signal transmission terminal 81, so as to prevent the input signal of the first signal transmission terminal 70 from acting on the first electrode 20 and the input signal of the third signal transmission terminal 80 from acting on the second electrode 20, thereby disrupting the normal operation of the ferroelectric complementary switching device. The interlayer insulating layer 40 includes, but is not limited to, oxide layers, nitride layers, high-k dielectric layers, etc. For example, the oxide layer may be an aluminum oxide layer. When the ferroelectric layer 10 forms a first crack A1 and a second crack A2, the first crack A1 and the second crack A2 will also extend through the interlayer insulating layer 40, so as to extend through the first conductive layer 50 and the second conductive layer 60.

[0068] In this embodiment, the interlayer insulating layer 40 also covers the area between the first electrode 20 and the second electrode 30, that is, it covers the surface of the exposed ferroelectric layer 10 between the first electrode 20 and the second electrode 30, so as to further ensure the electrical isolation between the first electrode 20 and the second electrode 30.

[0069] The first conductive layer 50 is located on the interlayer insulating layer 40 and corresponds to the first electrode 20. That is, the first conductive layer 50 is formed on the interlayer insulating layer 40 and corresponds to the region where the first electrode 20 is located. When the ferroelectric layer 10 forms a first crack A1 in the region corresponding to the first electrode 20, the first crack A1 extends and penetrates the first conductive layer 50 to divide the first conductive layer 50 into two electrically isolated parts. The second conductive layer 60 is located on the interlayer insulating layer 40 and corresponds to the second electrode 30. That is, the second conductive layer 60 is formed on the interlayer insulating layer 40 and corresponds to the region where the second electrode 30 is located. When the ferroelectric layer 10 forms a second crack A2 in the region corresponding to the second electrode 30, the second crack A2 extends and penetrates the second conductive layer 60 to divide the second conductive layer 60 into two electrically isolated parts.

[0070] Furthermore, the materials of the first conductive layer 50 and the second conductive layer 60 can be intermetallic alloy materials, such as MnPt or FePt. The intermetallic alloy material has low ductility, which allows the first crack A1 and the second crack A2 to extend and penetrate through the first conductive layer 50 and the second conductive layer 60 when the ferroelectric layer 10 forms the first crack A1 and the second crack A2.

[0071] Furthermore, in this embodiment, the materials of the first conductive layer 50 and the second conductive layer 60 are the same as the materials of the first electrode 20 and the second electrode 30. Since the first conductive layer 50, the second conductive layer 60, and the first electrode 20 and the second electrode 30 have the same ductility, it is convenient to select an appropriate voltage to further ensure that the first crack A1 and the second crack A2 can penetrate the first conductive layer 50 and the second conductive layer 60. In other embodiments of this disclosure, the material of the first conductive layer 50 may be different from the material of the first electrode 20 but have similar ductility to further avoid the situation where the first crack A1 only penetrates the first electrode 20 but not the first conductive layer 50; similarly, the material of the second conductive layer 60 may be different from the material of the second electrode 30 but have similar ductility to further avoid the situation where the second crack A2 only penetrates the second electrode 30 but not the second conductive layer 60.

[0072] Furthermore, in one embodiment of this disclosure, the first conductive layer 50, the second conductive layer 60, the first electrode 20, and the second electrode 30 are all made of the same material to reduce differences in voltage control and avoid loss of yield of ferroelectric complementary switching devices.

[0073] In this embodiment, the first signal transmission terminal 70 serves as the first input terminal of the electrical signal of the ferroelectric complementary switching device, and the second signal transmission terminal 71 serves as the first output terminal of the electrical signal of the ferroelectric complementary switching device. In another embodiment, the first signal transmission terminal 70 serves as the first output terminal of the electrical signal of the ferroelectric complementary switching device, and the second signal transmission terminal 71 serves as the first input terminal of the electrical signal of the ferroelectric complementary switching device. The first signal transmission terminal 71 and the second signal transmission terminal 72 are connected along a first lateral direction (e.g., ...). Figure 1 Arranged in the X direction, on the surface of the first conductive layer 50, the first crack A1 is along the second transverse direction (e.g., in the X direction). Figure 1 Extending in the Y direction, the first conductive layer 50 is divided into two independent parts, the first transverse direction intersecting the second transverse direction.

[0074] In this embodiment, the third signal transmission terminal 80 serves as the second input terminal of the electrical signal of the ferroelectric complementary switching device, and the fourth signal transmission terminal 81 serves as the second output terminal of the electrical signal of the ferroelectric complementary switching device. In another embodiment, the third signal transmission terminal 80 serves as the second output terminal of the electrical signal of the ferroelectric complementary switching device, and the fourth signal transmission terminal 81 serves as the second input terminal of the electrical signal of the ferroelectric complementary switching device. The third signal transmission terminal 80 and the fourth signal transmission terminal 81 are located along a first transverse direction (e.g., ...). Figure 1 The second crack A2 is arranged in the second transverse direction (e.g., in the X direction) on the surface of the second conductive layer 60. Figure 1 Extending in the Y direction, the second conductive layer 60 is divided into two independent parts.

[0075] The first signal transmission terminal 70 and the second signal transmission terminal 71 are independent of each other and there is no direct electrical connection between them. The third signal transmission terminal 80 and the fourth signal transmission terminal 81 are independent of each other and there is no direct electrical connection between them.

[0076] Furthermore, in another embodiment, one of the signal transmission terminals on the first conductive layer 50 is electrically connected to one of the signal transmission terminals on the second conductive layer 60, constituting the signal output terminal of the ferroelectric complementary switching device. Further, to simplify layout design, the signal transmission terminal on the first conductive layer 50 constituting the signal output terminal is closer to the second conductive layer 60 relative to another signal transmission terminal on the first conductive layer 50, and the signal transmission terminal on the second conductive layer 60 constituting the signal output terminal is closer to the first conductive layer 50 relative to another signal transmission terminal on the second conductive layer 60. For example, if the second signal transmission terminal 71 on the first conductive layer 50 is closer to the second conductive layer 60 relative to the first signal transmission terminal 70 on the first conductive layer 50, and the fourth signal transmission terminal 81 on the second conductive layer 60 is closer to the first conductive layer 50 relative to the third signal transmission terminal 80 on the second conductive layer 60, then the second signal transmission terminal 71 and the fourth signal transmission terminal 81 are electrically connected, constituting the signal output terminal of the ferroelectric complementary switching device.

[0077] When the first crack A1 corresponding to the first electrode 20 closes and the second crack A2 corresponding to the second electrode 30 separates, the electrical signal that needs to be transmitted through the ferroelectric complementary switching device is input through the first signal transmission terminal 70, conducted through the first conductive layer 50, and then output through the second signal transmission terminal 71. When the first crack A1 corresponding to the first electrode 20 separates and the second crack A2 corresponding to the second electrode 30 closes, the electrical signal that needs to be transmitted through the ferroelectric complementary switching device is input through the third signal transmission terminal 80, conducted through the second conductive layer 60, and then output through the fourth signal transmission terminal 81. Due to the electrical isolation effect of the interlayer insulation layer 40, the electrical signal that needs to be transmitted through the ferroelectric complementary switching device will not be transmitted to the first electrode 20 and the second electrode 30, thereby avoiding interference with the normal operation of the ferroelectric complementary switching device.

[0078] Furthermore, the first signal transmission terminal 70, the second signal transmission terminal 71, the third signal transmission terminal 80, and the fourth signal transmission terminal 81 can be metal terminals, and their materials include, but are not limited to, Pt, Au, Cu, or Ag. In this embodiment, the materials of the first electrode 20 and the second electrode 30 are the same as the materials of the first signal transmission terminal 70, the second signal transmission terminal 71, the third signal transmission terminal 80, and the fourth signal transmission terminal 81.

[0079] Furthermore, in this embodiment, in order to ensure that the first crack A1 can divide the first conductive layer 50 into two completely broken parts, in the direction perpendicular to the ferroelectric layer 10 (e.g., Figure 2 In the Z-direction, the orthographic projection of the first electrode 20 on the ferroelectric layer 10 overlaps with the orthographic projection of the first conductive layer 50 on the ferroelectric layer 10, meaning the orthographic projection of the first conductive layer 50 on the ferroelectric layer 10 is within the range of the orthographic projection of the first electrode 20 on the ferroelectric layer 10. If the orthographic projection of the first conductive layer 50 on the ferroelectric layer 10 is outside the range of the orthographic projection of the first electrode 20 on the ferroelectric layer 10, then the first crack A1 may only penetrate a portion of the first conductive layer 50 without completely separating the first conductive layer 50 into two broken parts, thus failing to achieve electrical isolation between the first signal transmission terminal 70 and the second signal transmission terminal 71.

[0080] Furthermore, in this embodiment, in order to ensure that the second crack A2 can divide the second conductive layer 60 into two completely broken parts, in the direction perpendicular to the ferroelectric layer 10 (e.g., Figure 2In the Z-direction, the orthographic projection of the second electrode 30 on the ferroelectric layer 10 overlaps with the orthographic projection of the second conductive layer 60 on the ferroelectric layer 10, meaning the orthographic projection of the second conductive layer 60 on the ferroelectric layer 10 is within the range of the orthographic projection of the second electrode 30 on the ferroelectric layer 10. If the orthographic projection of the second conductive layer 60 on the ferroelectric layer 10 is outside the range of the orthographic projection of the second electrode 30 on the ferroelectric layer 10, then the second crack A2 may only penetrate a portion of the second conductive layer 60 without completely separating the second conductive layer 60 into two broken parts, thus failing to achieve electrical isolation between the third signal transmission terminal 80 and the fourth signal transmission terminal 81.

[0081] Furthermore, in this embodiment, the interlayer insulating layer 40 covers a portion of the surfaces of the first electrode 20 and the second electrode 30, meaning that the interlayer insulating layer 40 does not cover the entire surfaces of the first electrode 20 and the second electrode 30. Therefore, the surfaces of the first electrode 20 and the second electrode 30 not covered by the interlayer insulating layer 40 can serve as electrical connection surfaces. For example, in some embodiments of this disclosure, a first conductive terminal 22 is provided on the surface of the first electrode 20 not covered by the interlayer insulating layer 40. The first conductive terminal 22 is connected to a voltage process circuit, and the voltage process circuit applies a potential to the first electrode 20 through the first conductive terminal 22. A second conductive terminal 32 is provided on the surface of the second electrode 30 not covered by the interlayer insulating layer 40. The second conductive terminal 32 is connected to a voltage process circuit, and the voltage process circuit applies a potential to the second electrode 30 through the second conductive terminal 32. In other embodiments of this disclosure, the first conductive terminal 22 and the second conductive terminal 32 may not be provided; instead, the voltage process circuit may be directly connected to the surfaces of the first electrode 20 and the second electrode 30 not covered by the interlayer insulating layer 40.

[0082] Figure 5These are scanning electron microscope (SEM) images of the ferroelectric complementary switching device provided in the first embodiment of this disclosure when the first electrode and the second electrode are exposed. (a) is an SEM image without applied voltage; (b) is an SEM image with a first voltage applied to the first electrode 20 and the second electrode 30 using a probe; and (c) is an SEM image with a second voltage applied to the first electrode 20 and the second electrode 30 using a probe. As can be seen from Figures (a) to (c), when no voltage is applied to the first electrode 20 and the second electrode 30, no cracks are formed on either electrode. When the first voltage is applied, a crack forms on the first electrode 20 (as indicated by arrow Crack-1 in the figure), but no crack forms on the second electrode 30. When the second voltage is applied, a crack forms on the second electrode 30 (as indicated by arrow Crack-2 in the figure), but no crack forms on the first electrode 20. Therefore, the ferroelectric complementary switching device provided in this public embodiment can achieve the function of complementary switching and has high reliability.

[0083] In the first embodiment, the interlayer insulation layer 40 is a continuous layer, while in other embodiments of this disclosure, the interlayer insulation layer may also be a discontinuous layer. For example, please refer to... Figure 6A and Figure 6B ,in, Figure 6A This is a top view schematic diagram of the ferroelectric complementary switching device provided in the second embodiment of this disclosure. Figure 6B It is along Figure 6A The cross-sectional schematic diagram of the C-C' line shown is illustrated in the second embodiment of this disclosure. The interlayer insulation layer includes a first insulating layer 40A and a second insulating layer 40B. The first insulating layer 40A and the second insulating layer 40B are independent of each other, meaning they are not connected. The first insulating layer 40A is disposed on the first electrode 20, and the first conductive layer 50 is disposed on the first insulating layer 40A. The first insulating layer 40A is used to electrically isolate the first electrode 20 from the first conductive layer 50 and from the first signal transmission terminal 70 and the second signal transmission terminal 71. The second insulating layer 40B is disposed on the second electrode 30, and the second conductive layer 60 is disposed on the second insulating layer 40B. The second insulating layer 40B is used to electrically isolate the second electrode 30 from the second conductive layer 60 and from the third signal transmission terminal 80 and the fourth signal transmission terminal 81.

[0084] This disclosure also provides a control method for a ferroelectric complementary switching device. The control method includes: applying a first voltage to the ferroelectric layer via the first and second electrodes to control the closure of the first crack and the separation of the second crack, thereby achieving electrical conduction between the first and second signal transmission terminals and electrical insulation between the third and fourth signal transmission terminals; applying a second voltage to the ferroelectric layer via the first and second electrodes to control the separation of the first crack and the closure of the second crack, thereby achieving electrical insulation between the first and second signal transmission terminals and electrical conduction between the third and fourth signal transmission terminals, wherein the first voltage and the second voltage have opposite polarities.

[0085] For example, please refer to Figure 1 and Figure 2 When a first voltage U1 is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30, the first crack A1 changes from a closed state to a separated state, and the second crack A2 changes from a separated state to a closed state. Then, the first signal transmission terminal 70 and the second signal transmission terminal 71 are electrically insulated, and the second input terminal 80 and the fourth signal transmission terminal 81 are electrically connected. The signal received by the third signal transmission terminal 80 is output through the fourth signal transmission terminal 81.

[0086] Please see Figure 3 and Figure 4 When a second voltage U2 is applied to the ferroelectric layer through the first electrode 20 and the second electrode 30, the first crack A1 changes from a separated state to a closed state, and the second crack A2 changes from a closed state to a separated state. Then, the first signal transmission terminal 70 and the second signal transmission terminal 71 are electrically connected, and the second input terminal 80 and the fourth signal transmission terminal 81 are electrically insulated. The signal received by the first signal transmission terminal 70 is output through the second signal transmission terminal 71.

[0087] Wherein, the first voltage U1 and the second voltage U2 have opposite polarities, that is, the first voltage U1 is a positive voltage and the second voltage U2 is a negative voltage, or the first voltage U1 is a negative voltage and the second voltage U2 is a positive voltage. For example, in this embodiment, the first voltage U1 is in the direction from the first electrode 20 to the second electrode 30 (e.g., Figure 1 The first voltage U1 is a positive voltage in the X direction, and the second voltage U2 is a negative voltage in the direction from the first electrode 20 to the second electrode 30. In other embodiments, the first voltage U1 is a negative voltage in the direction from the first electrode 20 to the second electrode 30, and the second voltage U2 is a positive voltage in the direction from the first electrode 20 to the second electrode 30.

[0088] For the ferroelectric layer 10, its ferroelectric domains have polarization directions. When the direction of the electric field formed by the voltage applied to the ferroelectric layer 10 is opposite to the polarization direction of the ferroelectric domains, the ferroelectric domains in the ferroelectric layer 10 will flip. Due to the pinning effect of defects and dopants in the ferroelectric layer 10 on the domain walls, stress will be generated on the ferroelectric domain walls. Cracks will separate at the stress concentration points. When the direction of the electric field formed by the voltage applied to the ferroelectric layer 10 is the same as the polarization direction of the ferroelectric domains, the stress will dissipate and the cracks will close. Therefore, in this embodiment of the present disclosure, a voltage is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30. The voltage forms an in-plane electric field within the ferroelectric layer 10. Below the first electrode 20 and below the second electrode 30, the directions of the electric field components along the direction perpendicular to the ferroelectric layer 10 are exactly opposite, and the polarization direction of the ferroelectric domains in the ferroelectric layer 10 is the same as the direction of one of the electric field components. This causes the cracks in the ferroelectric layer region where the direction of the electric field component is opposite to the polarization direction of the ferroelectric domain to separate, while the cracks in the ferroelectric layer region where the direction of the electric field component is the same as the polarization direction of the ferroelectric domain to close. Therefore, this embodiment of the present disclosure can achieve the function of the ferroelectric complementary switching device by changing the polarity of the voltage applied to the ferroelectric layer, which allows the cracks in different regions of the ferroelectric layer to separate selectively.

[0089] For example, such as Figure 2 As shown, the polarization direction of the ferroelectric domains in the ferroelectric layer 10 points towards the upper surface of the ferroelectric layer 10 (e.g., ...). Figure 2 In the Z-direction, when a first voltage U1 is applied to the ferroelectric layer 10 via the first electrode 20 and the second electrode 30, the in-plane electric field E1 formed by the first voltage U1 in the ferroelectric layer 10 below the first electrode 20 has an electric field component E1 in the Z-direction. Z1 Pointing to the lower surface of the ferroelectric layer 10, below the second electrode 30, the in-plane electric field E1 in the Z direction is the electric field component E1. Z2 The electric field component E1 points towards the upper surface of the ferroelectric layer 10. Z1 The direction is opposite to the polarization direction of the ferroelectric domains in ferroelectric layer 10, and the electric field component E1 Z2 If the direction is the same as the polarization direction D of the ferroelectric domains of the ferroelectric layer 10, then the first crack A1 changes from a closed state to a separated state, and the second crack A2 changes from a separated state to a closed state.

[0090] For example, such as Figure 4 As shown, the polarization direction of the ferroelectric domains in the ferroelectric layer 10 points towards the upper surface of the ferroelectric layer 10 (e.g., ...). Figure 4 In the Z-direction, when the voltage applied to the ferroelectric layer 10 via the first electrode 20 and the second electrode 30 changes from a first voltage U1 to a second voltage U2 with opposite polarity, the in-plane electric field E2 formed by the second voltage U2 within the ferroelectric layer 10 below the first electrode 20 will have an electric field component E2 in the Z-direction. Z1Pointing to the upper surface of the ferroelectric layer 10, below the second electrode 30, the in-plane electric field E2 in the Z direction is the electric field component E2. Z2 The electric field component E2 points towards the lower surface of ferroelectric layer 10. Z1 The direction is the same as the polarization direction D of the ferroelectric domains of ferroelectric layer 10, and the electric field component E2 Z2 If the direction of the crack A1 is opposite to the polarization direction D of the ferroelectric domains of the ferroelectric layer 10, then the first crack A1 changes from a separated state to a closed state, and the second crack A2 changes from a closed state to a separated state.

[0091] It is understood that in other embodiments of this disclosure, the polarization direction of the ferroelectric domains of the ferroelectric layer 10 may also point to the lower surface of the ferroelectric layer 10, in which case the separation state and the closure state of the first crack A1 and the second crack A2 are interchanged.

[0092] The first crack A1 can originate from the ferroelectric layer 10 along a direction perpendicular to the ferroelectric layer 10 (e.g., Figure 2 The conductive layer 50 extends (in the Z direction) and penetrates the first electrode 20, the interlayer insulating layer 40, and the first signal transmission terminal 70 and the second signal transmission terminal 71, and is divided into two independent parts by the first crack A1. When the first crack A1 is in a separated state, the two parts of the first conductive layer 50 are separated and not connected, thereby achieving electrical insulation between the first signal transmission terminal 70 and the second signal transmission terminal 71; when the first crack A1 is in a closed state, the two parts of the first conductive layer 50 are in contact and connected, thereby achieving electrical conduction between the first signal transmission terminal 70 and the second signal transmission terminal 71.

[0093] The second crack A2 originates from the ferroelectric layer 10 along a direction perpendicular to the ferroelectric layer 10 (e.g., Figure 4 The second conductive layer 60 extends (in the Z direction) and penetrates the second electrode 30, the interlayer insulating layer 40, and the second conductive layer 60 between the third signal transmission end 80 and the fourth signal transmission end 81, and the second conductive layer 60 is separated into two independent parts by the second crack A2. When the second crack A2 is in a separated state, the two parts of the second conductive layer 60 are separated and not connected, and the third signal transmission end 80 and the fourth signal transmission end 81 cannot be electrically connected through the second conductive layer 60, thereby disconnecting the signal transmission between the third signal transmission end 80 and the fourth signal transmission end 81; when the second crack A2 is in a closed state, the two parts of the second conductive layer 60 are in contact and connected, and the third signal transmission end 80 and the fourth signal transmission end 81 can be electrically connected through the second conductive layer 60, thereby enabling the third signal transmission end 80 and the fourth signal transmission end 81 to transmit signals.

[0094] It should be noted that after a crack is generated in the region corresponding to the first electrode 20 or the second electrode 30, the ferroelectric layer 10 will not generate a second crack in the corresponding region due to stress release. Therefore, there will be no situation where multiple cracks are generated in the region corresponding to the same electrode.

[0095] In some embodiments, a cyclic voltage can be applied to the ferroelectric layer 10 via the first electrode 20 and the second electrode 30 to control the separation and closure of the first crack and the second crack, for example, a triangular cyclic voltage and a pulse voltage. Figure 7A This is a schematic diagram of a triangular cyclic voltage, where the forward voltage of the triangular cyclic voltage reaches a certain value, for example, the peak value U. 峰 Ferroelectric domains flip, generating stress. The first crack A1 separates, and the second crack A2 closes. When the negative voltage of the triangular cyclic voltage reaches a certain value, such as the valley value U... 谷 The ferroelectric domains are flipped again, the first crack A1 closes, and the second crack A2 separates. Figure 7B This is a schematic diagram of a pulsed cyclic voltage, which represents a periodic commutation pulse. When the positive pulse voltage U... 正 When a certain value is reached, the ferroelectric domains flip, generating stress. The first crack A1 separates, and the second crack A2 closes. When the negative pulse voltage U... 负 When a certain value is reached, the ferroelectric domains are flipped again, the first crack A1 closes, and the second crack A2 separates.

[0096] The ferroelectric complementary switching device control method provided in this disclosure utilizes the selective separation of the first and second cracks to achieve the function of the ferroelectric complementary switching device. Compared with metal-oxide-semiconductor field-effect transistor (MOSFET) complementary switches, it has higher speed, lower power consumption, and smaller chip area. Furthermore, the manufacturing process is simple, compatible with Fe-NAND flash memory technology, and has low cost and high economic benefits. Moreover, the ferroelectric complementary switching device based on ferroelectric-nanocracks exhibits abrupt switching behavior and a high ON / OFF current ratio. Additionally, the entire first conductive layer 50 and second conductive layer 60 serve as conductive channels. At the first and second cracks, the metal contact interface (fracture surface) of the separated parts of the first conductive layer 50 and second conductive layer 60 has a large contact area, resulting in low contact resistance and fast signal transmission speed.

[0097] This disclosure also provides a method for preparing the above-mentioned ferroelectric complementary switching device. Figure 8 This is a schematic diagram illustrating the steps of the fabrication method of the ferroelectric complementary switching device provided in this embodiment. Please refer to [link / reference]. Figure 8The preparation method includes: step S801, providing a substrate; step S802, sequentially forming a ferroelectric layer, a first electrode, a second electrode, an interlayer insulating layer, a first conductive layer, a second conductive layer, a first signal transmission terminal, a second signal transmission terminal, a third signal transmission terminal, and a fourth signal transmission terminal on the surface of the substrate, wherein the first conductive layer corresponds to the first electrode, the second conductive layer corresponds to the second electrode, the first signal transmission terminal and the second signal transmission terminal are disposed on the first conductive layer, and the third signal transmission terminal and the fourth signal transmission terminal are disposed on the second conductive layer; step S803, forming a first crack and a second crack, wherein the first crack extends from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrates the second electrode, the interlayer insulating layer, and the first signal transmission terminal and the second electrode, the third signal transmission terminal, and the fourth signal transmission terminal on the surface of the substrate, respectively. The first conductive layer between the two signal transmission terminals, and the first crack does not penetrate the ferroelectric layer, the first conductive layer is divided into two independent parts by the first crack, the first signal transmission terminal and the second signal transmission terminal are respectively disposed on the two independent parts of the first conductive layer divided by the first crack; the second crack extends from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrates the second electrode, the interlayer insulating layer, and the second conductive layer between the third signal transmission terminal and the fourth signal transmission terminal, and the second crack does not penetrate the ferroelectric layer, the second conductive layer is divided into two independent parts by the second crack, the third signal transmission terminal and the fourth signal transmission terminal are respectively disposed on the two independent parts of the second conductive layer divided by the second crack.

[0098] Figures 9A-9D This is a schematic diagram of the device structure formed by the main steps of the fabrication method of the ferroelectric complementary switching device provided in the embodiment of the present invention.

[0099] Please refer to step S801 and Figure 9A Substrate 100 is provided.

[0100] The substrate 100 can be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon on Insulator) substrate, or a GOI (Germanium on Insulator) substrate, etc. In this embodiment, the substrate 100 is preferably a Si substrate, used to support the device structure thereon.

[0101] Please refer to step S802 and Figure 9BA ferroelectric layer 10, a first electrode 20, a second electrode 30, an interlayer insulating layer 4, a first conductive layer 50, a second conductive layer 60, and a first signal transmission terminal 70, a second signal transmission terminal 71, a third signal transmission terminal 80, and a fourth signal transmission terminal 81 are sequentially formed on the surface of the substrate 100. The first conductive layer 50 corresponds to the first electrode 20, the second conductive layer 60 corresponds to the second electrode 30, the first signal transmission terminal 70 and the second signal transmission terminal 71 are disposed on the first conductive layer 50, and the third signal transmission terminal 80 and the fourth signal transmission terminal 81 are disposed on the second conductive layer 60.

[0102] In one embodiment, a ferroelectric material layer can be formed on the surface of substrate 100 using processes such as chemical vapor deposition, atomic layer deposition, pulsed laser deposition, and molecular beam epitaxy. The ferroelectric material layer is then patterned using photolithography and etching processes to form the ferroelectric layer 10. In this embodiment, the material of the ferroelectric layer 10 is HfZrOx, which is suitable for hafnium-based complementary metal-oxide-semiconductor (CMOS) compatible ferroelectric NAND (Fe-NAND) flash memory, simplifying the fabrication process. In other embodiments of this disclosure, the material of the ferroelectric layer 10 can also be lead magnesium niobate-lead titanate (PMN-PT), lead zirconate titanate (PZT), lead indium niobate-lead titanate (PIN-PT), lead magnesium niobate-lead zirconate titanate-lead titanate (PMN-PZT-PT), BaTiO3 (BTO), etc.

[0103] In one embodiment, an electrode material layer can be formed on the surface of the ferroelectric layer 10 using processes such as chemical vapor deposition, atomic layer deposition, pulsed laser deposition, and molecular beam epitaxy. The electrode material layer is then patterned using photolithography and etching processes to form a first electrode 20 and a second electrode 30. The materials of the first electrode 20 and the second electrode 30 can be intermetallic alloys, such as MnPt or FePt.

[0104] In one embodiment, interlayer insulating material layers can be formed on the first electrode 20 and the second electrode 30 using processes such as chemical vapor deposition, atomic layer deposition, pulsed laser deposition, and molecular beam epitaxy. Then, the interlayer insulating material layer is patterned using photolithography and etching processes to form an interlayer insulating layer 40. In this embodiment, the interlayer insulating layer 40 may cover not only the first electrode 20 and the second electrode 30, but also the exposed surface of the ferroelectric layer 10. The interlayer insulating layer 40 includes, but is not limited to, oxide layers, nitride layers, and high-k dielectric layers; for example, the oxide layer may be an aluminum oxide layer.

[0105] In one embodiment, a conductive material layer can be formed on the interlayer insulating layer 40 using processes such as chemical vapor deposition, atomic layer deposition, pulsed laser deposition, and molecular beam epitaxy. Then, the conductive material layer is patterned using photolithography and etching processes to form a first conductive layer 50 and a second conductive layer 60. The materials of the first conductive layer 50 and the second conductive layer 60 can be intermetallic alloys, such as MnPt or FePt. The ductility of the first conductive layer 50 and the second conductive layer 60 is the same as or similar to that of the first electrode 20 and the second electrode 30. Further, in this embodiment, the materials of the first conductive layer 50 and the second conductive layer 60 are the same as those of the first electrode 20 and the second electrode 30. In other embodiments of this disclosure, the materials of the first conductive layer 50 and the second conductive layer 60 may be different from those of the first electrode 20 and the second electrode 30 but have similar ductility.

[0106] Signal transmission material layers can be formed on the first conductive layer 50 and the second conductive layer 60 using processes such as chemical vapor deposition, atomic layer deposition, pulsed laser deposition, and molecular beam epitaxy. Then, the signal transmission material layers are patterned using processes such as photolithography and etching to form a first signal transmission terminal 70, a second signal transmission terminal 71, a third signal transmission terminal 80, and a fourth signal transmission terminal 81. The first signal transmission terminal 70 and the second signal transmission terminal 71 are independent of each other and are not directly connected. The third signal transmission terminal 80 and the fourth signal transmission terminal 81 are also independent of each other and are not directly connected.

[0107] Please refer to step S802. Figure 9C and Figure 9D This forms the first crack A1 and the second crack A2.

[0108] The first crack A1 extends from the ferroelectric layer 10 in a direction perpendicular to the ferroelectric layer 10 (as shown by the Z direction in the figure) and penetrates the first electrode 20, the interlayer insulating layer 40, and the first conductive layer 50 between the first signal transmission terminal 70 and the second signal transmission terminal 71. The first conductive layer 50 is divided into two independent parts by the first crack A1. The first signal transmission terminal 70 and the second signal transmission terminal 71 are respectively disposed on the two independent parts of the first conductive layer 50 divided by the first crack A1.

[0109] The second crack A2 extends from the ferroelectric layer 10 in a direction perpendicular to the ferroelectric layer 10 (as shown by the Z direction in the figure) and penetrates the second electrode 30, the interlayer insulating layer 40, and the second conductive layer 60 between the third signal transmission terminal 80 and the fourth signal transmission terminal 81. The second conductive layer 60 is divided into two independent parts by the second crack A2. The third signal transmission terminal 80 and the fourth signal transmission terminal 81 are respectively disposed on the two independent parts of the second conductive layer 60 divided by the second crack A2.

[0110] In one embodiment of this disclosure, at least one of the first crack A1 and the second crack A2 may penetrate the ferroelectric layer 10, wherein the penetration direction may include the Z direction or the Y direction. In some embodiments of this disclosure, neither the first crack A1 nor the second crack A2 may penetrate the ferroelectric layer 10, and the penetration direction may include the Z direction or the Y direction. In particular, neither the first crack A1 nor the second crack A2 penetrates the ferroelectric layer 10 in the Y direction.

[0111] This disclosure also provides a method for forming the crack. Prior to forming the first crack A1 and the second crack A2, the ferroelectric layer has a defined ferroelectric domain polarization direction. The method for forming the crack includes the following steps: Please refer to... Figure 9C A first flip voltage U11 is applied to the ferroelectric layer 10 via the first electrode 20 and the second electrode 30, forming the first crack A1. (See also...) Figure 9D A second reversal voltage U22 is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30 to form the second crack A2. The second reversal voltage U11 has the opposite polarity to the first reversal voltage U22.

[0112] For the ferroelectric layer 10, its ferroelectric domains have polarization directions. When the direction of the electric field formed by the voltage applied to the ferroelectric layer 10 is opposite to the polarization direction of the ferroelectric domains, the ferroelectric domains in the ferroelectric layer 10 will flip. Due to the pinning effect of defects and dopants in the ferroelectric layer 10 on the domain walls, stress will be generated on the ferroelectric domain walls, and cracks will be formed at the stress concentration points.

[0113] In this disclosed embodiment, please continue to refer to Figure 9C A first switching voltage U11 is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30. The first switching voltage U11 forms an in-plane electric field E1 within the ferroelectric layer 10. Below the first electrode 20 and below the second electrode 30, the directions of the electric field components of this in-plane electric field along the direction perpendicular to the ferroelectric layer 10 are exactly opposite. For example, below the first electrode 20, the electric field component E1 of the in-plane electric field along the direction perpendicular to the ferroelectric layer 10 is... Z1The direction of the electric field in the plane below the second electrode 30 along the direction perpendicular to the ferroelectric layer 10 is E1. Z2 The directions are opposite. The polarization direction of the ferroelectric domains in the ferroelectric layer 10 is the same as the direction of one of the electric field components and opposite to the direction of the other. For example, the polarization direction of the ferroelectric domains in the ferroelectric layer 10 (which is in the same direction as the Z direction in the figure) is opposite to the electric field component E1 of the in-plane electric field below the second electrode 30 along the direction perpendicular to the ferroelectric layer 10. Z2 The direction is the same as that of the electric field component E1 in the plane below the first electrode 20 along the direction perpendicular to the ferroelectric layer 10. Z1 If the direction is opposite, the ferroelectric domains in the ferroelectric layer 10 will flip below the first electrode 20, generating stress on the ferroelectric domain walls, and the first crack A1 will form at the stress concentration point.

[0114] In this embodiment, a second switching voltage U22 is applied to the ferroelectric layer 10 via the first electrode 20 and the second electrode 30. The second switching voltage U22 forms an in-plane electric field within the ferroelectric layer 10. Below the first electrode 20 and below the second electrode 30, the directions of the electric field components of this in-plane electric field along the direction perpendicular to the ferroelectric layer 10 are exactly opposite. For example, below the first electrode 20, the electric field component E2 along the direction perpendicular to the ferroelectric layer 10 is... Z1 The direction is the same as the electric field component E2 of the in-plane electric field below the second electrode 30 along the direction perpendicular to the ferroelectric layer 10. Z2 The directions are opposite. The polarization direction of the ferroelectric domains in the ferroelectric layer 10 is the same as the direction of one of the electric field components and opposite to the direction of the other. For example, the polarization direction of the ferroelectric domains in the ferroelectric layer 10 (which is in the same direction as the Z direction in the figure) is opposite to the electric field component E2 of the in-plane electric field below the first electrode 20 along the direction perpendicular to the ferroelectric layer 10. Z1 The direction is the same as that of the electric field component E2 in the plane below the second electrode 30 along the direction perpendicular to the ferroelectric layer 10. Z2 If the direction is opposite, then below the second electrode 30, the ferroelectric domains in the ferroelectric layer 10 will flip, generating stress on the ferroelectric domain walls. Then, a second crack A2 will be formed at the stress concentration point. However, below the first electrode 20, affected by the change in the direction of the electric field, the stress in the ferroelectric layer dissipates, and the already formed first crack A1 closes.

[0115] In the above example, the polarization direction D of the ferroelectric domains of the ferroelectric layer 10 points to the lower surface of the ferroelectric layer 10. It can be understood that in other embodiments of this disclosure, the polarization direction D of the ferroelectric domains of the ferroelectric layer 10 may also point to the lower surface of the ferroelectric layer 10, in which case the order of formation of the first crack A1 and the second crack A2 is interchanged.

[0116] This disclosure also provides a method for forming the predetermined ferroelectric domain polarization direction. The method includes: before forming the first crack A1 and the second crack A2, applying a polarization voltage to the ferroelectric layer 10, such that the ferroelectric domain polarization direction of the ferroelectric layer is in the same direction as the polarization voltage, thereby forming the predetermined ferroelectric domain polarization direction D. The polarization voltage forms a vertical electric field within the ferroelectric layer 10 to form ferroelectric domain polarization directions D with the same direction within the ferroelectric layer.

[0117] For the ferroelectric layer 10, when no polarization voltage is applied, i.e., when no external electric field is applied, the ferroelectric domains are randomly distributed in the ferroelectric layer 10. However, when a polarization voltage is applied, i.e., when an external electric field is applied, the ferroelectric domains along the direction of the electric field grow, the ferroelectric domains against the direction of the electric field disappear, and the ferroelectric domains distributed in other directions rotate to the direction of the electric field, eventually forming ferroelectric domains consistent with the direction of the electric field, i.e., forming the predetermined ferroelectric domain polarization direction. In some embodiments, the electric field strength generated by the polarization voltage is greater than the coercive field of the ferroelectric domains to further ensure that ferroelectric domains with polarization directions consistent with the direction of the electric field can be formed.

[0118] The preparation method provided in this disclosure can prepare ferroelectric complementary switching devices with complementary switching functions. The manufacturing process is simple, compatible with Fe-NAND technology, low in cost, and economically beneficial.

[0119] This disclosure also provides a three-dimensional memory. The three-dimensional memory includes the ferroelectric complementary switching device described above. The ferroelectric complementary switching device can replace the CMOS complementary switching device in the three-dimensional memory. The application of the ferroelectric complementary switching device in the three-dimensional memory is illustrated below.

[0120] In some embodiments of this disclosure, the three-dimensional memory utilizes the ferroelectric complementary switching device to implement logic circuit functions.

[0121] For example, Figure 10 This is a schematic diagram of a logic circuit composed of ferroelectric complementary switching devices according to an embodiment of this disclosure. Please also refer to... Figure 1 and Figure 4The voltage levels applied to the first electrode 20 and the second electrode 30 are used as input signals, input from the input terminal IN. The second signal transmission terminal 71 and the fourth signal transmission terminal 81 are used together as the output terminal OUT. The first signal transmission terminal 70 is used as the first control signal input terminal D1, and the third signal transmission terminal 80 is used as the second control signal input terminal D2. The logic circuit function can be achieved by setting the levels of the first control signal input terminal D1 and the second control signal input terminal D2. The voltage supply circuit, controlled by the input signals to be input to the logic circuit, applies a first voltage and a second voltage to the first electrode 20 and the second electrode 30, achieving selective separation of the first crack and the second crack, thereby realizing the logic circuit function. For example, when the input signal to the logic circuit is low, the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30 under the control of the input signal to the logic circuit; when the input signal to the logic circuit is high, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30 under the control of the input signal to the logic circuit, thereby achieving selective separation of the first crack and the second crack; or, when the input signal to the logic circuit is high, the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30 under the control of the input signal to the logic circuit; when the input signal to the logic circuit is low, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30 under the control of the input signal to the logic circuit, thereby achieving selective separation of the first crack and the second crack.

[0122] Figure 11A It is to utilize Figure 10 Please refer to the truth table for the logic circuit shown that implements the buffer function. Figure 10 and Figure 11AThe first signal transmission terminal is connected to a low level, and the third signal transmission terminal is connected to a high level. That is, the true value of the input signal at the first control signal input terminal D1 is "0", and the true value of the input signal at the second control signal input terminal D2 is "1". When the input signal to be input to the logic circuit is low and its true value is "0", the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30, the first crack closes, the second crack separates, and the true value of the input signal at the input terminal IN is "0". Then the first signal transmission terminal and the second signal transmission terminal are connected, and the true value of the output signal at the output terminal OUT is "0". When the input signal to be input to the logic circuit is high and its true value is "1", the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30, the first crack separates, the second crack closes, and the true value of the input signal at the input terminal IN is "1". Then the third signal transmission terminal and the fourth signal transmission terminal are connected, and the true value of the output signal at the output terminal OUT is "1", thus realizing the function of the buffer circuit.

[0123] It is understood that, in another embodiment, when the input signal to be input to the logic circuit is low, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30; when the input signal to be input to the logic circuit is high, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30. In order to realize the function of the buffer circuit, the first signal transmission terminal is connected to the high level, and the third signal transmission terminal is connected to the low level.

[0124] Figure 11B It is to utilize Figure 10 Please refer to the truth table for the logic circuit shown that implements the NOT gate function. Figure 10 and Figure 11BThe first signal transmission terminal is connected to a high level, and the third signal transmission terminal is connected to a low level. That is, the true value of the input signal at the first control signal input terminal D1 is "1", and the true value of the input signal at the second control signal input terminal D2 is "0". When the input signal to be input to the logic circuit is low and its true value is "0", the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30, the first crack closes, the second crack separates, and the true value of the input signal at the input terminal IN is "0". Then the first signal transmission terminal and the second signal transmission terminal are connected, and the true value of the output signal at the output terminal OUT is "1". When the input signal to be input to the logic circuit is high and its true value is "1", the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30, the first crack separates, the second crack closes, and the true value of the input signal at the input terminal IN is "1". Then the third signal transmission terminal and the fourth signal transmission terminal are connected, and the true value of the output signal at the output terminal OUT is "0". The input signal to the logic circuit is output after being logically "NOT", realizing the function of the NOT gate circuit.

[0125] It is understood that, in another embodiment, when the input signal to be input to the logic circuit is low, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30; when the input signal to be input to the logic circuit is high, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30. In order to realize the function of the NOT gate circuit, the first signal transmission terminal is connected to the low level, and the third signal transmission terminal is connected to the high level.

[0126] Figure 11C It is to utilize Figure 10 Please refer to the truth table for the logic circuit shown that implements the AND gate function. Figure 10 and Figure 11CThe first signal transmission terminal is connected to a low level, and the third signal transmission terminal is connected to either a high level or a low level. That is, the true value of the input signal at the first control signal input terminal D1 is "0", and the true value of the input signal at the second control signal input terminal D2 is either "0" or "1". When the input signal to the logic circuit is low and its true value is "0", the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30. The first crack closes, the second crack separates, and the true value of the input signal at the input terminal IN is "0". Then, the first signal transmission terminal and the second signal transmission terminal are connected. Regardless of whether the true value of the input signal at the second control signal input terminal D2 is "0" or "1", the true value of the output signal at the output terminal OUT is always "0". When the input signal to the logic circuit is high and its true value is "1", the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30. A second voltage is applied to electrode 20 and the second electrode 30. The first crack separates and the second crack closes. The true value of the input signal at the input terminal IN is "1". Then the third signal transmission terminal and the fourth signal transmission terminal are connected. If the true value of the input signal at the second control signal input terminal D2 is "0", then the true value of the output signal at the output terminal OUT is "0". If the true value of the input signal at the second control signal input terminal D2 is "1", then the true value of the output signal at the output terminal OUT is "1". The input signal to the logic circuit and the input signal at the second control signal input terminal D2 are logically ANDed and then output to realize the AND gate circuit function.

[0127] It is understood that, in another embodiment, when the input signal to be input to the logic circuit is low, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30; when the input signal to be input to the logic circuit is high, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30. The first signal transmission terminal is connected to either a high or low level, and the third signal transmission terminal is connected to a low level. The input signal to the logic circuit and the input signal of the first control signal input terminal D1 are logically ANDed and then output to realize the AND gate circuit function.

[0128] Figure 11D It is to utilize Figure 10 Please refer to the truth table for the logic circuit that implements the OR gate function. Figure 10 and Figure 11DThe third signal transmission terminal is connected to a high level, and the first signal transmission terminal is connected to either a high or low level. That is, the true value of the input signal at the second control signal input terminal D2 is "1", and the true value of the input signal at the first control signal input terminal D1 is either "0" or "1". When the input signal to be input to the logic circuit is low (true value "0"), the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30. The first crack closes, the second crack separates, and the true value of the input signal at the input terminal IN is "0". Then, the first signal transmission terminal and the second signal transmission terminal are connected. If the true value of the input signal at the first control signal input terminal D1 is "0", then the true value of the output signal at the output terminal OUT is "0". If the true value of the input signal at the first control signal input terminal D1 is "1", then the true value of the output signal at the output terminal OUT is "1". When the input signal to the logic circuit is low (true value "0"), the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30. The first crack closes, the second crack separates, and the true value of the input signal at the input terminal IN is "0". Therefore, the first signal transmission terminal and the second signal transmission terminal are connected. When the input signal to the logic circuit is low (true value "0"), the voltage supply circuit applies a first voltage to the first electrode 20 and the second electrode 30. The first crack closes, the second crack separates, and the true value of the input signal at the input terminal IN is "0". When the input signal to the logic circuit is low (true value "0"), the first signal transmission terminal D1 is connected to a high level ... When the input signal of the logic circuit is high and its true value is "1", the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30. The first crack separates and the second crack closes. When the true value of the input signal of the input terminal IN is "1", the third signal transmission terminal and the fourth signal transmission terminal are connected. Regardless of whether the true value of the input signal of the first control signal input terminal D1 is "0" or "1", the true value of the output signal of the output terminal OUT is "1". The input signal to the logic circuit and the input signal of the first control signal input terminal D1 are logically ORed and then output to realize the OR gate circuit function.

[0129] It is understood that, in another embodiment, when the input signal to be input to the logic circuit is low, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30. When the input signal to be input to the logic circuit is high, the voltage supply circuit applies a second voltage to the first electrode 20 and the second electrode 30. The first signal transmission terminal is connected to the high level, and the third signal transmission terminal is connected to the low level or the high level. The input signal to the logic circuit and the input signal of the second control signal input terminal D2 are logically ORed and then output to realize the OR gate circuit function.

[0130] The three-dimensional memory includes a storage array region and a peripheral circuit region. The storage array region is used to store information, while the peripheral circuit region can be located above, below, or around the storage array region. The peripheral circuit region is used to control the corresponding storage array region. The ferroelectric complementary switching device can be disposed in the peripheral circuit region.

[0131] The ferroelectric complementary switching device can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), and there are no specific limitations.

[0132] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A ferroelectric complementary switching device, characterized by, The application relates to a ferroelectric memory device, comprising: a ferroelectric layer; a first electrode and a second electrode disposed on the ferroelectric layer and independent of each other, for applying a voltage to the ferroelectric layer; an interlayer insulating layer disposed on the first electrode and the second electrode; a first conductive layer disposed on the interlayer insulating layer and corresponding to the first electrode; a second conductive layer disposed on the interlayer insulating layer and corresponding to the second electrode; a first signal transmission end and a second signal transmission end disposed on the first conductive layer; a third signal transmission end and a fourth signal transmission end disposed on the second conductive layer; a first crack extending from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrating through the first electrode, the interlayer insulating layer and the first conductive layer between the first signal transmission end and the second signal transmission end, the first conductive layer being divided into two parts independent of each other by the first crack, the first signal transmission end and the second signal transmission end being disposed on the two parts of the first conductive layer divided by the first crack; a second crack extending from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrating through the second electrode, the interlayer insulating layer and the second conductive layer between the third signal transmission end and the fourth signal transmission end, the second conductive layer being divided into two parts independent of each other by the second crack, the third signal transmission end and the fourth signal transmission end being disposed on the two parts of the second conductive layer divided by the second crack; wherein changing the direction of the voltage applied to the ferroelectric layer can control the first crack and the second crack to be separated alternatively. The first crack does not penetrate through the ferroelectric layer, or / and the second crack does not penetrate through the ferroelectric layer. The first signal transmission end and the second signal transmission end are arranged in a first lateral direction on the first conductive layer, the first crack extends in a second lateral direction and penetrates through the first conductive layer; the third signal transmission end and the fourth signal transmission end are arranged in a first lateral direction on the second conductive layer, the second crack extends in a second lateral direction and penetrates through the second conductive layer; the first lateral direction intersects the second lateral direction. The interlayer insulating layer also covers the ferroelectric layer region between the first electrode and the second electrode. The interlayer insulating layer comprises: a first insulating layer disposed on the first electrode, the first conductive layer being disposed on the first insulating layer; a second insulating layer disposed on the second electrode, the second conductive layer being disposed on the second insulating layer, the first insulating layer and the second insulating layer being independent of each other. The interlayer insulating layer covers part of the surface of the first electrode and the second electrode, a first conductive terminal is disposed on the surface of the first electrode not covered by the interlayer insulating layer, and a second conductive terminal is disposed on the surface of the second electrode not covered by the interlayer insulating layer. The orthographic projection of the first electrode on the ferroelectric layer covers the orthographic projection of the first conductive layer on the ferroelectric layer. The orthographic projection of the second electrode on the ferroelectric layer covers the orthographic projection of the second conductive layer on the ferroelectric layer. ​ ​ ​ 2. The ferroelectric complementary switch device of claim 1, wherein, ​ 3. The ferroelectric complementary switch device of claim 1, wherein, ​ 4. The ferroelectric complementary switch device of claim 1, wherein, ​ 5. The ferroelectric complementary switch device of claim 1, wherein, ​ ​ ​ 6. The ferroelectric complementary switch device of claim 1, wherein, ​ 7. The ferroelectric complementary switch device of claim 1, wherein, ​ 8. The ferroelectric complementary switch device of claim 1, wherein, ​ 9. The ferroelectric complementary switch device of claim 1, wherein, The material of the first electrode is the same as the material of the first conductive layer.

10. The ferroelectric complementary switch device of claim 1, wherein, The material of the second electrode is the same as the material of the second conductive layer.

11. The ferroelectric complementary switch device of claim 1, wherein, One of the signal transmission ends on the first conductive layer is electrically connected with one of the signal transmission ends on the second conductive layer, and forms a signal output end of the ferroelectric complementary switch device.

12. The ferroelectric complementary switch device of claim 11, wherein, The signal transmission end on the first conductive layer which forms the signal output end is closer to the second conductive layer than the other signal transmission end on the first conductive layer, and the signal transmission end on the second conductive layer which forms the signal output end is closer to the first conductive layer than the other signal transmission end on the second conductive layer.

13. A method for fabricating a ferroelectric complementary switching device, characterized in that, The method comprises the following steps: providing a substrate; forming, on the surface of the substrate, a ferroelectric layer, a first electrode, a second electrode, an interlayer insulating layer, a first conductive layer, a second conductive layer, and a first signal transmission end, a second signal transmission end, a third signal transmission end and a fourth signal transmission end in sequence, the first conductive layer corresponding to the first electrode, the second conductive layer corresponding to the second electrode, the first signal transmission end and the second signal transmission end being arranged on the first conductive layer, and the third signal transmission end and the fourth signal transmission end being arranged on the second conductive layer; forming a first crack and a second crack, the first crack extending from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrating the second electrode, the interlayer insulating layer, and the first conductive layer between the first signal transmission end and the second signal transmission end, and the first conductive layer being divided into two parts by the first crack, and the first signal transmission end and the second signal transmission end being arranged on the two parts of the first conductive layer divided by the first crack respectively, and the second crack extending from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrating the second electrode, the interlayer insulating layer, and the second conductive layer between the third signal transmission end and the fourth signal transmission end, and the second conductive layer being divided into two parts by the second crack, and the third signal transmission end and the fourth signal transmission end being arranged on the two parts of the second conductive layer divided by the second crack respectively; before the first crack and the second crack are formed, the ferroelectric layer has a set ferroelectric domain polarization direction, and the method for forming the first crack and the second crack comprises the following steps: applying a first flipping voltage to the ferroelectric layer through the first electrode and the second electrode to form the first crack; applying a second flipping voltage to the ferroelectric layer through the first electrode and the second electrode to form the second crack, the second flipping voltage being opposite in polarity to the first flipping voltage.

14. The method of claim 13, wherein the ferroelectric complementary switch device is a ferroelectric field effect transistor (FeFET) device. The first crack does not penetrate the ferroelectric layer, and / or the second crack does not penetrate the ferroelectric layer.

15. The method of claim 13, wherein the ferroelectric complementary switch device is a ferroelectric metal-oxide-semiconductor field-effect transistor (FeMOSFET) device. After the ferroelectric layer is formed on the substrate, the method further comprises the following steps: applying a polarization voltage to the ferroelectric layer to make the ferroelectric domain polarization direction of the ferroelectric layer the same as the direction of the polarization voltage, and forming the set ferroelectric domain polarization direction.

16. A method of controlling a ferroelectric complementary switching device as claimed in any one of claims 1 to 12, characterized in that The method comprises the following steps: A first voltage is applied to the ferroelectric layer through the first electrode and the second electrode to control the separation of the first crack and the closure of the second crack, so as to realize electrical insulation between the first signal transmission end and the second signal transmission end and electrical conduction between the third signal transmission end and the fourth signal transmission end; a second voltage is applied to the ferroelectric layer through the first electrode and the second electrode to control the closure of the first crack and the separation of the second crack, so as to realize electrical conduction between the first signal transmission end and the second signal transmission end and electrical insulation between the third signal transmission end and the fourth signal transmission end, wherein the first voltage and the second voltage are opposite in polarity.

17. The method of controlling a ferroelectric complementary switch device according to claim 16, wherein, The first voltage or the second voltage is applied to the ferroelectric layer through the first electrode and the second electrode under the control of an input signal, and the logic circuit function is realized by setting the voltage levels of the first signal transmission end and the third signal transmission end.

18. A three-dimensional memory, comprising: The ferroelectric complementary switch device comprises the ferroelectric complementary switch device according to any one of claims 1-12.

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