Iq clock phase calibration

Abstract

A communication circuit is disclosed. The communication circuit includes a calibration system configured to receive clock signals having first and second clock phases and first and second duty cycles, respectively, wherein the calibration system is further configured to receive input data and to adjust the input data based in part on the input data and in part on the first and second duty cycles to generate adjusted data. The communication circuit further includes a mixer configured to receive the clock signals and to receive the adjusted data, wherein the mixer is configured to generate output data based on the clock signals and the adjusted data, and wherein due to the adjustment of the input data to generate the adjusted data, mismatches in the output data due to the first and second duty cycles being different are reduced.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to the following applications, the contents of which are incorporated herein by reference in their entirety:

[0003] The invention is entitled “IQ CLOCK PHASE CALIBRATION”, filed on March 31, 2022, with U.S. patent application number 17 / 710,983.

[0004] The invention is entitled “IQ CLOCK PHASE CALIBRATION” and is filed on November 22, 2021. The patent application number is 63 / 281,739. Technical Field

[0005] The topic described in this article relates to IQ clock phase calibration, and more specifically, to differential IQ clock phase calibration. Background Technology

[0006] In typical transmitters and receivers with quadrature mixers, passive mixers with non-overlapping clocks are used to up-convert and down-convert the I and Q baseband phases to or from the RF. In a system with four LO phases, ideally, the four LO phases are exactly 90 degrees phase-shifted from each other. The four LO phases can be generated using N-division phases, where, for example, N = 2. Due to mismatches in the generation of the four LO phases, the four LO phases have undesirable phase mismatches. This phase mismatch will result in phase and amplitude mismatches in the up-converted or down-converted signals. A system with reduced phase and amplitude mismatches is needed. Summary of the Invention

[0007] One aspect of the invention is a communication circuit including a calibration system configured to receive a plurality of clock signals, each having a clock phase and a duty cycle, wherein a first clock signal has a first clock phase and a second clock signal has a second clock phase, wherein the first clock phase and the second clock phase are different, wherein the first clock signal has a first duty cycle and the second clock signal has a second duty cycle, and wherein the first duty cycle and the second duty cycle are different, wherein the calibration system is further configured to receive input data and adjust the input data, in part based on the input data and in part based on the first duty cycle and the second duty cycle of the first clock signal and the second clock signal, to generate adjusted data. The communication circuit also includes a mixer configured to receive the plurality of clock signals and the adjusted data, wherein the mixer is configured to generate output data based on the plurality of clock signals and the adjusted data, and wherein, due to the adjustment of the input data to generate adjusted data, mismatches in the output data caused by the difference between the first duty cycle and the second duty cycle are reduced.

[0008] In some embodiments, the communication circuitry includes a frequency synthesizer configured to generate a plurality of clock signals.

[0009] In some embodiments, the duty cycle of the multiple clock signals or the inverted versions of the multiple clock signals is approximately 1 divided by the number of clock signals.

[0010] In some embodiments, the phases of the plurality of clock signals are separated by approximately 360 degrees divided by the number of clock signals.

[0011] In some embodiments, the calibration system is configured to generate a plurality of analog values, each of which corresponds to the duty cycle of one of a plurality of clock signals.

[0012] In some embodiments, the calibration system is configured to generate a plurality of digital values, each of which corresponds to one of the analog values.

[0013] In some embodiments, the calibration system is configured to store digital values ​​and adjust input data in part based on analog values ​​corresponding to a first duty cycle and a second duty cycle of a first clock signal and a second clock signal to generate adjusted data.

[0014] Another aspect of the invention is a method of operating a communication circuit including a calibration system and a mixer, wherein the method includes: using the calibration system to receive a plurality of clock signals, each having a clock phase and a duty cycle, wherein a first clock signal has a first clock phase and a second clock signal has a second clock phase, wherein the first clock phase and the second clock phase are different, wherein the first clock signal has a first duty cycle and the second clock signal has a second duty cycle, and wherein the first duty cycle and the second duty cycle are different. The method further includes: using the calibration system to receive input data; using the calibration system to adjust the input data, partly based on the input data and partly based on the first and second duty cycles of the first and second clock signals, to generate adjusted data; using the mixer to receive the plurality of clock signals; using the mixer to receive the adjusted data; and using the mixer to generate output data based on the plurality of clock signals and the adjusted data, wherein the mismatch in the output data caused by the difference between the first and second duty cycles is reduced due to the adjustment of the input data to generate the adjusted data.

[0015] In some embodiments, the communication circuitry includes a frequency synthesizer, and the method further includes generating a plurality of clock signals using the frequency synthesizer.

[0016] In some embodiments, the duty cycle of the multiple clock signals or the inverted versions of the multiple clock signals is approximately equal to 1 divided by the number of clock signals.

[0017] In some embodiments, the phases of the plurality of clock signals are separated by approximately 360 degrees divided by the number of clock signals.

[0018] In some embodiments, the method includes generating a plurality of analog values ​​using a calibration system, each of the plurality of analog values ​​corresponding to a duty cycle of one of a plurality of analog values ​​in a plurality of clock signals.

[0019] In some embodiments, the method includes generating a plurality of digital values ​​using a calibration system, each of the plurality of digital values ​​corresponding to one of the analog values.

[0020] In some embodiments, the method includes using a calibration system to store digital values ​​and adjusting input data in part based on analog values ​​corresponding to a first duty cycle and a second duty cycle of a first clock signal and a second clock signal to generate adjusted data.

[0021] Another aspect of the invention is a method of operating a communication circuit including a calibration system. The method includes: using the calibration system, receiving a plurality of clock signals, each having a clock phase and a duty cycle, wherein a first clock signal has a first clock phase and a second clock signal has a second clock phase, wherein the first clock signal and the second clock phase are different, wherein the first clock signal has a first duty cycle and the second clock signal has a second duty cycle, and wherein the first duty cycle and the second duty cycle are different. The method further includes using the calibration system to generate a plurality of digital values, each digital value corresponding to the duty cycle of one of the plurality of clock signals, and using the calibration system to store the digital values.

[0022] In some embodiments, the method includes using a calibration system to generate a plurality of analog values, each of which corresponds to the duty cycle of one of a plurality of clock signals; and using the calibration system to generate a plurality of digital values, each of which corresponds to one of the analog values.

[0023] In some embodiments, the method includes receiving input data using a calibration system, and adjusting the input data using the calibration system, partly based on the input data and partly based on stored digital values, to generate adjusted data.

[0024] In some embodiments, the communication circuit further includes a mixer, and the method further includes: receiving a plurality of clock signals using the mixer; receiving conditioned data using the mixer; and generating output data using the mixer based on the plurality of clock signals and the conditioned data, wherein mismatches in the output data caused by different duty cycles of the plurality of clock signals are reduced due to the conditioning of the input data to generate the conditioned data.

[0025] In some embodiments, the communication circuitry includes a frequency synthesizer, and the method further includes generating a plurality of clock signals using the frequency synthesizer.

[0026] In some embodiments, the duty cycle of the plurality of clock signals or the inverted versions of the plurality of clock signals is approximately equal to 1 divided by the number of clock signals, and the phases of the plurality of clock signals are phase-separated by approximately 360 degrees divided by the number of clock signals. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help to explain some principles associated with the disclosed embodiments.

[0028] Figure 1 This is a schematic diagram of a transmitter circuit according to one embodiment.

[0029] Figure 2A schematic diagram of a portion of the transmitter circuitry is shown.

[0030] Figure 3 It shows Figure 2 Timing diagram of certain clock phase signals of the circuit.

[0031] Figure 4 This is a flowchart of a method for calibrating an IQ calibration system according to an embodiment.

[0032] Figure 5 This is a flowchart of a method for transmitting data according to one embodiment;

[0033] Figure 6 It shows Figure 2 Timing diagram of some signals in the circuit.

[0034] In fact, similar reference numerals in drawings indicate similar structures, features, or elements. Detailed Implementation

[0035] As discussed in further detail below, the embodiments discussed herein illustrate circuitry and methods for generating and calibrating multiple clock phases.

[0036] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form part of this specification. The following description provides only one embodiment and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of the embodiments will provide those skilled in the art with an implementation description for carrying out one or more embodiments. It should be understood that various changes may be made in terms of the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain embodiments of the invention. However, it will be apparent, however, that the embodiments may be practiced without these specific details. The drawings and description are not intended to be limiting. The words “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0037] Figure 1 This is a schematic diagram of a transmitter circuit 100 according to one embodiment. The transmitter circuit 100 includes an antenna or antenna array 110, a switch 120, an RF link 130, and a controller 140. A specific example of the transmitter circuit 100 is shown. Other embodiments of the transmitter circuit may be used.

[0038] The antenna or antenna array 110 can be any antenna or antenna array. For example, in some embodiments, the antenna or antenna array 110 includes 1, 2, 3, 4 or more antennas. In some embodiments, the antenna or antenna array 110 includes a linear antenna array. In some embodiments, the antenna or antenna array 110 includes a two-dimensional antenna array, such as having a multi-row linear antenna array.

[0039] In embodiments where the antenna or antenna array 110 includes a single antenna, this single antenna can be directly connected to RF link 130, and switch 120 can be omitted. In embodiments where the antenna or antenna array 110 includes multiple antennas, each antenna can be directly connected to a separate RF link. Each RF link can have the characteristics of RF link 130.

[0040] Antenna or antenna array 110 can be configured to transmit RF signals to receiver circuitry. RF signals include high-frequency signals at a carrier frequency modulated using low-frequency information signals. As controlled by controller 140, for example by a programmable electrical connection formed by switch 120, the high-frequency signals are transmitted from one of the antennas in antenna or antenna array 110.

[0041] The controller 140 is configured to provide digital signals to the RF link 130, wherein the digital signals encode information signals to be transmitted by the antenna or antenna array 110.

[0042] RF link 130 includes a digital-to-analog converter (DAC) circuit 132, a mixer 136, a frequency synthesizer 134, and a power amplifier (PA) 138. RF link 130 is merely an example, and other embodiments of RF links may be used alternatively. For example, as those skilled in the art will understand, in some embodiments, one or more amplifiers and / or filters may be included.

[0043] The digital signal is processed by the digital-to-analog converter 132 using techniques known in the art to generate an analog baseband signal (BB signal) representing the digital signal. Various digital-to-analog converter structures known in the art can be used.

[0044] Mixer 136 receives an analog baseband signal output from digital-to-analog converter 132 and an oscillator signal at the carrier frequency generated by frequency synthesizer 134. In response to the analog baseband signal and the oscillator signal, mixer 136 up-converts the analog baseband signal from analog-to-digital converter 132 to a high-frequency signal using techniques known in the art. Various mixer structures known in the art can be used. The resulting high-frequency signal is modulated at the carrier frequency to include information from the low-frequency information signal.

[0045] Power amplifier 138 is configured to receive high-frequency signals and drive them, for example, according to a programmable electrical connection formed by switch 120, to one of the antennas from the antenna or antenna array 110, as controlled by controller 140. Power amplifier 138 drives the high-frequency signals to one of the antennas using techniques known in the art. Various power amplifier structures known in the art can be used.

[0046] As those skilled in the art will understand, using a communication connection ( Figure 1 (Not shown in the image), control signals from controller 140 can control certain variable functions of, for example, switch 120, power amplifier 138, frequency synthesizer 134, mixer 136, and digital-to-analog converter 132, as understood by those skilled in the art.

[0047] Control signals from controller 140 can, for example, control switch 120 to control which of the multiple antennas the RF link 130 uses to drive the high-frequency signal.

[0048] In an embodiment having multiple antennas, each connected to one of multiple RF links, the controller 140 can generate control signals for each of the RF links.

[0049] Figure 2 The transmitter circuit (such as) is shown. Figure 1 A schematic diagram of a portion of the transmitter circuit shown. In the illustrated embodiment, a portion of the transmitter circuit includes a frequency synthesizer 134, a mixer 236, a DAC circuit 232, and an IQ calibration system 240.

[0050] In the illustrated embodiment, it can be with Figure 1 Frequency synthesizer 234, similar to or identical to frequency synthesizer 134, includes a divide-by-two circuit 233 and a duty cycle adjustment circuit 235. In alternative embodiments, other circuitry and / or architectures may be used. In this embodiment, frequency synthesizer 234 is configured to generate four clock phases offset from each other by approximately 90 degrees. In some embodiments, a different number of clock phases are generated, for example, offset by approximately a fixed angle, where, for example, the number of phases multiplied by a fixed angle equals 360 degrees. In this embodiment, the generated clock phases are used by a specific mixer 236. In some embodiments, other mixers or other circuitry may be used. In this embodiment, mixer 236 is an up-conversion mixer 236 of the transmitter circuitry and may have similar characteristics to... Figure 1 The mixer 136 has similar or identical features.

[0051] As shown, in this embodiment, the divide-by-two circuit 233 receives, for example, a differential clock signal generated at least partially using a local oscillator circuit. Furthermore, as... Figure 3 As shown, the frequency divider circuit 233 generates four initial clock phases LO000_50, LO090_50, LO180_50, and LO270_50, wherein each of the four initial clock phases LO000_50, LO090_50, LO180_50, and LO270_50 has a frequency equal to f. LO The frequency and approximately 50% duty cycle. Any divide-by-two circuit architecture can be used.

[0052] As shown, in this embodiment, the duty cycle adjustment circuit 235 receives four initial clock phases: LO000_50, LO090_50, LO180_50, and LO270_50. Furthermore, as... Figure 3 As shown, the duty cycle adjustment circuit 235 generates four mixer clock phases LO000, LO090, LO180, and LO270, wherein each of the four mixer clock phases LO000, LO090, LO180, and LO270 has a frequency equal to f. LO The frequency and a duty cycle of nearly 25% (1 divided by the number of mixer clock phases).

[0053] In the illustrated embodiment, the duty cycle adjustment circuit 235 includes an architecture that performs four flips and four logical AND operations. In some embodiments, different duty cycle adjustment circuit architectures are used.

[0054] like Figure 3 As shown, due to delay mismatches in the circuitry used to generate the four mixer clock phases LO000, LO090, LO180, and LO270, the four mixer clock phases LO000, LO090, LO180, and LO270 have different duty cycles, which, although close to 25%, are not identical. This results in the RFOut signal, when used by an upconverter mixer, including significant phase and amplitude mismatches due to the different duty cycles, as understood by those skilled in the art, unless compensated.

[0055] like Figure 2 As shown, the IQ calibration system 240 includes an IQ calibration circuit 248 and a duty cycle detection circuit, which includes a low-pass filter 242 for each clock phase, a multiplexer circuit 244, and an ADC 246.

[0056] Each low-pass filter 242 is configured to receive one of the clock phases and generate an analog signal corresponding to the average analog value of the received clock phase. In response to a signal from a controller (not shown), a multiplexer circuit 244 is configured to connect the input of ADC 246 to one of the low-pass filters. A digital representation of the analog signal from the low-pass filter connected thereto is then provided to the IQ calibration circuit 248.

[0057] The IQ calibration circuit 248 is configured to store a digital representation of the analog signal of the low-pass filter. Furthermore, the IQ calibration circuit 248 is configured to receive I and Q input data, for example, from a controller, and generate regulated I and Q data, which are then converted into analog signals by the DAC circuit 232 for use in the up-conversion mixer. As discussed in more detail below, the regulated I and Q data are generated based on the I and Q input data and the stored digital representation of the analog signal of the low-pass filter. As discussed in more detail below, the regulated I and Q data is generated such that the RFOut signal does not include, or includes significantly less, the phase and amplitude mismatch caused by the different duty cycles of the four mixer clock phases LO000, LO090, LO180, and LO270.

[0058] RFOut phase and amplitude errors caused by mixer clock phase duty cycle mismatch

[0059] The high-level durations of mixer clock phases LO000, LO090, LO180, and LO270 are as follows:

[0060] T1 = T0 / 4 + te1,

[0061] T2 = T0 / 4 + te2,

[0062] T3 = T0 / 4 + te3, and

[0063] T4 = T0 / 4 + te4,

[0064] Where te1, te2, te3, and te4 are the errors in the high-level duration of the mixer clock phases LO000, LO090, LO180, and LO270, respectively. In some embodiments, te1 + te2 + te3 + te4 = 0.

[0065] The durations between the centers of adjacent high-level times for mixer clock phases LO000, LO090, LO180, and LO270 are as follows:

[0066] td12=T0 / 4+(te1+te2) / 2

[0067] td13=T0 / 2+(te1+2te2+te3) / 2

[0068] td14=3T0 / 4+(te1+2te2+2te3+te4) / 2=3T0 / 4+(te2+te3) / 2,

[0069] td12, td13, and td14 are as follows: Figure 6 As shown.

[0070] The amplitude and phase equations are as follows:

[0071]

[0072] The approximate amplitude and phase equations are as follows:

[0073]

[0074] The approximate IQ Cartesian equation is as follows:

[0075]

[0076] The approximate IQ difference Cartesian equation is as follows:

[0077]

[0078]

[0079] The approximate IQ differential magnitude and phase equations are as follows:

[0080]

[0081] The approximate equations for the magnitude and phase mismatch of I and Q are as follows:

[0082]

[0083] In some embodiments, the IQ differential magnitude and phase equations can be calculated as follows:

[0084] LO_I = LO000 – LO180

[0085] LO_Q = LO090 – LO270

[0086] The ratio of the I phase to the Q phase is expressed as a complex number with a real part R and an imaginary part X.

[0087]

[0088] Amplitude and phase mismatch can be calculated as follows:

[0089]

[0090] Accordingly, in some embodiments, the IQ calibration circuit 248 is configured to determine errors te1, te2, te3, and te4 respectively based on corresponding digital representations of corresponding analog signals from corresponding low-pass filters. The IQ calibration circuit 248 is also configured to generate regulated I and Q data for the upconversion mixer according to the amplitude mismatch equation indicated above.

[0091] The corrected complex baseband signal can be expressed as:

[0092] BB corrected =A(1+∈)e -i(φ+θ) =BB(1+∈)e -i(θ) ,

[0093] Where A and Φ are the amplitude and phase of the BB data before correction. I and Q are the phases after correction, obtained by taking the real and imaginary parts of BB_corrected.

[0094] In some embodiments, different, for example, more or less precise I and Q amplitude and phase mismatch equations may be used, wherein the IQ calibration circuit 248 is accordingly configured to generate differentially regulated I and Q data based on the different I and Q amplitude and phase mismatch equations. In some embodiments, the different I and Q amplitude and phase mismatch equations are based on other approximations and are more or less precise than those shown in paragraph 0 above. In some embodiments, the different I and Q amplitude and phase mismatch equations are based in part on one or more circuit or circuit performance parameters of the IQ calibration system 240 circuitry. For example, the different I and Q amplitude and phase mismatch equations may be based in part on the resistance and / or capacitance parameters of a low-pass filter.

[0095] Figure 4 This is a flowchart of a method 400 for calibrating an IQ calibration system 240 according to an embodiment. Method 400 can be performed by a transmitter circuit (such as...) Figure 1 The transmitter 100) executes the method. In some embodiments, the transmitter's controller has instructions stored therein that, when executed, cause the transmitter to perform method 400.

[0096] At 410, the controller sends a connection signal to multiplexer 244, causing multiplexer 244 to electrically connect either the first LPF or the other LPF in LPF 242 to ADC 246. The connection signal encodes an identifier for which of the LPF 242 will be electrically connected to ADC 246. In response to the connection signal, multiplexer 244 electrically connects the identified LPF 242 to ADC 246.

[0097] At 420, ADC 246 receives voltage from the LPF 242 electrically connected to it. Furthermore, the controller sends a conversion signal to ADC 246. In response to the conversion signal, ADC 246 converts the received voltage from the electrically connected LPF 242 into a digital value that encodes the analog value of the received voltage. In some embodiments, after sending a connection signal to multiplexer 244, the controller waits for at least a predetermined delay time before sending the conversion signal to ADC 246. During this delay time, the voltage at the input of ADC 246 stabilizes to a value corresponding to the average duty cycle of the clock signal received by the LPF 242 connected to ADC 246 via multiplexer 244.

[0098] At 430, ADC 246 provides digital values ​​to IQ calibration circuit 248.

[0099] At 440, the controller sends a storage signal to the IQ calibration circuit 248. In response to the storage signal, the IQ calibration circuit 248 causes the digital value to be stored in the digital memory.

[0100] At 450, the controller determines whether to connect ADC 246 to another LPF 242. This determination can be made, for example, based on whether the IQ calibration circuit 248 has stored the digital value of each of the LPFs 242. For instance, if the IQ calibration circuit 248 has not stored the digital value of at least one of the LPFs 242, the controller can determine that one of the LPFs without stored digital values ​​should be connected to ADC 246. Conversely, if the IQ calibration circuit has stored all the digital values ​​of the LPFs 242, the controller can determine that ADC 246 should not be connected to the other LPF 242.

[0101] If at 450, the controller determines to connect ADC 246 to another LPF 242, and another occurrence at 410, the controller sends a connection signal to multiplexer 244, causing multiplexer 244 to electrically connect either the first LPF or the other LPF in LPF 242 to ADC 246. Otherwise, if at 450, the controller determines not to connect ADC to another LPF 242, then method 400 ends.

[0102] After the execution of method 400, the controller can proceed according to the various aspects discussed above and / or according to the reference. Figure 5 Method 500 discussed enables the transmitter to transmit data modified by the IQ calibration circuit 248 using stored digital values.

[0103] Figure 5 This is a flowchart of a data transmission method 500 according to one embodiment. Method 500 can be implemented by a transmitter circuit (such as...) Figure 1The transmitter 100) executes the method. In some embodiments, the transmitter's controller has instructions stored therein that, when executed, cause the transmitter to perform method 500.

[0104] In 510, the IQ calibration circuit 248 receives input data from the controller, for example. For instance, the IQ calibration circuit 248 can receive I and Q input data from the controller.

[0105] At 520, the IQ calibration circuit 248 accesses stored data representing duty cycle information of the s clock signals to be used by the mixer 236. In some embodiments, the stored data representing the duty cycle information is stored using a method similar to or the same as method 400.

[0106] At 530, the IQ calibration circuit generates regulated data based in part on the input data received at 510 and in part on the duty cycle information accessed at 520.

[0107] At 540, DAC circuit 232 receives regulated data from IQ calibration circuit 248 and generates an analog signal based on the received regulated data.

[0108] At 550, DAC circuit 232 provides analog signals to mixer 236.

[0109] At 560, mixer 236 receives an analog signal from DAC circuit 232 and a clock signal from frequency synthesizer 234, wherein the duty cycle information accessed at 520 corresponds to and characterizes the duty cycle of the clock signal. Furthermore, mixer 236 converts the analog signal from DAC circuit 232 in response to the received clock signal to generate output data, for example, to be provided to an amplifier, such as amplifier 138 of transmitter 100. Because the input data is regulated to generate regulated data, mismatches in the output data caused by different duty cycles of the clock signals are reduced.

[0110] One or more aspects or features of the subject matter described herein can be implemented in digital electronic circuit systems, integrated circuit systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof. These different aspects or features can be implemented in one or more computer programs executable and / or interpretable on a programmable system, which includes at least one programmable processor, which may be dedicated or general-purpose, coupled to receive and transmit data and instructions from and to a storage system, at least one input device, and at least one output device. The programmable system or computing system can include clients and servers. Clients and servers are typically geographically separated and typically interact via a communication network. The client-server relationship is generated by computer programs running on their respective computers and having a client-server relationship with each other.

[0111] These computer programs (which may also be referred to as programs, software, software applications, applications, components, or code) include machine instructions for programmable processors and can be implemented in high-level procedural languages, object-oriented programming languages, functional programming languages, logic programming languages, and / or assembly / machine languages. As used herein, the term "machine-readable medium" refers to any computer program product, apparatus, and / or device (e.g., disk, optical disk, memory, and programmable logic device, PLD) used to provide machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal used to provide machine instructions and / or data to a programmable processor. Machine-readable media can store such machine instructions non-transitory, such as non-transitory solid-state memory or magnetic hard disk drives or any equivalent storage medium. Machine-readable media can alternatively or additionally store such machine instructions transiently, such as processor caches or other random access memory associated with one or more physical processor cores.

[0112] To provide interaction with a user, one or more aspects or features of the subject matter described herein can be implemented on a computer having a display device (e.g., a cathode ray tube (CRT), liquid crystal display (LCD), or light emitting diode (LED) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user. For example, feedback provided to the user can be any form of sensory feedback, such as visual, auditory, or tactile feedback; and input from the user can be received in any form, including but not limited to sound, speech, or tactile input. Other possible input devices include, but are not limited to, touchscreens or other touch-sensitive devices, such as single-point or multi-point resistive or capacitive trackpads, speech recognition hardware and software, optical scanners, optical pointers, digital image capture devices, and associated interpretation software.

[0113] In the above description and claims, phrases such as “at least one of…” or “one or more of…” may appear after a combined list of elements (components) or features. The term “and / or” may also appear in a list of two or more elements (components) or features. Unless the context in which it is used implicitly or explicitly contradicts itself, such phrases are intended to mean either one of the listed elements or features individually, or any of the listed elements or features in combination with any of the other listed elements or features. For example, the phrases “at least one of A and B,” “one or more of A and B,” and “A and / or B” are each intended to mean “A only,” “B only,” or “A and B together.” Similar interpretations are also intended for lists comprising three or more items. For example, the phrases “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, and / or C” are each intended to mean “A only,” “B only,” “C only,” “A and B together,” “A and C together,” “B and C together,” or “A and B and C together.” The use of the term "based on" in the foregoing and claims is intended to mean "at least partially based on," so that unreferenced features or elements (components) are also permitted.

[0114] Depending on the desired configuration, the subject matter described herein can be embodied in systems, apparatus, methods, and / or articles. The embodiments set forth in the foregoing description do not represent all embodiments consistent with the subject matter described herein. Rather, they are merely examples of aspects consistent with the described subject matter. Although some variations have been described in detail above, other modifications or additions are possible. In particular, additional features and / or variations may be provided in addition to those set forth herein. For example, the above embodiments may refer to various combinations and sub-combinations of the disclosed features, and / or combinations and sub-combinations of several other features disclosed above. Furthermore, the logical flows depicted in the drawings and / or described herein do not necessarily require the specific order or sequential order shown to achieve the desired results. Other embodiments may also be within the scope of the claims.

Claims

1. A communication circuit comprising: a calibration system configured to receive a plurality of clock signals each having a clock phase and a duty cycle, wherein a first clock signal has a first clock phase and a second clock signal has a second clock phase, wherein the first clock phase and the second clock phase are different, wherein the first clock signal has a first duty cycle and the second clock signal has a second duty cycle, and wherein the first duty cycle and the second duty cycle are different, wherein the calibration system is further configured to receive input data and to adjust the input data based in part on the input data and in part on the first duty cycle and the second duty cycle of the first clock signal and the second clock signal to generate adjusted data; and a mixer configured to receive the plurality of clock signals and to receive the adjusted data, wherein the mixer is configured to generate output data based on the plurality of clock signals and the adjusted data, and wherein due to the adjustment of the input data to generate the adjusted data, a mismatch in the output data due to the first duty cycle and the second duty cycle being different is reduced.

2. The communication circuit of claim 1, comprising a frequency synthesizer configured to generate the plurality of clock signals; wherein the duty cycles of the plurality of clock signals or an inverted version of the plurality of clock signals are approximately 1 divided by the number of clock signals; the phases of the plurality of clock signals are separated in phase by approximately 360 degrees divided by the number of clock signals.

3. The communication circuit of claim 1, wherein the calibration system is configured to generate a plurality of analog values each corresponding to a duty cycle of one of the plurality of clock signals.

4. The communication circuit of claim 3, wherein the calibration system is configured to generate a plurality of digital values each corresponding to one of the analog values.

5. The communication circuit of claim 4, wherein the calibration system is configured to store the digital values and to adjust the input data based in part on analog values corresponding to the first duty cycle and the second duty cycle of the first clock signal and the second clock signal to generate adjusted data.

6. A method of operating a communication circuit comprising a calibration system and a mixer, wherein the method comprises: with the calibration system, receiving a plurality of clock signals each having a clock phase and a duty cycle, wherein a first clock signal has a first clock phase and a second clock signal has a second clock phase, wherein the first clock phase and the second clock phase are different, wherein the first clock signal has a first duty cycle and the second clock signal has a second duty cycle, and wherein the first duty cycle and the second duty cycle are different; with the calibration system, receiving input data; with the calibration system, adjusting the input data based in part on the input data and in part on the first duty cycle and the second duty cycle of the first clock signal and the second clock signal to generate adjusted data; and with the mixer, receiving the plurality of clock signals and the adjusted data; and with the mixer, generating output data based on the plurality of clock signals and the adjusted data. adjusting input data based in part on the input data and in part on the first duty cycle and the second duty cycle of the first clock signal and the second clock signal to generate adjusted data using the calibration system; receiving the plurality of clock signals using the mixer; receiving the adjusted data using the mixer; and generating output data based on the plurality of clock signals and the adjusted data using the mixer, wherein due to the adjusting of the input data to generate the adjusted data, mismatches in the output data due to the first duty cycle and the second duty cycle being different are reduced.

7. The method of claim 6, wherein the communication circuit includes a frequency synthesizer, and the method further comprises generating the plurality of clock signals using the frequency synthesizer; wherein the duty cycles of the plurality of clock signals or an inverted version of the plurality of clock signals are approximately 1 divided by the number of clock signals; the phases of the plurality of clock signals are separated in phase by approximately 360 degrees divided by the number of clock signals.

8. The method of claim 6, further comprising generating a plurality of analog values each corresponding to a duty cycle of one of the plurality of clock signals using the calibration system.

9. The method of claim 8, further comprising generating a plurality of digital values each corresponding to one of the analog values using the calibration system.

10. The method of claim 9, further comprising storing the digital values using the calibration system, and adjusting the input data based in part on the analog values corresponding to the first duty cycle and the second duty cycle of the first clock signal and the second clock signal to generate the adjusted data.

11. A method of operating a communication circuit including a calibration system, wherein the method comprises: receiving a plurality of clock signals each having a clock phase and a duty cycle using the calibration system, wherein a first clock signal has a first clock phase, and a second clock signal has a second clock phase, wherein the first clock phase and the second clock phase are different, wherein the first clock signal has a first duty cycle, and the second clock signal has a second duty cycle, and wherein the first duty cycle and the second duty cycle are different; generating a plurality of digital values each corresponding to a duty cycle of one of the plurality of clock signals using the calibration system; and storing the digital values using the calibration system; receiving input data using the calibration system; and adjusting the input data based in part on the input data and in part on the stored digital values to generate adjusted data using the calibration system; wherein the communication circuit further includes a mixer, and wherein the method further comprises: receiving the plurality of clock signals using the mixer; receiving the adjusted data using the mixer; and generating output data based on the plurality of clock signals and the adjusted data using the mixer, wherein due to the adjusting of the input data to generate the adjusted data, mismatches in the output data due to the first duty cycle and the second duty cycle being different are reduced. With the mixer, output data is generated based on the plurality of clock signals and the adjusted data, where due to the adjusting of the input data to generate the adjusted data, mismatches in the output data due to duty cycle differences of the plurality of clock signals are reduced.

12. The method of claim 11, further comprising: generating, with the calibration system, a plurality of analog values, each of the plurality of analog values corresponding to a duty cycle of one of the plurality of clock signals; and generating, with the calibration system, a plurality of digital values, each of the plurality of digital values corresponding to one of the analog values.

13. The method of claim 11, wherein the communication circuitry comprises a frequency synthesizer, and the method further comprises generating, with the frequency synthesizer, the plurality of clock signals; wherein a duty cycle of the plurality of clock signals or an inverted version of the plurality of clock signals is approximately equal to 1 divided by a number of clock signals, and wherein phases of the plurality of clock signals are separated in phase by approximately 360 degrees divided by a number of clock signals.

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