Clock generation circuit and compensation circuit thereof

Abstract

The present invention discloses a clock generation circuit and its compensation circuit. The clock generation circuit receives a reference clock signal generated by a reference clock circuit and inputs it to an input divider and a fractional phase-locked circuit. The input divider generates an input divided-frequency signal, which is then fed to a counter and a gain error circuit. The counter generates a count signal based on the input divided-frequency signal and a spread spectrum signal. The gain error circuit generates an integer division parameter and a decimal division parameter based on the input divided-frequency signal and the count signal, which are then fed to the fractional phase-locked circuit to generate a clock output signal. The input divider, the counter, and the gain error circuit form the compensation circuit, which is used to compensate the fractional phase-locked circuit for generating the clock output signal.

Description

Technical Field

[0001] The present invention relates to a clock generation circuit and a compensation circuit thereof, and in particular, utilizes a frequency division integer parameter and a frequency division fraction parameter in combination with a spread spectrum signal and a reference clock signal to perform frequency division to output an appropriate output clock signal. Background Art

[0002] Modern integrated circuits (ICs) all have at least one phase-locked loop (PLL) circuit to provide the various clock frequencies required by the IC. Furthermore, as semiconductor manufacturing processes improve, process complexity and IC operation complexity increase, and the various clock frequencies used during operation may not be integer multiples. For example, the same IC may require clocks of 66 MHz, 100 MHz, and 133 MHz. Using a PLL to generate the various frequencies required within an IC is the most economical method. Specifically, the fixed-frequency pulse signal output by the PLL is divided by a frequency divider, resulting in a pulse signal output at a fixed frequency. However, to obtain pulse signal outputs of different frequencies, multiple PLL circuits are required to provide multiple pulse signal outputs. This consumes a significant amount of circuit area and consumes high power. Consequently, a single PLL circuit has been developed that connects multiple frequency dividers to provide pulse signal outputs of different frequencies.

[0003] Many electronic circuits today, even microelectronic circuits such as integrated circuits (ICs), require a clock source as a fundamental signal generator. Therefore, it's common to design a high-frequency crystal oscillator into a microprocessor (MCU). However, in addition to providing a high-frequency clock signal, this circuit design also requires a considerable current input to drive the oscillator. Consequently, power-sensitive applications require a relatively low-power, or even lower-frequency, clock source for timing functions. Therefore, the 32.768kHz quartz crystal oscillator was developed to meet this need. The oscillation signal generated by the quartz crystal oscillator can be divided 15 times by the frequency divider inside the quartz clock generator to obtain a 1Hz clock signal. 1Hz means the second hand moves once per second. Therefore, the frequency divider inside the quartz clock can only divide the frequency 15 times. If the 32.768kHz oscillation signal is replaced with an oscillation signal of another frequency, the oscillation signal will no longer be a 1Hz signal after being divided 15 times, and the time indicated by the electronic clock will be inaccurate. 32.768k = 32768 = 2 to the 15th power. Therefore, electronic devices can be used for data transmission and provide more convenient and accurate timekeeping.

[0004] For example, embedded microcontroller (MCU) systems have traditionally relied on a low-frequency 32.768kHz quartz crystal oscillator to generate a low-frequency oscillation signal to drive the MCU's internal oscillator for timekeeping and fault recovery. This paper proposes an on-chip 32.768kHz clock generator with background calibration to achieve excellent frequency accuracy. This frequency accuracy is achieved by reusing the system clock (HFXO) to intermittently assist with background calibration. However, this frequency division method requires the HFXO to be enabled, and the frequency divider must remain enabled even in sleep mode, resulting in significant power consumption in the clock generation circuit.

[0005] To address the aforementioned issues, the present invention provides a clock generation circuit and its compensation circuit. The counter is configured to combine an input frequency division signal with a spread spectrum signal to generate a count signal for a gain error circuit, which then generates corresponding integer and fractional frequency division parameters for a fractional phase-locked circuit. The fractional phase-locked circuit then compensates for the integer and fractional frequency division parameters to generate a corresponding output pulse signal. This reduces power consumption while the clock generation circuit is enabled. Summary of the Invention

[0006] One object of the present invention is to provide a clock generation circuit that combines an input frequency-divided signal with a spread spectrum signal to generate a count signal for a gain error circuit, thereby generating corresponding integer and fractional frequency-divided parameters for a fractional phase-locked circuit to compensate the fractional phase-locked circuit and generate a corresponding output pulse signal. This reduces power consumption of the clock generation circuit while it is in an enabled state.

[0007] The present invention discloses a clock generation circuit comprising a reference clock generation circuit, an input divider, a counter, a gain error circuit, and a fractional phase-locked circuit. The reference clock generation circuit generates a reference clock signal to the input divider and the fractional phase-locked circuit. The input divider generates an input divider signal based on the reference clock signal to the counter and the gain error circuit. The counter receives the input divider signal and a spread spectrum signal to generate a count signal to the gain error circuit. The gain error circuit receives the input divider signal and the count signal to generate a divider integer parameter and a divider fractional parameter. Thus, the compensation circuit of the present invention is not enabled, and the divider integer parameter and the divider fractional parameter provided by the compensation circuit of the present invention are equivalent to those generated using the reference clock signal. Therefore, the compensation circuit of the present invention reduces power consumption.

[0008] The present invention provides an embodiment, wherein the fractional phase-locked circuit includes a phase / frequency detector, a charge pump element, a loop filter, a voltage-controlled oscillator, an output frequency divider, a multi-divisor frequency divider, and a modulator. The phase / frequency detector is coupled to the reference clock generation circuit and a timing control circuit. The timing control circuit generates a timing control signal and an enable signal. The phase / frequency detector receives the reference clock signal and the timing control signal to generate a charge-discharge control signal accordingly. The charge pump element is coupled to the phase / frequency detector and the timing control circuit to receive the charge-discharge control signal and the enable signal for charging and discharging. The loop filter is coupled to the charge pump element to generate a potential signal according to the charging and discharging of the charge pump element. The voltage-controlled oscillator is coupled to the loop filter to receive the potential signal to generate a voltage-controlled oscillation signal accordingly. The output frequency divider, The multi-divisor frequency divider is coupled to the voltage-controlled oscillator and receives the voltage-controlled oscillation signal to generate an output clock signal accordingly. The multi-divisor frequency divider receives the voltage-controlled oscillation signal and a summing signal to generate a feedback frequency division signal to the timing control circuit, so that the timing control circuit generates the timing control signal and the enable signal. The modulator is coupled to the multi-divisor frequency divider and a summing unit. The modulator and the summing unit are coupled to the gain error circuit together. The modulator receives the feedback frequency division signal and the frequency division fractional parameter to generate a modulation signal to the summing unit. The summing unit receives the frequency division integer parameter and the modulation signal to generate the summing signal to the multi-divisor frequency divider.

[0009] The present invention provides an embodiment, wherein the clock generation circuit further includes a spread spectrum clock generator coupled to the counter to generate the spread spectrum signal to the counter.

[0010] The present invention provides an embodiment, wherein the gain error circuit further generates a spread spectrum enable signal to the spread spectrum clock generator to control the enablement of the spread spectrum clock generator.

[0011] The present invention provides an embodiment in which the compensation circuit further includes a temperature sensor coupled to the gain error circuit to sense an ambient temperature to generate a temperature compensation signal to the gain error circuit. The gain error circuit further generates the frequency division fractional parameter and the frequency division integer parameter based on the temperature compensation signal.

[0012] The present invention provides an embodiment in which a gain error circuit includes a comparison form element, a gain summing unit, and an arithmetic unit. The comparison form element is coupled to the temperature sensor and generates a temperature compensation parameter based on the temperature compensation signal. The gain summing unit is coupled to the comparison form element, the counter, and a storage unit. The storage unit stores a frequency division parameter. The gain summing unit receives the temperature compensation parameter, the frequency division parameter, and the count signal and generates a summed arithmetic parameter accordingly. The arithmetic unit is coupled to the gain summing unit and generates the fractional frequency division parameter and the integer frequency division parameter based on the summed arithmetic parameter.

[0013] The present invention provides an embodiment in which the gain error circuit includes a gain summing unit and an arithmetic unit. The gain summing unit is coupled to the counter and a storage unit, the storage unit storing a frequency division parameter. The gain summing unit receives the temperature compensation parameter, the frequency division parameter, and the count signal to generate a summed arithmetic parameter. The arithmetic unit is coupled to the gain summing unit to generate the fractional frequency division parameter and the integer frequency division parameter based on the summed arithmetic parameter.

[0014] The present invention further provides a compensation circuit that generates a frequency division integer parameter and a frequency division fractional parameter to a fractional phase-locked circuit, causing the fractional phase-locked circuit to generate an output clock signal based on a reference clock signal, the frequency division fractional parameter, and the frequency division integer parameter. The compensation circuit includes an input frequency divider, a counter, and a gain error circuit. The input frequency divider generates an input frequency division signal based on the reference clock signal, which is transmitted to the counter and the gain error circuit. The counter receives the input frequency division signal and a spread spectrum signal to generate a count signal to the gain error circuit, causing the gain error circuit to receive the input frequency division signal and the count signal to generate the frequency division integer parameter and the frequency division fractional parameter. Thus, the compensation circuit of the present invention does not remain in an enabled state, and the frequency division integer parameter and the frequency division fractional parameter provided by the compensation circuit of the present invention are equivalent to those generated using the reference clock signal, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 : It is a block diagram of a clock generation circuit according to an embodiment of the present invention;

[0016] Figure 2 : It is a block diagram of a detailed circuit of a compensation circuit according to an embodiment of the present invention;

[0017] Figure 3 : which is a block diagram of a clock generation circuit according to another embodiment of the present invention; and

[0018] Figure 4 : It is a block diagram of a detailed circuit of a compensation circuit according to another embodiment of the present invention.

[0019]

Figure number comparison

[0020] 10. Clock Generation Circuit

[0021] 12 Reference clock generation circuit

[0022] 14 Spread spectrum clock generation circuit

[0023] 20 Fractional phase-locked circuit

[0024] 22 Phase / Frequency Detector

[0025] 24 Charge Pump Components

[0026] 26 Loop filter

[0027] 28 Voltage Controlled Oscillator

[0028] 30 Output frequency divider

[0029] 32 Multi-Divisor Frequency Divider

[0030] 34 Timing Control Circuit

[0031] 36 Modulator

[0032] 38 total units

[0033] 40 Compensation Circuit

[0034] 42 Input Frequency Divider

[0035] 44 counter

[0036] 46 Gain Error Circuit

[0037] 462 Gain Summing Unit

[0038] 464 storage units

[0039] 466 Arithmetic Unit

[0040] 468 Comparison form element

[0041] 48 Temperature Sensor

[0042] α frequency division factor parameter

[0043] Σout modulation signal

[0044] CP EN Enable signal

[0045] f IN Input pulse signal

[0046] f OUT Output pulse signal

[0047] f MO Spread spectrum signal

[0048] k counting signal

[0049] k 32k Frequency division parameters

[0050] k TC Temperature compensation parameters

[0051] N is the integer parameter for frequency division

[0052] SUM sum signal

[0053] TC temperature sensor signal

[0054] T EN Timing control signal

[0055] V PF Charge and discharge control signal

[0056] V CP Charge and discharge signals

[0057] V Filter Potential signal

[0058] V VCO voltage-controlled oscillator signal

[0059] V M Input frequency division signal

[0060] V MMD Feedback frequency division signal DETAILED DESCRIPTION

[0061] In order to further understand and appreciate the structural features and effects achieved by the present invention, preferred embodiments and detailed descriptions are provided as follows:

[0062] In view of the fact that in conventional clock generation circuits, the frequency divider remains enabled, thereby increasing power consumption, the present invention proposes a clock generation circuit and a compensation circuit thereof to solve the problem of the conventional technology causing the frequency divider to remain enabled, resulting in increased power consumption.

[0063] The following further describes the characteristics and structure of a clock generation circuit disclosed in the present invention:

[0064] First, see Figure 1, which is a block diagram of a clock generation circuit according to an embodiment of the present invention. As shown in the figure, the clock generation circuit 10 of the present invention includes a fractional PLL circuit 20 and a compensation circuit 40. The compensation circuit 40 generates a frequency division integer parameter N and a frequency division fraction parameter α to the fractional PLL circuit 20, so that the fractional PLL circuit 20 generates a frequency division integer parameter N and a frequency division fraction parameter α according to a reference clock signal f. OSC The frequency division decimal parameter α and the frequency division integer parameter N generate an output clock signal f OUT In addition, the clock generation circuit 10 is further coupled to a reference clock circuit 12, which generates the reference clock signal f OSC .

[0065] The fractional phase-locked phase-locked circuit 20 includes a phase / frequency detector 22, a charge pump element 24, a loop filter 26, a voltage-controlled oscillator 28, an output frequency divider 30, a multi-divisor frequency divider 32, a timing control circuit 34, a modulator 36, and a summing unit 38. The phase / frequency detector 22 is coupled to a reference clock generation circuit 12 and the timing control circuit 34. The charge pump element 24 is coupled to the loop filter 26. The loop filter 26 is coupled to the voltage-controlled oscillator 28. The voltage-controlled oscillator 28 is coupled to the output frequency divider 30 and the multi-divisor frequency divider 32. The multi-divisor frequency divider 32 is coupled to the timing control circuit 34, the modulator 36, and the summing unit 38. The modulator 36 and the summing unit 38 are further coupled to the compensation circuit 40.

[0066] The timing control circuit 34 generates a timing control signal T EN Same as the performance signal CP EN The phase / frequency detector 22 receives the reference clock signal f OSC and the timing control signal T EN , to generate a corresponding charge and discharge control signal V PF The charge pump element 24 receives the charge and discharge control signal V PF and the enabling signal CP EN Charge and discharge are performed, thus forming a charge and discharge signal V CP , in particular, a potential signal V is formed in the loop filter 26 Filter , and through the potential signal V Filter The voltage controlled oscillator 28 is controlled to generate a voltage controlled oscillation signal V VCO The output frequency divider 30 and the multi-divisor frequency divider 32 receive the voltage-controlled oscillation signal V generated by the voltage-controlled oscillator 28. VCO The output frequency divider 30 is based on the voltage controlled oscillation signal V VCO Generates a corresponding output clock signal f OUT , and the multi-divisor frequency divider 32 receives the voltage-controlled oscillation signal V VCOThe summing signal generated by the summing unit 38 is used to generate a corresponding feedback frequency division signal V MMD to the timing control circuit 34, so that the timing control circuit 34 generates the timing control signal T EN and the enabling signal CP EN The modulator 36 receives the feedback frequency-divided signal V MMD and the frequency division factor parameter α to generate a modulation signal Σ OUT To the summing unit 38, the summing unit 38 receives the frequency division integer parameter N and the modulation signal Σ OUT , to generate the sum signal SUM to the multi-divisor divider 32. As can be seen from the above description, the multi-divisor divider 32 to the timing control circuit 34, and the timing control signal T EN 、The enable signal CP EN 、The feedback frequency division signal V MMD and the voltage-controlled oscillation signal V VCO The signal transmission is equivalent to the voltage controlled oscillator 28 performing feedback control on the phase / frequency detector 22 and the charge pump element 24 .

[0067] Please also refer to Figure 2 The compensation circuit 40 of the present invention includes an input frequency divider 42, a counter 44, and a gain error circuit 46. In addition, the compensation circuit 40 is further coupled to a spread spectrum generation circuit 14. The input frequency divider 42 is coupled to the reference clock generation circuit, the counter 44, and the gain error circuit 46. In particular, the input frequency divider 42 is coupled to the enable port EN of the counter 44. The input frequency divider 42 receives the reference clock signal f OSC , to generate an input frequency division signal V M The counter 44 receives the input frequency divider 42 of the input frequency divider signal V M , and receives the spread spectrum signal f generated by the spread spectrum generating circuit 14 MO , to generate a corresponding counting signal k, so that the gain error circuit 46 receives the input frequency division signal V M The counting signal k generates the frequency division integer parameter N and the frequency division fraction parameter α, so that the fractional PLL circuit 20 generates the corresponding clock output signal f according to the frequency division integer parameter N and the frequency division fraction parameter α. OUT .

[0068] Specifically, the gain error circuit 46 includes a gain summing unit 462, a storage unit 464, and a calculation unit 466. The gain summing unit 462 is coupled to the counter and a storage unit. The storage unit stores a frequency division parameter k. 32k The gain summing unit 462 receives the frequency division parameter k 32kA summing operation parameter Δcode is generated corresponding to the count signal k. The operation unit is coupled to the gain summing unit 462 to generate the frequency division integer parameter N and the frequency division fractional parameter α according to the summing operation parameter Δcode, and output them to the fractional phase-locked circuit 20. In particular, the frequency division fractional parameter α is output to the modulator 36, and the frequency division integer parameter N is output to the summing unit 38. Therefore, the frequency division integer parameter N and the frequency division fractional parameter α of this embodiment correspond to the frequency division parameter k. 32k and the counting signal k.

[0069] It can be seen that the compensation circuit 40 of the present invention compensates the fractional PLL circuit 20 by using the integer frequency division parameter N and the fractional frequency division parameter α, thereby allowing the fractional PLL circuit 20 to generate the corresponding output clock signal f OUT , at the same time, the spread spectrum signal f MO , because the fractional phase-locked circuit 20 is compensated by the compensation circuit 40, it is not the spread spectrum signal f MO The reference clock generator 12 and the spread spectrum clock generator 14 are connected externally to the fractional phase-locked circuit 20 and the compensation circuit. Alternatively, the reference clock generator 12 and the spread spectrum clock generator 14 are built into the reference clock generator 12 or the spread spectrum clock generator 14.

[0070] Since the clock generation circuit 10 is further provided with a reference clock generation circuit 12 and a spread spectrum clock generation circuit 14 in addition to the compensation circuit 40, the ambient temperature will also affect the operation of the clock generation circuit 10. Therefore, a temperature compensation mechanism may be further provided to compensate for the error caused by temperature.

[0071] See also Figure 3 , which is a block diagram of a clock generation circuit according to another embodiment of the present invention. Figure 1 and Figure 3 The difference is Figure 3 The compensation circuit 40 is further provided with a temperature sensor 48 to complement the temperature compensation mechanism of the compensation circuit 40. The gain error circuit 46 is coupled to the temperature sensor 48 and is configured to generate a gain error signal at the input frequency division signal V M When the counting signal k fails to match, a temperature enabling signal TP is generated to the temperature sensor 48 to enable the temperature sensor 48. The temperature sensor 48 then detects the environment (not shown) in which the clock generating circuit 10 is located, and accordingly generates a temperature sensing signal TC to the gain error circuit 46 to perform temperature compensation on the frequency division integer parameter N and the frequency division fractional parameter α.

[0072] For details, please refer to Figure 4 , and Figure 2 The difference is Figure 4 A reference window element 466 is further provided in the gain error circuit 46, which is coupled to the temperature sensor 48, thereby receiving the temperature sensing signal TC to find the corresponding temperature compensation parameter K according to the temperature sensing signal TC. TC , and input to the gain summing unit 462. Therefore, the gain summing unit 462 of this embodiment is based on the temperature compensation parameter K TC The summed operation parameter Δcode is generated to the operation unit 466. Therefore, the frequency division integer parameter N and the frequency division fraction parameter α of this embodiment correspond to the temperature compensation parameter K. TC To avoid the error caused by high ambient temperature affecting the clock output signal f OUT accuracy.

[0073] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications in the shape, structure, characteristics and spirit described in the scope of the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A clock generation circuit, characterized in that: It includes: A reference clock generating circuit generates a reference clock signal; an input frequency divider coupled to the reference clock generating circuit, receiving the reference clock signal to generate an input frequency-divided signal; a counter coupled to the input frequency divider, receiving the input frequency-divided signal and a spread spectrum signal to generate a corresponding counting signal; a gain error circuit coupled to the input frequency divider and the counter, receiving the input frequency division signal and the counting signal to generate a frequency division integer parameter and a frequency division fractional parameter; as well as A fractional phase-locked circuit is coupled to the reference clock generation circuit and the gain error circuit, receives the reference clock signal, the frequency division integer parameter and the frequency division decimal parameter, and generates a clock output signal accordingly.

2. The clock generation circuit according to claim 1, wherein: The fractional phase-locked circuit comprises: a phase / frequency detector coupled to the reference clock generation circuit and a timing control circuit, the timing control circuit generating a timing control signal and an enable signal, the phase / frequency detector receiving the reference clock signal and the timing control signal to generate a charge / discharge control signal accordingly; a charge pump element coupled to the phase / frequency detector and the timing control circuit to receive the charge-discharge control signal and the enable signal for charge-discharge; a loop filter coupled to the charge pump element and generating a potential signal according to the charge and discharge of the charge pump element; a voltage-controlled oscillator coupled to the loop filter, receiving the potential signal to correspondingly generate a voltage-controlled oscillation signal; an output frequency divider coupled to the voltage-controlled oscillator, receiving the voltage-controlled oscillation signal to correspondingly generate an output clock signal; a multi-divisor frequency divider receiving the voltage-controlled oscillation signal and a summing signal to generate a corresponding feedback frequency-dividing signal to the timing control circuit, so that the timing control circuit generates the timing control signal and the enabling signal; as well as A modulator is coupled to the multi-divisor frequency divider and a summing unit. The modulator and the summing unit are coupled to the gain error circuit. The modulator receives the feedback frequency division signal and the frequency division fractional parameter to generate a modulation signal to the summing unit. The summing unit receives the frequency division integer parameter and the modulation signal to generate the summed signal to the multi-divisor frequency divider.

3. The clock generation circuit according to claim 1, wherein: The invention further comprises a spread spectrum clock generator coupled to the counter to generate the spread spectrum signal to the counter.

4. The clock generation circuit according to claim 3, wherein: The gain error circuit further generates a spread spectrum enabling signal to the spread spectrum clock generator to control the enabling of the spread spectrum clock generator.

5. The clock generation circuit according to claim 1, wherein: The device further comprises a temperature sensor coupled to the gain error circuit for sensing an ambient temperature to generate a temperature compensation signal to the gain error circuit. The gain error circuit further generates the frequency division fraction parameter and the frequency division integer parameter according to the temperature compensation signal.

6. The clock generation circuit according to claim 5, wherein: The gain error circuit is provided with: a control window element coupled to the temperature sensor and generating a temperature compensation parameter according to the temperature compensation signal; a gain summing unit coupled to the control form element, the counter, and a storage unit, wherein the storage unit stores a frequency division parameter. The gain summing unit receives the temperature compensation parameter, the frequency division parameter, and the counting signal to generate a summing operation parameter accordingly; and An operation unit is coupled to the gain summing unit and generates the frequency division decimal parameter and the frequency division integer parameter according to the summing operation parameter.

7. The clock generation circuit according to claim 1, wherein: The gain error circuit is provided with: a gain summing unit coupled to the counter and a storage unit, wherein the storage unit stores a frequency division parameter, and the gain summing unit receives the frequency division parameter and the counting signal to generate a summing operation parameter accordingly; and An operation unit is coupled to the gain summing unit and generates the frequency division decimal parameter and the frequency division integer parameter according to the summing operation parameter.

8. A compensation circuit, characterized in that: The compensation circuit generates a frequency division integer parameter and a frequency division fractional parameter to a fractional phase-locked circuit, so that the fractional phase-locked circuit generates an output clock signal according to a reference clock signal, the frequency division fractional parameter and the frequency division integer parameter. The compensation circuit includes: an input frequency divider receiving the reference clock signal to generate an input frequency-divided signal; a counter receiving the input frequency-divided signal and a spread spectrum signal to generate a corresponding counting signal; as well as A gain error circuit receives the input frequency division signal and the counting signal to correspondingly generate the frequency division integer parameter and the frequency division fractional parameter.

9. The compensation circuit according to claim 8, wherein: The compensation circuit is further coupled to a spread spectrum clock generator, which generates the spread spectrum signal to the counter.

10. The compensation circuit according to claim 8, wherein: The compensation circuit is further coupled to a temperature sensor. The temperature sensor senses an ambient temperature and generates a temperature compensation signal to the gain error circuit. The gain error circuit further generates the frequency division fraction parameter and the frequency division integer parameter according to the temperature compensation signal.

11. The compensation circuit according to claim 8, wherein: The fractional phase-locked circuit comprises: a phase / frequency detector coupled to a reference clock generation circuit and a timing control circuit, receiving the reference clock signal from the reference clock generation circuit and a timing control signal from the timing control circuit to generate a charge / discharge control signal accordingly; a charge pump element coupled to the phase / frequency detector to receive the charge and discharge control signal and the enable signal generated by the timing control circuit to perform charge and discharge; a loop filter coupled to the charge pump element and generating a potential signal according to the charge and discharge of the charge pump element; a voltage-controlled oscillator coupled to the loop filter, receiving the potential signal to correspondingly generate a voltage-controlled oscillation signal; an output frequency divider coupled to the voltage-controlled oscillator, receiving the voltage-controlled oscillation signal to correspondingly generate an output clock signal; a multi-divisor frequency divider receiving the voltage-controlled oscillation signal and a summing signal to generate a corresponding feedback frequency-dividing signal; the timing control circuit generates the timing control signal to the phase / frequency detector and generates the enabling signal to the charge pump element according to the feedback frequency-dividing signal; as well as A modulator is coupled to the multi-divisor frequency divider and a summing unit. The modulator and the summing unit are coupled to the gain error circuit. The modulator receives the feedback frequency division signal and the frequency division fractional parameter to generate a modulation signal to the summing unit. The summing unit receives the frequency division integer parameter and the modulation signal to generate the summed signal to the multi-divisor frequency divider.

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