Solid-state imaging device, driving method of solid-state imaging device, and electronic equipment

Abstract

Provided are a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic device, which are not affected by optical specifications and can suppress the reduction in SNR at a junction between signals with different conversion gains. A pixel (200) selectively connects a floating diffusion layer FD11 to a first capacitor CS11 via a first connecting element LG11-Tr, thereby changing the capacitance of FD11 to a first capacitor or a second capacitor and switching the conversion gain to a first conversion gain (HCG) determined by the first capacitor or a second conversion gain (MCG) determined by the second capacitor. FD11 is connected to a second capacitor CS12 via a second connecting element SG11-Tr, thereby changing the capacitance of FD11 to a third capacitor and switching the conversion gain of SF11-Tr to a third conversion gain (LCG) determined by the third capacitor.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and electronic equipment. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensors have been put into practical use as solid-state imaging devices (image sensors) using photoelectric conversion elements that detect light and generate electric charges.

[0003] CMOS image sensors are widely used as a part of various electronic devices, including digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), car cameras, and portable terminal devices (mobile devices) such as mobile phones.

[0004] CMOS image sensors have an FD amplifier in each pixel, including a photodiode (photoelectric conversion element) and a floating diffusion layer (FD). The mainstream reading type of this CMOS image sensor is column-parallel output, that is, a row in the pixel array is selected and read simultaneously in the column output direction.

[0005] Generally speaking, each pixel of a CMOS image sensor is constructed as, for example, corresponding to one photodiode, including four elements as active elements: a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element (amplifier element), and a selection transistor as a selection element.

[0006] In order to improve the performance, various methods for realizing a high-quality CMOS image sensor with a high dynamic range (HDR) have been proposed (for example, see Patent Documents 1, 2, and 3).

[0007] Patent document 1 describes a CMOS image sensor that achieves a high dynamic range. The pixel includes a photodiode PD that generates charge in response to incident light. The charge from the photodiode PD is coupled to a voltage source and discharged, or can be transferred to a charge accumulation area such as an accumulation diode.

[0008] If the charge generated in the charge accumulation region exceeds a first charge level, the charge may overflow to the first accumulation capacitor via the first transistor. If the charge generated exceeds a second charge level higher than the first charge level, the charge may overflow via the second transistor. The charge overflowing through the second transistor can be discharged or transferred to the second accumulation capacitor for subsequent reading.

[0009] Patent Document 2 describes a solid-state image pickup device that realizes a wide dynamic range, a control method thereof, and an electronic device that aims to suppress the influence of PLS.

[0010] A solid-state image acquisition device includes a pixel array unit in which a plurality of pixels are arranged. Some of the pixels within the pixel array unit are unit pixels having at least one photoelectric conversion element and an overflow integration capacitor (LOFIC). Furthermore, the solid-state image acquisition device includes an A / D converter for one or more unit pixels within the pixel array unit.

[0011] Patent Document 3 describes a CMOS image sensor that can achieve a wide dynamic range while maintaining high sensitivity at a high S / N ratio.

[0012] The pixel array has the following structure. Each pixel includes a photodiode PD for receiving light and generating and accumulating photocharges, and an accumulation capacitor CS coupled to the photodiode PD via a transfer transistor Tr1 for accumulating the photocharges overflowing from the photodiode PD. The accumulation capacitor CS is configured to accumulate the photocharges overflowing from the photodiode PD.

[0013] Prior art literature

[0014] Patent Literature

[0015] Patent Document 1: US10791292B1

[0016] Patent Document 2: US10547802B2

[0017] Patent Document 3: US20080266434A1 Summary of the Invention

[0018] Technical problems to be solved by the present invention

[0019] As described above, a CMOS image sensor (CIS) can be configured using various special structures that improve the dynamic range of pixels.

[0020] The construction of lateral overflow integration capacitor (LOFIC) is one of the ways to achieve a high dynamic range.

[0021] However, LOFIC has a significant problem in that the SNR is degraded at the junction (junction) of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal.

[0022] In other words, the kTC noise of the LCG signal cannot be eliminated by the LOFIC configuration alone, so the SNR at the junction of the HCG signal and the LCG signal is reduced.

[0023] One method for achieving minimal SNR degradation is to use dual conversion gain (gain) readout, and triple conversion gain readout technology with LOFIC and split pixel.

[0024] However, this pixel structure (split pixel type) presents several optical specification issues, including the optical structure, different angle responses, and different quantum efficiencies (QEs), or responsiveness between large and small photodiodes (PDs).

[0025] The present invention provides a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic device capable of suppressing a decrease in SNR at a junction between signals having different conversion gains without being affected by optical specifications.

[0026] Solutions to the Problem

[0027] A solid-state imaging device according to a first aspect of the present invention includes a pixel that performs photoelectric conversion and can read a signal corresponding to at least three conversion gains, the pixel including: a floating diffusion layer that holds transferred charge in order to read it as a voltage signal and converts the charge into a voltage corresponding to a capacitance; a photoelectric conversion element that accumulates charge corresponding to the amount of incident light during an exposure period; a transfer element that is maintained in a non-conductive state during the exposure period and in a conductive state during a transfer period and transfers the charge accumulated by the photoelectric conversion element to the floating diffusion layer; a reset element that can perform a reset process for at least discharging the accumulated charge in the floating diffusion layer; and a first capacitor element that is configured to store the accumulated charge in the floating diffusion layer. The conversion gain is controlled to be in a connected state or a non-connected state with the floating diffusion layer; a first connecting element selectively connects the floating diffusion layer to the first capacitor element; a second capacitor element can accumulate overflow charges overflowing from the photoelectric conversion element; a second connecting element selectively connects the floating diffusion layer and the second capacitor element; an overflow path can allow the charges overflowing from the photoelectric conversion element to overflow toward the formation area of ​​the second capacitor element; an overflow gate element is formed on the overflow path to perform conduction control of the overflow path; and a source follower element amplifies and outputs the voltage signal converted in the floating diffusion layer.

[0028] A second aspect of the present invention is a method for driving a solid-state imaging device, the solid-state imaging device including a pixel that performs photoelectric conversion and can read a signal corresponding to at least three conversion gains, the pixel including: a floating diffusion layer that holds transferred charge for reading as a voltage signal and converts the charge into a voltage corresponding to a capacitance; a photoelectric conversion element that accumulates charge corresponding to an amount of incident light during an exposure period; a transfer element that remains in a non-conductive state during the exposure period and in a conductive state during a transfer period and transfers the charge accumulated in the photoelectric conversion element to the floating diffusion layer; a reset element that can perform a reset process for at least discharging the accumulated charge in the floating diffusion layer; a first capacitor element that is controlled to be either connected to or disconnected from the floating diffusion layer according to the conversion gain; a first connecting element that selectively connects the floating diffusion layer to the first capacitor element; a second capacitor element that can accumulate overflow charge from the photoelectric conversion element; and a second connecting element that selectively The floating diffusion layer and the second capacitor are connected; an overflow path is configured to allow charge overflowing from the photoelectric conversion element to overflow toward a region where the second capacitor is formed; an overflow gate element is formed on the overflow path and is configured to control the conduction of the overflow path; a source follower element is configured to amplify and output a voltage signal converted in the floating diffusion layer; the floating diffusion layer and the first capacitor are selectively connected via the first connecting element, thereby changing the capacitance of the floating diffusion layer to the first capacitor or the second capacitor, and switching the conversion gain to a first conversion gain determined by the first capacitor or a second conversion gain determined by the second capacitor; the floating diffusion layer and the second capacitor are connected via the second connecting element, thereby changing the capacitance of the floating diffusion layer to a third capacitor, and switching the conversion gain to a third conversion gain determined by the third capacitor.

[0029] An electronic device according to a third aspect of the present invention includes: a solid-state imaging device; and an optical system for forming an image of a subject on the solid-state imaging device, wherein the solid-state imaging device includes pixels that perform photoelectric conversion and can read signals corresponding to at least three conversion gains, the pixels including: a floating diffusion layer that holds transferred charge so as to be read as a voltage signal and converts the charge into a voltage corresponding to a capacitance; a photoelectric conversion element that accumulates charge corresponding to an amount of incident light during an exposure period; a transfer element that remains in a non-conductive state during the exposure period and remains in a conductive state during a transfer period and transfers the charge accumulated by the photoelectric conversion element to the floating diffusion layer; and a reset element that can reset at least the floating diffusion layer. A reset process for discharging accumulated charge; a first capacitor element, which is controlled to be in a connected state or a non-connected state with the floating diffusion layer according to the conversion gain; a first connecting element, which selectively connects the floating diffusion layer to the first capacitor element; a second capacitor element, which can accumulate overflow charge overflowing from the photoelectric conversion element; a second connecting element, which selectively connects the floating diffusion layer and the second capacitor element; an overflow path, which can allow the charge overflowing from the photoelectric conversion element to overflow toward the formation area of ​​the second capacitor element; an overflow gate element, which is formed on the overflow path and is used to perform conduction control of the overflow path; and a source follower element, which amplifies and outputs the voltage signal converted in the floating diffusion layer.

[0030] Effects of the Invention

[0031] According to the present invention, it is possible to suppress a decrease in SNR at a connection point between signals having different conversion gains without being affected by optical specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present invention.

[0033] Figure 2 This is a circuit diagram showing a configuration example of a pixel in the solid-state imaging device according to the first embodiment of the present invention.

[0034] Figure 3 This is a diagram for explaining the photoelectric conversion characteristics related to triple conversion gain reading in the solid-state imaging device according to the first embodiment of the present invention.

[0035] Figure 4 This is a timing chart for explaining an example of a read sequence in the dual conversion gain read mode and the overflow read mode for pixels of the solid-state imaging device according to the first embodiment of the present invention.

[0036] Figure 5These are diagrams showing an operation sequence and potential transition for explaining the operation under low illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0037] Figure 6 These are diagrams showing an operation sequence and potential transition for explaining the operation under medium illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0038] Figure 7 These are diagrams showing an operation sequence and potential transition for explaining the operation under high illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0039] Figure 8 Graphs showing linearity characteristics, noise characteristics, and SNR characteristics of a composite signal of read signals in a triple conversion gain read mode of the solid-state imaging device according to the first embodiment of the present invention.

[0040] Figure 9 This is a circuit diagram showing a configuration example of a readout pixel in a solid-state imaging device according to a second embodiment of the present invention.

[0041] Figure 10 This is a timing chart for explaining an example of a read sequence in the dual conversion gain read mode and the overflow read mode for pixels of the solid-state imaging device according to the second embodiment of the present invention.

[0042] Figure 11 These are diagrams showing an operation sequence and potential transition for explaining the operation under low illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the second embodiment of the present invention.

[0043] Figure 12 These are diagrams showing an operation sequence and potential transition for explaining the operation under medium illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the second embodiment of the present invention.

[0044] Figure 13 These are diagrams showing an operation sequence and potential transition for explaining the operation under high illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the second embodiment of the present invention.

[0045] Figure 14 This is a circuit diagram showing a configuration example of a readout pixel in a solid-state imaging device according to a third embodiment of the present invention.

[0046] Figure 15 This is a timing chart for explaining an example of a read sequence in a dual conversion gain read mode and an overflow read mode for pixels of the solid-state imaging device according to the third embodiment of the present invention.

[0047] Figure 16 These are diagrams showing an operation sequence and potential transition for explaining the operation under low illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the third embodiment of the present invention.

[0048] Figure 17 These are diagrams showing an operation sequence and potential transition for explaining the operation under medium illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the third embodiment of the present invention.

[0049] Figure 18 These are diagrams showing an operation sequence and potential transition for explaining the operation under high illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the third embodiment of the present invention.

[0050] Figure 19 This is a circuit diagram showing a configuration example of a readout pixel in a solid-state imaging device according to a fourth embodiment of the present invention.

[0051] Figure 20 This is a timing chart for explaining an example of a read sequence in the dual conversion gain read mode and the overflow read mode for pixels of the solid-state imaging device according to the fourth embodiment of the present invention.

[0052] Figure 21 These are diagrams showing an operation sequence and potential transition for explaining operations in a dual conversion gain read mode and an overflow read mode for a pixel of the solid-state imaging device according to the fourth embodiment of the present invention.

[0053] Figure 22 This is a circuit diagram showing a configuration example of a pixel of a solid-state imaging device according to a fifth embodiment of the present invention.

[0054] Figure 23 This is a diagram showing an example of the configuration of an electronic device to which the solid-state imaging device according to an embodiment of the present invention is applied. DETAILED DESCRIPTION

[0055] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0056] (First embodiment)

[0057] Figure 1 This is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment of the present invention.

[0058] Figure 2 This is a circuit diagram showing a configuration example of a pixel in the solid-state imaging device according to the first embodiment of the present invention.

[0059] Figure 3 (A) and (B) are diagrams for explaining conversion gain and capacitance related to triple conversion gain reading in the solid-state imaging device according to the first embodiment of the present invention.

[0060] In this embodiment, the solid-state imaging device 10 is constituted by, for example, a CMOS image sensor.

[0061] like Figure 1 As shown, the solid-state imaging device 10 includes the following main components: a pixel unit 20 as a photographing unit, a vertical scanning circuit (row scanning circuit) 30, a reading circuit (column reading circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60.

[0062] Among these components, for example, the vertical scanning circuit 30 , the reading circuit 40 , the horizontal scanning circuit 50 , and the timing control circuit 60 constitute a pixel signal reading section 70 .

[0063] As will be described in detail below, in the first embodiment, the solid-state imaging device 10 has the following basic structure: the pixels 200 arranged in rows and columns in the pixel section 20. Figure 2 The composition shown.

[0064] In other words, the pixel 200 is configured to include: a floating diffusion layer FD (Floating Diffusion) 11 that holds transferred charge so as to read it as a voltage signal; a photodiode PD11 that serves as a photoelectric conversion element and accumulates charge corresponding to the amount of incident light during an exposure period PEXP; a transfer transistor TG11-Tr that serves as a transfer element and is maintained in a non-conductive state during the exposure period PEXP but is maintained in a conductive state during a transfer period and transfers the charge accumulated in the photodiode PD11, which serves as a photoelectric conversion element, to the floating diffusion layer FD11; and a reset transistor RST11-Tr that serves as a reset element capable of performing a reset process for discharging the accumulated charge in the floating diffusion layer FD11.

[0065] Furthermore, the pixel 200 is configured to include: a first capacitor CS11 serving as a first capacitance element controlled to be connected or disconnected with the floating diffusion layer FD11 in accordance with a conversion gain; a first switching transistor LG11-Tr serving as a first connecting element for selectively connecting the floating diffusion layer FD11 to the first capacitor CS11 serving as the first capacitance element; a second capacitor CS12 serving as a second capacitance element capable of accumulating overflow charge from the photodiode PD11 serving as a photoelectric conversion element; and a second switching transistor SG11-Tr serving as a second connecting element for selectively connecting the floating diffusion layer FD11 to the second capacitor CS12 serving as the second capacitance element.

[0066] Moreover, the pixel 200 is constructed to include: an overflow path OVFP that can allow the charge overflowing from the photodiode PD11 serving as a photoelectric conversion element to overflow in the direction of the formation area of ​​the second capacitor CS2 serving as a second capacitor element; an overflow path transistor LO11-Tr serving as an overflow gate element formed on the overflow path OVFP for performing conduction control of the overflow path OVFP; a source follower transistor SF11-Tr serving as a source follower element that outputs the voltage signal converted in the floating diffusion layer FD11; and a selection transistor SEL11-Tr serving as a selection element.

[0067] The pixel 200 of this embodiment selectively connects the floating diffusion layer FD11 and the first capacitor CS11, which serves as a first capacitance element, via the first switching transistor LG11-Tr, which serves as a first connecting element, under the control of the reading unit 70. This allows the capacitance of the floating diffusion layer FD11 to be changed to the first capacitance or the second capacitance, and switches to a first conversion gain (e.g., high conversion gain: HCG) determined by the first capacitance or a second conversion gain (e.g., middle conversion gain: MCG) determined by the second capacitance.

[0068] Moreover, under the control of the reading unit 70, the pixel 200 connects the floating diffusion layer FD11 and the second capacitor CS12 as the second capacitor element through the second switching transistor SG11-Tr as the second connecting element, thereby changing the capacitance of the floating diffusion layer FD11 to the third capacitance and switching to the third conversion gain determined by the third capacitance (for example, low conversion gain: LCG: Low Conversion Gain).

[0069] like Figure 3As shown, the pixel 200 is configured to, under the control of the reading unit 70, be capable of performing: a first conversion gain mode reading in which the pixel signal is read according to the first conversion gain (high conversion gain: HCG) corresponding to the first capacitor during a specified dual conversion gain reading mode; and a second conversion gain mode reading in which the pixel signal is read according to the second conversion gain (medium conversion gain: MCG) corresponding to the second capacitor (different from the first capacitor).

[0070] Moreover, the pixel 200 is configured to be able to perform a conversion gain mode read in which the pixel signal is read according to the third conversion gain (low conversion gain: LCG) corresponding to the third capacitor during an overflow read mode (LOFIC) read mode designated following the dual conversion gain read mode under the control of the read unit 70.

[0071] Pixel 200 is provided with a structure such as a lateral overflow integration capacitor (hereinafter referred to as "LOFIC" (Lateral Overflow Integration Capacitor)), which, under the control of the reading unit 70, performs a two-sampling reading mode (LOFIC mode) operation under low illumination conditions using the accumulated charge of the photoelectric conversion element, i.e., the photodiode PD11, and the third conversion gain (single gain) related to the overflow charge.

[0072] As described above, in the first embodiment, the pixel 200 does not need to be divided into pixels, in order to achieve the minimum SNR reduction, such as Figure 3 As shown, triple conversion gain reading is performed, namely: a first conversion gain mode reading is performed for reading the pixel signal according to the first conversion gain corresponding to the first capacitor (e.g., high conversion gain: HCG); a second conversion gain mode reading is performed for reading the pixel signal according to the second conversion gain corresponding to the second capacitor (different from the first capacitor) (e.g., medium conversion gain: MCG); and a third conversion gain mode reading is performed for reading the pixel signal according to the third conversion gain corresponding to the third capacitor (e.g., low conversion gain: LCG).

[0073] (Specific Circuit Configuration of Pixel 200)

[0074] Here, it is explained Figure 2 The specific circuit structure of the pixel 200.

[0075] Here, a configuration example of a pixel 200 having a LOFIC structure is described.

[0076] In the pixel unit 20 , read pixels 200 including photodiodes (photoelectric conversion elements) and in-pixel amplifiers are arranged in a two-dimensional matrix of N rows×M columns.

[0077] For example Figure 2 As shown, this pixel 200 is constructed to include: a photodiode PD11 as a photoelectric conversion element, a transfer transistor TG11-Tr as a transfer element, a reset transistor RST11-Tr as a reset element, a source follower transistor SF11-Tr as a source follower element, a selection transistor SEL11-Tr as a selection element, a first switching transistor LG11-Tr as a first connecting element, a second switching transistor SG11-Tr as a second connecting element, an overflow path transistor LO11-Tr as an overflow gate element, a first capacitor CS11 as a first capacitance element, a second capacitor CS12 as a second capacitance element, a floating diffusion layer FD11, a first node ND11 connected to the floating diffusion layer FD11, a second node ND12, and a third node ND13 connected to the second capacitor CS12.

[0078] In the first embodiment, the photodiode PD11 of the pixel 200 is formed of a high-capacitance photodiode.

[0079] In addition, in the pixel 200, the floating diffusion layer FD11, the first capacitor CS11, and the second capacitor CS12, the capacitance (capacitance) are set as follows (see also Figure 3 (B) in the figure.

[0080] The capacitance CFD of the floating diffusion FD11 is formed to be very small to achieve high gain and low noise. The capacitance CS1 of the first capacitor CS11 is set to be a medium capacitance larger than the capacitance of the high-capacitance photodiode PD11 to minimize the reduction in SNR.

[0081] The capacitance CS2 of the second capacitor CS12 is set to a very large capacitance (electrostatic capacitance) for high FWC (Full Well Capacity). The capacitance CS2 of the second capacitor CS12 is larger than the capacitance CS1 of the first capacitor CS11 and the capacitance CFD of the floating diffusion layer FD11.

[0082] Furthermore, the capacitance CS1 of the first capacitor CS11 is mainly used for a medium conversion gain, and the capacitance CS2 of the second capacitor CS12 is also used for a low conversion gain.

[0083] The high-capacitance photodiode PD11 generates and accumulates signal charges (electrons in this case) in an amount corresponding to the amount of incident light.

[0084] In the following, a case where the signal charges are electrons and each transistor is an n-type transistor is described. However, the signal charges may be holes and each transistor may be a p-type transistor.

[0085] In each pixel 200, a buried photodiode (PPD) is used as the photodiode (PD). Interface states caused by defects such as dangling bonds exist on the substrate surface where the photodiode (PD) is formed. Consequently, a large amount of charge (dark current) is generated due to thermal energy, making it impossible to read accurate signals.

[0086] In embedded photodiodes (PPDs), the charge accumulation section of the photodiode (PD) is embedded within the substrate, reducing the risk of dark current mixing into the signal.

[0087] The transfer transistor TG11 -Tr is connected between the photodiode PD11 and the floating diffusion layer FD11 (and the first node ND11 ), and is controlled by a control signal TG.

[0088] The transfer transistor TG11 -Tr is selected and turned on while the control signal TG is at a high level (H), and transfers the charges (electrons) photoelectrically converted by the photodiode PD11 and accumulated in the accumulation node to the floating diffusion layer FD11 .

[0089] Reset transistor RST11-Tr, in Figure 2 In the example, the first switching transistor LG11-Tr connected to the power supply potential VAAPIX and the floating diffusion layer FD11 via the first node ND11 and the second switching transistor SG11-Tr connected via the second node ND12 are controlled by the control signal RST.

[0090] The reset transistor RST11 -Tr is selected and turned on while the control signal RST is at the H level, thereby resetting at least the floating diffusion FD11 to the power supply potential VAAPIX.

[0091] In the first embodiment, the reset transistor RST11 -Tr and the transfer transistor TG11 -Tr are held in an on state, and the floating diffusion layer FD11 and the photodiode PD11 are reset.

[0092] The first switching transistor LG11 -Tr is connected between the floating diffusion FD11 and the first capacitor CS11 via the first node ND11 .

[0093] The first switching transistor LG11-Tr is controlled by a control signal LG applied to its gate via a control line. The first switching transistor LG11-Tr is selected and turned on when the control signal LG is at an H level, connecting the floating diffusion FD11 to the first capacitor CS11.

[0094] In the first embodiment, the reset transistor RST11 -Tr and the first switching transistor LG11 -Tr are held in an on state, and the floating diffusion layer FD11 and the first capacitor CS11 are reset.

[0095] The second switching transistor SG11 -Tr is connected between the floating diffusion FD11 (and the reset transistor RST11 -Tr) and the second capacitor CS12 via the second node ND12 .

[0096] The second switching transistor SG11-Tr is controlled by a control signal SG applied to its gate via a control line. The second switching transistor SG11-Tr is selected and turned on when the control signal SG is at an H level, connecting the floating diffusion FD11 (and the reset transistor RST11-Tr) to the second capacitor CS12.

[0097] In the first embodiment, the reset transistor RST11 -Tr and the second switching transistor SG11 -Tr are held in an on state, and the floating diffusion layer FD11 and the second capacitor CS12 are reset.

[0098] The overflow path transistor LO11 -Tr is connected between the charge accumulation node of the photodiode PD11 and the second capacitor CS12 via the third node ND13 .

[0099] The overflow path transistor LO11-Tr is controlled by a control signal LO applied to a gate via a control line.

[0100] The overflow path transistor LO11 -Tr is selected and placed in an on state while the control signal LO is at the H level, thereby connecting the charge accumulation node of the photodiode PD11 to the second capacitor CS12 .

[0101] Furthermore, if Figure 2 As shown, in this first embodiment, the overflow path OVFP forms a path (solid arrow) that enables the overflow charge of the photodiode PD11 to overflow to the second capacitor CS12 through the overflow path transistor LO11-Tr and the third node ND13, and also forms a path (dashed arrow) that enables the overflow charge of the second capacitor CS12 to pass through the second switching transistor SG11-Tr, the second node ND12, and the reset transistor RST11-Tr and be discarded to the power supply potential VAAPIX.

[0102] The source follower transistor SF11 -Tr and the selection transistor SEL11 -Tr are connected in series between the power supply potential VAAPIX and the vertical signal line LSGN11 .

[0103] The gate of the source follower transistor SF-Tr is connected to the floating diffusion layer FD11 , and the selection transistor SEL-Tr is controlled by a control signal SEL applied to the gate via a control line.

[0104] The selection transistor SEL11-Tr is selected and turned on during the selection period when the control signal SEL is at H level, thereby causing the source follower transistor SF11-Tr to output the voltage signal (VRST1, VSIG1) converted by the floating diffusion layer FD11 to the vertical signal line LSGN11.

[0105] In the pixel portion 20 , the pixel circuits 200 are arranged in N rows×M columns. Therefore, there are N control lines and M vertical signal lines.

[0106] exist Figure 1 In FIG, each control line is represented as one row scanning control line.

[0107] The vertical scanning circuit 30 drives pixels in the shutter row and the reading row through the row scanning control lines in response to the control of the timing control circuit 60 .

[0108] Furthermore, the vertical scanning circuit 30 outputs a row selection signal of a row address for a read row for reading a signal and a shutter row for resetting the charge accumulated in the photodiode PD11 based on the address signal.

[0109] The reading circuit 40 may be configured to include a plurality of column signal processing circuits (not shown) arranged corresponding to the column outputs of the pixel unit 20 , and column-parallel processing may be performed by the plurality of column signal processing circuits.

[0110] The horizontal scanning circuit 50 scans and transfers the signals processed by the plurality of column signal processing circuits of the reading circuit 40 in the horizontal direction, and outputs the scanned signals to a signal processing circuit (not shown).

[0111] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel unit 20 , the vertical scanning circuit 30 , the reading circuit 40 , the horizontal scanning circuit 50 , and the like.

[0112] When the dual conversion gain read mode MDCG is designated, the read unit 70 executes the second conversion gain reset read process MCGRRD, the first conversion gain reset read process HCGRRD, the first conversion gain read process HCGSRD, and the second conversion gain read process MCGSRD.

[0113] When the overflow read mode MOVF (MLOFIC) related to the overflow charge is designated, the read section 70 executes the third conversion gain read process LCGSRD and the third conversion gain reset read process LCGRRD.

[0114] In the first embodiment, the reading section 70 executes a reading process in the dual conversion gain reading mode MDCG as a reading mode process after starting the exposure period PEXP, and then performs a reading sequence control to execute the overflow reading mode MOVF (MLOFIC).

[0115] For example, the reading unit 70 maintains the reset transistor RST11-Tr, the first switching transistor LG11-Tr, the second switching transistor SG11-Tr, and the transfer transistor TG11-Tr in the on state for a specified period, resets the photodiode PD11, the floating diffusion layer FD11, the first capacitor CS11, and the second capacitor CS12 and performs shutter processing, so that the transfer transistor TG11-Tr is in the non-conducting state and starts the exposure period PEXP.

[0116] Moreover, after the reading unit 70 starts the exposure period PEXP, it sequentially performs the second conversion gain reset reading process MCGRRD, the first conversion gain reset reading process HCGRRD, the first conversion gain signal reading process HCGSRD, and the second conversion gain signal reading process MCGSRD as the processing of the dual conversion gain reading mode DMCG.

[0117] Next, the readout unit 70 executes the third conversion gain signal readout process LCGSRD as an overflow readout mode process related to overflow charge. The readout unit 70 then maintains the reset transistor RST11-Tr, the first switching transistor LG11-Tr, and the second switching transistor SG11-Tr in an on state for a predetermined period, dumps all charges in the floating diffusion layer FD11, the first capacitor CS11, and the second capacitor CS12 to the power supply potential VAAPIX, performs a shutter process, and then sequentially executes the third conversion gain reset readout process LCGRRD.

[0118] Here, an example of a read sequence for the pixels 200 in the solid-state imaging device according to the first embodiment will be described.

[0119] Figure 4 (A) to (E) are timing charts for explaining an example of a read sequence in the dual conversion gain read mode and the overflow read mode for the pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0120] Figure 5 (A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under low illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0121] Figure 6(A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under medium illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0122] Figure 7 (A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under high illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0123] Figure 4 (A) in FIG. 1 represents the control signal RST of the reset transistor RST11-Tr. Figure 4 (B) in FIG. 1 represents the control signal SG of the second switching transistor SG11-Tr. Figure 4 (C) in FIG. 1 represents the control signal LG of the first switching transistor LG11-Tr. Figure 4 (D) in FIG1 represents the control signal TG of the transmission transistor TG11-Tr. Figure 4 (E) in FIG. 1 represents the control signal LO of the overflow path transistor LO11 -Tr.

[0124] As described below, the read sequence of the pixel in the dual conversion gain read mode and the overflow read mode is basically performed in the same manner under low illumination, medium illumination, and high illumination.

[0125] Before the processing of the dual conversion gain reading mode MDCG begins, the control signals RST, SG, LG, TG, and LO are set to a high level during a specified period, and the reset transistor RST11-Tr, the second switching transistor SG11-Tr, the first switching transistor LG11-Tr, the transmission transistor TG11-Tr, and the overflow path transistor LO11-Tr are maintained in an on state during a specified period.

[0126] As a result, the photodiode PD11, the floating diffusion layer FD11, the first capacitor CS11, and the second capacitor CS12 are reset to the fixed potential VAAPIX. That is, the shutter operation is performed ( Figure 4 (A)~(E)).

[0127] Then, when the transfer transistor TG11-Tr is switched from the conductive state to the non-conductive state, the exposure time PEXP starts ( Figure 4 (D) in the.

[0128] After the exposure period PEXP ends and the read period begins, the control signals RST and LG are switched to high level, turning on the reset transistor RST11-Tr and the first switching transistor LG11-Tr, thereby resetting the floating diffusion FD11 and the first capacitor CS11.

[0129] Here, after a predetermined period has passed since the control signal RST and the control signal LG were switched to high level, only the control signal RST is switched to low level and the reset transistor RST11 -Tr is switched to a non-conductive state, which becomes a first reset signal reading period.

[0130] At this time, the control signal LG is still maintained at a high level, and the first switching transistor LG11-Tr is in the on state. Therefore, the charge of the floating diffusion layer FD11 and the charge of the first capacitor CS11 are shared, and the gain of the floating diffusion layer FD11 is switched to the second conversion gain MCG determined by the second capacitance including the capacitance CFD of the floating diffusion layer FD11 and the capacitance CS1 of the first capacitor CS11.

[0131] Then, during the reading of the first reset signal after the reset processing, the second conversion gain reset reading processing MCGRRD is performed, and the second read reset signal MCGRST (ADC) converted according to the second conversion gain MCG determined by the second capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr, and the specified processing is performed on this second read reset signal MCGRST (ADC).

[0132] Next, after the first reset signal read period, the control signal LG is switched to a low level, and the first switching transistor LG11-Tr is switched to a non-conductive state, entering the second reset signal read period. At this point, the first capacitor CS11 is disconnected from the floating diffusion FD11, separating the charge in the floating diffusion FD11 from the charge in the first capacitor CS11. The gain of the floating diffusion FD11 (source-follower transistor SF11-Tr) is switched to the first conversion gain HCG, which is determined by the first capacitor CFD of the floating diffusion FD11.

[0133] Then, during the second reset signal reading period, the first conversion gain reset reading process HCGRRD is performed, and the first read reset signal HCGRST (ADC) converted according to the first conversion gain HCG determined by the first capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr, and the prescribed processing is performed on this first read reset signal HCGRST (ADC).

[0134] Next, during the first transfer period following the second reset signal read period, control signal TG is switched to a high level, and transfer transistor TG11-Tr remains in the on state, transferring the accumulated charge in photodiode PD11 to floating diffusion FD11. After the first transfer period, control signal TG is switched to a low level, and transfer transistor TG11-Tr is switched to a non-conductive state.

[0135] Next, during the first signal reading period following the first transmission period, the first conversion gain signal reading process HCGSRD is performed, and the first read signal HCGSIG(ADC) converted according to the first conversion gain determined by the first capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr, and the prescribed processing is performed on this first read signal HCGSIG(ADC).

[0136] Then, the reset level HCGRSTADC and the signal level HCGSIGADC are maintained, or CDS calculation is performed based on the difference between the reset level and the signal level.

[0137] Next, after the first conversion gain read process HCGSRD, the control signal LG is switched from a low level to a high level, the first switching transistor LG11 -Tr is switched to an on state, and the first capacitor CS11 is connected to the floating diffusion FD11 .

[0138] As a result, the charge of the floating diffusion FD11 and the charge of the first capacitor CS11 are shared, and the gain of the floating diffusion FD11 is switched to the second conversion gain MCG determined by the second capacitor.

[0139] Next, during the second transfer period following the first signal read period, control signal TG is switched to a high level, and transfer transistor TG11-Tr remains in the on state, transferring the accumulated charge in photodiode PD11 to floating diffusion layer FD11. After the second transfer period, control signal TG is switched to a low level, and transfer transistor TG11-Tr is switched to a non-conductive state.

[0140] Then, during the second signal reading period following the second transmission period after the first signal reading period, the second conversion gain signal reading processing MCGSRD is performed, and the second reading signal MCGSIG (ADC) converted according to the second conversion gain MCG determined by the second capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr, and the prescribed processing is performed on this second reading signal MCGSIG (ADC).

[0141] Then, the reset level MCGRSTADC and the signal level MCGSIGADC are maintained, or CDS calculation is performed based on the difference between the reset level MCGRSTADC and the signal level MCGSIGADC. Here, the read mode is switched from the dual conversion gain read mode to the LOFIC read mode.

[0142] Furthermore, the dual conversion gain reading process only reads the accumulated charge of the photodiode PD11 using two gains, but during the LOFIC reading, the charge that exceeds the saturation of the photodiode PD11 and overflows and is accumulated in the second capacitor CS12 is also read.

[0143] After the second conversion gain read process MCGSRD, the control signal SG is switched from a low level to a high level, the second switching transistor SG11 -Tr is switched to an on state, and the second capacitor CS12 is connected to the floating diffusion FD11 .

[0144] Thus, the charge FDC of the floating diffusion FD11 is shared with the charges of the first capacitor CS11 and the second capacitor CS12 , and the gain of the floating diffusion FD11 is switched to the third conversion gain LCG determined by the third capacitor.

[0145] Then, in the third signal reading period after the second signal reading period, the third conversion gain signal reading process LCGSRD is executed, and the third read signal LCG(LOFIC)SIG(ADC) converted according to the third conversion gain LCG determined by the third capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr. Figure 4 In (B)), a predetermined process is performed on the third read signal LCGSIG(ADC).

[0146] Next, in the second reset processing period after the third signal read period, the control signal RST is switched to a high level, and the reset transistor RST11-Tr is switched to a conductive state, thereby resetting the floating diffusion FD11, the first capacitor CS11, and the second capacitor CS12.

[0147] Here, after a predetermined period has passed since the control signal RST was switched to the high level, the control signal RST is switched to the low level and the reset transistor RST11 -Tr is switched to the non-conductive state, which becomes the third reset signal reading period.

[0148] At this time, the control signals LG and SG still maintain a high level, and the first switching transistor LG11-Tr and the second switching transistor SG11-Tr are in the on state. Therefore, the charge of the floating diffusion layer FD11 is shared with the charge of the first capacitor CS11 and the second capacitor CS12, and the gain of the floating diffusion layer FD11 is maintained at the third conversion gain LCG determined by the third capacitance including the capacitance CFD of the floating diffusion layer FD11, the capacitance CS1 of the first capacitor CS11, and the capacitance CS2 of the second capacitor CS12.

[0149] Then, during the third reset signal reading period after the reset processing, the third conversion gain reset reading processing LCGRRD is executed, and the third read reset signal LOFIC(LCG)RST(ADC) converted according to the third conversion gain LCG determined by the third capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr ( Figure 4 (B) and (C) in the figure, the specified processing is performed on this third read reset signal LOFIC(LCG)RST(ADC).

[0150] Then, the reset level LCGRSTADC and the signal level LCGSIGADC are maintained, or CDS calculation is performed based on the difference between the reset level LCGRSTADC and the signal level LCGSIGADC.

[0151] As described above, in the solid-state imaging device 10 of the first embodiment, Figure 5 As shown in (A) in FIG, the floating diffusion layer FD11 is reset before the first read reset signal HCGRST is read. Therefore, the FD dark current charged in the floating diffusion layer FD11 can be removed (no FD dark current exists).

[0152] In addition, in the solid-state imaging device 10 of the first embodiment, as shown in FIG. Figure 6 As shown in (C), the floating diffusion FD11 and the first capacitor CS11 are reset before the second read reset signal MCGRST is read. Therefore, there is no FD / CS dark current charged in the floating diffusion FD11 and the first capacitor CS11.

[0153] However, the second capacitor CS12 as the second capacitance element is a node that accumulates charges during the accumulation period, and therefore cannot remove the dark current.

[0154] As described above, according to the first embodiment, the pixel 200 is configured to include: a floating diffusion layer FD11 that holds transferred charges and reads them as a voltage signal; a photodiode PD11 that accumulates charges corresponding to the amount of incident light during the exposure period PEXP; a transfer transistor TG11-Tr that is maintained in a non-conductive state during the exposure period PEXP and in a conductive state during the transfer period and transfers the charges accumulated in the photodiode PD11 to the floating diffusion layer FD11; and a reset transistor RST11-Tr that can perform a reset process for discharging the accumulated charges in the floating diffusion layer FD11.

[0155] Furthermore, the pixel 200 is configured to include: a first capacitor CS11 that is controlled to be connected to or disconnected from the floating diffusion layer FD11 in accordance with the conversion gain; a first switching transistor LG11-Tr that selectively connects the floating diffusion layer FD11 to the first capacitor CS11; a second capacitor CS12 that can accumulate overflow charge from the photodiode PD11; and a second switching transistor SG11-Tr that selectively connects the floating diffusion layer FD11 to the second capacitor CS12.

[0156] Moreover, the pixel 200 is constructed to include: an overflow path OVFP that can allow the charge overflowing from the photodiode PD11 to overflow toward the formation area of ​​the second capacitor CS12, an overflow gate element LO11-Tr formed on the overflow path OVFP and used to perform conduction control of the overflow path OVFP, and a source follower transistor SF11-Tr that amplifies and outputs the voltage signal converted in the floating diffusion layer FD11.

[0157] The pixel 200 of this first embodiment selectively connects the floating diffusion layer FD11 and the first capacitor CS11 via the first switching transistor LG11-Tr under the control of the reading unit 70, thereby changing the capacitance of the floating diffusion layer FD11 to the first capacitor or the second capacitor and switching the conversion gain of the floating diffusion layer FD11 to the first conversion gain (high conversion gain: HCG) determined by the first capacitor or the second conversion gain (medium conversion gain: MCG) determined by the second capacitor.

[0158] Moreover, in the pixel 200, under the control of the reading unit 70, the floating diffusion layer FD11 and the second capacitor CS12 are connected through the second switching transistor SG11-Tr, so that the capacitance of the floating diffusion layer FD11 can be changed to the third capacitor and the conversion gain can be switched to the third conversion gain (low conversion gain: LCG) determined by the third capacitor.

[0159] Like this, in this first embodiment, pixel 200 performs triple conversion gain reading, which performs a first conversion gain mode reading for reading pixel signals according to a first conversion gain corresponding to a first capacitor (e.g., high conversion gain: HCG), a second conversion gain mode reading for reading pixel signals according to a second conversion gain corresponding to a second capacitor (different from the first capacitor) (e.g., medium conversion gain: MCG), and a third conversion gain mode reading for reading pixel signals according to a third conversion gain corresponding to a third capacitor (e.g., low conversion gain: LCG), thereby achieving minimum SNR reduction at the mode-to-mode point without setting a split pixel.

[0160] In other words, according to the first embodiment, it is possible to suppress a decrease in the SNR at the connection point between signals having different conversion gains without being affected by optical specifications.

[0161] Furthermore, according to the first embodiment, the dynamic range can be expanded with a small pixel size by using a predetermined reading mode.

[0162] According to the first embodiment, a substantially higher dynamic range and a higher frame rate can be achieved.

[0163] Moreover, if Figure 8 As shown in (A) to (C) in the figure, according to the first embodiment, high dynamic range signals can be read using a linear response method, and high sensitivity / low noise signals can be read using HCG. This can prevent inter-pixel signal deviation caused by saturation fluctuations.

[0164] (Second embodiment)

[0165] Figure 9 This is a circuit diagram showing a configuration example of a readout pixel in a solid-state imaging device according to a second embodiment of the present invention.

[0166] Figure 10 (A) to (F) are timing charts for explaining an example of a read sequence in the dual conversion gain read mode and the overflow read mode for the pixel of the solid-state imaging device according to the second embodiment of the present invention.

[0167] Figure 11 (A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under low illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the second embodiment of the present invention.

[0168] Figure 12 (A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under medium illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the second embodiment of the present invention.

[0169] Figure 13 (A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under high illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the second embodiment of the present invention.

[0170] Figure 9 (A) in FIG. 1 represents the control signal RST of the reset transistor RST11-Tr. Figure 9 (B) in FIG. 1 represents the control signal R_RD of the third switching transistor R_RD11-Tr. Figure 9 (C) in FIG. 1 represents the control signal SG of the second switching transistor SG11-Tr. Figure 9 (D) in FIG. 1 represents the control signal LG of the first switching transistor LG11-Tr. Figure 9 (E) in FIG1 represents the control signal TG of the transmission transistor TG11-Tr. Figure 9 (F) in FIG. 1 represents the control signal LO of the overflow path transistor LO11 -Tr.

[0171] The pixel 200A of the solid-state imaging device 10A according to the second embodiment differs from the pixel 200 of the solid-state imaging device 10 according to the first embodiment described above in the following points.

[0172] In the pixel 200A of the solid-state imaging device 10A of the second embodiment, a third switching transistor R_RD11-Tr is connected between the connection node (second node) ND12 of the reset transistor RST11-Tr and the second switching transistor SG11-Tr and the floating diffusion layer FD11, serving as a third connection element selectively controlled to be in a conductive state and a non-conductive state by a control signal R_RD.

[0173] The third switching transistor R_RD11-Tr, such as Figure 10 As shown in (A) to (B) in FIG. 3 , in the first reset period, the reset transistor RST11 -Tr is switched to a high level in the same period as the control signal RST of the reset transistor RST11 -Tr, and is kept in an on state during this period.

[0174] In addition, the third switching transistor R_RD11-Tr, as shown Figure 10 As shown in (A) to (C) in FIG1 , when switching from the dual conversion gain reading mode to the LOFIC reading mode, the second switching transistor SG11 -Tr is switched to a high level at the same timing as the control signal SG and is kept in an on state.

[0175] Except for this configuration, in the solid-state imaging device 10A of the second embodiment, the read sequence in the dual conversion gain read mode and the overflow read mode for pixels is performed in the same manner as that of the solid-state imaging device of the first embodiment.

[0176] Therefore, detailed description thereof is omitted here.

[0177] The other configurations are the same as those of the first embodiment described above.

[0178] According to the second embodiment, the same effects as those of the first embodiment can be obtained, and the following effects can also be obtained.

[0179] In other words, according to this second embodiment, the floating diffusion FD11 and the second capacitor CS12 can be connected only during the setting period of the third conversion gain LCG. When the capacitance of the second capacitor CS12 is not necessary, unnecessary charge can be prevented from flowing into the floating diffusion FD11 and causing charge mixing (forming a false signal). This in turn reduces the number of adjacent transistors that determine the conversion gain of the floating diffusion FD11, making it possible to set the conversion gain with high precision.

[0180] (Third embodiment)

[0181] Figure 14 This is a circuit diagram showing a configuration example of a readout pixel in a solid-state imaging device according to a third embodiment of the present invention.

[0182] Figure 15 (A) to (D) are timing charts for explaining an example of a read sequence in the dual conversion gain read mode and the overflow read mode for pixels of the solid-state imaging device according to the third embodiment of the present invention.

[0183] Figure 16 (A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under low illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the third embodiment of the present invention.

[0184] Figure 17 (A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under medium illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the third embodiment of the present invention.

[0185] Figure 18 (A) to (H) are diagrams showing an operation sequence and potential transition for explaining the operation under high illumination in the dual conversion gain read mode and the overflow read mode of the pixel of the solid-state imaging device according to the third embodiment of the present invention.

[0186] Figure 14 (A) in FIG. 1 represents the control signal RST of the reset transistor RST11-Tr. Figure 14 (B) in FIG. 1 represents the control signal SG of the second switching transistor SG11-Tr. Figure 14 (C) in FIG. 1 represents the control signal LG of the first switching transistor LG11-Tr. Figure 14 (D) in FIG. 5 represents the control signal TG of the transfer transistor TG11 -Tr.

[0187] The pixel 200B of the solid-state imaging device 10B according to the third embodiment differs from the pixel 200 of the solid-state imaging device 10 according to the first embodiment described above in the following points.

[0188] In the pixel 200B of the solid-state imaging device 10B of the third embodiment, the overflow path transistor LO11-Tr as the overflow gate element and the second switching transistor SG11-Tr as the second connection element share the third node ND13 and the second node ND12.

[0189] Furthermore, the second switching transistor SG11 -Tr serving as a shared second connecting element is connected between the floating diffusion FD11 and the reset transistor RST11 -Tr serving as a reset element, and a connection node thereof forms a second node ND12 .

[0190] Furthermore, the second capacitor CS12 as a second capacitance element is connected to the second node ND12 which is a connection node between the second switching transistor SG11 -Tr as a second connection element and the reset transistor RST11 -Tr as a reset element.

[0191] Furthermore, the first switching transistor LO11 -Tr as a first connecting element and the first capacitor CS11 as a first capacitive element are connected in series between the floating diffusion FD11 connected to the first node ND11 and the reference potential VSS.

[0192] In the solid-state imaging device 10B of the third embodiment, as shown in FIG. Figure 15 As shown in (A) in FIG, the floating diffusion layer FD11 is not reset before the first read reset signal HCGRST is read, so the FD dark current charged in the floating diffusion layer FD11 cannot be completely removed (FD dark current exists).

[0193] As described above, although a slight FD dark current exists in the reading phase of the first read reset signal HCGRST, it can be removed by the CDS process.

[0194] Except for this configuration, in the solid-state imaging device 10B of the third embodiment, the read sequence in the dual conversion gain read mode and the overflow read mode for pixels is performed in the same manner as that of the solid-state imaging device of the first embodiment.

[0195] Therefore, detailed description thereof is omitted here.

[0196] The other configurations are the same as those of the first embodiment described above.

[0197] According to the third embodiment, the same effects as those of the first embodiment can be obtained, and the circuit configuration can be simplified.

[0198] (Fourth embodiment)

[0199] Figure 19 This is a circuit diagram showing a configuration example of a readout pixel in a solid-state imaging device according to a fourth embodiment of the present invention.

[0200] Figure 20 (A) to (D) are timing charts for explaining an example of a read sequence in the dual conversion gain read mode and the overflow read mode for pixels of the solid-state imaging device according to the fourth embodiment of the present invention.

[0201] Figure 21 (A) to (X) in FIG. 4 are diagrams showing an operation sequence and potential transition for explaining operations in the dual conversion gain read mode and the overflow read mode for the pixel of the solid-state imaging device according to the fourth embodiment of the present invention.

[0202] Figure 20 (A) in FIG. 1 represents the control signal RST of the reset transistor RST11-Tr. Figure 20 (B) in FIG. 1 represents the control signal SG of the second switching transistor SG11-Tr. Figure 20 (C) in FIG. 1 represents the control signal LG of the first switching transistor LG11-Tr. Figure 20 (D) in FIG. 5 represents the control signal TG of the transfer transistor TG11 -Tr.

[0203] The pixel 200C of the solid-state imaging device 10C according to the fourth embodiment differs from the pixel circuit 200B of the solid-state imaging device 10B according to the third embodiment described above in the following points.

[0204] In a pixel 200C of a solid-state imaging device 10C according to the fourth embodiment, a first switching transistor LG11-Tr, serving as a first connecting element, is connected in series between a floating diffusion FD11 and a second switching transistor SG11-Tr, serving as a second connecting element. Furthermore, a fourth node ND14 is formed by the connection node between the first switching transistor LG11-Tr, serving as the first connecting element, and the second switching transistor SG11-Tr, serving as the second connecting element.

[0205] Furthermore, the second switching transistor SG11 -Tr serving as a shared second connection element is connected between the second switching transistor SG11 -Tr serving as the second connection element and the reset transistor RST11 -Tr serving as the reset element, and a connection node thereof forms a second node ND12 .

[0206] Furthermore, the first capacitor CS11 as the first capacitance element is connected to the fourth node ND14 which is the connection node between the first switching transistor LG11 -Tr and the second switching transistor SG11 -Tr.

[0207] Furthermore, the second capacitor CS12 serving as a second capacitance element is connected to a second node ND12 which is a connection node between the second switching transistor SG11 -Tr and the reset transistor RST11 -Tr serving as a reset element.

[0208] In the solid-state imaging device 10C of the fourth embodiment, as shown in FIG. Figure 20 As shown in (A), the floating diffusion FD11 is not reset before the first read reset signal HCGRST is read. Therefore, the FD dark current flowing into the floating diffusion FD11 cannot be completely eliminated (FD dark current exists). In this way, although some FD dark current exists during the reading phase of the first read reset signal HCGRST, it can be eliminated through the CDS process.

[0209] Except for this configuration, in the solid-state imaging device 10C of the fourth embodiment, the read sequence in the dual conversion gain read mode and the overflow read mode for pixels is performed in the same manner as that of the solid-state imaging device of the first embodiment.

[0210] Therefore, detailed description thereof is omitted here.

[0211] The other configurations are the same as those of the third embodiment described above.

[0212] According to the fourth embodiment, the same effects as those of the third embodiment can be obtained, and the circuit configuration can be simplified.

[0213] (Fifth embodiment)

[0214] Figure 22This is a circuit diagram showing a configuration example of a pixel circuit of a solid-state imaging device 10D according to a fifth embodiment of the present invention.

[0215] The pixel 200D of the solid-state imaging device 10D according to the fifth embodiment differs from the pixel 200 of the solid-state imaging device 10 according to the first embodiment described above in the following points.

[0216] The solid-state imaging device 10D according to the fifth embodiment has a pixel sharing structure in which a plurality of (two in the present embodiment) adjacent pixels 200 - 1 and 200 - 2 share a floating diffusion layer FD11 .

[0217] In the solid-state imaging device 10D according to the fifth embodiment, adjacent pixels 200 - 1 and 200 - 2 share a first switching transistor LG11 -Tr as a first connection element and a first capacitor CS11 as a first capacitance element.

[0218] In addition, in the pixel sharing structure of this example, the source follower transistor SF11 -Tr and the selection transistor SEL11 -Tr are also shared.

[0219] The other configurations are the same as those of the first embodiment described above.

[0220] According to the fifth embodiment, the same effects as those of the first embodiment can be obtained, and the pixel size can be reduced and the circuit configuration can be further simplified.

[0221] (Application examples to electronic devices)

[0222] Furthermore, the solid-state imaging devices 10 , 10A, 10B, 10C, and 10D described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, portable terminals, surveillance cameras, and medical endoscope cameras.

[0223] Figure 23 This is a diagram showing an example of the configuration of an electronic device incorporating an imaging system to which the solid-state imaging device according to an embodiment of the present invention is applied.

[0224] like Figure 23 As shown, the electronic device 300 includes a CMOS image sensor 310 to which the solid-state imaging devices 10 , 10A, 10B, 10C, and 10D of the present embodiment can be applied.

[0225] Furthermore, the electronic device 300 includes an optical system (lens, etc.) 420 that guides incident light to the pixel region of the CMOS image sensor 310 (to form an image of a subject).

[0226] The electronic device 300 includes a signal processing circuit (PRC) 330 that processes an output signal of the CMOS image sensor 310 .

[0227] The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310 .

[0228] The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor including a liquid crystal display, or can be output to a printer. In addition, it can adopt various forms, such as being directly recorded on a storage medium such as a memory card.

[0229] As described above, by mounting the solid-state imaging devices 10 , 10A, 10B, 10C, and 10D as the CMOS image sensor 310 , a high-performance, compact, and low-cost imaging system can be provided.

[0230] Furthermore, the present invention can be used in electronic devices such as surveillance cameras and medical endoscope cameras, which have limitations on camera installation conditions such as installation size, number of connectable cables, cable length, and installation height.

[0231] Description of main component symbols

[0232] 10, 10A, 10B, 10C, 10D: Solid-state imaging devices

[0233] 20: Pixel Department

[0234] 200, 200A~200D, 200-1, 200-2: pixels

[0235] PD11: Photodiode

[0236] FD11: floating diffusion layer

[0237] TG11-Tr: Transfer transistor

[0238] RST11-Tr: Reset transistor

[0239] SF11-Tr: Source follower transistor

[0240] LG11-Tr: 1st switching transistor

[0241] SG11-Tr: 2nd switching transistor

[0242] CS11: Capacitor 1

[0243] CS12: Second capacitor

[0244] LO11-Tr: Overflow path transistor

[0245] 300: Electronic equipment

[0246] 310:CMOS image sensor

[0247] 320: Optical System

[0248] 330: Signal Processing Circuit (PRC)

Claims

1. A solid-state imaging device, characterized in that: comprising pixels that perform photoelectric conversion and can read signals corresponding to at least three conversion gains, The pixels include: a floating diffusion layer that holds the transferred charge and converts the charge into a voltage corresponding to the capacitance in order to read it as a voltage signal; The photoelectric conversion element accumulates charge corresponding to the amount of incident light during the exposure period; a transfer element that is kept in a non-conductive state during the exposure period and is kept in a conductive state during the transfer period and transfers the charge accumulated in the photoelectric conversion element to the floating diffusion layer; a reset element capable of performing a reset process of at least discharging accumulated charges of the floating diffusion layer; a first capacitance element controlled to be in a connected state or a disconnected state with respect to the floating diffusion layer according to a conversion gain; a first connecting element selectively connecting the floating diffusion layer and the first capacitor element; a second capacitor element capable of accumulating overflow charges from the photoelectric conversion element; a second connecting element selectively connecting the floating diffusion layer and the second capacitor element; an overflow path capable of causing the charge overflowing from the photoelectric conversion element to overflow toward the formation region of the second capacitor element; an overflow gate element formed on the overflow path for performing conduction control of the overflow path; The source follower element amplifies and outputs the voltage signal converted in the floating diffusion layer.

2. The solid-state imaging device according to claim 1, wherein The pixels include: The third connecting element selectively connects the second connecting element and the floating diffusion layer.

3. The solid-state imaging device according to claim 1, wherein The overflow gate element and the second connection element are shared, The shared second connection element is connected between the floating diffusion layer and the reset element. The second capacitive element is connected to a connection node between the second connecting element and the reset element. The first connection element and the first capacitance element are connected in series between the floating diffusion layer and a reference potential.

4. The solid-state imaging device according to claim 1, wherein The overflow gate element and the second connection element are shared, The first connecting element and the shared second connecting element are connected in series between the floating diffusion layer and the reset element. The first capacitance element is connected to a connection node between the first connection element and the second connection element, and the second capacitance element is connected to a connection node between the second connection element and the reset element.

5. The solid-state imaging device according to claim 1, wherein comprising a pixel portion in which a plurality of the pixels are arranged, The pixel portion comprises: In the pixel sharing structure, at least two adjacent pixels share the floating diffusion layer.

6. The solid-state imaging device according to claim 5, wherein the pixel portion, The reset element is shared by at least two adjacent pixels.

7. The solid-state imaging device according to claim 5, wherein the pixel portion, The first capacitive element and the first connecting element are shared by at least two adjacent pixels.

8. The solid-state imaging device according to any one of claims 1 to 7, wherein comprising: a pixel portion in which the pixels are arranged; and a reading section that reads a pixel signal from the pixel of the pixel section, The reading unit selectively connects the floating diffusion layer and the first capacitor element via the first connecting element, thereby changing the capacitance of the floating diffusion layer to the first capacitor or the second capacitor, and switching the conversion gain to a first conversion gain determined by the first capacitor or a second conversion gain determined by the second capacitor; The reading unit connects the floating diffusion layer and the second capacitance element via the second connection element, thereby changing the capacitance of the floating diffusion layer to a third capacitance and switching the conversion gain to a third conversion gain determined by the third capacitance.

9. The solid-state imaging device according to claim 8, wherein The reading section sequentially performs a second conversion gain reset reading process, a first conversion gain reset reading process, a first conversion gain signal reading process, and a second conversion gain signal reading process in a dual conversion gain reading mode. The reading section sequentially performs a third conversion gain signal reading process and a third conversion gain reset reading process in an overflow reading mode for overflow charges.

10. The solid-state imaging device according to claim 9, wherein The reading unit maintains the reset element, the first connecting element, the second connecting element, and the transfer element in a conductive state for a predetermined period, resets the photoelectric conversion element, the floating diffusion layer, the first capacitor element, and the second capacitor element, and sets the transfer element to a non-conductive state and starts an exposure period. The reading section sequentially performs the second conversion gain reset reading process, the first conversion gain reset reading process, the first conversion gain signal reading process, and the second conversion gain signal reading process as processing in the dual conversion gain reading mode. Next, the reading section sequentially performs the third conversion gain signal reading process and the third conversion gain reset reading process as processes in the overflow reading mode regarding the overflowing charge.

11. The solid-state imaging device according to claim 10, wherein The reading section performs a reset process of the floating diffusion layer by the reset element before the first conversion gain reset reading process in the dual conversion gain reading mode.

12. The solid-state imaging device according to claim 10, wherein The reading unit performs the following processing after a predetermined period has passed since the start of the exposure period: The second conversion gain reset read process switches the first connection element to an on state during a predetermined period and connects the first capacitor element to the floating diffusion layer, so that the charge of the floating diffusion layer and the charge of the first capacitor element are shared, thereby switching the gain of the floating diffusion layer to the second conversion gain determined by the second capacitor. During the first reset read period, a second read reset signal converted according to the second conversion gain determined by the second capacitor of the floating diffusion layer is read from the source follower element, and a predetermined process is performed on the second read reset signal. The first conversion gain reset read process switches the first connection element to a non-conductive state and disconnects the first capacitor element from the floating diffusion layer, thereby separating the charge of the floating diffusion layer from the charge of the first capacitor element, thereby switching the gain of the floating diffusion layer to the first conversion gain determined by the first capacitor; in a second reset read period following the first reset read period, reads a first read reset signal converted based on the first conversion gain determined by the first capacitor of the floating diffusion layer from the source follower element, and performs predetermined processing on the first read reset signal; The first conversion gain signal reading process reads a first read signal converted according to the first conversion gain determined by the first capacitance of the floating diffusion layer from the source follower element during a first reading period following the first transfer period after the second reset reading period, and performs a predetermined process on the first read signal; The second conversion gain signal reading process includes switching the first connection element to an on state and connecting the first capacitor element to the floating diffusion layer after the first conversion gain signal reading process, so that the charge of the floating diffusion layer is shared with the charge of the first capacitor element, thereby switching the gain of the floating diffusion layer to the second conversion gain determined by the second capacitor. In a second reading period following a second transfer period following the first reading period, a second reading signal converted according to the second conversion gain determined by the second capacitor of the floating diffusion layer is read from the source follower element, and a predetermined process is performed on the second reading signal. And it can also perform the following processing: The third conversion gain signal reading process includes, after the second conversion gain signal reading process, switching the second connection element to an on state and connecting the second capacitor element to the floating diffusion layer, so that the charge of the floating diffusion layer is shared with the charge of the first capacitor element and the second capacitor element, thereby switching the gain of the floating diffusion layer to the third conversion gain determined by the third capacitor element; in a third reading period following the second reading period, reading a third read signal converted according to the third conversion gain determined by the third capacitor element from the source follower element, and performing predetermined processing on the third read signal; The third conversion gain reset and read processing is to read a third read reset signal converted according to the third conversion gain determined by the third capacitance of the floating diffusion layer from the source follower element after the floating diffusion layer is reset by the reset element, and perform predetermined processing on the third read reset signal.

13. The solid-state imaging device according to claim 11, wherein The reading unit performs the following processing after a predetermined period has passed since the start of the exposure period: The second conversion gain reset read process switches the first connection element to an on state during a predetermined period and connects the first capacitor element to the floating diffusion layer, so that the charge of the floating diffusion layer is shared with the charge of the first capacitor element, thereby switching the gain of the floating diffusion layer to the second conversion gain determined by the second capacitor. After the floating diffusion layer is reset by the reset element, a second read reset signal converted according to the second conversion gain determined by the second capacitor of the floating diffusion layer is read from the source follower element during a first reset read period, and predetermined processing is performed on the second read reset signal. The first conversion gain reset read process switches the first connection element to a non-conductive state and disconnects the first capacitor element from the floating diffusion layer, thereby separating the charge of the floating diffusion layer from the charge of the first capacitor element, thereby switching the gain of the floating diffusion layer to the first conversion gain determined by the first capacitor; in a second reset read period following the first reset read period after the reset process, a first read reset signal converted based on the first conversion gain determined by the first capacitor of the floating diffusion layer is read from the source follower element, and a predetermined process is performed on the first read reset signal; The first conversion gain signal reading process reads a first read signal converted according to the first conversion gain determined by the first capacitance of the floating diffusion layer from the source follower element in a first reading period following the first transfer period after the second reset reading period, and performs a predetermined process on the first read signal; The second conversion gain signal reading process includes switching the first connection element to an on state and connecting the first capacitor element to the floating diffusion layer after the first conversion gain signal reading process, so that the charge of the floating diffusion layer is shared with the charge of the first capacitor element, thereby switching the gain of the floating diffusion layer to the second conversion gain determined by the second capacitor. In a second reading period following a second transfer period following the first reading period, a second reading signal converted according to the second conversion gain determined by the second capacitor of the floating diffusion layer is read from the source follower element, and a predetermined process is performed on the second reading signal. And it can also perform the following processing: The third conversion gain signal reading process includes, after the second conversion gain signal reading process, switching the second connection element to an on state and connecting the second capacitor element to the floating diffusion layer, so that the charge of the floating diffusion layer is shared with the charge of the first capacitor element and the second capacitor element, thereby switching the gain of the floating diffusion layer to the third conversion gain determined by the third capacitor element; in a third reading period following the second reading period, reading a third read signal converted according to the third conversion gain determined by the third capacitor element from the source follower element, and performing predetermined processing on the third read signal; as well as The third conversion gain reset read process is to read a third read reset signal converted according to the third conversion gain determined by the second capacitance of the floating diffusion layer from the source follower element after the floating diffusion layer is reset by the reset element, and perform predetermined processing on the third read reset signal.

14. The solid-state imaging device according to claim 12 or 13, wherein: The reading section executes the second conversion gain reset reading process and the first conversion gain reset reading process during the exposure period.

15. A method for driving a solid-state imaging device, characterized in that: The solid-state imaging device includes pixels that perform photoelectric conversion and can read signals corresponding to at least three conversion gains. The pixels include: a floating diffusion layer that holds the transferred charge and converts the charge into a voltage corresponding to the capacitance in order to read it as a voltage signal; The photoelectric conversion element accumulates charge corresponding to the amount of incident light during the exposure period; a transfer element that is kept in a non-conductive state during the exposure period and is kept in a conductive state during the transfer period and transfers the charge accumulated in the photoelectric conversion element to the floating diffusion layer; a reset element capable of performing a reset process of at least discharging accumulated charges of the floating diffusion layer; a first capacitance element controlled to be in a connected state or a disconnected state with respect to the floating diffusion layer according to a conversion gain; a first connecting element selectively connecting the floating diffusion layer and the first capacitor element; a second capacitor element capable of accumulating overflow charges from the photoelectric conversion element; a second connecting element selectively connecting the floating diffusion layer and the second capacitor element; an overflow path capable of causing the charge overflowing from the photoelectric conversion element to overflow toward the formation region of the second capacitor element; an overflow gate element formed on the overflow path for performing conduction control of the overflow path; The source follower element amplifies and outputs the voltage signal converted in the floating diffusion layer. selectively connecting the floating diffusion layer and the first capacitor element via the first connecting element, thereby changing the capacitance of the floating diffusion layer to the first capacitor or the second capacitor, and switching the conversion gain to a first conversion gain determined by the first capacitor or a second conversion gain determined by the second capacitor; The floating diffusion layer and the second capacitor are connected via the second connecting element. Therefore, the capacitance of the floating diffusion layer can be changed to the third capacitance, and the conversion gain can be switched to the third conversion gain determined by the third capacitance.

16. An electronic device, characterized in that include: a solid-state imaging device; and an optical system for forming an image of a subject on the solid-state imaging device, The solid-state imaging device includes pixels that perform photoelectric conversion and can read signals corresponding to at least three conversion gains. The pixels include: a floating diffusion layer that holds the transferred charge and converts the charge into a voltage corresponding to the capacitance in order to read it as a voltage signal; The photoelectric conversion element accumulates charge corresponding to the amount of incident light during the exposure period; a transfer element that is kept in a non-conductive state during the exposure period and is kept in a conductive state during the transfer period and transfers the charge accumulated in the photoelectric conversion element to the floating diffusion layer; a reset element capable of performing a reset process of at least discharging accumulated charges of the floating diffusion layer; a first capacitance element controlled to be in a connected state or a disconnected state with respect to the floating diffusion layer according to a conversion gain; a first connecting element selectively connecting the floating diffusion layer and the first capacitor element; a second capacitor element capable of accumulating overflow charges from the photoelectric conversion element; a second connecting element selectively connecting the floating diffusion layer and the second capacitor element; an overflow path capable of causing the charge overflowing from the photoelectric conversion element to overflow toward the formation region of the second capacitor element; an overflow gate element formed on the overflow path for performing conduction control of the overflow path; The source follower element amplifies and outputs the voltage signal converted in the floating diffusion layer.

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