Cap stacking for high frequency processing

Abstract

An exemplary semiconductor processing chamber may include a substrate support positioned within a processing region of the semiconductor processing chamber. The chamber may include a cover plate. The chamber may include a gas box positioned between the cover plate and the substrate support. The gas box may be characterized by a first surface and a second surface opposite the first surface. The gas box may define a central hole. The gas box may define an annular channel in the first surface of the gas box, the annular channel extending through the gas box around the central hole. The gas box may include an annular outer cover extending across the annular channel defined in the first surface of the gas box. The chamber may include a baffle plate positioned between the gas box and the substrate support. The chamber may include a ferrite block positioned between the cover plate and the baffle plate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 16 / 844,089, filed on April 9, 2020, entitled “LID STACK FOR HIGH FREQUENCY PROCESSING,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present technology relates to components and equipment used to manufacture semiconductors. More specifically, the present technology relates to process chamber distribution components and other semiconductor processing equipment. Background Art

[0004] The manufacture of integrated circuits is made possible by processes that produce intricately patterned layers of material on a substrate surface. Producing patterned material on a substrate requires controlled methods for forming and removing materials. Chamber components typically deliver process gases to a substrate to deposit a film or remove material. The process gas may be plasma enhanced to increase the reactivity of the produced effluent. However, depending on the aspect of the plasma enhancement, the material may not be uniformly deposited on the substrate.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology addresses these and other needs. Summary of the invention

[0006] An exemplary semiconductor processing chamber may include a substrate support positioned within a processing region of the semiconductor processing chamber. The chamber may include a cover plate. The chamber may include a gas box positioned between the cover plate and the substrate support. The gas box may be characterized by a first surface and a second surface opposite the first surface. The gas box may define a central hole. The gas box may define an annular channel in the first surface of the gas box, the annular channel extending through the gas box around the central hole. The gas box may define a recessed ledge extending around the annular channel in the first surface of the gas box. The gas box may include an annular cover disposed on the recessed ledge and extending across the annular channel defined in the first surface of the gas box. The chamber may include a baffle plate positioned between the gas box and the substrate support. The chamber may include a ferrite block positioned between the cover plate and the baffle plate. The chamber may include a panel positioned between the baffle plate and the substrate support.

[0007] In some embodiments, the ferrite block may be characterized by an annular shape extending around a central hole of the air box. The chamber may include an insulator positioned between the air box and the cover plate. The insulator may define a central hole that is axially aligned with a central hole defined through the air box, and the ferrite block may extend around the insulator. The ferrite block may be or include a plurality of blocks extending around the air box. The ferrite block may be disposed in a dielectric material. The dielectric material may be characterized by a dielectric constant less than or about 3.7. The dielectric material may be or include polytetrafluoroethylene or polyetheretherketone. The air box may define a second annular channel within the air box, and the ferrite block may be disposed in the second annular channel. The dielectric spacer may be positioned on the ferrite block disposed in the second annular channel. The dielectric spacer may define a recess within the dielectric spacer, and the outer cover may be disposed in the recess within the dielectric spacer. The dielectric spacer may form a vertical spacing between the outer cover and the ferrite block, and the dielectric spacer may form a radial gap between the outer cover and the air box.

[0008] Some embodiments of the present technology may encompass a semiconductor processing chamber including a substrate support positioned within a processing region of the semiconductor processing chamber. The chamber may include a cover plate. The chamber may include a gas box positioned between the cover plate and the substrate support. The gas box may be characterized by a first surface and a second surface opposite the first surface. The gas box may define a central hole. The gas box may define an annular channel in the first surface of the gas box, the annular channel extending through the gas box around the central hole. The gas box may define a recessed ledge extending around the annular channel in the first surface of the gas box. The gas box may include an annular cover disposed on the recessed ledge and extending across the annular channel defined in the first surface of the gas box. The chamber may include a ferrite block positioned between the cover plate and the gas box. The chamber may include a baffle plate positioned between the gas box and the substrate support. The chamber may include a panel positioned between the baffle plate and the substrate support.

[0009] In some embodiments, the ferrite block may be characterized by an annular shape extending around a central hole of the air box. The chamber may include an insulator positioned between the air box and the cover plate. The insulator may define a central hole that is axially aligned with a central hole defined through the air box, and the ferrite block may extend around the insulator. The ferrite block may include a plurality of blocks extending around the air box. The ferrite block may be disposed within a dielectric material. The dielectric material may be or include polytetrafluoroethylene or polyetheretherketone.

[0010] Some embodiments of the present technology may include a semiconductor processing chamber gas box. The gas box may be characterized by a first surface and a second surface opposite the first surface. The gas box may define a central hole. The gas box may define an annular channel in the first surface of the gas box, the annular channel extending through the gas box around the central hole. The gas box may include a ferrite block, the ferrite block disposed in the annular channel. The gas box may include a dielectric spacer disposed on the ferrite block. The gas box may include a cover disposed on the dielectric spacer.

[0011] In some embodiments, the dielectric spacer may define a recess in a surface of the dielectric spacer opposite to a surface contacting the ferrite block. The housing may be seated in the recess. The dielectric spacer may form a vertical spacing between the housing and the ferrite block, and the dielectric spacer may form a radial gap between the housing and the gas box. The ferrite block may include a plurality of blocks extending around the annular channel in the first surface of the gas box.

[0012] This technology can provide several benefits over conventional systems and techniques. For example, embodiments of the present technology can allow the use of higher frequency power in plasma processing. In addition, based on the control of the standing wave effect generated by the high frequency plasma, the chamber can improve the uniformity of deposition. These and other embodiments (and many of their advantages and features) are described in more detail in conjunction with the following description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The nature and advantages of the disclosed technology may be further understood by referring to the remainder of the specification and the accompanying drawings.

[0014] Figure 1 A top view of an exemplary processing system in accordance with some embodiments of the present technology is shown.

[0015] Figure 2 A schematic cross-sectional view of an exemplary plasma system according to some embodiments of the present technology is shown.

[0016] Figure 3 A schematic partial cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown.

[0017] Figure 4 A schematic cross-sectional view of an exemplary airbox is shown in accordance with some embodiments of the present technology.

[0018] Figure 5A A schematic top view of an exemplary ferrite block in accordance with some embodiments of the present technology is shown.

[0019] Figure 5B A schematic top view of an exemplary ferrite block in accordance with some embodiments of the present technology is shown.

[0020] Figure 6 Operations of an exemplary method of semiconductor processing in accordance with some embodiments of the present technology are illustrated.

[0021] Several drawings are included as schematic illustrations. It should be understood that the drawings are for illustration purposes and should not be considered to be in actual size proportions unless specifically stated to be so. Furthermore, as schematic illustrations, the drawings are provided to aid understanding and may not include all aspects or information as compared to actual presentation and may include content that is exaggerated for illustrative purposes.

[0022] In the accompanying drawings, similar components and / or features may have the same reference numerals. In addition, individual components of the same type may be distinguished by a letter following the reference numeral, which distinguishes similar components. If only the first reference numeral is used in the specification, its description may apply to any of the similar components having the same first reference numeral, regardless of its letter. DETAILED DESCRIPTION

[0023] Plasma enhanced deposition processes can energize one or more component precursors to promote film formation on a substrate. Any number of material films can be produced to develop semiconductor structures, including conductive films and dielectric films, as well as films that facilitate material transfer and removal. For example, in 3D NAND manufacturing, a set of material layers can be first deposited before forming individual memory cells within the structure. The structure can include alternating layers of placeholder materials and dielectric materials. The formation of these layers can be performed in a single processing chamber, where purge operations performed between material formations can protect the integrity of each layer formed.

[0024] As technology continues to expand, the number of storage cells can be increased by increasing the number of layer pairs initially formed. For example, more than 20, more than 50, more than 100, or more than 150 pairs of material layers can be initially deposited on a substrate. This amount of processing to form the initially deposited layers can be time-consuming, which can increase manufacturing costs. Many plasma processes are performed at about 13 MHz, which provides a certain deposition rate for each layer. Increasing to ultra-high frequency ("VHF") processing, such as greater than or about 27 MHz, greater than or about 40 MHz or greater, can increase the plasma density, thereby increasing the deposition rate. However, based on the inhomogeneity of the plasma generated at these frequencies, VHF processing may reduce the uniformity of the deposited material. For example, VHF plasma may include an inherent standing wave effect generated by the VHF current used to form the plasma. The standing wave effect in the electromagnetic field formed above the substrate being processed may cause the formed plasma to bend toward the substrate. This bending may occur near the edge of the substrate, which may result in differences in ion trajectories and energies across the plasma, and some areas of the volume may not substantially contain plasma, so the deposition rate is low, or there is no deposition.

[0025] In some 3D NAND stacks, pairs of initially deposited layers may include alternating layers of, for example, oxides and nitrides, and while oxide deposition may be more affected by temperature or gas flow, nitrides may be more sensitive to plasma density or RF voltage. Therefore, compromising processing conditions in conventional techniques may not be feasible because the effects implemented to improve deposition of one film may have an opposite effect on another film to be deposited. The present technology overcomes these challenges by utilizing one or more chamber components that can improve the uniformity of deposition by controlling the standing wave effect generated by the VHF plasma. By incorporating ferrite structures into the processing chamber, the RF current applied to the plasma can be adjusted to reduce the effects of the plasma voltage. Ferrites can have an effect on the RF field and plasma distribution, and can redistribute the flux more evenly throughout the volume. As a result, improved film formation can occur, and deposition uniformity can be improved at higher deposition rates promoted by VHF plasma.

[0026] Although the remainder of the disclosure will routinely identify specific deposition processes utilizing the disclosed techniques, it will be readily appreciated that the systems and methods are equally applicable to other deposition and cleaning chambers, and processes that may occur in the chambers. Therefore, the techniques should not be considered limited to use with only these specific deposition processes or chambers. Prior to describing additional variations and adjustments to the system in accordance with embodiments of the present technology, the present disclosure will discuss one possible system and chamber that may include a cover stack component in accordance with specific embodiments of the present technology.

[0027] Figure 1 A top view of one embodiment of a processing system 100 having deposition, etching, baking and curing chambers according to an embodiment is shown. In the figure, a pair of front-opening wafer pods 102 supply substrates of various sizes, which are received by a robot 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f located in the tandem sections 109a-c. A second robot 110 may be used to transport substrate wafers back and forth between the holding area 106 and the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f may be configured to perform various substrate processing operations, including forming stacks of semiconductor materials as described herein, as well as plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and other substrate processing, including annealing, ashing, and the like.

[0028] The substrate processing chambers 108a-f may include one or more system components to deposit, anneal, cure, and / or etch dielectric or other films on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit dielectric material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit a stack of alternating dielectric films on a substrate. Any one or more of the described processes may be performed in one or more chambers separate from the manufacturing system shown in different embodiments. It will be appreciated that the system 100 contemplates additional configurations of deposition, etching, annealing, and curing chambers for dielectric films.

[0029] Figure 2 A schematic cross-sectional view of an exemplary plasma system 200 according to some embodiments of the present technology is shown. The plasma system 200 can show a pair of processing chambers 108 that can be assembled in one or more of the series sections 109 described above and can include a lid stack component according to embodiments of the present technology, and as further explained below. The plasma system 200 can generally include a chamber body 202 having a sidewall 212, a bottom wall 216, and an inner sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B can be similarly configured and can include the same components.

[0030] For example, the processing region 220B (components of the processing region 220B may also be included in the processing region 220A) may include a pedestal 228 disposed in the processing region through a channel 222 formed in the bottom wall 216 in the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface (e.g., a body portion) of the pedestal. The pedestal 228 may include a heating element 232, such as a resistive heating element, which may heat and control the temperature of the substrate at a desired processing temperature. The pedestal 228 may also be heated by a remote heating element, such as a lamp assembly or any other heating device.

[0031] The body of the base 228 can be coupled to the guide rod 226 by the flange 233. The guide rod 226 can electrically couple the base 228 to a power outlet or power box 203. The power box 203 can include a drive system that controls the lifting and movement of the base 228 within the processing area 220B. The guide rod 226 can also include a power interface to provide power to the base 228. The power box 203 can also include an interface for electrical power and temperature indicators, such as a thermocouple interface. The guide rod 226 can include a base assembly 238 suitable for removably coupling with the power box 203. The circumferential ring 235 is shown as being above the power box 203. In some embodiments, the circumferential ring 235 can be a shoulder suitable for acting as a mechanical stop or platform, and the shoulder is configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power box 203.

[0032] Rods 230 may be included through channels 224 formed in the bottom wall 216 of the processing region 220B and may be used to position substrate lift pins 261 disposed through the body of the pedestal 228. The substrate lift pins 261 may selectively space the substrate 229 from the pedestal to facilitate replacement of the substrate 229 by a robot for transferring the substrate 229 into and out of the processing region 220B through the substrate transfer port 260.

[0033] The chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 may house one or more precursor dispensing systems 208 coupled to the lid 204. The precursor dispensing system 208 may include a precursor inlet channel 240 that may deliver reactants and cleaning precursors through a dual channel showerhead 218 into the processing region 220B. The dual channel showerhead 218 may include an annular base plate 248 having a baffle plate 244 disposed between the annular base plate 248 and a face plate 246. A radio frequency ("RF") source 265 may be coupled to the dual channel showerhead 218, and the RF source 265 may power the dual channel showerhead 218 to facilitate the generation of a plasma region between the face plate 246 and the pedestal 228 of the dual channel showerhead 218. In some embodiments, the RF source may be coupled to other portions of the chamber body 202, such as the pedestal 228, to facilitate the generation of a plasma. A dielectric isolator 258 may be disposed between the cover 204 and the dual channel showerhead 218 to prevent conduction of RF power to the cover 204. A shadow ring 206 may be disposed on the periphery of the pedestal 228 that engages the pedestal 228.

[0034] An optional cooling channel 247 may be formed in the annular base plate 248 of the precursor distribution system 208 to cool the annular base plate 248 during operation. A heat transfer fluid (such as water, glycol, gas, etc.) may be circulated through the cooling channel 247 so that the base plate 248 is maintained at a predetermined temperature. The liner assembly 227 is disposed within the processing region 220B and in close proximity to the sidewalls 201, 212 of the chamber body 202 to prevent the sidewalls 201, 212 from being exposed to the processing environment within the processing region 220B. The liner assembly 227 may include a circumferential pump cavity 225 coupled to a pump system 264, which is configured to exhaust gases and byproducts from the processing region 220B and control the pressure within the processing region 220B. A plurality of exhaust ports 231 may be formed on the chamber liner assembly 227. The exhaust port 231 is configured to allow gas to flow from the processing region 220B to the circumferential pump cavity 225 in a manner that facilitates processing within the system 200 .

[0035] Figure 3 A schematic partial cross-sectional view of an exemplary semiconductor processing chamber 300 is shown in accordance with some embodiments of the present technology. Figure 3 This may include the above Figure 2 One or more components discussed above may be shown, and more details related to the chamber may be shown. In some embodiments, chamber 300 is understood to include any features or aspects of system 200 previously discussed. Chamber 300 may be used to perform semiconductor processing operations, including deposition of materials as previously described (e.g., 3D NAND stacking), as well as other deposition, removal, and cleaning operations. Chamber 300 may show a partial view of a processing area of ​​a semiconductor processing system, and may not include all components, such as the remote plasma unit previously illustrated, which should be understood to be incorporated into some embodiments of chamber 300.

[0036] As mentioned above, Figure 3A portion of a processing chamber 300 may be shown. The chamber 300 may include a plurality of lid stack components that may facilitate the transfer or distribution of materials through the processing chamber into a processing region 305, such as a substrate 306 that may be positioned in an area on a base 310. A chamber lid plate 315 may extend across one or more plates of the lid stack and may provide structural support for components such as a remote plasma unit previously shown for the system 200. The lid plate 315 may provide access to the interior space of the processing chamber 300, such as through a hole. An inlet manifold 320 may be positioned on the lid plate and may provide coupling to a remote plasma unit, which may provide precursors or plasma effluents for chamber cleaning or other processing operations. The inlet manifold 320 may define a central aperture 322 that may extend around a central axis of the chamber or inlet manifold. The processing chamber 300 may also include an insulator 325 that may electrically and / or thermally isolate the inlet manifold from other lid stack components. The insulator 325 may further define a central bore 327, which may be axially aligned with the central bore 322 of the inlet manifold 320. The processing chamber 300 may further include a gas box 330 on which the insulator may be positioned.

[0037] The gas box 330 is characterized by a first surface 331 and a second surface 332 that can be opposite to the first surface. The gas box can define a central hole 333 that can extend completely through the gas box from the first surface to the second surface. The central hole 333 can be axially aligned with the central hole of the inlet manifold 320 and can be axially aligned with the central hole of the insulator 325. The hole can define a channel that can be used at least in part to transport plasma effluent from a remote plasma unit located on the inlet manifold.

[0038] The airbox 330 may include additional features. For example, the airbox 330 may define an annular channel 340 that may allow a cooling fluid to flow around the airbox and may allow for additional temperature control. As shown, the annular channel 340 may be defined in a first surface 331 of the airbox 330. The annular channel 340 may extend around a central hole 333 and may also be concentric with the central hole. An outer cover 342 may extend around the cooling channel to form an airtight seal. For example, the airbox may define a recessed ledge 341 in the first surface 331 of the airbox that extends around the annular channel. The outer cover 342, which may be characterized by an annular or other geometric shape, may be placed on the recessed ledge around the annular channel.

[0039] In some embodiments, semiconductor processing chamber 300 may also include additional components, such as baffle plate 350 and faceplate 355. Baffle plate 350 may define a plurality of holes that may be used as throttles to increase radial diffusion to improve uniformity of delivery. As shown, volume 352 may be formed or defined between gas box 330 and baffle plate 350, which may allow a certain amount of lateral or radial diffusion of the precursor before extending through the baffle plate. Faceplate 355 may then deliver the precursor to a processing region that may be at least partially defined from above by the faceplate.

[0040] As shown, the gas box 330 can be electrically coupled to the baffle plate 350 and the panel 355, which can be used as plasma generation electrodes. In some embodiments, the components of the cover stack can be used as electrodes for generating plasma, such as hot electrodes. A power source such as the previously described RF source 265 can deliver power to the cover stack components, which can be electrically coupled to each other. For example, in some embodiments, the RF source can be coupled to the gas box, which can distribute power to the panel 355, where plasma can be generated in the processing area 305. In some embodiments, the RF source can deliver power at any number of frequencies, and in some embodiments can deliver power at high or ultra-high frequencies, such as greater than or about 20 MHz, such as 27 MHz, greater than or equal to 40 MHz, greater than or about 60 MHz or higher. Unlike conventional techniques that may produce non-uniform plasma when operating at these frequencies, the present technology can incorporate components or be configured to improve the effects of VHF plasma power, which can produce more uniform plasma and deposition compared to conventional techniques.

[0041] For example, in some embodiments, the present technology may incorporate a ferrite block 360 into the cover stack. In some embodiments, the ferrite block may be included in or associated with the air box. For example, in some embodiments, the ferrite block 360 may be positioned between the cover plate 315 and the baffle plate 350, and may be positioned in association with the air box 330. The ferrite block 360 may be in direct contact with the air box 330, such as being directly disposed on the first surface 331 and / or the outer cover 342, or may be included in the dielectric material 362, as shown. As will be further described below, the ferrite block may also be incorporated into the air box. The ferrite block 360 may be characterized as annular, and may also extend around the central hole 333 of the air box 330 as shown. The ferrite block may also be positioned to extend around the insulator 325. In additional embodiments shown, the ferrite blocks may also be positioned to be disposed above or below the panel, for example, ferrite block 365a may be disposed above the panel around the baffle, or ferrite block 365b may be disposed below the panel and in contact with the panel. Although block 365 may not be included in some embodiments, one or both of ferrite blocks 365a, 365b may be incorporated with ferrite block 360 in embodiments of the present technology.

[0042] The dielectric material 362 can be any dielectric material into which the ferrite block 360 can be incorporated. For example, the dielectric material 362 can improve the structural integrity of the more fragile ferrite material and can affect the distribution of the field through the material. Therefore, the dielectric material 362 can be selected based on the dielectric constant of the material or based on the mechanical properties of the material. For example, although ceramic or quartz materials can be used in some embodiments, these materials can similarly be more fragile and easily damaged. In addition, these materials can be characterized by a higher dielectric constant, which can overcompensate for the effect on the plasma, which can further adjust the field effect and reduce the uniformity of the plasma by further reducing the center profile, while increasing the non-uniformity of the deposition. Thus, in some embodiments, the dielectric material can be or include a material characterized by a dielectric constant of less than or about 3.8, and can be less than or about 3.7, less than or about 3.6, less than or about 3.5, less than or about 3.4, less than or about 3.3, less than or about 3.2, less than or about 3.1, less than or about 3.0, less than or about 2.9, less than or about 2.8, less than or about 2.7, less than or about 2.6, less than or about 2.5, less than or about 2.4, less than or about 2.3, less than or about 2.2, less than or about 2.1, or less. Exemplary materials that can provide mechanical support for the ferrite as well as a lower dielectric constant can be polytetrafluoroethylene, polyetheretherketone or other polyaryletherketones, and any other material that provides similar properties.

[0043] The ferrite block 360 may be or include a ferrite material, which may be or include iron, steel, nickel and / or zinc alloys, and any other number of materials or material combinations including ferromagnetic ceramic oxides for high frequency applications. The ferrite block 360 may have ferromagnetic properties that may modulate the magnetic field component of the electromagnetic field induced by the RF current flowing through the cover stack component. The ferrite block may reduce or eliminate the magnetic field component of the electromagnetic field along a vertical direction through the chamber. The standing wave pattern in this vertical direction may then extend outside the ferrite block and may narrow inside the ferrite block. This may facilitate redistribution of the plasma flux, which may affect the plasma profile within the processing region of the chamber. For example, as previously described, due to the stronger plasma voltage effect, nitride deposition may occur with greater non-uniformity, which may result in a deposit that may have a much greater central thickness and a radial profile across the substrate. By modulating the VHF plasma by doping ferrites as described throughout this disclosure, the electric field can be spread out from the center, which can cause the plasma to similarly spread out further from the center and can reduce the center high deposition. With the increase in radial uniformity of the plasma within the processing region 305, the non-uniformity of deposition can also be reduced, thereby improving the overall deposition process.

[0044] Figure 4 A schematic cross-sectional view of an exemplary gas box 330 according to some embodiments of the present technology is shown. This figure may show additional details of the gas box to illustrate the incorporation of a ferrite block within the gas box 330. As previously described, the gas box 330 may be characterized by a first surface 331, such as facing the inlet manifold. The gas box 330 may also be characterized by a second surface 332 opposite the first surface, which may, for example, face the processing area. The gas box 330 may define a central hole 333 and may define an annular channel 340, which may be defined in the first surface 331 as previously described. An outer cover 342 may be coupled to the gas box to seal the annular channel 340, which in some embodiments may allow a cooling fluid to flow through the channel. The gas box 330 may also define a second annular channel 405 within the first surface 331, and the ferrite block 360 may be disposed in the second annular channel 405. Second annular passage 405 may be formed around central bore 333 and may be radially inward from first annular passage 340 as shown, although the positions of the passages may be reversed. However, in some embodiments, improved cooling may be provided across the airbox by including annular passage 340 radially outward of the second annular passage.

[0045] In some embodiments, the gas box 330 may be or include a conductive material that may facilitate electrical operation of the gas box as part of a powered electrode. Thus, in some embodiments, a dielectric spacer 410 may be included that is disposed above the ferrite block 360. If the ferrite is completely contained within the gas box, the gas box may effectively shield the ferrite and limit or prevent any interaction with the RF field. In some embodiments, the cover 415 may be located above the dielectric spacer. In some embodiments, the dielectric spacer 410 may form a gap between the cover 415 and the gas box, and between the cover 415 and the ferrite block 360. For example, the dielectric spacer 410 may define a recess in which the cover 415 may be disposed. A radial gap may then be formed between the gas box and the inner annular surface and / or the outer annular surface of the cover 415. Thus, in some embodiments, the cover 415 may not directly contact the ferrite block 360 or the gas box 330. Additionally, in some embodiments, the cover 415 may include tabs or may extend radially along one side to the airbox to allow coupling of components. The dielectric spacer 410 may be any material previously described, and in some embodiments, the resulting gap may be at least about 1 mm, and may be greater than or about 2 mm, greater than or about 3 mm, greater than or about 4 mm, greater than or about 5 mm, greater than or about 6 mm, greater than or about 7 mm, or greater. Although a ferrite block is shown below the dielectric spacer, in some embodiments, as previously described, the spacer may be part of the dielectric material surrounding the ferrite block. The first surface of the dielectric material may extend further from the ferrite surface to form a recess, and the cover 415 may be placed in the recess.

[0046] Figure 5A and Figure 5B Schematic top views of exemplary ferrite blocks 360a and ferrite blocks 360b are shown in accordance with some embodiments of the present technology. These blocks may include any features, components, or characteristics of the ferrite blocks previously described, and exemplary ferrite blocks that may be combined with a processing chamber in accordance with some embodiments of the present technology may be shown. Ferrite block 360a shows an embodiment utilizing a single annular ferrite block, which may be included in a dielectric material 362, as previously described. Ferrite block 360b shows an embodiment utilizing multiple ferrite blocks and the multiple ferrite blocks may be included in a dielectric material 362 (e.g., formed around an annular shape). It should be understood that any number of ferrite blocks may be utilized in embodiments of the present technology and may be characterized by any number of shapes.

[0047] Figure 6Operations of an exemplary method 600 of semiconductor processing according to some embodiments of the present technology are shown. The method can be performed in various processing chambers, including the processing system 200 described above, or the chamber 300, which can include a gas box according to embodiments of the present technology, such as the gas box 330. The method 600 can include a number of optional operations, which may or may not be specifically related to some embodiments of the method according to the present technology.

[0048] Method 600 may include a processing method that may include operations for forming material films at high frequencies or other deposition operations, such as producing stacks of 3D NAND films, which may be formed at higher deposition rates and may be produced with higher deposition uniformity relative to conventional processing. The method may include optional operations before method 600 is started, or the method may include additional operations. For example, method 600 may include operations performed in a different order than that shown. In some embodiments, method 600 may include flowing one or more precursors into a processing chamber at operation 605. For example, before the precursors are delivered to a processing area of ​​a chamber (e.g., included in system 200), the precursors may be flowed into the chamber and then flowed through one or more of a gas box, a baffle, or a panel as described above.

[0049] In some embodiments, the precursor may be or include a nitrogen-containing precursor for depositing a nitride layer, such as in conjunction with an operation to deposit an oxide layer using an oxygen-containing precursor. In some embodiments, a ferrite block may be included in association with the gas box, or incorporated into the gas box as previously described. Any other features of the aforementioned gas box may also be included, including any aspects of the gas box 330. In operation 610, a plasma of the precursor may be generated in the processing region, for example, by providing RF power to a panel to generate the plasma. The plasma may be generated at any frequency previously described, such as greater than or about 27 MHz, greater than or about 40 MHz, or higher. In operation 615, the material formed in the plasma may be deposited on the substrate. In some embodiments, depending on the thickness of the deposited material, the deposited material may be characterized in that the thickness at the center of the substrate is approximately 10% or within 10% greater than the thickness near the middle or edge region along the radius of the substrate.

[0050] Additionally, the thickness at the center of the substrate may be within about 9% greater than or about 9% of the thickness near the middle or edge region along the radius of the substrate, and may be within about 8% greater than or about 8%, within about 7% greater than or about 7%, within about 6% greater than or about 6%, within about 5% greater than or about 5%, within about 4% greater than or about 4%, within about 3% greater than or about 3%, within about 2% greater than or about 2%, within about 1% greater than or about 1%, or may be substantially similar or uniform at various locations along the substrate. According to some embodiments of the present technology, by utilizing ferrite blocks with a high frequency plasma deposition process, the deposition rate may be more than 50% higher than deposition performed at a lower frequency, while the uniformity of the plasma and deposition may be improved compared to conventional processes.

[0051] In the above description, for the purpose of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these specific details or with additional details.

[0052] After several embodiments have been disclosed, those skilled in the art will appreciate that various modifications, alternative structures, and equivalents may be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements are not described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be considered to limit the scope of the present technology.

[0053] Where a numerical range is provided, it is understood that, unless the context clearly dictates otherwise, each intermediate value between the upper and lower limits of this range is also specifically disclosed, to the smallest decimal of the lower limit unit. Any narrower range between any stated value or unstated intermediate value within the range is included with any other stated or intermediate value within the range. The upper and lower limits of these smaller ranges may be independently included or excluded within this range, and each range in the smaller range that includes one, both, or neither of the upper and lower limits is also included in the present technology, and is subject to any specifically excluded limitations in the stated range. When the stated range includes one or both of the upper and lower limits, the range that excludes either or both of these upper and lower limits is also included.

[0054] As used in the specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a block" includes a plurality of such blocks and reference to "the precursor" includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

[0055] Furthermore, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including” as used in this specification and the appended claims are meant to specify the presence of stated features, integers, components, or operations, but they do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing chamber, comprising: a substrate support positioned within a processing region of the semiconductor processing chamber; Cover plate; a gas box positioned between the cover plate and the substrate support, the gas box being characterized by a first surface and a second surface opposite the first surface, wherein the gas box defines a central aperture, wherein the gas box defines an annular channel in the first surface of the gas box, the annular channel extending through the gas box around the central aperture, wherein the gas box defines a recessed ledge in the first surface of the gas box, the recessed ledge extending around the annular channel, and wherein the gas box includes an annular outer cover disposed on the recessed ledge and extending across the annular channel defined in the first surface of the gas box; a baffle plate positioned between the gas box and the substrate support, wherein the baffle plate defines a plurality of apertures that function as a throttle for flowing a gas through the throttle; a ferrite block positioned between the cover plate and the baffle plate; as well as A faceplate is positioned between the barrier plate and the substrate support.

2. The semiconductor processing chamber of claim 1 wherein the ferrite block is characterized by an annular shape extending around the central hole of the gas box.

3. The semiconductor processing chamber of claim 2, further comprising: An insulator is positioned between the gas box and the cover plate, wherein the insulator defines a central hole axially aligned with the central hole defined through the gas box, wherein the ferrite block extends around the insulator.

4. The semiconductor processing chamber of claim 1 wherein the ferrite block comprises a plurality of blocks extending around the gas box.

5. The semiconductor processing chamber of claim 1, wherein the ferrite block is disposed within a dielectric material.

6. The semiconductor processing chamber of claim 5, wherein the dielectric material is characterized by a dielectric constant less than or equal to 3.

7.

7. The semiconductor processing chamber of claim 6, wherein the dielectric material comprises polytetrafluoroethylene or polyetheretherketone.

8. The semiconductor processing chamber of claim 1, wherein the gas box defines a second annular channel within the gas box, and wherein the ferrite block is disposed within the second annular channel.

9. The semiconductor processing chamber of claim 8, wherein a dielectric spacer is disposed on the ferrite block disposed within the second annular channel.

10. The semiconductor processing chamber of claim 9, wherein the dielectric spacer defines a recess within the dielectric spacer, and wherein an outer cover is disposed within the recess within the dielectric spacer.

11. The semiconductor processing chamber of claim 10, wherein the dielectric spacer forms a vertical spacing between the housing and the ferrite block, and wherein the dielectric spacer forms a radial gap between the housing and the gas box.

12. A semiconductor processing chamber comprising: a substrate support positioned within a processing region of the semiconductor processing chamber; Cover plate; a gas box positioned between the cover plate and the substrate support, the gas box being characterized by a first surface and a second surface opposite the first surface, wherein the gas box defines a central aperture, wherein the gas box defines an annular channel in the first surface of the gas box, the annular channel extending through the gas box around the central aperture, wherein the gas box defines a recessed ledge in the first surface of the gas box, the recessed ledge extending around the annular channel, and wherein the gas box includes an annular outer cover disposed on the recessed ledge and extending across the annular channel defined in the first surface of the gas box; a ferrite block positioned between the cover plate and the gas box; a baffle plate positioned between the gas box and the substrate support, wherein the baffle plate defines a plurality of apertures that function as a throttle for flowing a gas through the throttle; as well as A faceplate is positioned between the barrier plate and the substrate support.

13. The semiconductor processing chamber of claim 12 wherein the ferrite block is characterized by an annular shape extending around the central aperture of the gas box.

14. The semiconductor processing chamber of claim 13, further comprising: An insulator is positioned between the gas box and the cover plate, wherein the insulator defines a central hole axially aligned with the central hole defined through the gas box, wherein the ferrite block extends around the insulator.

15. The semiconductor processing chamber of claim 13, wherein the ferrite block comprises a plurality of blocks extending around the gas box.

16. The semiconductor processing chamber of claim 12, wherein the ferrite block is disposed within a dielectric material, and wherein the dielectric material comprises polytetrafluoroethylene or polyetheretherketone.

17. A semiconductor processing chamber gas box, comprising: An upper surface and a lower surface, the lower surface is opposite to the upper surface, wherein: The air box defines a central aperture, the air box defining an annular passage in the upper surface of the air box, the annular passage extending through the air box around the central aperture, The ferrite block is placed in the annular channel. A dielectric spacer is disposed on the ferrite block, An annular outer cover is disposed on the dielectric spacer, and the annular outer cover is disposed in the annular channel. the air box defining an additional annular passage in the upper surface of the air box, The additional annular channel extends radially outside the annular channel and partially through the thickness of the airbox, and The additional annular passage defines a volume configured for flow of a cooling fluid therethrough.

18. The semiconductor processing chamber gas box of claim 17, wherein the dielectric spacer defines a recess in a surface of the dielectric spacer opposite a surface contacting the ferrite block, and wherein the annular housing is disposed within the recess.

19. The semiconductor processing chamber gas box of claim 18, wherein the dielectric spacer forms a vertical spacing between the annular housing and the ferrite block, and wherein the dielectric spacer forms a radial gap between the annular housing and the gas box.

20. The semiconductor processing chamber gas box of claim 17, wherein the ferrite block comprises a plurality of blocks extending around the annular channel in the upper surface of the gas box.

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