System for performing set operations using multi-core processing units and methods thereof

Abstract

Set operations are performed using sparse matrix operations provided by multi-core processing units, such as graphics processing units. Before using hash tables, set operations are converted to operand matrices and sparse matrix operations. Input sets are converted to matrices, identifying matrix operations corresponding to set operations, and one or more operands of the set operations are also represented within matrices. Matrix operations are then performed on these matrices to obtain output matrices, which are then converted to output sets.

Description

BACKGROUND

[0001] Processing units can have multiple cores, each of which is capable of performing tasks in parallel with one another. Conventional central processing units (or CPUs) have multiple complex cores, each of which can perform complex tasks. On the other hand, graphics processing units (GPUs) have a relatively large number of relatively small cores. As a result, GPUs facilitate performing a large number of simpler tasks with a very high degree of parallelism and efficiency.

[0002] GPU manufacturers typically provide GPU function libraries that the GPU manufacturer anticipates would be useful for the GPU to perform. These functions include matrix operations. As a result, GPU libraries typically provide matrix operation functions that can be performed on one- or two-dimensional matrices. These matrix operations include operations on sparse matrices (matrices that are mostly composed of zeros) as well as dense matrices (matrices that are mostly composed of non-zero values). However, the GPU libraries do not include set operations.

[0003] A set is a collection of data items (ordered or unordered) that supports two main operations: insertion and query (or lookup). Each data item can be any data item, such as a single value or a key-value pair. One way to implement a set and set operations on a graphics processing unit is to represent the set in the form of a hash table. Industry standard hash table implementations on GPUs provide slightly different variants of bounded hash tables (basic hash tables / compact hash tables / multi-value hash tables), but all of these variants have one thing in common - fixed size (32-bit) keys and values. This limits the domain of elements that can be stored in a single hash table to approximately 2^32 (or nearly 4 billion). A major factor in the reason for this limitation is the relatively small device memory size. This limitation makes the development of highly parallel, especially for large data volume, GPU algorithms challenging. Also, the presence of hashing adds significant overhead to the insertion / retrieval logic of hash sets. SUMMARY

[0004] This summary is provided to introduce some concepts of the disclosure in a simplified form that are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] The principles described herein relate to performing set operations using sparse matrix operations provided by a multi-core processing unit, such as a graphics processing unit. Moreover, the set operations are performed without using a hash table to store the set, and without using hash operations in order to perform the set operations (such as insertion and query) on the hash table. Making such hash operations typically requires placing a lock on the hash table, thereby passing through a limited set of hash operations at a time.

[0006] Thus, by converting set operations to sparse matrix operations, and prior to using hash tables, set operations can be performed with high parallelism and thus very efficiently and quickly. As an example, multiple elements can be added to a very large set, or multiple elements can be queried from a large set using a single and fast operation. Moreover, since set operations are converted to sparse matrix operations, such set operations can be performed by a multi-core processing unit even if set operations are not provided in the library of the multi-core processing unit. Thus, the principles described herein also unlock the potential of multi-core processing units to efficiently and quickly perform set operations.

[0007] According to the principles described herein, an input set is represented as a first set of matrices, the first set of matrices including at least a first matrix having a bit value at each location having an index with the same value as the input set. The system then identifies a set operation and one or more operands to be performed using the set operation. These one or more operands are then represented in the form of a second set of matrices, the second set of matrices including a second matrix having a bit value at each location having an index with the same value as any of the one or more operands. A sparse matrix operation corresponding to the set operation is then identified. The multi-core processing unit then performs the sparse matrix operation using the first set of matrices and the second set of matrices, resulting in an output matrix. The output matrix is then converted to an output set, the output set representing the result of performing the set operation on the input set to produce the output set.

[0008] Additional features and advantages will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the teachings herein. Features and advantages of the application will be realized and attained by the instrumentalities specifically pointed out in the appended claims and will not limit the scope of the application, which is defined by the appended claims. The features and advantages of the application will become more fully apparent as the description is BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to describe the manner in which the above-recited and other features and advantages can be obtained, a more particular description will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments and are not therefore to be considered to be limiting of its scope, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

[0010] Figure 1 An example computing system in which the principles described herein can be employed is illustrated;

[0011] Figure 2A flowchart illustrating a method for performing set operations using a sparse matrix library of a multi-core processing unit according to the principles described herein is illustrated; and

[0012] Figure 3 A computing environment including a multi-core processing unit is illustrated, and can perform Figure 2 a method. DETAILED DESCRIPTION

[0013] The principles described herein relate to performing set operations using sparse matrix operations provided by a multi-core processing unit, such as a graphics processing unit. Moreover, the set operations are performed without using a hash table to store the sets, and without using hash operations in order to perform set operations, such as insertions and queries, on the hash table. Performing such hash operations typically requires placing a lock on the hash table, thereby limiting the set of hash operations that can be performed at a time.

[0014] Accordingly, by converting set operations to sparse matrix operations, and prior to using a hash table, set operations can be performed with a high degree of parallelism, and thus very efficiently and quickly. As an example, a large number of elements can be added to a very large set, or a large number of elements can be queried from a large set using a single and fast operation. Moreover, because the set operations are converted to sparse matrix operations, such set operations can be performed by the multi-core processing unit even if the set operations are not provided in the library of the multi-core processing unit. Accordingly, the principles described herein also unlock the potential of the multi-core processing unit to efficiently and quickly perform set operations.

[0015] According to the principles described herein, an input set is represented as a first set of matrices, the first set of matrices including at least a first matrix having a bit value at each location having an index with a same value as the input set. The system then identifies a set operation, and one or more operands to be performed using the set operation. These one or more operands are then represented in the form of a second set of matrices, the second set of matrices including a second matrix having a bit value at each location having an index with a same value as any of the one or more operands. A sparse matrix operation corresponding to the set operation is then identified. The multi-core processing unit then performs the sparse matrix operation using the first set of matrices and the second set of matrices, thereby obtaining an output matrix. The output matrix is then converted to an output set, the output set representing a result of performing the set operation on the input set to produce the output set.

[0016] Because the principles described herein are performed in the context of a computing system, some introductory discussion of computing systems will be presented with reference to Figure 1 A computing environment including a multi-core processing unit is illustrated, and can perform Figure 2 a method. Figure 3To describe performing set operations using matrix operations of a multi-core processing unit.

[0017] Computing systems are now increasingly taking a wide variety of forms. Computing systems may be handheld, portable, laptop / computer, desktop, server, distributed, or even specially programmed hearing devices. A computing system may have different processors, operating systems, and input and output devices. A typical handheld computing system, such as a smart phone, might include a home- button or other input element and a touch screen for input, as well as a microphone for input and a speaker for output. More specifically, the smart phone might include an application-specific integrated circuit (ASIC) for processing efficiency, a microprocessor, such as a G3, G4, Intel Core, or the like, a memory, such as RAM, ROM, Flash, or the like, a storage medium, such as a hard disk or other large memory, and many more components. A desktop computer might include many more or different components than a handheld computer. For example, it might include a large flat screen monitor for a display, a keyboard and a number of other input devices, including a mouse, a printer, and so on. Similarly, a server will often include multiple components and resources.

[0018] As Figure 1 illustrated in its most basic configuration, a computing system 100 includes at least one hardware processing unit 102 and memory 104. The processing unit 102 includes a general- purpose processor. Although not required, the processing unit 102 also can include a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or some other specialized circuitry. In one embodiment, the memory 104 includes physical system memory. This physical system memory can be volatile, non-volatile, or some combination of the two. In a second embodiment, memory is non-volatile mass storage for example, a physical storage medium. If the computing system is distributed, the processing, memory, and / or storage capability can be distributed as well.

[0019] The computing system 100 also has associated storage and / or storage capacity. The storage includes physical, tangible storage and / or storage capacity. The storage can be volatile, non-volatile, or some combination of the two. The storage can be local to the computing system 100, or it can be distributed across many computing systems. The storage can be a physical storage medium, or it can be distributed across a network of computing systems.

[0020] One of ordinary skill in the computer arts will recognize that the structure of an executable component resides on a computer-readable medium, such that, when interpreted for execution by one or more processors of a computing system (e.g., by a processor thread), causes the computing system to perform a function. This structure can be computer-readable directly by the processor (as is the case if the executable component is binary). Alternatively, the structure can be structured to be interpretable and / or compiled (whether in a single stage or in multiple stages) so as to generate such binary that can be directly interpreted by the processor. This understanding of example structures of an executable component is well within the understanding of one of ordinary skill in the computer arts when using the term "executable component."

[0021] The term "executable component" is also well understood by one of ordinary skill in the art to include structures such as hard-coded or hard-wired logic gates that are implemented exclusively or nearly exclusively in hardware, such as within a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or any other specialized circuitry. Thus, the term "executable component" is a term of art to one of ordinary skill in the computing arts for structures, whether implemented in software, hardware, or a combination.

[0022] In the description below, embodiments are described with reference to actions performed by one or more computing systems. If such actions are implemented in software, one or more processors (of the associated computing system performing the action) direct operation of the computing system in response to computer-executable instructions constituting an executable component having been executed. For example, such computer-executable instructions can be included on one or more computer-readable media forming a computer program product. An example of such operation involves the manipulation of data. If such actions are implemented exclusively or nearly exclusively in hardware, such as in a FPGA or ASIC, the computer-executable instructions can be hard-coded or hard-wired logic gates. The computer-executable instructions (and the manipulated data) can be stored in the memory 104 of the computing system 100. Computing system 100 can also contain communication channels 108 that allow the computing system 100 to communicate with other computing systems over, for example, network 110.

[0023] While not all computing systems require a user interface, in some embodiments, the computing system 100 includes a user interface system 112 for interaction with a user. The user interface system 112 can include output mechanisms 112A as well as input mechanisms 112B. The principles described herein are not limited to precise output mechanisms 112A or input mechanisms 112B as these will depend on the nature of the device. However, output mechanisms 112A can include, for example, speakers, displays, tactile outputs, virtual or augmented reality, holograms, and the like. Examples of input mechanisms 112B can include, for example, microphones, touchscreens, virtual or augmented reality, holograms, cameras, keyboards, mice or other pointer input, any type of sensor, and the like.

[0024] Embodiments described herein can include or utilize special-purpose or general-purpose computing systems that include computer hardware, such as, for example, one or more processors and system memory, as discussed in greater detail below. Embodiments described herein also include physical and other computer-readable media for carrying or storing computer-executable instructions and / or data structures. Such computer-readable media can be any available media that can be accessed by a general purpose or special purpose computing system. Computer-readable media that store computer-executable instructions are physical storage media. Computer-readable media that carry computer-executable instructions are transmission media. Thus, by way of example, and not limitation, embodiments of the application can comprise at least two distinctly different kinds of computer-readable media: storage media and transmission media.

[0025] Computer-readable storage media includes RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other physical and tangible storage medium which can be used to store desired program code means in the form of computer-executable instructions or data structures and which can be accessed by a general purpose or special purpose computing system.

[0026] A "network" is defined as one or more data links that enable the transport of electronic data between computing systems and / or modules and / or other electronic devices. When information is transferred or provided over a network or another communications connection (either hardwired, wireless, or a combination of hardwired or wireless) to a computing system, the computing system properly views the connection as a transmission medium. Transmission media can include a network and / or data links which can be used to carry desired program code means in the form of computer-executable instructions or data structures and which can be accessed by a general purpose or special purpose computing system. Combinations of the above should also be included within the scope of computer-readable media.

[0027] Further, upon reaching various computing system components, program code means in the form of computer-executable instructions or data structures can be transferred automatically from transmission media to storage media (or vice versa). For example, computer-executable instructions or data structures received by way of network or data linkage can be buffered in RAM within a network interface module (e.g., a "NIC"), and then eventually transferred to computing system RAM and / or to less volatile storage media at computing system at a later time. Thus, it should be understood that storage media can be included in computing system components that also (or even primarily) utilize transmission media.

[0028] For example, computer-executable instructions include instructions and data which, when executed at a processor, cause a general purpose computing system, special purpose computing system, or special purpose processing device to perform a certain function or group of functions. Alternatively, or in addition, the computer-executable instructions can configure the computing system to perform a certain function or group of functions. The computer-executable instructions can be, for example, binary coded machine instructions or even, in the case of an interpreter, source code. As used

[0029] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the described features or acts described above. Rather, the described features and acts are disclosed as example forms of implementing the claims.

[0030] Those skilled in the art will appreciate that the application can be practiced in network computing environments with many types of computing system configurations, including personal computers, desktop computers, laptop computers, message processors, hand-held devices, multi-processor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframe computers, mobile telephones, PDAs, pagers, routers, switches, datacenters, wearable devices (such as glasses), and the like. The application can also be practiced in distributed system environments where local and remote computing system, both are

[0031] Those skilled in the art will further appreciate that the application can be practiced in a cloud computing environment. Cloud computing environments can be distributed and / or non-distributed. In a distributed cloud computing environment, components of the cloud computing environment can be distributed across multiple organizations and / or multiple components can be owned by different organizations. In this description and the following claims, "cloud computing" is defined as a model for enabling on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services). The definition of "cloud computing" is not limited to any of the numerous advantages that can be obtained from such a model when properly deployed.

[0032] For the processes and methods disclosed herein, the operations performed in the processes and methods can be implemented in differing order. Furthermore, the outlined operations are only provided as examples, and some of the operations can be optional, combined into fewer steps and operations, supplemented with further operations or expanded into additional operations without detracting from the essence of the disclosed embodiments.

[0033] Figure 2 A flowchart of a method 200 for performing a collective operation using a sparse matrix library of a multi-core processing unit is illustrated in accordance with the principles described herein. In one embodiment, the method 200 is performed by a computing system, such as the computing system 100 of Figure 1 As an example, a graphics processing unit performs the action 230 within the method 200, while another more general purpose processing unit performs the remainder of the method 200. As an example, the actions 201, 202, 211, 221, 222, and 240 can be performed by a computing system, such as the computing system 100 of Figure 1 In this case, the actions can be performed in response to at least one hardware processing unit 102, which can be a general purpose processing unit different from the graphics processing unit performing the action 230, executing one or more computer-executable instructions stored in the memory 104. In particular, the computer-executable instructions are structured such that, when executed by the at least one hardware processing unit 102, the computing system 100 performs the method 200.

[0034] Figure 3 A computing environment 300 including a multi-core processing unit 350 is illustrated. In the illustrated case, the multi-core processing unit has four cores 351-354. However, the ellipsis 355 indicates that there can be more cores of the multi-core processing unit 350. As an example, the multi-core processing unit 350 can be a graphics processing unit that includes hundreds or thousands of different cores, each of which is capable of performing tasks in parallel.

[0035] Multi-core processing unit 350 includes function library 360, which is typically provided with multi-core processing unit 350 and can be extracted by programmers to operate multi-core processing unit. As an example, graphics processing unit typically has a matrix library (such as matrix library 361), and possibly other functions (such as indicated by ellipsis 362). A typical graphics processing unit's matrix library typically includes dense matrix functions and sparse matrix functions. Furthermore, for each of the dense and sparse matrix categories, the matrix library has functions for operating on one-dimensional and two-dimensional matrices. Such matrices typically have a domain of up to 2^32 (or approximately 4 billion) in each dimension.

[0036] Environment 300 also includes several executable components, each of which is described above for... Figure 1 The executable component 106 is constructed as described. For example, environment 300 includes set / matrix transformation component 310, general set / matrix operation transformation component 330, operand / matrix transformation component 340, and matrix / set transformation component 380. Because Figure 2 Method 200 can be used Figure 3 Executed in environment 300, it will now be frequently referenced. Figure 3 Environment 300 to describe Figure 2 Method 200.

[0037] refer to Figure 2 Method 200 includes obtaining the input set (action 201). Figure 3 In this example, the input set is denoted as input set 301. It is this input set that will undergo specific set operations. In a simplified example referred to below as the "simple example," it is assumed that the input set is {1, 3}, where {1, 3} is a set with two elements, one with the value 1 and the other with the value 3. This simple example is for illustrative purposes only. This example is simple in several ways, namely, the number of elements in the set is very small, and the values ​​of the elements are within a small range (i.e., from 1 to 3). Real-world input sets can be very large and include any number of values. However, for proper understanding, the principle will be described with reference to the example and how the principle can be extended to more complex examples.

[0038] Refer again Figure 2 Method 200 then includes representing the input set as a first matrix set that includes at least the first matrix (action 211). Figure 3In this case, the set / matrix conversion component 310 uses the input set 301 to generate a first set of matrices 311, which includes a first matrix 311 A and possibly other matrices represented by ellipsis 311 B. In one example, each element in the input set is a value, in which case the first set of matrices 311 includes only the first matrix 311 A. However, in another example discussed in further detail below, each element in the input set is a key-value pair. In this case, the first set of matrices 311 would include a first matrix for the key and another matrix for the corresponding value.

[0039] Now, assume that the input set includes only values as elements. This is the case in the simple example where the input set is {1, 3}. In this case, the first set of matrices 311 includes only the first matrix 311 A. Specifically, the first matrix includes a bit value (e.g., binary 1) at each position having an index with the same value as an element of the input set, and otherwise has the opposite binary value (e.g., binary 0). In our example, the values of the elements within the input set {1, 3} fall within the range of 0 to 3. Thus, the input set {1, 3} is converted to the matrix

[0101] .

[0040] Here, there is a binary 1 at the first position, which represents the first element (with value 1) in the input set {1, 3}. In the convention here, the left-most element in the set is at the zeroth position. There is also a binary 1 at the third position, which represents the second element (with value 3) in the input set {1, 3}. The value at the zeroth index position of the first matrix

[0101] is binary 0, which represents that there is no element in the input set {1, 3} with value 0. Likewise, the value at the second index position of the first matrix

[0101] is also binary 0, which represents that there is no element in the input set {1, 3} with value 0. Thus, in the simple example, the input set {1, 3} is an example of the input set 301, and the first matrix

[0101] is an example of the corresponding first matrix 311 A.

[0041] In this simple example, the first matrix is a one-dimensional matrix with only four elements. However, each matrix in the first set of matrices should be structured in a way that the multi-core processing unit accepts that matrix as input. For example, if the multi-core processing unit is to perform a function on a one-dimensional sparse matrix of size 2^32, then the first matrix would take the form of a sparse matrix with binary 1 at index positions 1 and 3 and binary 0 at all other positions.

[0042] A particular set operation is performed on the input set. Thus, the method 200 includes obtaining the operation for that particular set (act 202). Referring back to FIG. 2, the method 200 includes obtaining the operation for the input set (act 202). In this example, the operation is a set intersection operation. Thus, the method 200 includes obtaining the set intersection operation (act 202). Figure 3The specific set operation 302 is illustrated as including a general set operation 303 and one or more operation objects 304. As an example, the general set operation 303 can be an insert or a query. The operation object(s) 304 identify what element(s) will be operated on according to the general set operation. As an example, assume a specific set operation of "insert 2 into the set." This can be broken down into the general set operation of "insert" and the operation object of "2."

[0043] Referring to Figure 2 The matrix operation corresponding to the general set operation is identified (act 221). Further, the operation object(s) of the specific set operation are represented in a second set of matrices including a second matrix (act 222). For example, in the environment 300, the general set operation 303 of the specific set operation 302 is provided to the general set / matrix operation conversion component 330 to generate the general matrix operation 331. The conversion can be a simple mapping of the operation. For example, an insert set operation is mapped to a bitwise logical "OR" sparse matrix operation. On the other hand, a query set operation is mapped to a bitwise logical "AND" sparse matrix operation.

[0044] Further, the identified operation object(s) of the specific set operation are represented in a second set of matrices including a second matrix (act 222). For example, in the environment 300, the operation object(s) 304 of the specific set operation 302 are provided to the operation object / matrix conversion component 340, which generates the second set of matrices 341 including the second matrix 341A and possibly other matrices represented by ellipsis 341B. In the case where the input set includes only values, the second set of matrices 341 includes only the second matrix 341A. If the input set includes key-value pairs, there can be a case where there are other matrices included within the second set of matrices 341 as well (depending on the general matrix operation). Figure 3

[0045] ​To illustrate, in the simple example where the input set is {1, 3}, assume that the particular set operation is to insert 2 into the set. Here, as previously mentioned, the general set operation is the insert set operation, while the corresponding matrix operation is the bitwise logical "or" matrix operation. Further, the second matrix is generated such that it has a bit value (e.g., binary 1) at each position having an index with the same value as any of the operands, and otherwise has an opposite bit value (e.g., binary 0) at other index positions of the second matrix. Thus, again assuming a matrix having four index positions 0, 1, 2, and 3, the value at the second index position is set to binary 1 (indicating that the element having the value 2 in this case will be operated on - inserted), and the values at the other index positions are each set to logical 0. Thus, if 2 is to be inserted into the input set {1, 3}, the second matrix takes the form

[0010] .

[0046] The matrix inputs for the multi-core processing unit are now ready. Thus, the multi-core processing unit performs the identified sparse matrix operation on the first set of matrices and the second set of matrices to generate an output matrix (act 230). In Figure 3 , the first set of matrices 311 and the second set of matrices 341 are provided to the multi-core processing unit 350, which performs the general matrix operation 331 on the two sets of matrices 311 and 341, resulting in the output matrix 371. In the simple example of inserting 2 into the input set {1, 3}, the multi-core processing unit bitwise logically "ors" the matrix

[0101] with the matrix

[0010] to obtain the output matrix

[0111] .

[0047] Returning to Figure 2 , the output matrix is then converted to an output set (act 240), completing the performance of the particular set operation on the input set. Referring to Figure 3 , the matrix / set conversion component 380 converts the output matrix 371 to the output set 381. In the simple example, the output set is generated with elements having values corresponding to any index position of the output matrix having a bit value (e.g., binary 1). Thus, in the simple example, the output matrix

[0111] is converted to the output set {1, 2, 3}.

[0048] The method 200 is repeated for different input sets and different particular set operations. For example, assume that the set operation "query whether the set has a 1" is to be applied to the input set {1, 2, 3}. Here, the first matrix is obtained by representing the input set {1, 2, 3} as the matrix

[0111] . The general matrix operation corresponding to the general set operation of "query" is the bitwise logical "and". Furthermore, the operand is "1", so the second matrix is

[0100] . Performing the bitwise logical "and" on the two matrices

[0111] and

[0100] yields the output matrix

[0100] . This output matrix is interpreted as "yes, there is a 1 in the input set" because there is a binary 1 at the index position corresponding to the value 1 (at the first index position).

[0049] The principles just described can be applied to sets of increased complexity, and to cases where there are multiple (and possibly large numbers of) operands. Take the case where the input set is {0, 4, 5, 9, 15} and is represented by the first sparse matrix [1000110001000001]. Now assume that the set operation is to insert 10, 13, and 14 into the input set. The second matrix will be [0000000000100110] with binary 1s at index positions 10, 13, and 14. The corresponding general matrix operation for the insert set operation is the bitwise logical "or". Thus, the multi-core processing unit will perform the bitwise logical "or" on the two matrices [1000110001000001] and [0000000000100110] to obtain the output matrix [1000110001100111], which translates to the output set of {0, 4, 5, 9, 10, 13, 14, 15}. Similarly, to query whether 6 and 10 are in this output set, the input set {0, 4, 5, 9, 10, 13, 14, 15} will be represented as the first matrix [1000110001100111], and the logical "and" with the second matrix [0000001000100000] will be performed to obtain the output matrix [0000000000100000] to infer that 6 is not in the input set, but 10 is in the input set.

[0050] Now, consider that the input set can have any of the values that map to 2^32. In this case, the input set is converted to a one-dimensional sparse matrix, and the operand is also converted to a one-dimensional sparse matrix. For the insert operation, the two sparse matrices are bitwise logical ORed, and for the lookup operation, the two sparse matrices are bitwise logical ANDed. If the input set can have any of the values that map to 2^64, then the input set and the operand set are converted to two-dimensional sparse matrices of dimension 2^32 by 2^32. Then, using one fast operation that uses a multi-core processing unit, especially if a graphics processing unit is used, multiple values are quickly inserted into, or looked up from, even such large sets.

[0051] In the above example, the input set is a set of values. In this case, the first matrix set is just the first matrix, and the second matrix set representing the operand is just the second matrix. Furthermore, the insert operation is performed by bitwise logical ORing the first matrix and the second matrix, and the lookup operation is performed by bitwise logical ANDing the first matrix and the second matrix. However, the input set can also be a set of key-value pairs. In this case, the first matrix set includes a first matrix representing the keys and another matrix representing the corresponding values (which we will call the "third matrix"). Furthermore, the second matrix set includes the second matrix and another matrix depending on the general set operation (which we will call the "fourth matrix").

[0052] For illustrative purposes only, we will use the input set {b=5, d=6}, which we will refer to herein as the "simple key-value example." Here, the first matrix has a binary 1 at every position where the corresponding key is present. For example, assume that the zeroth index position is a binary 1 if and only if the input set has an element with the key "a"; the first position is a binary 1 if and only if the input set has an element with the key "b"; the second position is a binary 1 if and only if the input set has an element with the key "c," and so on. Thus, in this case, the first matrix set includes a first matrix representing the keys, where the first matrix has bit values (e.g., binary 1) corresponding to the positions in the input set where the keys are present. Here, the keys in the input set {b=5, d=6} are "b" corresponding to index position 1 and "d" corresponding to index position 3. Thus, the first matrix will be

[0101] . Furthermore, the first matrix set will also include a third matrix representing the corresponding values. The third matrix includes the values at every position with an index that is in the same position as the corresponding key for that value. Thus, in this simple example where the input set is {b=5, d=6}, the third matrix will be

[0506] . Thus, with reference to Figure 3 In this example, the first matrix set 311 includes the first matrix

[0101] representing the keys and the third matrix

[0506] representing the values.

[0053] In this simple key-value example, assume that the set operation is a write operation that writes values corresponding to one or more keys to the input set. In this case, the second matrix set of the second matrix includes a bit value at each position corresponding to any of the one or more keys to be written, and a fourth matrix representing the corresponding values of the one or more keys, where the fourth matrix includes a value at each position having an index with the same position as the corresponding key for the value.

[0054] As an illustrative example, assume that the simple key-value example is extended to show what would happen if there were a write command to write a = 4 and c = 7 to the input set. Here, two new key-value pairs (a = 4 and c = 7) are added to the input set. Since a and c are the operands of the write operation, the second matrix becomes

[1010] . Further, the fourth matrix becomes

[4070] , which represents the values of "a" and "c" to be written. The matrix operation includes a bitwise logical "or" of the first matrix

[0101] and the second matrix

[1010] to obtain a first intermediate matrix

[1111] . This first intermediate matrix represents that the output set will include keys for a, b, c, and d. Further, the matrix operation also includes an addition of the third matrix

[0506] and the fourth matrix

[4070] to obtain a second intermediate matrix

[4576] . From this, the output set can be populated as {a = 4, b = 5, c = 7, d = 6}. In other words, the output set is represented as having keys (or a, b, c, and d) corresponding to the binary 1 positions of the first intermediate matrix

[1111] , and for each key, the value of the key is represented as corresponding to the index within the second intermediate matrix at the same position as the corresponding key in the first intermediate matrix.

[0055] Continuing with the illustrative example, assume that the next set operation is to read a and b from the input set {a = 4, b = 5, c = 7, d = 6}. Here, the first matrix

[1111] represents the keys, and the third matrix

[4576] represents the corresponding values. The operands are a and b, so the second matrix is

[1100] , with binary 1s at the positions corresponding to the keys to be read. The matrix operation will include a bitwise logical "and" of the first matrix and the second matrix to generate a first intermediate matrix, which in this case will be

[1100] . Further, the third matrix (e.g.,

[4576] ) is multiplied by the first matrix

[1111] to obtain a second intermediate matrix, which in this case will be

[4500] . The output set is then obtained by the two matrices (key matrix and value matrix). The key matrix is the first intermediate matrix

[1100] and represents the keys (a and b) of the key-value pairs being read. The value matrix is the second intermediate matrix

[4500] representing the corresponding values of the keys being read. Thus, the read operation will read two key-value pairs including a = 4 and b = 5.

[0056] Continuing with this illustrative example, now assume that the a = 4 and b = 5 key-value pairs are to be deleted from the input set. Here, the first matrix will again include a bit value (e.g., binary 1) at each position corresponding to a key of the input set. Since keys a, b, c, and d are all present in the input set's key-value pairs {a = 4, b = 5, c = 7, d = 6}, the first matrix will again be

[1111] . The second matrix includes a bit value (e.g., binary 1) at each position corresponding to a key to be deleted. In this case, since a = 4 and b = 5 are to be deleted, the second matrix will be

[1100] . The bitwise complement of the second matrix,

[0011] , is found, and the bitwise logical AND is applied to the complement of the first matrix and the second matrix to obtain

[0011] . This is the first intermediate matrix representing the keys in the corresponding output set. Then, the multiplication of the third matrix

[4576] is applied to the complement of the second matrix

[0011] to obtain the second intermediate matrix

[0076] representing the values of the output set. Thus, the output set is derived from the first intermediate matrix representing the keys

[0011] and the second intermediate matrix representing the values

[0076] , such that the output set is {c = 7, d = 6}. Note that a = 4 and b = 5 have been deleted.

[0057] Now, consider that the input set can have values that map to any one of 2^32 key-value pairs. In this case, the input set is converted to two one-dimensional sparse matrices (one for keys and one for values), and the operand is also converted to one or two one-dimensional sparse matrices. The principles just described can be extended to operations that insert and query multiple items in an input set that is this large. If the input set can have values that map to any one of 2^64 values, then the input set and the set of operands are converted to two-dimensional sparse matrices of dimension 2^32 by 2^32. Then, one fast operation using a multi-core processing unit (especially if a graphics processing unit is used) is utilized to quickly insert multiple values into, or quickly query multiple values from, even this large of a set.

[0058] Thus, the principles described herein advantageously utilize multi-core processing units, such as graphics processing units, to perform very fast set operations on large input sets. The application can be implemented in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the application is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims

1. A computing system configured to use a sparse matrix library of a multi-core processing unit to perform set operations using one or more matrix operations provided by the multi-core processing unit, wherein the sparse matrix library includes functions for operating on one-dimensional or two-dimensional matrices having a domain of at most 2^32 in each dimension, such that the set operations are converted into the one or more matrix operations, thereby achieving efficient execution of the set operations by the multi-core processing unit even though the multi-core processing unit does not provide the set operations in its sparse matrix library, the computing system comprising: One or more processors; as well as One or more computer-readable media having computer-executable instructions thereon, the computer-executable instructions being executable by the one or more processors to cause the computing system to: The input set is represented as a first matrix set including at least a first matrix, the first matrix including bit values ​​at each position having the same values ​​as the elements of the input set; Identify the set operation to be performed on the input set; The identifier is used for one or more operands in the set operation identified on the input set; The one or more operands are represented by a second set including a second matrix set, the second matrix set including at least a second matrix, the second matrix including bit values ​​at each position having an index that has the same value as any operand in the one or more operands; Identify the sparse matrix operation corresponding to the set operation; The sparse matrix operation is performed on the first matrix and the second matrix using the multi-core processing unit to obtain an output matrix, wherein the multi-core processing unit is configured to perform the operation on the first matrix and the second matrix even when the first matrix and the second matrix are one-dimensional or two-dimensional matrices and when the domain of the first matrix or the second matrix is ​​extended to at most 2^32 in each dimension; and The output matrix is ​​represented as an output set, which represents the result of performing the set operation on the input set.

2. The computing system according to claim 1, wherein the input set is a value set.

3. The computing system according to claim 2, wherein the set operation includes an insertion operation that inserts one or more values ​​into the input set to generate the output set, wherein the one or more operands are the one or more values ​​to be inserted, and the matrix operation includes a bitwise logical "OR" operation.

4. The computing system according to claim 2, wherein the set operation includes a query operation to check whether the input set includes one or more values, the one or more operands being the one or more values ​​to be queried, and the matrix operation includes a bitwise logical AND operation.

5. The computing system of claim 1, wherein the input set comprises a set of key-value pairs, and representing the input set as a first matrix set comprises representing the input set as a first matrix representing a key, the first matrix including bit values ​​at each position corresponding to a key of the input set, the first matrix set further comprising a third matrix representing a corresponding value, the third matrix including the value at each position having an index having the same position as the key corresponding to the value.

6. The computing system of claim 5, wherein the set operation includes a write operation to write a value corresponding to one or more keys from the input set, the second matrix includes bit values ​​at each position corresponding to any key among the one or more keys, the second matrix set including a fourth matrix representing the corresponding values ​​of the one or more keys, the fourth matrix including the value at each position having an index having the same position as the key corresponding to the value.

7. The computing system according to claim 6, wherein the matrix operation includes performing a bitwise logical "OR" operation on the first matrix and the second matrix to generate a first intermediate matrix, and adding the third matrix and the fourth matrix to generate a second intermediate matrix.

8. The computing system according to claim 7, wherein representing the output matrix as an output set comprises: The output set is represented as having keys corresponding to the positions in the first intermediate matrix; as well as For each of the keys, the value of the key is represented as corresponding to an index in the second intermediate matrix, the index being at the same position as the corresponding key in the first intermediate matrix.

9. The computing system of claim 5, wherein the input set comprises a set of key-value pairs and the first matrix represents a key in the set of key-value pairs, the first matrix comprising bit values ​​at each position corresponding to a key in the input set, the set operation comprising a read operation of reading one or more key-value pairs from the set of key-value pairs, and the second matrix comprising bit values ​​at each position corresponding to any key in the key of the key-value pair to be read from the set of key-value pairs.

10. The computing system according to claim 9, wherein the matrix operation includes performing a bitwise logical AND operation on the first matrix and the second matrix to generate a first intermediate matrix, and multiplying the third matrix and the first matrix to generate a second intermediate matrix.

11. The computing system according to claim 10, wherein representing the output matrix as an output set comprises: The output set is represented as having keys corresponding to the positions in the first intermediate matrix; as well as For each of the keys, the value of the key is represented as corresponding to the index position in the second intermediate matrix, the index position being at the same position as the corresponding key in the first intermediate matrix.

12. The computing system of claim 1, wherein the input set comprises a set of key-value pairs, and the first matrix represents a key in the set of key-value pairs, the first matrix including bit values ​​at each position corresponding to a key in the input set, the set operation including a deletion operation of deleting one or more key-value pairs from the set of key-value pairs, and the second matrix including bit values ​​at each position corresponding to any key in the key of the key-value pair to be deleted from the set of key-value pairs.

13. The computing system of claim 12, wherein the matrix operation includes performing a bitwise logical AND operation on the first matrix and the second matrix to generate an output matrix representing a set of substitution keys.

14. The computing system according to claim 1, wherein the multi-core processing unit is a graphics processing unit.

15. The computing system according to claim 1, wherein the first matrix, the second matrix and the output matrix are each two-dimensional.

16. A method for using a sparse matrix library of a multi-core processing unit to perform set operations using one or more matrix operations provided by the multi-core processing unit, wherein the sparse matrix library includes functions for operating on one-dimensional or two-dimensional matrices having at most 2^32 fields in each field, such that the set operations are converted into the one or more matrix operations, thereby achieving efficient execution of the set operations by the multi-core processing unit even though the multi-core processing unit does not provide the set operations in its sparse matrix library, the method comprising: The input set is represented as a first matrix set including at least a first matrix, the first matrix including bit values ​​at each position having the same values ​​as the elements of the input set; Identify the set operation to be performed on the input set; The identifier is used for one or more operands in the set operation identified on the input set; The one or more operands are represented by a second set including a second matrix set, the second matrix set including at least a second matrix, the second matrix including bit values ​​at each position having an index that has the same value as any operand in the one or more operands; Identify the sparse matrix operation corresponding to the set operation; The sparse matrix operation is performed on the first matrix and the second matrix using the multi-core processing unit to obtain an output matrix, wherein the multi-core processing unit is configured to perform the operation on the first matrix and the second matrix even when the first matrix and the second matrix are one-dimensional or two-dimensional matrices and when the domain of the first matrix or the second matrix is ​​extended to at most 2^32 in each dimension; and The output matrix is ​​represented as an output set, which represents the result of performing the set operation on the input set.

17. The method of claim 16, wherein the input set is a set of values.

18. The method of claim 17, wherein the set operation includes an insertion operation of inserting one or more values ​​into the input set to generate the output set, the one or more operands being the one or more values ​​to be inserted, and the matrix operation includes a bitwise logical "OR" operation.

19. The method of claim 17, wherein the set operation includes a query operation to determine whether the input set includes one or more values, the one or more operands being the one or more values ​​to be inserted, and the matrix operation includes a bitwise AND operation.

20. A method for performing set operations using a processor's sparse matrix library to perform set operations using one or more matrix operations provided by the processor, wherein the sparse matrix library includes functions for operating on one-dimensional or two-dimensional matrices having a domain of at most 2^32 in each dimension, such that the set operations are converted into the one or more matrix operations, thereby enabling efficient execution of the set operations by the processor even though the processor does not provide the set operations in its sparse matrix library, the method comprising: The input set of key-value pairs is represented as a first matrix set, the first matrix set including a first matrix representing the keys, the first matrix including bit values ​​at each position corresponding to the keys of the input set, the first matrix set also including a third matrix representing the corresponding values, the third matrix including the values ​​at each position having the same index as the key corresponding to the value; Identify the set operation to be performed on the input set; The identifier is used for one or more operands in the set operation identified on the input set; The one or more operands are represented by a second matrix set comprising at least a second matrix, the second matrix comprising bit values ​​at each position having an index that has the same value as any operand among the one or more operands; Identify the sparse matrix operation corresponding to the set operation; The processor performs the sparse matrix operation on the first matrix and the second matrix to obtain an output matrix, wherein the processor is configured to perform the operation on the first matrix and the second matrix even when the first matrix and the second matrix are one-dimensional or two-dimensional matrices and when the domain of the first matrix or the second matrix is ​​extended to at most 2^32 in each dimension; and The output matrix is ​​represented as an output set, which represents the result of performing the set operation on the input set.

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