A novel control method for automatically synchronizing communication of an SPI master device by an SPI slave device

Abstract

The application discloses a novel control method for automatically synchronizing communication of a SPI master device by a SPI slave device, and comprises the following steps: the SPI master device sends a CS chip selection signal; the SPI slave device detects whether the CS chip selection signal exists, if not, the SPI master device sends the CS chip selection signal again until the SPI slave device detects the CS chip selection signal; a timer of the SPI slave device captures the rising edge of the CS and records the number of the rising edge of the CS, and judges whether the set capture number is reached, if not, the number of the rising edge of the CS is continuously recorded until the set capture number is reached; when the set capture number is reached, the initialization of the SPI slave device is completed; and the SPI slave device starts receiving data. The application adds a timer in the SPI slave device, captures the rising edge of the CS by timing, selects to complete the initialization of the SPI slave device in the interval of sending twice data, guarantees the correctness of receiving data, and makes the master-slave SPI communication more flexible.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of communication, and particularly relates to a novel control method for automatically synchronizing SPI master communication of SPI slave. BACKGROUND

[0002] SPI is a kind of serial communication protocol, and its communication principle is simple. SPI communication in a master-slave mode is generally realized through four lines, i.e., a serial clock line (SCLK), a host input / slave output data line MISO, a host output / slave input data line MOSI, and a slave selection line CS which is low active. The SCLK signal line can only be controlled and sent by a master device. In a SPI-based communication device, at least one master device needs to exist, and multiple SPI slave devices can be mounted under the same master device.

[0003] The SPI communication principle in a master-slave mode is that the start of data reception of a slave device is controlled by a CS chip selection pin in SPI communication. When the CS is at a low level, the slave device is selected and valid data is received. The SPI serial transmission feature indicates that SPI data transmission is performed bit by bit. The transmission of each bit of data is controlled by the clock of the master device (i.e., the transmission of a bit in a single byte is performed at each edge of the clock).

[0004] In the SPI master-slave device communication process, the standard flow generally starts the SPI slave device first. After the SPI slave device is ready, the master SPI device starts to send data. However, in actual engineering practice, if the SPI master-slave device cannot be strictly initialized according to the standard flow, the data received from the SPI will be incorrect. SUMMARY

[0005] The present application aims to provide a novel control method for automatically synchronizing SPI master communication of SPI slave, so as to solve the problems in the background.

[0006] The application discloses a novel control method for automatically synchronizing SPI master device communication of an SPI slave device, and the method is characterized in that the initialization of the SPI slave device is completed in the interval of twice data transmission of the SPI master device (namely between the rising edge of the chip select (CS) and the following falling edge).

[0007] Meanwhile, the novel control method for automatically synchronizing SPI master device communication of an SPI slave device is characterized in that the rising edge of the chip select (CS) of the slave SPI is captured by multiple rising edges, and then the SPI slave device is initialized formally, so that the interference of the CS of the SPI communication in the starting moment of the SPI slave device is effectively avoided, the abnormal phenomena such as interference and jitter of external environment in the starting moment of the component are effectively prevented, the rising edge of the captured CS is prevented from being wrong, the initialization time of the slave SPI is prevented from being inaccurate, and the incorrectness of the SPI received data is finally prevented.

[0008] To achieve the above object, the application provides the following technical scheme: a novel control method for automatically synchronizing SPI master device communication of an SPI slave device, comprising the following steps.

[0009] S1: the SPI master device transmits a CS chip select signal;

[0010] S2: the SPI slave device detects whether there is the CS chip select signal, if not, the SPI master device transmits the CS chip select signal again until the SPI slave device detects the CS chip select signal;

[0011] S3: the timer of the SPI slave device captures the rising edge of the CS and records the number of the rising edges of the CS, and judges whether the set capturing number is reached, if not, the number of the rising edges of the CS is continuously recorded until the set capturing number is reached;

[0012] S4: when the set capturing number is reached, the initialization of the SPI slave device is completed;

[0013] S5: the SPI slave device starts receiving data.

[0014] Preferably, the timer peripheral device is arranged in the SPI slave device, and the capturing function of the hardware timer is configured.

[0015] Preferably in any of the above solutions, the SPI slave device is set as one of FLASH, RAM, network controller, LCD display driver, A / D converter and MCU.

[0016] Technical effects and advantages of the present application: The novel SPI slave device automatic synchronization SPI master device communication control method overcomes the traditional master-slave SPI start time strictly following the standard process (first starting the SPI slave device, and then the master SPI device starts sending data after the SPI slave device is ready), the present application adds a timer in the SPI slave device, captures the rising edge of CS by the timer, selects to complete the initialization of the SPI slave device within the interval of sending twice data (i.e. between the rising edge of CS and the immediately following falling edge), and still can guarantee the correctness of receiving data, so that the master-slave SPI communication is more flexible. BRIEF DESCRIPTION OF DRAWINGS

[0017] Fig. 1 is a master-slave SPI communication diagram of the present application;

[0018] Fig. 2 is a control flow diagram of the present application. DETAILED DESCRIPTION

[0019] The specific embodiments of the present application will be further described below in conjunction with the accompanying drawings. It should be noted that the description of the embodiments is used to help understand the present application, but does not constitute a limitation of the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0020] The present application provides a novel SPI slave device automatic synchronization SPI master device communication control method as shown in Figs. 1-2 The method comprises the following steps:

[0021] S1: The SPI master device sends a CS chip selection signal;

[0022] S2: A timer peripheral is set in the SPI slave device, the capture function of the hardware timer is configured, the SPI slave device is set as one of FLASH, RAM, network controller, LCD display driver, A / D converter and MCU, and the SPI slave device detects whether there is a CS chip selection signal, if not, the SPI master device sends the CS chip selection signal again until the SPI slave device detects the CS chip selection signal;

[0023] S3: The timer of the SPI slave device captures the rising edge of CS and records the number of times of the rising edge of CS, judges whether the set capture number is reached, if not, continues to record the number of times of the rising edge of CS until the set capture number is reached;

[0024] S4: When the set number of captures is reached, then the initialization of the SPI slave is complete;

[0025] S5: The SPI slave begins receiving data.

[0026] Although the embodiments of the present application have been shown and described above, it should be understood by those ordinary skilled in the art that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present application, and those ordinary skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present application.

Claims

1. A novel control method for automatically synchronizing SPI slave device communication with SPI master device, characterized by: The following steps are involved: S1: SPI master sends CS chip select signal; S2: The SPI slave device detects whether there is a CS chip select signal. If not, the SPI master device sends the CS chip select signal again until the SPI slave device detects a CS chip select signal. S3: The timer of the SPI slave device regularly captures the rising edge of CS and records the number of CS rising edges to determine whether the set number of captures is reached. If not, it continues to record the number of CS rising edges until the set number of captures is reached. S4: When the set number of captures is reached, the initialization of the SPI slave device is completed; S5: SPI slave device starts receiving data.

2. The control method for automatically synchronizing SPI master device communication with an SPI slave device according to claim 1, wherein: The SPI slave device is provided with a timer peripheral and a capture function of a hardware timer is configured.

3. The control method for automatically synchronizing SPI master device communication with an SPI slave device according to claim 1, wherein: The SPI slave device is configured as one of FLASH, RAM, network controller, LCD display driver, A / D converter and MCU.

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