A modeling method of a surface potential-based compact model of a GaAs process pHEMT

Abstract

A modeling method of a surface potential-based GaAs process pHEMT compact model comprises: establishing a surface potential-based GaAs pHEMT compact intrinsic model; establishing a surface potential-based GaAs pHEMT compact extrinsic model; combining the physical structure and behavior mechanism of the GaAs pHEMT device, and establishing a compact model and a model topological structure based on intrinsic and extrinsic model equation architectures; describing the surface potential-based GaAs pHEMT compact model by using a Verilog-A language; and giving a compact model parameter extraction method. The method solves the problems that the existing GaAs PHEMT model is difficult to describe the characteristics of a complex and non-uniform surface potential function, the approximate solution is inaccurate, and the channel charge model equation is discontinuous and cannot be used for nonlinear circuit simulation.

Description

Technical Field

[0001] This invention relates to microelectronic device modeling technology, and more particularly to a modeling method for a surface potential-based compact model of a gallium arsenide (GaAs) process pseudo-high electron mobility transistor (pHEMT), specifically a modeling method for a surface potential-based compact model of a GaAs process pHEMT. Background Technology

[0002] GaAs pHEMTs are considered competitive three-terminal devices in the microwave / millimeter-wave device and circuit fields due to their superior performance, including lower output resistance, higher transconductance, greater current handling capability, higher operating frequency, and lower noise. Currently, low-noise amplifiers and power amplifiers made using GaAs pHEMTs are widely used in satellite communications, radar systems, test systems, and navigation systems. GaAs pHEMT models are closely linked to user process lines, serving as a bridge between Electronic Design Automation (EDA) technology and Integrated Circuits (ICs). They play an irreplaceable role in optimizing device structures, reducing circuit development time, promoting upstream and downstream industry integration, reducing development and operating costs, establishing a healthy industrial ecosystem, and enhancing the overall competitiveness of the industry. However, due to limitations in understanding the physical nature of GaAs pHEMTs and the complexity of solving their equations, there have been few breakthroughs in GaAs pHEMT device models, and the development of compact models remains a challenge for both industry and academia. Internationally, GaAs pHEMT nonlinear models used in commercial IC simulation software include the STATZ model used in PSPICE, the Curtice symmetric and asymmetric models developed by EEsof, and the EEHEMT model developed by Agilent Technologies. Existing mainstream models are insufficient to meet the simulation requirements of MMIC CAD and are therefore impractical. The increasing complexity, power, and frequency of GaAs pHEMT structures, along with constantly evolving circuit design requirements, present new challenges and problems for accurate model development and parameter extraction. Developing a compact GaAs pHEMT model has become a recognized challenge in both industry and academia. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of existing GaAs pHEMT modeling techniques by providing a modeling method for a compact model of the GaAs pHEMT surface potential base. This method aims to solve problems such as the difficulty of existing GaAs pHEMT models in describing complex and non-uniform surface potential function characteristics, inaccurate numerical algorithms with approximate solutions, discontinuous channel charge model equations, and inability to be used for nonlinear circuit simulation. Therefore, a more accurate compact model of GaAs pHEMT needs to be established.

[0004] This invention proposes a modeling method for a compact pHEMT model of GaAs process based on surface potential, comprising the following steps:

[0005] S1. Derivation of intrinsic model equations (channel current model and channel charge model) to establish a compact intrinsic model of GaAspHEMT based on surface potential;

[0006] S2. Derivation of the eigenmodel equations: Establishment of a compact eigenmodel of GaAs pHEMT based on surface potential;

[0007] S3. Combining the physical structure and behavioral mechanism of GaAs pHEMT devices, based on the surface potential mechanism, we derive and establish a compact model and its model topology for the intrinsic and extrinsic model equations of GaAsspHEMT devices.

[0008] S4. Describe the surface potential-based GaAs pHEMT compact model established in step S3 using Verilog-A language, so that the compact model can be compiled, linked and used in the EDA software.

[0009] S5, Compact Model Parameter Extraction and Model Validation

[0010] S5-1. Perform on-chip testing on actual GaAs PHEMT devices to obtain various performance test data of GaAs PHEMT devices, including DC characteristics, AC characteristics, and RF characteristics of the devices. Based on the test data, extract parameters for the compact model.

[0011] S5-2, Compact Model Verification, provides a comparison of the device output characteristics, transfer characteristics, transconductance characteristics, capacitance-voltage characteristics, and RF characteristics curves between the test and simulation results.

[0012] The beneficial effects of this invention are:

[0013] (1) The method of deriving the current and charge / capacitance equations of the compact intrinsic model by solving the surface potential equation of the device breaks through the existing GaAs pHEMT device modeling technology. It can solve the physical problems of heterojunction and the numerical algorithm problems caused by the simultaneous self-consistent solution of classical carrier transport equation and new effects in the existing physical model.

[0014] (2) The formula for calculating charge density was re-derived, which solved the problem of difficult bonding in the charge model;

[0015] (3) Considering the correlation between the bias voltage and temperature of charge transport, a thermally assisted tunneling transport mode is proposed to accurately describe the leakage current characteristics of complex gate-source and gate-drain. The gate-source leakage current equation and the gate-drain leakage current equation are derived using the Schottky junction model. The surface potential of each layer of the device is accurately solved to obtain the compact gate-source leakage current model and the source-drain leakage current model based on the surface potential. Attached Figure Description

[0016] Figure 1 The overall workflow for device testing and compact model parameter extraction;

[0017] Figure 2 This is the topology of a compact model of a GaAs pHEMT device, where the area inside the dashed box is the intrinsic part and the area outside the dashed box is the extrinsic part.

[0018] Figure 3 Leakage voltage V for T = 300K d =0V to 1.5V, gate voltage v g = -1.5V to 0V, Leakage Current-Leakage Voltage i in Silicon-based GaAs pHEMT Device Testing and Model Simulation d -v d curve;

[0019] Figure 4 T = 300K, gate voltage v g = -1.5V to 0V, leakage voltage v d =0V to 1.5V, GaAs pHEMT device testing and model simulation (a) Leakage current-gate voltage i d -v g Curve (b) Transconductance-gate voltage g m -v g curve

[0020] Figure 5 T = 300K, Freq = 2GHz, leakage voltage V d =5V, gate voltage v g = -1.5V to 0V(a) Gate-source capacitance C gs With gate bias v g (b) The curve showing the relationship between the changes in gate-drain capacitance C gd With gate bias v g Change relationship curve

[0021] Figure 6 Silicon-based GaAs pHEMT under multiple bias conditions (leakage voltage V) d =5V, gate voltage v g Comparison of S-parameter test and simulation results in the 0.4~40GHz frequency band (-1.5V to -0.8V)

[0022] Figure 7 This describes the process for extracting all parameters from a compact device model. Detailed Implementation

[0023] The specific implementation method is described below with reference to the accompanying drawings.

[0024] The derivation of the intrinsic model equations (channel current model and channel charge model) and the specific implementation of the GaAspHEMT compact intrinsic model based on surface potential are as follows:

[0025] S1-1. The influence of GaAs PHEMT Fermi potential and heterojunction is directly incorporated into the Poisson equation. Based on the carrier distribution in the channel, the Poisson equation (1) is written as follows:

[0026]

[0027] Among them Ψ s ε is the surface potential, q is the charge, and ε is the surface charge. InGaAs P is the dielectric constant, and NInGaAs in the right brackets represents majority electrons. InGaAs Empty holes due to low birth rate;

[0028] The surface potential model equation (2) is established to characterize different device structures and mechanisms of GaAs pHEMT, and the expression is as follows:

[0029]

[0030] Ψ on the surface potential of GaAs pHEMT s It manifests as (V) gs -V fb ) and V cs implicit function, V gs It is the gate-source voltage, V cs It is the voltage applied between the channel and the source, V fb Ψ is the flat-band voltage, γ is the volume factor, and Ψ is the volume factor. F For the Fermi potential, V T Threshold voltage;

[0031] S1-2. Solve the surface potential model equation (2) established in step S1-1. Use the band structure and Poisson's equation in the channel to obtain the initial surface potential of the depletion and accumulation regions in the channel. Apply the Taylor series expansion approximation method to obtain the surface potential Ψ. s Approximate analytical solution;

[0032] S1-3, First, obtain the surface potential Ψ according to step S1-2. s The approximate analytical solution subdivides the working region of the GaAs pHEMT device into three regions, namely Ψ s <0,0<Ψ s<3V T Ψ s >3V T Then, the charge density q of the above three regions is solved using formulas (3) to (5) respectively. i :

[0033] In Ψ s When <0, the charge density q i The calculation is shown in formula (3).

[0034]

[0035] In 0<Ψ s <3V T At that time, the charge density q i The calculation is shown in formula (4).

[0036]

[0037] In Ψ s >3V T At that time, the charge density q i The calculation is shown in formula (5).

[0038]

[0039] Where ξ m This represents the channel potential.

[0040] S1-4. The charge density q calculated above i The terminal charge obtained by integrating the charge density along the y-direction is used to establish the charge model using the following formulas (6) to (8), where formulas (6) to (8) represent the leakage charge Q of the entire working area, respectively. dd Source charge Q ss Gate charge Q gg The equation;

[0041]

[0042]

[0043]

[0044] Where μ is the electron mobility, W is the gate width, and L is the gate length;

[0045] The device charge is divided into three terminal charges: leakage charge Q. dd Source charge Q ss Gate charge Q gg By using the partial derivative of the voltage with respect to these three terminal charges, six capacitors can be obtained:

[0046]

[0047] i and j can be set as the gate (G), drain (D), and source (S) of the pHEMT.

[0048] The derivation of the eigenmodel equations and the specific implementation of establishing a compact eigenmodel of GaAs pHEMT based on surface potential are as follows:

[0049] S2-1. Establish the gate-source leakage current equation and gate-drain leakage current equation based on the Schottky junction surface potential:

[0050] Using the approximate analytical solution method for the surface potential as described in S1-2, the surface potential of the Schottky junction is calculated, and a Schottky junction model is established. Based on the transport mechanism of the gate leakage current under different bias voltage and temperature conditions, the gate-source leakage current equation and the gate-drain leakage current equation are derived to obtain accurate gate-source leakage current and gate-drain leakage current, where both the gate-source and gate-drain leakage currents are proportional to the gate area. Considering that the thermally assisted tunneling transport mode is the main charge transport mechanism, equations (10) to (13) are used to characterize the gate-source leakage current I of the eigenstructure model. gs , grid leakage current I gd :

[0051]

[0052]

[0053]

[0054]

[0055] Where I js J is the reverse saturation current at the source. js N represents the reverse saturation current density at the source. js I is the emission coefficient at the source end. jd J is the drain-side reverse saturation current. jd N is the reverse saturation current density at the drain terminal. jd V is the emission coefficient at the drain end. g φ is the gate voltage. b It is the Schottky barrier, and Area is the area of ​​the Schottky knot;

[0056] S2-2, Deriving the drain-source current I ds Equations, completing the compact eigenmodel:

[0057] The compact intrigumentary model of GaAs pHEMT based on surface potential is calculated, and the expression is as follows:

[0058]

[0059] Ids =0, x g ≤0 (15)

[0060] In the compact eigenmodel, parameter β1 is the aspect ratio of the channel. To normalize the surface potential equation, the variable x is introduced. g x g =(V gs -V fb ) / V T ,Δψ=ψ sd -ψ ss ψ is the change in surface potential within the channel. sd It is the surface potential at the drain end, ψ ss It is the surface potential at the source end;

[0061] μ eff It is the electric field mobility, which is defined as shown in equation (16).

[0062]

[0063] Where μ min μ max n ref α and n are fitting parameters, where n represents the doping concentration; parameter μ max This represents the mobility of undoped samples, primarily scattering via lattice scattering; μ min It represents the mobility of heavily doped materials, primarily due to impurity scattering; the parameter α measures μ. min to μ max The rate of change coefficient; n ref It is μ min With μ max The carrier concentration corresponding to the intermediate mobility, μ x These are parameters of the empirical mobility model; μ E and θ μ These are the corresponding empirical parameters that take into account the decrease in mobility caused by alloy disorder scattering, interface roughness scattering, and lattice vibration scattering; the compact intriguing model parameter CS characterizes Coulomb scattering.

[0064] E of equation (17) eff By calculating the surface potential at the midpoint (φ) ss +φ sd The effective vertical electric field is obtained by ) / 2, assuming that the surface potential varies linearly along the channel, E eff The calculation formula is as follows:

[0065]

[0066] Where ε is the vacuum permittivity and d is the thickness of the InGaAs layer;

[0067] Step S3, combining the physical structure and behavioral mechanism of GaAs pHEMT devices, derives and establishes the intrinsic and extrinsic model equations of GaAs pHEMT devices based on the surface potential mechanism. The specific implementation of the compact model and model topology is as follows:

[0068] Step S3 combines the intrinsic surface potential base current and charge models characterizing channel carrier transport and charge storage behavior proposed in steps S1 and S2 with the extrinsic model describing the extrinsic structural behavior of GaAs pHEMT devices, establishing a compact model topology that describes the device's physical structure and behavioral mechanism. The EDA tool uses the Spice simulator's core solver mode, requiring the transistor model to be described in Spice netlist form when written to the simulator; therefore, the corresponding device model is described using an equivalent circuit topology. The model topology includes the inductor L... g Resistance R g Diode I gs Capacitor C gsx Variable capacitor C gs Inductor L d Resistance R d Diode I gd Capacitor C gdx Variable capacitor C gd Inductor L s Resistance R s Diode I gs Capacitor C ds Capacitor C dsx DC current source I ds .

[0069] The inductor L g One end is connected to resistor R g One end of the inductor L is connected to the other end. g The other end is connected to the gate G terminal, and the resistor R g The other end is connected to diode I gs The positive terminal of the capacitor C is connected to the positive terminal. gsx and variable capacitor C gs In parallel with diode I gs The two ends of the inductor L; d One end is connected to resistor R d One end of the inductor L is connected to the other end. d The other end is connected to the drain terminal D, and the resistor R d The other end is connected to diode I gd The capacitor C is connected to the negative terminal. gdx and variable capacitor C gd In parallel with diode I gd The two ends of the diode I; gsThe positive terminal of diode I gd The positive terminal of the inductor L is connected to the positive terminal; s One end is connected to resistor R s One end of the inductor L is connected to the other end. s The other end is connected to the source terminal S, and the resistor R s The other end is connected to diode I gs The diode I is connected to the negative terminal. gd The negative terminal and resistor R s A DC current source I is connected in series at the other end. ds The capacitor C ds Capacitor C dsx Connected in parallel at I ds The two ends.

[0070] like Figure 2 The physical meaning of each component in the model topology is explained below:

[0071] L g L d L s For bias-independent device port leads with high-frequency parasitic inductance, if the source and drain metal leads are long and the application frequency is high, a pair of R / / L parallel networks need to be connected in series outside each of the three nodes G, D, and S to characterize the metal skin effect that appears at high frequencies.

[0072] R g R d R s Gate, drain, and source contact resistances independent of bias voltage;

[0073] C dsx C gsx C gdx Parasitic capacitances of drain-source, gate-source, and gate-drain in bias-independent layout;

[0074] C gs C gd C ds : The result of the bias voltage calculation based on the total gate charge;

[0075] I ds : A bias-dependent diode connected in parallel across the gate and source terminals;

[0076] R th C th I th Thermoelectric circuit elements, which are independent of bias voltage, are used to characterize the power dissipation under the thermal effect of the device. In continuous wave applications, the thermoelectric circuit can be disabled and the self-heating effect of the device can be replaced by an empirical model. If a heat sink structure is used and it is necessary to estimate the junction temperature change of the device caused by the heat sink, the thermoelectric circuit model is required.

[0077] The bias-independent portion mentioned above is mainly caused by layout parasites, gate diode I. gd and I gs The model is derived using the Schottky junction model. By accurately solving the surface potential of each layer, the gate-source leakage current model and the gate-drain leakage current model based on the surface potential are obtained.

[0078] Step S4 constructs a compact model and model topology for the intrinsic and extrinsic model equations of the GaAs pHEMT device established in step S3, and describes it using Verilog-A language. The specific implementation of the compact model is as follows:

[0079] The source code for the GaAs pHEMT device model, describing its topology and equations, is written in Verilog-A. This source code is directly compiled and linked to various commercial circuit simulators, such as Agilent ADS, Cadence, and Hspice software, enabling the model to be compiled, linked, and used in EDA software (it should be noted that EDA software is conventional commercial software and represents a standard application). This also addresses the interface issues for the model to be integrated into simulators and supported in design applications. The Verilog-A source code architecture is as follows:

[0080]

[0081]

[0082]

[0083] Step S5: Compact model parameter extraction and model validation:

[0084] S5-1. Perform on-wafer testing on the actual GaAs pHEMT device to obtain performance test data, including DC characteristics, AC characteristics, and RF characteristics. Based on the test data, extract parameters for the compact model. The specific method is as follows:

[0085] S5-1-1. Measuring the scattering parameter S under GaAs pHEMT device cutoff conditions, at which time dV ds / dI ds =0 corresponds to a short circuit in the channel of the topology, from which bias-independent parasitic element parameters, including parasitic inductance-leakage and source contact resistance R, can be accurately extracted. d R s High-frequency drain and source parasitic inductance of port leads L d L s ;

[0086] S5-1-2. Measure the scattering parameter S of the GaAs pHEMT device under zero bias. At this time, the topology is equivalent to a passive network. Using the parameters extracted in step S5-1-1, an approximate extraction method is used to convert the scattering parameter S into impedance and admittance parameters, and the parasitic element parameters, including the parasitic inductance L, are directly extracted. g , gate contact resistance R g Layout drain-source parasitic capacitance C ds Layout gate-source parasitic capacitance C gsx Layout gate-drain parasitic capacitance C gdx 。;

[0087] S5-1-3. Measure the DC current and voltage characteristics of the GaAs pHEMT device. Use EDA software fitting method to obtain model parameters including transconductance g. m Drain-source current I ds And by I th =I ds ×V ds Obtain the thermocurrent I of the thermoelectric circuit element th ;

[0088] S5-1-4. Measure the AC characteristics of the GaAs pHEMT device. Obtain the voltage-capacitance characteristic curve of the device by measuring the scattering parameter S over the entire operating region. Use EDA software to extract the three-terminal charge model parameters of the compact intrinsic model of the GaAs pHEMT, including the gate-drain capacitance C. gdi Gate-source capacitance C gsi Source-drain capacitance C dsi ;

[0089] S5-1-5. Measure the scattering parameter S within the set frequency range, and extract the radio frequency characteristic parameters using EDA software.

[0090] S5-1-6. The model parameters extracted in steps S5-1-1 to S5-1-2 are optimized and determined using the stochastic optimization algorithm in EDA software. (It should be noted that the stochastic optimization algorithm is a conventional algorithm, therefore it will not be specifically described or explained in this embodiment.)

[0091] S5-2, Compact Model Verification, provides a comparison of the device output characteristics, transfer characteristics, transconductance characteristics, capacitance-voltage characteristics, and RF characteristics between the test and simulation results.

[0092] Table 1 shows the DC testing scheme for pHEMT in silicon-based GaAs.

[0093] Table 1 DC Test Scheme

[0094]

[0095] Table 2 shows the CV testing scheme for silicon-based GaAs pHEMT devices.

[0096] Table 2 CV Test Plan

[0097]

[0098] Table 3 shows the RF characteristic test scheme for silicon-based GaAs pHEMTs.

[0099] Table 3 RF Characteristic Test Scheme

[0100]

[0101] In this embodiment, Figures 3-6 The test data and model simulation data were compared. The fitting between the device test data and the model simulation results shows that the compact model of the GaAs pHEMT surface potential base device can well reflect the transmission, transfer, and RF characteristics of the GaAs pHEMT device, verifying the effectiveness of the modeling technique proposed in this invention and the accuracy of the compact model. The above device test and model simulation results verify the actual characterization capability and accuracy of the compact model. The compact model of the GaAs pHEMT surface potential base device can well reflect the electrical characteristics of the actual device, proving the effectiveness of the modeling technique proposed in this invention and the accuracy of the compact model.

Claims

1. A modeling method for a compact pHEMT model of GaAs process based on surface potential, characterized in that, Includes the following steps: S1. Derivation of intrinsic model equations: Establishment of a compact intrinsic model of GaAs pHEMT based on surface potential; S2. Derivation of the eigenmodel equations: Establishment of a compact eigenmodel of GaAs pHEMT based on surface potential; S3. Combining the physical structure and behavioral mechanism of GaAs pHEMT devices, a compact model and model topology are derived based on the surface potential mechanism to establish the intrinsic and extrinsic model equations of GaAsspHEMT devices. S4. The intrinsic and extrinsic model equations of the GaAs pHEMT device established in step S3 are used to construct a compact model and model topology, and described using Verilog-A language to obtain a compact model. S5, Compact Model Parameter Extraction and Model Validation S5-1. Perform on-wafer testing on the actual GaAs pHEMT device to obtain performance test data of the GaAs pHEMT device, including the device's DC characteristics, AC characteristics, and RF characteristics. Based on the test data, extract parameters from the compact model. S5-2, Compact Model Verification, provides a comparison of the device output characteristics, transfer characteristics, transconductance characteristics, capacitance-voltage characteristics, and RF characteristics curves between the test and simulation. S1 is specifically as follows: S1-1. The influence of GaAs pHEMT Fermi potential and heterojunction is directly incorporated into the Poisson equation. Based on the carrier distribution in the channel, the Poisson equation (1) is written as follows: （1） Among them Ψ s Let q be the surface potential and q be the charge. The dielectric constant is shown in the square brackets on the right. For majority electrons, Empty holes due to low birth rate; A compact intrinsic model of GaAs pHEMT based on surface potential is established to characterize different device structures and mechanisms. The expression is as follows: （2） Ψ on the surface potential of GaAs pHEMT s V gs -V fb and V cs implicit function, V gs It is the gate-source voltage, V cs It is the voltage applied between the channel and the source, V fb Ψ is the flat-band voltage, γ is the volume factor, and Ψ is the flat-band voltage. F For Fermi potential, V T Threshold voltage; S1-2. Solve the GaAs pHEMT compact intrinsic model (2) based on surface potential established in step S1-1. Use the band structure and Poisson equation in the channel to obtain the initial solution of the surface potential in the depletion region and accumulation region in the channel. Apply the Taylor series expansion approximation method to obtain the surface potential Ψ. s Approximate analytical solution; S1-3, First, obtain the surface potential Ψ according to step S1-2. s The approximate analytical solution subdivides the working region of the GaAs pHEMT device into three regions, namely Ψ s <0, 0<Ψ s < 3V T Ψ s > 3V T Then, the charge density q of the above three regions is solved by formulas (3) to (5) respectively. i : In Ψ s When <0, the charge density q i The calculation is shown in formula (3). （3） In 0<Ψ s <3V T At that time, the charge density q i The calculation is shown in formula (4). （4） In Ψ s > 3V T At that time, the charge density q i The calculation is shown in formula (5). （5） S1-4. The charge density q calculated above i The terminal charge obtained by integrating the charge density along the y-direction is used to establish the charge model using the following formulas (6) to (8), where formulas (6) to (8) represent the leakage charge Q of the entire working area, respectively. dd Source charge Q ss Gate charge Q gg The equation; （6） （7） （8） Where μ is the electron mobility, W is the gate width, and L is the gate length; The device charge is divided into three terminal charges: leakage charge Q. dd Source charge Q ss Gate charge Q gg By partially differentiating the terminal voltage from these three terminal charges, we can obtain six capacitors: （9） i and j can be set as the gate (G), drain (D), and source (S) of the GaAs pHEMT.

2. The modeling method for a compact PHEMT model of GaAs process based on surface potential as described in claim 1, characterized in that, S2 is specifically as follows: S2-1. Establish the gate-source leakage current equation and the gate-drain leakage current equation. Using the approximate analytical solution method for the surface potential as described in S1-2, the surface potential of the Schottky junction is calculated, and a Schottky junction model is established. Based on the transport mechanism of the gate leakage current under different bias voltage and temperature conditions, the gate leakage current equation is derived to obtain the accurate gate leakage current. The gate leakage current is proportional to the gate area, and the thermally assisted tunneling transport mode is the main charge transport mechanism. Equations (10) to (13) are used to characterize the gate-source leakage current I of the eigenstructure model. gs , grid leakage current I gd : （10） （11） （12） （13） Among them I js J is the reverse saturation current at the source. js N represents the reverse saturation current density at the source. js I is the emission coefficient at the source end. jd J is the drain-side reverse saturation current. jd N is the reverse saturation current density at the drain terminal. jd V is the emission coefficient at the drain end. g Gate voltage, It is the Schottky barrier, and Area is the area of ​​the Schottky knot; S2-2, Deriving the drain-source current I ds The equations were used to complete a compact eigenmodel of GaAs pHEMT based on surface potential. The compact intrigumentary model of GaAs pHEMT based on surface potential is calculated, and the expression is as follows: （14） ， （15） Among them, the GaAs pHEMT compact eigenmodel parameters based on surface potential 1 represents the aspect ratio of the channel. To normalize the surface potential equation, the variable x is introduced. g , , ψ sd It is the surface potential at the drain end, ψ ss It is the surface potential at the source end. It is the electric field mobility, defined as （16） Where μ min μ max n ref α and n are fitting parameters, where n represents the doping concentration; parameter μ max It is the mobility of undoped samples, and the main scattering mechanism is lattice scattering; μ min It represents the mobility of heavily doped materials, primarily due to impurity scattering; the parameter α measures μ. min to μ max The rate of change coefficient; n ref It is μ min With μ max The carrier concentration corresponding to the intermediate mobility These are parameters of the empirical mobility model; and These are the corresponding empirical parameters that take into account the decrease in mobility caused by alloy disorder scattering, interface roughness scattering, and lattice vibration scattering; the compact intriguing model parameter CS characterizes Coulomb scattering. E eff It utilizes the surface potential at the midpoint To obtain an effective vertical electric field, it is assumed that the surface potential varies linearly along the channel. （17） in The vacuum permittivity, The thickness is the InGaAs layer.

3. The modeling method for a compact PHEMT model of GaAs process based on surface potential as described in claim 2, characterized in that, S3 is specifically as follows: Using EDA tools in the Spice simulator's core solver mode requires that transistor models be described in Spice netlist form when written to the simulator. Therefore, the corresponding device models are described using equivalent circuit topologies, including inductors. ,resistance ,diode ,capacitance Variable capacitor ,inductance ,resistance ,diode ,capacitance Variable capacitor ,inductance ,resistance ,diode ,capacitance ,capacitance DC current source The inductor One end is connected to the resistor One end of the inductor is connected to the other end. The other end is connected to the gate G terminal, the resistor The other end is connected to the diode The capacitor is connected to the positive terminal. and variable capacitor In parallel with diode The two ends of the inductor; One end is connected to the resistor One end of the inductor is connected to the other end. The other end of the resistor is connected to the drain terminal D. The other end is connected to the diode The capacitor is connected to the negative terminal. and variable capacitor In parallel with diode The two ends of the diode; positive terminal and diode The positive terminal is connected; the inductor One end is connected to the resistor One end of the inductor is connected to the other end. The other end of the resistor is connected to the source S terminal. The other end is connected to the diode The diode is connected to the negative terminal. negative terminal and resistor A DC current source I is connected in series at the other end. ds The capacitor ,capacitance Connected in parallel The two ends.

4. The modeling method for a compact PHEMT model of GaAs process based on surface potential as described in claim 3, characterized in that, S4 is specifically as follows: The source code for the GaAs pHEMT device model topology and equations is described using Verilog-a language. The source code is then directly compiled by a compiler and linked to the model library of a commercial circuit simulation software.

5. The modeling method for a compact PHEMT model of GaAs process based on surface potential as described in claim 4, characterized in that, S5 is specifically as follows: S5-1-1. Measuring the scattering parameter S under GaAs pHEMT device cutoff conditions, at which time dV ds / dI ds =0, corresponding to a short circuit in the channel of the topology, from which bias-independent parasitic element parameters, including parasitic inductance-leakage and source contact resistance R, can be accurately extracted. d R s High-frequency drain and source parasitic inductance of port leads L d L s ; S5-1-2. Measure the scattering parameter S of the GaAs pHEMT device under zero bias. At this time, the topology is equivalent to a passive network. Using the parameters extracted in step S5-1-1, an approximate extraction method is used to convert the scattering parameter S into impedance and admittance parameters, and the parasitic element parameters, including the parasitic inductance L, are directly extracted. g , gate contact resistance R g Layout drain-source parasitic capacitance C ds Layout gate-source parasitic capacitance C gsx Layout gate-drain parasitic capacitance C gdx ; S5-1-3. Measure the DC current and voltage characteristics of the GaAs pHEMT device. Use EDA software fitting method to obtain model parameters including transconductance g. m Drain-source current I ds , and by Obtain the thermocurrent I of the thermoelectric circuit element th ; S5-1-4. Measure the AC characteristics of the GaAs pHEMT device. Obtain the voltage-capacitance characteristic curve of the device by measuring the scattering parameter S over the entire operating region. Use EDA software to extract the three-terminal charge model parameters of the compact intrinsic model of the GaAs pHEMT, including the gate-drain capacitance C. gdi Gate-source capacitance C gsi Source-drain capacitance C dsi ; S5-1-5. Measure the scattering parameter S within the set frequency range, and extract the radio frequency characteristic parameters using EDA software. S5-1-6. Optimize and determine the model parameters extracted in steps S5-1-1 to S5-1-2 using the stochastic optimization algorithm of EDA software.

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