A threshold voltage information processing method and system

Abstract

The present application discloses a threshold voltage information processing method and system, comprising: obtaining first multi-level flash memory information; building a first flash memory channel system model based on the first multi-level flash memory information; obtaining first data information, performing LDPC encoding, performing signal preprocessing on the encoded first data information, and then performing a data programming operation to write it into an erased flash memory cell; performing channel noise interference in the flash memory cell based on the first flash memory channel system model to obtain first threshold voltage information; performing post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information; performing a read operation based on the second threshold voltage information to obtain a log-likelihood ratio value of the second threshold voltage information, and decoding the second threshold voltage information using an LDPC decoding algorithm to correct errors. This method achieves the technical effects of reducing the bit error rate while reducing read latency, accurately compensating for noise, and improving the reliability of flash memory storage.

Description

Technical Field

[0001] The present application relates to the field of information processing technology, and in particular to a threshold voltage information processing method and system. Background Art

[0002] With the rapid development of economy and science and technology, massive amounts of data are constantly being generated. In the era of big data, personal computers, mobile phones, and large data processing centers all need to store the data they generate. How to quickly store and process this data and reduce the cost of data storage is of great significance to promoting the development of the big data era.

[0003] Currently, the main approaches to improving flash memory reliability are signal processing and error correction coding. Since inter-cell interference and persistent noise are the primary noise factors affecting storage reliability, a reread mechanism is currently used to compensate for the impact of noise on the threshold voltage. LDPC error correction codes are used to reduce the bit error rate.

[0004] However, while optimizing the read reference voltage can achieve the lowest raw bit error rate, existing channel detection and noise interference elimination algorithms significantly increase read latency, thereby reducing the overall performance of the storage system, leading to increased storage costs and reduced storage efficiency. There is a technical problem in being unable to simultaneously reduce the bit error rate and read latency, accurately compensate for noise, and improve the reliability of flash memory storage. Summary of the Invention

[0005] The purpose of this application is to provide a threshold voltage information processing method and system to solve the technical problems in the prior art that it is impossible to reduce the read delay while reducing the bit error rate, accurately compensate for noise, and improve the reliability of flash memory storage.

[0006] In view of the above problems, the present application provides a threshold voltage information processing method and system.

[0007] In a first aspect, the present application provides a threshold voltage information processing method, which is implemented by a threshold voltage information processing system, wherein the method includes: obtaining first multi-level flash memory information; building a first flash memory channel system model based on the first multi-level flash memory information; obtaining first data information, performing LDPC encoding on the first data information, and erasing the flash memory unit of the first flash memory channel system model; performing signal preprocessing on the encoded first data information, and then performing a data programming operation to write the erased flash memory unit; performing channel noise interference in the flash memory unit based on the first flash memory channel system model, and obtaining first threshold voltage information; performing post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information; performing a read operation based on the second threshold voltage information to obtain a log-likelihood ratio of the second threshold voltage information, and performing error correction processing on the second threshold voltage information by decoding through an LDPC decoding algorithm.

[0008] On the other hand, the present application also provides a threshold voltage information processing system for executing a threshold voltage information processing method as described in the first aspect, wherein the system includes: a first obtaining unit, the first obtaining unit being used to obtain first multi-level flash memory information; a first building unit, the first building unit being used to build a first flash memory channel system model based on the first multi-level flash memory information; a first encoding unit, the first encoding unit being used to obtain first data information, perform LDPC encoding on the first data information, and perform an erasing operation on the flash memory unit of the first flash memory channel system model; a first writing unit, the first writing unit being used to perform signal preprocessing on the encoded first data information, and then perform a data programming operation to write the erased flash memory unit; a second obtaining unit, the second obtaining unit being used to perform channel noise interference in the flash memory unit based on the first flash memory channel system model, to obtain first threshold voltage information; a third obtaining unit, the third obtaining unit being used to perform post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information; and a first processing unit, the first processing unit being used to perform a read operation based on the second threshold voltage information, obtain a log-likelihood ratio value of the second threshold voltage information, and perform error correction processing on the second threshold voltage information by decoding through an LDPC decoding algorithm.

[0009] In a third aspect, the present application also provides a threshold voltage information processing system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in the first aspect when executing the program.

[0010] In a fourth aspect, a computer-readable storage medium stores a computer program, which, when executed by a processor, implements the method according to any one of the first aspects.

[0011] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0012] The embodiment of the present application obtains first multi-level flash memory information, then builds a first flash channel system model based on the first multi-level flash memory information; obtains first data information, performs LDPC encoding on the first data information, and performs an erasing operation on the flash memory cells of the first flash channel system model; then performs signal preprocessing on the encoded first data information, and then performs a data programming operation to write the erased flash memory cells; after performing channel noise interference in the flash memory cells based on the first flash channel system model, obtains first threshold voltage information; performs post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information; performs a read operation based on the second threshold voltage information to obtain a log-likelihood ratio value of the second threshold voltage information, and decodes the second threshold voltage information using an LDPC decoding algorithm to perform error correction processing. This achieves the technical effect of reducing the bit error rate while reducing read latency, accurately compensating for noise, and improving data storage reliability by establishing a model that analyzes the threshold voltage information, the changing trend of the threshold voltage distribution of flash memory cells, and the error rate under various noise interference conditions.

[0013] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in this application or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely exemplary, and a person of ordinary skill in the art can obtain other drawings based on the provided drawings without any creative work.

[0015] Figure 1 This is a flowchart of a threshold voltage information processing method for this application;

[0016] Figure 2 This is a flow chart of obtaining first threshold voltage information in a threshold voltage information processing method of the present application;

[0017] Figure 3This is a flow chart of a method for processing threshold voltage information of the present application, which performs signal preprocessing on the encoded first data information and then performs a data programming operation to write the erased flash memory unit;

[0018] Figure 4 This is a flow chart of obtaining second threshold voltage information in a threshold voltage information processing method of the present application;

[0019] Figure 5 This is a structural diagram of a threshold voltage information processing system of the present application;

[0020] Figure 6 This is a schematic diagram of the structure of an exemplary electronic device of this application.

[0021] Explanation of the accompanying drawings: first obtaining unit 11, first building unit 12, first encoding unit 13, first writing unit 14, second obtaining unit 15, third obtaining unit 16, first processing unit 17, electronic device 300, memory 301, processor 302, communication interface 303, bus architecture 304. DETAILED DESCRIPTION

[0022] This application provides a threshold voltage information processing method and system to solve the technical problem in the prior art of being unable to simultaneously reduce the bit error rate and read latency, accurately compensate for noise, and improve the reliability of flash memory storage. The present application achieves the technical effect of simultaneously reducing the bit error rate and read latency, accurately compensating for noise, and improving the reliability of data storage.

[0023] The acquisition, storage, use, and processing of data in this application's technical solution comply with relevant national laws and regulations.

[0024] Below, the technical solutions in this application will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, rather than all the embodiments of this application. It should be understood that this application is not limited to the example embodiments described herein. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. It should also be noted that, for the convenience of description, only the parts related to this application, rather than all of them, are shown in the accompanying drawings.

[0025] The present application provides a threshold voltage information processing method, which is applied to a threshold voltage information processing system, wherein the method includes: obtaining first multi-level flash memory information; building a first flash memory channel system model based on the first multi-level flash memory information; obtaining first data information, performing LDPC encoding on the first data information, and performing an erasing operation on the flash memory unit of the first flash memory channel system model; performing signal preprocessing on the encoded first data information, and then performing a data programming operation to write the erased flash memory unit; performing channel noise interference in the flash memory unit based on the first flash memory channel system model, thereby obtaining first threshold voltage information; performing post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information; performing a read operation based on the second threshold voltage information to obtain a log-likelihood ratio value of the second threshold voltage information, and decoding the second threshold voltage information through an LDPC decoding algorithm to perform error correction processing on the second threshold voltage information.

[0026] After introducing the basic principles of the present application, various non-limiting implementation methods of the present application will be specifically introduced in conjunction with the drawings in the specification.

[0027] Example 1

[0028] like Figure 1 As shown, the present application provides a threshold voltage information processing method, wherein the method is applied to a threshold voltage information processing system, and the method specifically includes the following steps:

[0029] Step S100: obtaining first multi-level flash memory information;

[0030] Specifically, multi-level cell (MLC) technology allows each MLC cell to store 2 bits of information, with threshold voltages represented by 11, 10, 00, and 01. This doubles the storage density of SLC. High-density storage can significantly reduce storage costs, as exemplified by high-density NAND flash memory. A multi-level flash memory cell consists of a CMOS transistor with a floating gate. Electrons are stored in the floating gate, which then controls the stored charge between oxide layers. The amount of charge determines the data stored in the flash memory cell. Different electron counts result in different threshold voltages, so different voltages applied between the gate and source result in different currents read by the drain. This allows different information to be represented based on the threshold voltage. Therefore, the first multi-level flash memory information can be read based on the threshold voltage. This first multi-level flash memory information represents the data encoded in the flash memory cell. This provides basic data for subsequent model building.

[0031] Step S200: building a first flash memory channel system model according to the first multi-level flash memory information;

[0032] Specifically, the first flash memory channel system model is a mathematical model used to simulate storage cells. Based on the first multi-level flash memory information as input data, the data storage process, the results of noise interference, and the deviation of the threshold voltage can be displayed in the model. The first flash memory channel system model can better analyze the characteristics of flash memory and simulate the flash memory operation process from a more intuitive perspective. As a result, a model is provided for analyzing threshold voltage information, analyzing the changing trend of the threshold voltage distribution of flash memory storage cells, and the error rate of interference under various noises. At the same time, the technical effect of reducing the bit error rate while reducing the read delay, accurately compensating for noise, and improving the reliability of data storage is achieved.

[0033] Step S300: obtaining first data information, performing LDPC encoding on the first data information, and performing an erasing operation on the flash memory unit of the first flash memory channel system model;

[0034] Specifically, the first data information is data information to be stored in the first flash channel system model and serves as the basis for subsequent analysis. The first data information is LDPC encoded using LDPC encoding technology. The flash memory unit is a unit that stores the encoded first data information. Erasing the flash memory unit of the first flash channel system model is performed to provide space for subsequent programming states, and the data in the flash memory unit must be erased before programming. By LDPC encoding the first data, a technical effect can be achieved that lays the foundation for subsequent processing with a low bit error rate.

[0035] Step S400: After performing signal preprocessing on the encoded first data information, performing a data programming operation to write the erased flash memory unit;

[0036] Specifically, the signal preprocessing of the encoded first data information is to avoid the read amplification problem, that is, the interference data of other pages will be read out first, and the number of pages actually read out will increase, which will lead to an increase in read delay. By knowing the interference page in advance, the threshold voltage offset that may be caused by the victim data is predicted, and preprocessing is performed. The signal preprocessing is used to estimate the channel noise interference intensity and is implemented by the flash memory controller. The data is estimated by the existing technology. The threshold voltage is transferred to the desired position. Among them, the data programming operation is written to the flash memory unit after erasure. The first data information is programmed and written to the flash memory unit after erasure. A low bit error rate can be achieved, and the technical effect of improving the reliability of flash memory storage can be achieved.

[0037] Step S500: Obtaining first threshold voltage information after performing channel noise interference in the flash memory unit based on the first flash memory channel system model;

[0038] Specifically, to analyze the error rate of the threshold voltage of flash memory cells under various noise interferences, the first flash memory channel system model is artificially subjected to channel noise interference. Optionally, the channel noise interference includes: random telegraph noise, which refers to the increase in traps generated at the oxide layer interface due to electron transitions as the number of programming and erasing cycles of the flash memory device increases. More charge is trapped in the traps, which causes the oxide layer electric field potential to decrease, causing subsequent erase operations to become suboptimal; interference between adjacent cells, which refers to the parasitic coupling capacitance effect between the threshold voltage of a storage cell and adjacent cells, which interferes with the threshold voltage signal of adjacent cells; and persistent noise, which refers to the large number of electrons captured by charge traps during large-scale program / erase cycles, forming a percolation path. This will seriously damage the insulation properties of the oxide layer, thereby generating retention noise, which significantly affects data credibility. The specific noise interference method to be used is determined by the staff and is not restricted here.

[0039] Specifically, the first threshold voltage information refers to the threshold voltage information of the flash memory cell after being subjected to noise interference. By subjecting the model to noise interference, the degree of noise impact on the threshold voltage can be intuitively seen, achieving the technical effect of providing a basis for subsequent noise compensation.

[0040] Step S600: performing post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information;

[0041] Specifically, the post-compensation adjustment of the first threshold voltage refers to obtaining the first threshold voltage information after noise interference, thereby knowing the offset of the disturbed threshold voltage and estimating the corresponding interference strength between adjacent cells. The post-compensation operation can be completed by subtracting the estimated interference amount from the detected disturbed threshold voltage. The second threshold voltage information refers to the threshold voltage information after post-compensation adjustment. This achieves the technical effect of further adjusting the second threshold voltage to support the subsequent actual use of error correction codes.

[0042] Step S700: performing a read operation based on the second threshold voltage information to obtain a log-likelihood ratio value of the second threshold voltage information, and performing error correction processing on the second threshold voltage information by decoding through an LDPC decoding algorithm.

[0043] Specifically, by reading the second threshold voltage information, estimating the compensated threshold voltage probability density function through maximum likelihood estimation, and finally decoding the second threshold voltage information through an LDPC decoding algorithm to perform error correction, the technical effects of reducing the bit error rate while reducing read latency, accurately compensating for noise, and improving the reliability of flash memory storage are achieved.

[0044] Further, such as Figure 2 As shown, after performing channel noise interference in the flash memory unit based on the first flash memory channel system model to obtain first threshold voltage information, step S500 in this embodiment of the application further includes:

[0045] Step S510: estimating channel noise interference intensity information based on a signal preprocessing technique to obtain first estimated interference intensity information;

[0046] Step S520: obtaining threshold voltage offset information based on the first estimated interference intensity information;

[0047] Step S530: monitoring the threshold voltage of the first data information to obtain threshold voltage information of the interfered unit;

[0048] Step S540: adjusting the threshold voltage information of the interfered unit according to the threshold voltage offset information to obtain the first threshold voltage information.

[0049] Specifically, the signal preprocessing technology is used to estimate the intensity of channel noise interference and is implemented by a flash memory controller. The first estimated interference intensity information refers to information on the degree of predicted noise interference intensity, which is used to obtain the offset of the threshold voltage after being interfered with by noise. The threshold voltage offset information refers to the offset of the threshold voltage after being interfered with by noise relative to the threshold voltage under normal circumstances, which is the basis for subsequent adjustment of the interference amount. By monitoring the threshold voltage of the first data information, the threshold voltage information of the interfered unit is obtained. The threshold voltage of the interfered unit is adjusted based on the estimated offset to obtain the first threshold voltage information. By predicting the interference intensity, the first threshold voltage information after the offset is adjusted is obtained, thereby achieving a technical effect that lays the foundation for subsequent post-compensation operations.

[0050] Further, such as Figure 3 As shown, step S600 in this embodiment of the application further includes:

[0051] Step S610: After writing the first data information into the flash memory unit, monitoring the threshold voltage information of each flash memory unit in the first multi-level flash memory information to obtain the threshold voltage range of each flash memory unit;

[0052] Step S620: obtaining a threshold voltage upper limit value set based on the threshold voltage range of each flash memory cell;

[0053] Step S630: estimating the threshold voltage of each flash memory cell based on the threshold voltage upper limit value set to obtain an estimated voltage value set.

[0054] Further, such as Figure 4 As shown, in performing post-compensation adjustment on the first threshold voltage information to obtain the second threshold voltage information, step S600 in the embodiment of the present application further includes:

[0055] Step S640: obtaining threshold voltage offset information of each disturbing flash memory cell;

[0056] Step S650: obtaining total threshold voltage offset information of victim cells based on the threshold voltage offset information of each disturbing flash memory cell;

[0057] Step S660: performing post-compensation adjustment based on the victim cell total threshold voltage offset information and the estimated voltage value set to obtain the second threshold voltage information.

[0058] Specifically, the threshold voltage range of each flash memory cell is obtained by monitoring, and then the threshold voltage upper limit value set is obtained. The threshold voltage of each flash memory cell is estimated based on the threshold voltage upper limit value set, and the estimated voltage value set is used. The threshold voltage upper limit value refers to the maximum threshold voltage value in the threshold voltage range of each flash memory cell. The voltage values ​​in the estimated voltage value set are not the actual threshold voltage values ​​of each flash memory cell, but are estimated based on the actual maximum threshold voltage value. This achieves the technical effect of providing basic data for subsequently reducing the threshold voltage read latency based on the estimated voltage values.

[0059] Specifically, after monitoring the threshold voltage information of each flash memory cell in the first multi-level flash memory information and obtaining the threshold voltage range of each flash memory cell, threshold voltage offset information of the disturbed flash memory cell is determined. The threshold voltage offset information of each disturbing flash memory cell is the difference between the threshold voltage of the disturbed flash memory cell and the threshold voltage under normal conditions, and the total threshold voltage offset information of the victim cell is the total offset information obtained by aggregating the threshold voltage offset information of each disturbing flash memory cell.

[0060] Specifically, post-compensation adjustment technology is significantly effective in improving the reliability of flash memory data storage, but it introduces monitoring delays, limiting the application of signal processing technology in flash memory. By using the estimated voltage value set, read operations are reduced, thereby compensating for the increased monitoring delay. This approach, by analyzing the changes in the threshold voltage signal affected by interference and estimating the threshold voltage of each flash memory cell based on the upper threshold voltage limit, reduces the disadvantages of post-compensation and achieves the technical effect of supporting the use of error correction codes in subsequent flash memory storage.

[0061] Furthermore, step S600 in the embodiment of the present application further includes:

[0062] Step S670: Based on the channel noise interference, obtain channel interference factor information and channel interference intensity information;

[0063] Step S680: Obtaining a first compensation offset value based on the channel interference factor information and the channel interference intensity information;

[0064] Step S690: performing threshold voltage correction on the second threshold voltage information based on the first compensation offset value.

[0065] Specifically, the corresponding channel interference factor information and the channel interference intensity information are obtained according to the selected channel noise interference mode. The channel interference factor information refers to the factors that affect the generation of the channel noise interference. Optionally, the channel interference factor information includes the migration speed of carriers, the distance between flash memory array units, the data storage time, the amount of charge stored at the floating gate level of the transistor, etc., which can be selected according to actual conditions and are not limited here. The channel interference intensity information is the intensity information of the noise interference generated by the channel interference factor. Optionally, the channel interference intensity information includes the degree of threshold voltage signal offset, the magnitude of the parasitic capacitance coupling effect between storage units, etc.

[0066] Specifically, the first compensation offset value is an adjustment value of the second threshold voltage information required to overcome the channel noise interference. Further, the second threshold voltage information is threshold voltage corrected according to the first compensation offset value to offset the influence of the noise interference.

[0067] Specifically, due to the interference of various noises, errors may occur in reading the threshold voltage during the decoding stage, thereby greatly reducing the decoding performance. Therefore, by obtaining the first compensation offset value, the second threshold voltage information can be corrected to improve the accuracy of the threshold voltage, thereby achieving the technical effect of improving storage reliability.

[0068] Furthermore, in performing a read operation based on the second threshold voltage information to obtain a log-likelihood ratio value of the second threshold voltage information, and performing error correction processing on the second threshold voltage information by decoding using an LDPC decoding algorithm, step S700 in this embodiment of the present application further includes:

[0069] Step S710: Generate threshold voltage sequences of the interfered unit and the interferer unit using the first flash memory channel system model to form a two-dimensional training data set, wherein the flash memory channel noise sources of the first flash memory channel system model include random telegraph noise, persistent noise, and inter-unit interference;

[0070] Step S720: Obtaining the unit state of the LDPC decoding of the two-dimensional training data set, and performing one-hot encoding on the unit state to obtain a data label set;

[0071] Step S730: Train a convolutional neural network model based on the two-dimensional training data set and the data label set to obtain a flash channel detection model.

[0072] Specifically, by subjecting the first flash channel system model to noise interference, a threshold voltage sequence of the interfered unit and the interfering unit is obtained as a two-dimensional training data set. The information in the sequence is decoded using LDPC. If the decoding is successful, the decoded state after one-hot encoding preprocessing is used as a label to obtain the data label set. The data label set is used to train the convolutional neural network model to detect the second threshold voltage information.

[0073] Specifically, the flash channel detection model is a mathematical model obtained by training the two-dimensional training dataset and the first data label set as input data. Furthermore, the flash channel detection model is a mathematical logic model built on a convolutional neural network model. It utilizes the continuous convergence of data for analysis and then outputs converged information based on machine learning, i.e., the status of the flash memory cells as a simulation result. This achieves the technical effect of accurately detecting storage performance and improving storage reliability.

[0074] Furthermore, step S700 in the embodiment of the present application further includes:

[0075] Step S740: obtaining threshold voltage information of a first interfering unit and a first interfered unit based on the first data information;

[0076] Step S750: Arrange the threshold voltage information to obtain first input sequence information;

[0077] Step S760: inputting the first input sequence information into the flash channel detection model to obtain state probability information of the flash memory unit;

[0078] Step S770: Obtaining first verification information based on the state probability information;

[0079] Step S780: verifying the log-likelihood ratio of the second threshold voltage information based on the first verification information to obtain a first verification result.

[0080] Specifically, the first interfering unit is a unit that generates noise interference in the first data information, and the first interfered unit is a unit that is interfered with by noise in the first data information. The first input sequence information is obtained by arranging the threshold voltage information of the first interfering unit and the first interfered unit in a certain order, including but not limited to sequence information obtained by arranging in time sequence. The state probability information obtained for the flash memory unit refers to the probability that the flash memory unit is in a certain channel. Exemplarily, the certain channel can be one of 11, 10, 00, and 01. The first verification information is the log-likelihood ratio value obtained by calculating the log-likelihood ratio value based on the obtained state probability, that is, the predicted log-likelihood ratio value information calculated after prediction by the flash channel detection model. Furthermore, by verifying the log-likelihood ratio of the first verification information and the second threshold voltage information, a first verification result is obtained. The first verification result is the error analysis result of the log-likelihood ratio. The first verification result can be used to determine whether the adjusted storage state is normal or whether the adjusted storage state still has significant interference. Furthermore, those skilled in the art can adaptively adjust the second threshold voltage based on the first verification result. For example, if the first verification result shows that the two log-likelihood ratios are within a certain error range, no adjustment is made; if they are outside the certain error range, the second threshold voltage is thresholded again. This achieves the technical effect of reducing latency and improving error correction performance.

[0081] In summary, the application provides one The threshold voltage information processing method has the following technical effects:

[0082] 1. By obtaining first multi-level flash memory information; building a first flash memory channel system model based on the first multi-level flash memory information; obtaining first data information, performing LDPC encoding on the first data information, and performing an erasing operation on the flash memory unit of the first flash memory channel system model; performing signal preprocessing on the encoded first data information, and then performing a data programming operation to write the erased flash memory unit; performing channel noise interference in the flash memory unit based on the first flash memory channel system model to obtain first threshold voltage information; performing post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information; performing a read operation based on the second threshold voltage information to obtain a log-likelihood ratio value of the second threshold voltage information, and performing error correction processing on the second threshold voltage information by decoding the second threshold voltage information using an LDPC decoding algorithm, the technical effects of reducing bit error rate while reducing read latency, accurately compensating for noise, and improving the reliability of flash memory storage are achieved.

[0083] 2. Perform threshold voltage monitoring on the first data information to obtain threshold voltage information of the interfered unit. By obtaining the first compensation offset value, the second threshold voltage information can be corrected to improve the accuracy of the threshold voltage, thereby achieving the technical effect of improving storage reliability.

[0084] 3. Based on the threshold voltage ranges of the flash memory cells, a set of threshold voltage upper bounds is obtained, and the threshold voltage of each flash memory cell is estimated based on the set of threshold voltage upper bounds to obtain a set of estimated voltage values. By analyzing the changes in the threshold voltage signal affected by interference and estimating the threshold voltage of each flash memory cell based on the threshold voltage upper bounds, the read latency is reduced, thereby mitigating the disadvantages of post-compensation and providing support for the use of error correction codes in subsequent flash memory storage.

[0085] Example 2

[0086] Based on the same inventive concept as the threshold voltage information processing method in the above embodiment, Figure 5 As shown, the present application also provides a threshold voltage information processing system, the system comprising:

[0087] A first obtaining unit 11, wherein the first obtaining unit 11 is configured to obtain first multi-level flash memory information;

[0088] A first building unit 12, the first building unit 12 is used to build a first flash memory channel system model according to the first multi-level flash memory information;

[0089] a first encoding unit 13, configured to obtain first data information, perform LDPC encoding on the first data information, and perform an erasing operation on the flash memory unit of the first flash channel system model;

[0090] A first writing unit 14, configured to perform signal preprocessing on the encoded first data information and then perform a data programming operation to write the data into the erased flash memory unit;

[0091] A second obtaining unit 15 is configured to obtain first threshold voltage information after performing channel noise interference in the flash memory unit based on the first flash memory channel system model;

[0092] a third obtaining unit 16, configured to perform post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information;

[0093] The first processing unit 17 is configured to perform a read operation based on the second threshold voltage information, obtain a log-likelihood ratio value of the second threshold voltage information, and perform error correction processing on the second threshold voltage information by decoding the information through an LDPC decoding algorithm.

[0094] Furthermore, the system further comprises:

[0095] a fourth obtaining unit, configured to estimate channel noise interference intensity information based on a signal preprocessing technique to obtain first estimated interference intensity information;

[0096] a fifth obtaining unit, configured to obtain threshold voltage offset information based on the first estimated interference intensity information;

[0097] a sixth obtaining unit, configured to monitor a threshold voltage of the first data information to obtain threshold voltage information of an interfered unit;

[0098] A seventh obtaining unit is configured to adjust the threshold voltage information of the interfered unit according to the threshold voltage offset information to obtain the first threshold voltage information.

[0099] Furthermore, the system further comprises:

[0100] an eighth obtaining unit, configured to, after writing the first data information into the flash memory unit, monitor the threshold voltage information of each flash memory unit in the first multi-level flash memory information to obtain a threshold voltage range of each flash memory unit;

[0101] a ninth obtaining unit, configured to obtain a threshold voltage upper limit value set based on the threshold voltage range of each flash memory cell;

[0102] A tenth obtaining unit is configured to estimate the threshold voltage of each flash memory cell based on the threshold voltage upper limit value set to obtain an estimated voltage value set.

[0103] Furthermore, the system further comprises:

[0104] an eleventh obtaining unit, configured to obtain threshold voltage offset information of each interference flash memory cell;

[0105] a twelfth obtaining unit, configured to obtain total threshold voltage offset information of victim cells based on the threshold voltage offset information of each disturbing flash memory cell;

[0106] A thirteenth obtaining unit is configured to perform post-compensation adjustment based on the victim cell total threshold voltage offset information and the estimated voltage value set to obtain the second threshold voltage information.

[0107] Furthermore, the system further comprises:

[0108] a fourteenth obtaining unit, configured to obtain channel interference factor information and channel interference intensity information based on the channel noise interference;

[0109] a fifteenth obtaining unit, configured to obtain a first compensation offset value based on the channel interference factor information and the channel interference intensity information;

[0110] A first correction unit is configured to perform threshold voltage correction on the second threshold voltage information based on the first compensation offset value.

[0111] Furthermore, the system further comprises:

[0112] a first generating unit, configured to generate, by using the first flash memory channel system model, a threshold voltage sequence of an interfered unit and an interfering unit to form a two-dimensional training data set, wherein the flash memory channel noise sources of the first flash memory channel system model include random telegraph noise, persistent noise, and inter-unit interference;

[0113] a sixteenth obtaining unit, the sixteenth obtaining unit being configured to obtain a unit state of LDPC decoding of the two-dimensional training data set, and to perform one-hot encoding on the unit state to obtain a data label set;

[0114] A seventeenth obtaining unit is used to train a convolutional neural network model based on the two-dimensional training data set and the data label set to obtain a flash channel detection model.

[0115] Furthermore, the system further comprises:

[0116] an eighteenth obtaining unit, configured to obtain threshold voltage information of the first interfering unit and the first interfered unit based on the first data information;

[0117] a nineteenth obtaining unit, configured to arrange the threshold voltage information to obtain first input sequence information;

[0118] a twentieth obtaining unit, configured to input the first input sequence information into the flash channel detection model to obtain state probability information of the flash memory unit;

[0119] a twenty-first obtaining unit, configured to obtain first verification information based on the state probability information;

[0120] The twenty-second obtaining unit is configured to verify the log-likelihood ratio of the second threshold voltage information based on the first verification information to obtain a first verification result.

[0121] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. Figure 1 The threshold voltage information processing method and specific examples in the first embodiment are also applicable to the threshold voltage information processing system of the present embodiment. Through the detailed description of the threshold voltage information processing method above, those skilled in the art will clearly understand the threshold voltage information processing system of the present embodiment. Therefore, for the sake of brevity, a detailed description is not given here. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For relevant details, please refer to the description of the method section.

[0122] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0123] Example 3

[0124] Based on the same inventive concept as the threshold voltage information processing method in the aforementioned embodiment, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method in embodiment 1 is implemented.

[0125] Exemplary electronic devices

[0126] Reference below Figure 6 To describe the electronic device of this application,

[0127] Based on the same inventive concept as a threshold voltage information processing method in the aforementioned embodiment, the present application also provides a threshold voltage information processing system, including: a processor, the processor is coupled to a memory, the memory is used to store a program, when the program is executed by the processor, the system executes the steps of the method described in embodiment one.

[0128] The electronic device 300 includes: a processor 302, a communication interface 303, and a memory 301. Optionally, the electronic device 300 may further include a bus architecture 304. The communication interface 303, the processor 302, and the memory 301 may be interconnected via the bus architecture 304; the bus architecture 304 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus architecture 304 may be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0129] The processor 302 may be a CPU, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the present application.

[0130] The communication interface 303 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), wired access network, etc.

[0131] The memory 301 can be a ROM or other type of static storage device that can store static information and instructions, a RAM or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, a laser disc, an optical disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory can exist independently and be connected to the processor via the bus architecture 304. The memory can also be integrated with the processor.

[0132] The memory 301 is used to store computer-executable instructions for executing the solution of the present application, and the execution is controlled by the processor 302. The processor 302 is used to execute the computer-executable instructions stored in the memory 301, thereby implementing a threshold voltage information processing method provided in the above embodiment of the present application.

[0133] Those skilled in the art will understand that the various numerical numbers such as the first and second involved in this application are only for the convenience of description, and are not used to limit the scope of this application, nor do they indicate the order of precedence. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one" refers to one or more. At least two refers to two or more. "At least one", "any one" or similar expressions refer to any combination of these items, including any combination of single items (individuals) or plural items (individuals). For example, at least one item (individual, kind) of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0134] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0135] The various illustrative logic units and circuits described in this application may be implemented or operated by a design comprising a general purpose processor, a digital signal processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general purpose processor may be a microprocessor, which may alternatively be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration.

[0136] The steps of the method or algorithm described in this application can be directly embedded in hardware, software units executed by a processor, or a combination of the two. The software units can be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from the storage medium and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and the storage medium can be arranged in an ASIC, and the ASIC can be arranged in a terminal. Optionally, the processor and the storage medium can also be arranged in different components in the terminal. These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are performed on the computer or other programmable device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable device provide for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0137] Although the present application has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and drawings are merely illustrative of the present application and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the scope of the present application. Thus, the present application is intended to include such modifications and variations as fall within the scope of the present application and its equivalents.

Claims

1. A threshold voltage information processing method, characterized in that: The method comprises: Obtaining first multi-level flash memory information; Building a first flash memory channel system model according to the first multi-level flash memory information; Obtaining first data information, performing LDPC encoding on the first data information, and performing an erasing operation on a flash memory unit of the first flash memory channel system model; After performing signal preprocessing on the encoded first data information, performing a data programming operation to write the erased flash memory unit; After performing channel noise interference in the flash memory unit based on the first flash memory channel system model, first threshold voltage information is obtained; performing post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information; performing a read operation based on the second threshold voltage information to obtain a log-likelihood ratio value of the second threshold voltage information, and performing error correction processing on the second threshold voltage information by decoding the information using an LDPC decoding algorithm; After writing the first data information into the flash memory unit, monitoring the threshold voltage information of each flash memory unit in the first multi-level flash memory information to obtain the threshold voltage range of each flash memory unit; Obtaining a threshold voltage upper limit value set based on the threshold voltage range of each flash memory cell; The threshold voltage of each flash memory cell is estimated based on the threshold voltage upper limit value set to obtain an estimated voltage value set.

2. The method according to claim 1, wherein After performing channel noise interference in the flash memory unit based on the first flash memory channel system model, obtaining first threshold voltage information, the method includes: estimating channel noise interference intensity information based on a signal preprocessing technique to obtain first estimated interference intensity information; obtaining threshold voltage offset information based on the first estimated interference strength information; Performing threshold voltage monitoring on the first data information to obtain threshold voltage information of an interfered unit; The threshold voltage information of the interfered unit is adjusted according to the threshold voltage offset information to obtain the first threshold voltage information.

3. The method according to claim 1, wherein The method of performing post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information includes: Obtaining threshold voltage offset information of each interfering flash memory cell; Based on the threshold voltage offset information of each interfering flash memory cell, obtaining the total threshold voltage offset information of the victim cell; A post-compensation adjustment is performed based on the victim cell total threshold voltage offset information and the estimated voltage value set to obtain the second threshold voltage information.

4. The method according to claim 1, wherein The method comprises: Based on the channel noise interference, obtaining channel interference factor information and channel interference intensity information; Obtaining a first compensation offset value based on the channel interference factor information and the channel interference strength information; Threshold voltage correction is performed on the second threshold voltage information based on the first compensation offset value.

5. The method according to claim 1, wherein The method comprises: Generate threshold voltage sequences of the interfered unit and the interferer unit through the first flash memory channel system model to form a two-dimensional training data set, wherein the flash memory channel noise sources of the first flash memory channel system model include random telegraph noise, persistent noise and inter-unit interference; Obtaining a unit state of LDPC decoding of the two-dimensional training data set, and performing one-hot encoding on the unit state to obtain a data label set; A convolutional neural network model is trained based on the two-dimensional training data set and the data label set to obtain a flash channel detection model.

6. The method according to claim 5, wherein The method comprises: Based on the first data information, obtaining threshold voltage information of a first interfering unit and a first interfered unit; Arranging the threshold voltage information to obtain first input sequence information; Inputting the first input sequence information into the flash memory channel detection model to obtain state probability information of the flash memory unit; Based on the state probability information, obtaining first verification information; The log-likelihood ratio value of the second threshold voltage information is verified based on the first verification information to obtain a first verification result.

7. A threshold voltage information processing system, characterized in that: The system is applied to the method according to any one of claims 1 to 6, and the system comprises: a first obtaining unit, configured to obtain first multi-level flash memory information; a first building unit, configured to build a first flash memory channel system model according to the first multi-level flash memory information; a first encoding unit, configured to obtain first data information, perform LDPC encoding on the first data information, and perform an erasing operation on a flash memory unit of the first flash channel system model; a first writing unit, configured to perform signal preprocessing on the encoded first data information and then perform a data programming operation to write the data into the erased flash memory unit; a second obtaining unit, configured to obtain first threshold voltage information after performing channel noise interference in the flash memory unit based on the first flash memory channel system model; a third obtaining unit, configured to perform post-compensation adjustment on the first threshold voltage information to obtain second threshold voltage information; The first processing unit is configured to perform a read operation based on the second threshold voltage information, obtain a log-likelihood ratio value of the second threshold voltage information, and perform error correction processing on the second threshold voltage information by decoding the information through an LDPC decoding algorithm.

8. A threshold voltage information processing system, characterized in that: include: A processor, the processor is coupled to a memory, the memory is used to store a program, when the program is executed by the processor, the system is enabled to perform the steps of any one of the methods of claims 1 to 6.

9. A computer program product, characterized in that The storage medium stores a computer program, which implements the steps of the method according to any one of claims 1 to 6 when executed by a processor.

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