Array substrate, manufacturing method thereof and display device

Abstract

This application discloses an array substrate, its fabrication method, and a display device. The array substrate includes a display area and a surrounding border area. The array substrate includes a substrate, driving transistors, switching transistors, and gate driving transistors. The driving transistors and switching transistors are disposed on the substrate. The driving transistors and switching transistors are located in the display area. The driving transistor includes a first active portion. The switching transistor includes a second active portion. The gate driving transistor is located in the border area. The gate driving transistor includes a third active portion. The first, second, and third active portions are made of the same material. The carrier concentrations of the second and third active portions are both greater than the carrier concentration of the first active portion, which improves the mobility of the switching transistors and gate driving transistors while simultaneously enhancing the stability of the driving transistors, thereby ensuring the transistor performance requirements of different regions in the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, its fabrication method, and a display device. Background Technology

[0002] The array substrate typically includes thin-film transistors (TFTs). TFTs are generally classified into three types: amorphous silicon transistors, polycrystalline silicon transistors, and oxide semiconductor transistors. The active layer of an amorphous silicon transistor is formed from amorphous silicon. Because the active layer of an amorphous silicon transistor is formed from amorphous silicon, its fabrication process is simple, it has good uniformity, and low mobility. The active layer of a polycrystalline silicon transistor is formed from polycrystalline silicon, resulting in high mobility, but its fabrication process is complex and its uniformity is poor. The active layer of an oxide semiconductor transistor uses oxide semiconductors, which offer good uniformity, high mobility, simple fabrication process, and low cost.

[0003] Different regions within an array substrate have varying requirements for TFT performance. For instance, TFTs in the display area require high stability and low off-state current, while TFTs in the bezel area require high mobility. Currently, transistors using the same material for the active layer cannot meet the performance requirements of different regions, resulting in poor performance of the array substrate. Summary of the Invention

[0004] This application provides an array substrate, a method for fabricating the same, and a display device, which improves the mobility of the switching transistor and the gate driving transistor, and also improves the stability of the driving transistor.

[0005] This application provides an array substrate, the array substrate including a display area and a border area surrounding the display area, the array substrate comprising:

[0006] substrate;

[0007] A driving transistor and a switching transistor are disposed on the substrate, the driving transistor and the switching transistor being located in the display area, the driving transistor including a first active portion, and the switching transistor including a second active portion; and

[0008] A gate driving transistor is disposed on the substrate, the gate driving transistor is located in the border region, and the gate driving transistor includes a third active portion;

[0009] The first active part, the second active part, and the third active part are all made of the same material, and the carrier concentration of the second active part and the carrier concentration of the third active part are both greater than the carrier concentration of the first active part.

[0010] Optionally, in some embodiments of this application, the thickness of the second active portion and the thickness of the third active portion are both greater than the thickness of the first active portion.

[0011] Optionally, in some embodiments of this application, the thickness of the second active portion is the same as the thickness of the third active portion.

[0012] Optionally, in some embodiments of this application, the width of the second active portion and the width of the third active portion are both smaller than the width of the first active portion.

[0013] Optionally, in some embodiments of this application, the driving transistor, the switching transistor, and the gate driving transistor are disposed on the same layer, the driving transistor is located on the side of the switching transistor away from the gate driving transistor, and the first active portion, the second active portion, and the third active portion are disposed on the same layer and spaced apart on the substrate.

[0014] Optionally, in some embodiments of this application, the thickness of the first active part is 99-999 angstroms, and the thickness of the second active part and the thickness of the third active part are both 100-1000 angstroms.

[0015] Optionally, in some embodiments of this application, the thickness of the first active portion is 150-349 angstroms, and the thicknesses of the second and third active portions are 350-1000 angstroms.

[0016] Optionally, in some embodiments of this application, the materials of the first active part, the second active part, and the third active part all contain at least indium and zinc.

[0017] Optionally, in some embodiments of this application, the materials of the first active portion, the second active portion, and the third active portion all include metal oxide semiconductors.

[0018] This application also provides a display device, which includes an array substrate as described above.

[0019] This application also provides a method for fabricating an array substrate, the array substrate including a display area and a border area surrounding the display area, the fabrication method comprising:

[0020] Provide a substrate; and

[0021] A first semiconductor material is disposed on the substrate and patterned to form a first active portion, the first active portion being located in the display area; a second semiconductor material is disposed on the substrate and patterned to form a second active portion and a third active portion spaced apart, the second active portion being located in the display area and the third active portion being located in the border area;

[0022] or,

[0023] A second semiconductor material is disposed on the substrate and patterned to form a second active portion and a third active portion spaced apart. The second active portion is located in the display area, and the third active portion is located in the border area. A first semiconductor material is disposed on the substrate and patterned to form a first active portion, which is located in the display area.

[0024] Wherein, the first semiconductor material and the second semiconductor material are the same, and the carrier concentration of the second active part and the carrier concentration of the third active part are both greater than the carrier concentration of the first active part.

[0025] This application discloses an array substrate, its fabrication method, and a display device. The array substrate includes a display area and a border area surrounding the display area. The array substrate includes a substrate, driving transistors, switching transistors, and gate driving transistors. The driving transistors and switching transistors are disposed on the substrate. The driving transistors and switching transistors are located in the display area. The driving transistor includes a first active portion. The switching transistor includes a second active portion. The gate driving transistor is located in the border area. The gate driving transistor includes a third active portion. The first, second, and third active portions are made of the same material. The carrier concentrations of the second and third active portions are both greater than the carrier concentration of the first active portion, which improves the mobility of the switching transistors and gate driving transistors while simultaneously increasing the stability of the driving transistors, thereby ensuring the transistor performance requirements of different regions in the array substrate. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of the array substrate provided in the embodiments of this application.

[0028] Figure 2This is a schematic diagram showing the relationship between carrier concentration and mobility in the active portion of the array substrate provided in this application embodiment.

[0029] Figure 3 This is a planar schematic diagram of the switching transistor in the array substrate provided in the embodiments of this application.

[0030] Figure 4 This is a first type of data graph showing the current and voltage of the switching transistor and the gate drive transistor in the array substrate provided in this application embodiment.

[0031] Figure 5 This is a second data graph showing the current and voltage of the switching transistors and gate drive transistors in the array substrate provided in this application embodiment.

[0032] Figure 6 This is a third type of data graph showing the current and voltage of the switching transistors and gate drive transistors in the array substrate provided in this application embodiment.

[0033] Figure 7 This is a flowchart of the steps of the method for fabricating an array substrate provided in the embodiments of this application.

[0034] Figure label:

[0035] Array substrate 10; display area 11; bezel area 12; substrate 100; buffer layer 200; driving transistor 300; first active portion 310; light-shielding portion 320; first gate insulating portion 330; first gate 340; first source 350; first drain 360; switching transistor 400; second active portion 410; second gate insulating portion 420; second gate 430; second source 440; second drain 450; gate driving transistor 500; third active portion 510; third gate insulating portion 520; third gate 530; third source 540; third drain 550; interlayer dielectric layer 600; first via 601; second via 602; third via 603; fourth via 604; fifth via 605; sixth via 606; seventh via 607; passivation layer 700. Detailed Implementation

[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device. In this application, "reaction" can be a chemical reaction or a physical reaction.

[0037] This application discloses an array substrate, its fabrication method, and a display device. The array substrate includes a display area and a border area surrounding the display area. The array substrate includes a substrate, a driving transistor, a switching transistor, and a gate driving transistor. The driving transistor and the switching transistor are disposed on the substrate. The driving transistor and the switching transistor are located in the display area, and the driving transistor includes a first active portion. The switching transistor includes a second active portion. The gate driving transistor is located in the border area. The gate driving transistor includes a third active portion. The first active portion, the second active portion, and the third active portion are made of the same material. The carrier concentrations of the second active portion and the third active portion are both greater than the carrier concentration of the first active portion.

[0038] In this application, the carrier concentration is proportional to the mobility. Therefore, the carrier concentrations of the second active part and the third active part are set to be greater than the carrier concentration of the first active part. This improves the mobility of the switching transistor and the gate drive transistor while also improving the stability of the drive transistor, thereby ensuring the transistor performance requirements of different regions in the array substrate.

[0039] Please see Figure 1 This application provides an array substrate 10. The array substrate 10 includes a display area 11 and a border area 12 surrounding the display area 11. The array substrate 10 includes a substrate 100, a buffer layer 200, a driving transistor 300, a switching transistor 400, a gate driving transistor 500, an interlayer dielectric layer 600, and a passivation layer 700.

[0040] A driving transistor 300 and a switching transistor 400 are disposed on the substrate 100 and located in the display area 11. The driving transistor 300 includes a first active portion 310. The switching transistor 400 includes a second active portion 410. A gate driving transistor 500 is disposed on the substrate 100 and located in the border area 12. The gate driving transistor 500 includes a third active portion 510. The first active portion 310, the second active portion 410, and the third active portion 510 are all made of the same material. The carrier concentrations of the second active portion 410 and the third active portion 510 are both greater than the carrier concentration of the first active portion 310. Specifically, the driving transistor 300, the switching transistor 400, and the gate driving transistor 500 are disposed on the same layer, allowing for rapid fabrication of the array substrate 10. The driving transistor 300 is located on the side of the switching transistor 400 away from the gate driving transistor 500. The first active portion 310, the second active portion 410, and the third active portion 510 are disposed on the substrate 100 at intervals on the same layer. The array substrate 10 also includes an interlayer dielectric layer 600 and a buffer layer 200. The array substrate 10 also includes a light-shielding portion 320. The driving transistor 300 also includes a first gate insulating portion 330, a first gate 340, a first source 350, and a first drain 360. The switching transistor 400 also includes a second gate insulating portion 420, a second gate 430, a second source 440, and a second drain 450. The gate driving transistor 500 also includes a third gate insulating portion 520, a third gate 530, a third source 540, and a third drain 550.

[0041] Next, a light-shielding portion 320 is disposed on the substrate 100. A buffer layer 200 covers the substrate 100 and the light-shielding portion 320. A first active portion 310, a second active portion 410, and a third active portion 510 are disposed on the buffer layer 200 at intervals on the same layer. The second active portion 410 is disposed between the first active portion 310 and the third active portion 510. The first active portion 310 is located above the light-shielding portion 320, and the orthographic projection of the light-shielding portion 320 onto the substrate 100 covers the orthographic projection of the first active portion 310 onto the substrate 100. The first active portion 310, the second active portion 410, and the third active portion 510 each include a channel region and non-channel regions disposed on both sides of the channel region. A first gate insulating portion 330, a second gate insulating portion 420, and a third gate insulating portion 520 are disposed at intervals on the same layer.

[0042] A first gate insulating portion 330 is located on a first active portion 310. A second gate insulating portion 420 is located on a second active portion 410. A third gate insulating portion 520 is located on a third active portion 510. A first gate 340, a second gate 430, and a third gate 530 are disposed on the same layer and spaced apart. A first gate 340 is located on a first gate insulating portion 330. A second gate 430 is located on a second gate insulating portion 420. A third gate 530 is located on a third gate insulating portion 520. An interlayer dielectric layer 600 covers the first active portion 310, the second active portion 410, the third active portion 510, the first gate insulating portion 330, the second gate insulating portion 420, the third gate insulating portion 520, the first gate 340, the second gate 430, and the third gate 530. The interlayer dielectric layer 600 has a first through-hole 601, a second through-hole 602, a third through-hole 603, a fourth through-hole 604, a fifth through-hole 605, a sixth through-hole 606, and a seventh through-hole 607. The first through-hole 601 and the second through-hole 602 penetrate the interlayer dielectric layer 600 to expose the first active portion 310. The third through-hole 603 penetrates the interlayer dielectric layer 600 and the buffer layer 200 to expose the light-shielding portion 320. The fourth through-hole 604 and the fifth through-hole 605 penetrate the interlayer dielectric layer 600 to expose the second active portion 410. The sixth through-hole 606 and the seventh through-hole 607 penetrate the interlayer dielectric layer 600 to expose the third active portion 510. The first source electrode 350, the first drain electrode 360, the second source electrode 440, the second drain electrode 450, the third source electrode 540, and the third drain electrode 550 are disposed on the interlayer dielectric layer 600 in the same layer and spaced apart. The first drain electrode 360 ​​extends into the first through hole 601 and connects to one end of the first active part 310. The first source electrode 350 extends into the second through hole 602 and connects to the other end of the first active part 310, and the first source electrode 350 extends into the third through hole 603 and connects to the light-shielding part 320. The second drain electrode 450 extends into the fourth through hole 604 and connects to one end of the second active part 410. The second source electrode 440 extends into the fifth through hole 605 and connects to the other end of the second active part 410. The third drain electrode 550 extends into the sixth through hole 606 and connects to one end of the third active part 510. The third source electrode 540 extends into the seventh through hole 607 and connects to the other end of the third active part 510.

[0043] Please see Figure 2 In this application, under the same temperature, the carrier concentration is proportional to the mobility. Therefore, the carrier concentration of the second active part 410 and the carrier concentration of the third active part 510 are both set to be greater than the carrier concentration of the first active part 310. This can improve the mobility of the switching transistor 400 and the gate driving transistor 500 while improving the stability of the driving transistor 300, thereby ensuring the transistor performance requirements of different regions in the array substrate 10.

[0044] Please continue reading. Figure 1In one embodiment, the materials of the first active portion 310, the second active portion 410, and the third active portion 510 are the same. The thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 are both greater than the thickness T1 of the first active portion 310.

[0045] In this application, it has been experimentally proven that the carrier concentration of the film layer is directly proportional to the thickness of the film layer and the carrier concentration of the film layer material. Therefore, under the premise that other conditions remain unchanged, that is, with the same film layer material, by setting the thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 to be greater than the thickness T1 of the first active portion 310, the carrier concentration of the second active portion 410 and the third active portion 510 are both greater than the carrier concentration of the first active portion 310. This allows for an increase in the mobility of the switching transistor 400 and the gate drive transistor 500, while also improving the stability of the drive transistor 300, thereby ensuring the transistor performance requirements of different regions in the array substrate 10.

[0046] Furthermore, in this application, the thickness of the second active portion 410 is the same as the thickness of the third active portion 510. Therefore, when fabricating the array substrate 100, the second active portion 410 and the third active portion 510 can be patterned using the same mask, simplifying the process.

[0047] In one embodiment, the carrier concentration of the material in the second active portion 410 and the third active portion 510 is greater than the carrier concentration of the material in the first active portion 310. The thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 are both greater than the thickness T1 of the first active portion 310.

[0048] In this embodiment, by setting the thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 to be greater than the thickness T1 of the first active portion 310, the carrier concentration of the material of the second active portion 410 and the material of the third active portion 510 are both set to be greater than the carrier concentration of the material of the first active portion 310. That is, the carrier concentration of the film layer is changed by using both the material and the thickness of the film layer. This ensures that the transistor performance requirements of different regions in the array substrate 10 are met, while avoiding the increase in the thickness of the film layer to improve the mobility of the film layer, which would lead to an increase in the thickness of the array substrate 10 and be detrimental to achieving a thinner design.

[0049] Please see Figure 3In one embodiment, the width W2 of the second active portion 410 and the width of the third active portion 510 are both smaller than the width of the first active portion 310. That is, while the thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 are both greater than the thickness T1 of the first active portion 310, the width W2 of the second active portion 410 and the width of the third active portion 510 are set to be smaller than the width of the first active portion 310. The structures of the driving transistor 300 and the gate driving transistor 500 can be found in [reference needed]. Figure 3 The structure of the switching transistor 400 shown is illustrated.

[0050] The formula for current is I DS Where is the transistor's operating current, W is the width of the active region, and L is the length of the active region. μ is the transistor's mobility, and C... i V is the gate capacitance per unit area. GS V is the source-to-gate voltage. DS V is the drain-to-gate voltage. th This is the threshold voltage of the transistor.

[0051] According to the current formula, when the current remains constant, because the thickness T2 of the second active part 410 and the thickness T3 of the third active part 510 are both greater than the thickness T1 of the first active part 310, the mobility of the second active part 410 and the mobility of the third active part 510 are both greater than the mobility of the first active part 310. Without changing C... i V GS V DS and V th In this case, as the mobility of the active portion increases, even if the aspect ratio of the active portion is reduced, the operating current of the transistor will not be affected. Therefore, in this application, the width W2 of the second active portion 410 and the width of the third active portion 510 are both set to be smaller than the width of the first active portion 310. While ensuring the transistor performance requirements of different regions in the array substrate 10, the size of the gate drive transistor 500 and the switching transistor 400 can be reduced. The gate drive transistor 500 is located in the border area 12, which reduces the area occupied by the gate drive transistor 500 in the border area 12, thereby achieving a narrow border design. The switching transistor 400 is located in the display area 11. The reduction in the size of the switching transistor 400 reduces the area occupied by the switching transistor 400 in the display area 11, thereby reducing the size of the sub-pixels. This allows the display area 11 to hold more switching transistors 400 than the prior art, thereby increasing the number of sub-pixels and improving the resolution of the array substrate 10.

[0052] It should be noted that, Figure 3Only a plan view of the switching transistor 400 is shown; plan views of the driving transistor 300 and the gate driving transistor 500 are not shown. This does not mean that they are not shown; the switching transistor 400 is merely used as an example for illustration. It should be noted that the planar structure of the switching transistor 400 is the same as that of the driving transistor 300 and the gate driving transistor 500. The difference between the planar structure of the switching transistor 400 and the planar structures of the driving transistor 300 and the gate driving transistor 500 lies in the fact that the width of the first active portion 310 is different from the width W2 of the second active portion 410 and the width of the third active portion 510.

[0053] Please continue reading. Figure 1 In this application, the materials of the first active part 310, the second active part 410 and the third active part 510 all include metal oxide semiconductor, low temperature polycrystalline silicon or other semiconductor materials.

[0054] In one embodiment, the materials of the first active portion 310, the second active portion 410, and the third active portion 510 all contain at least indium and zinc. Specifically, the materials of the first active portion 310, the second active portion 410, and the third active portion 510 include at least one of indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide. The carrier concentration of indium zinc tin oxide is greater than that of indium gallium zinc tin oxide. The carrier concentration of indium gallium zinc tin oxide is greater than that of indium gallium zinc oxide. The materials of the first active portion 310, the second active portion 410, and the third active portion 510 can also be other materials, which are not limited here.

[0055] In this application, because the carrier concentration of the material containing indium and zinc is relatively high, the first active part 310, the second active part 410 and the third active part 510 are all formed using materials containing indium and zinc. This allows for further improvement in the mobility of the switching transistor 400 and the gate drive transistor 500, while also improving the stability of the drive transistor 300, thereby further ensuring the transistor performance requirements of different regions in the array substrate 10.

[0056] In one embodiment, the thickness T1 of the first active portion 310 is 99-999 angstroms. The thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 are both 100-1000 angstroms. Specifically, the thickness T1 of the first active portion 310 can be 99 angstroms, 200 angstroms, 300 angstroms, 600 angstroms, or 999 angstroms, etc. The thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 can be 100 angstroms, 400 angstroms, 800 angstroms, 900 angstroms, or 1000 angstroms, etc. These are not listed exhaustively, as long as the thicknesses of the second active portion 410 and the third active portion 510 are both greater than the thickness of the first active portion 310 within the aforementioned thickness range.

[0057] In this application, the thickness T1 of the first active portion 310 is 99-999 angstroms. The thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 are both 100-1000 angstroms. This allows for further improvement in the mobility of the switching transistor 400 and the gate drive transistor 500, while also further improving the stability of the drive transistor 300, thereby further ensuring the transistor performance requirements of different regions in the array substrate 10.

[0058] In one embodiment, the thickness T1 of the first active portion 310 is 150-349 angstroms. The thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 are 350-1000 angstroms. Specifically, the thickness T1 of the first active portion 310 can be 150 angstroms, 200 angstroms, 300 angstroms, 340 angstroms, or 349 angstroms, etc. The thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 can be 350 angstroms, 400 angstroms, 800 angstroms, 900 angstroms, or 1000 angstroms, etc.

[0059] In one embodiment, the light-shielding portion 320 is made of metal. The metal includes at least one of copper, molybdenum, and titanium. In this application, the light-shielding portion 320 is formed of metal, which allows it to prevent external light from entering the first active portion 310 while also serving as a trace, thereby increasing the wiring design space.

[0060] In one embodiment, the thickness h1 of the light-shielding portion 320 is 500-20000 angstroms. Specifically, the thickness h1 of the light-shielding portion 320 can be 500 angstroms, 1000 angstroms, 5000 angstroms, 10000 angstroms, 15000 angstroms, or 20000 angstroms, etc. In this application, the thickness h1 of the light-shielding portion 320 is set to 500-20000 angstroms, making it difficult for light to penetrate the light-shielding portion 320, reducing the influence of external light on the first active portion 310, thereby ensuring the stability of the driving transistor 300.

[0061] In one embodiment, the material of the buffer layer 200 includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. The thickness h2 of the buffer layer 200 is 300-10000 angstroms. Specifically, the thickness h2 of the buffer layer 200 can be 300 angstroms, 2000 angstroms, 5000 angstroms, 8000 angstroms, or 10000 angstroms, etc.

[0062] In one embodiment, the materials of the first gate insulating portion 330, the second gate insulating portion 420, and the third gate insulating portion 520 all include at least one of silicon nitride and silicon oxide. The first gate insulating portion 330 may be composed of one or more film layers. The second gate insulating portion 420 and the third gate insulating portion 520 are also composed of one or more film layers, which will not be described in detail here.

[0063] In one embodiment, the thicknesses of the first gate insulating portion 330, the second gate insulating portion 420, and the third gate insulating portion 520 are all 1000-3000 angstroms. Specifically, the thicknesses of the first gate insulating portion 330, the second gate insulating portion 420, and the third gate insulating portion 520 can all be 1000 angstroms, 1500 angstroms, 2000 angstroms, or 3000 angstroms, etc. Setting the thicknesses of the first gate insulating portion 330, the second gate insulating portion 420, and the third gate insulating portion 520 to 1000-3000 angstroms can prevent the diffusion of electrons from the first gate 340, the second gate 430, and the third gate 530 to the first active portion 310, the second active portion 410, and the third active portion 510, thereby ensuring the performance of the driving transistor 300, the gate driving transistor 500, and the switching transistor 400.

[0064] In one embodiment, the material of the interlayer dielectric layer 600 includes at least one of silicon nitride and silicon oxide. The thickness of the interlayer dielectric layer 600 is 2000-10000 angstroms. The thickness of the interlayer dielectric layer 600 can be 2000 angstroms, 5000 angstroms, 8000 angstroms, 9000 angstroms, or 10000 angstroms, etc.

[0065] In one embodiment, the materials of the first source 350, first drain 360, second source 440, second drain 450, third source 540, and third drain 550 all include at least one of molybdenum, copper, aluminum, and titanium, and may also be alloys. The thickness of the first source 350, first drain 360, second source 440, second drain 450, third source 540, and third drain 550 is 2000-10000 angstroms. The thickness of the first source 350, first drain 360, second source 440, second drain 450, third source 540, and third drain 550 may be 2000 angstroms, 5000 angstroms, 8000 angstroms, 9000 angstroms, or 10000 angstroms, etc.

[0066] In one embodiment, the passivation layer 700 is made of at least one of silicon nitride and silicon oxide. The thickness of the passivation layer 700 is 1000-5000 angstroms. Specifically, the thickness of the passivation layer 700 can be 1000 angstroms, 2000 angstroms, 4000 angstroms, or 5000 angstroms.

[0067] In another embodiment, the driving transistor 300 is located on the side of the switching transistor 400 near the gate driving transistor 500.

[0068] In another embodiment, the driving transistor 300 is located on a different layer from the switching transistor 400 and the gate driving transistor 500.

[0069] In another embodiment, the driving transistor 300, the switching transistor 400, and the gate driving transistor 500 may also be bottom-gate transistors, which is not limited here.

[0070] Please see Figures 4-6 As an example, the thickness T2 of the second active part 410 and the thickness T3 of the third active part 510 are both set to be the same. Figures 4-6 The thickness T in the figure refers to the thickness T2 of the second active part 410 and the thickness T3 of the third active part 510. It should be noted that... Figures 4-6 middle, I D That is, I in the current formula DS V G That is, V in the current formula GS V D That is, V in the current formula DS . Figure 4 In the figure, the aspect ratio W / L = 6.5um / 6.5um and the thickness T is set to 300 angstroms. The switching transistor 400 and the gate drive transistor 500 are tested. The corresponding data are substituted into the current formula, and the mobility is obtained as 12 ± 1.58 cm / Vs. Figure 5 In the figure, the aspect ratio W / L = 6.5um / 6.5um and the thickness T is set to 350 angstroms. The switching transistor 400 and the gate drive transistor 500 are tested. The corresponding data are substituted into the current formula, and the mobility is 15.3±1.1cm / Vs. Figure 6 In the figure, the aspect ratio W / L = 6.5um / 6.5um and the thickness T is set to 400 angstroms. The switching transistor 400 and the gate drive transistor 500 are tested. The corresponding data are substituted into the current formula, and the mobility obtained is 19±1.3cm / Vs.

[0071] In summary, by setting the thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 to be greater than the thickness T1 of the first active portion 310, that is, increasing the thickness T2 of the second active portion 410 and the thickness T3 of the third active portion 510 while keeping the thickness T1 of the first active portion 310 unchanged, the mobility of the switching transistor 400 and the gate drive transistor 500 can be improved, thereby ensuring the transistor performance requirements of different regions in the array substrate 10.

[0072] This application also provides a display device, which includes the array substrate provided in this application. The display device can be a direct-view display device, such as an organic light-emitting diode display panel. Optionally, the display device can also be a backlight display device, such as a liquid crystal display device. There are no limitations herein.

[0073] This application also provides a method for fabricating an array substrate, the array substrate including a display area and a border area surrounding the display area, the fabrication method including:

[0074] B11. Provide a substrate.

[0075] B12. A first semiconductor material is disposed on a substrate and patterned to form a first active portion, the first active portion being located in the display area; a second semiconductor material is disposed on a substrate and patterned to form a second active portion and a third active portion spaced apart, the second active portion being located in the display area and the third active portion being located in the border area.

[0076] or,

[0077] A second semiconductor material is disposed on a substrate and patterned to form a second active portion and a third active portion spaced apart. The second active portion is located in the display area and the third active portion is located in the border area. A first semiconductor material is disposed on a substrate and patterned to form a first active portion. The first active portion is located in the display area.

[0078] The first semiconductor material is the same as the second semiconductor material, and the carrier concentrations of the second active part and the third active part are both greater than the carrier concentration of the first active part.

[0079] In this application, the first active part, the second active part, and the third active part are fabricated using two processes, resulting in different carrier mobilities in the first active part, the second active part, and the third active part. This allows the active parts formed using the same material to meet the performance requirements of different transistors.

[0080] Please continue reading. Figure 1 This application also provides a method for fabricating an array substrate 10. The specific details are as follows.

[0081] B11. Provide a substrate.

[0082] Please see Figure 7 Specifically, a substrate 100 is provided, and the substrate 100 is cleaned.

[0083] Then, a layer of material for the light-shielding portion 320 is deposited and patterned to form the light-shielding portion 320.

[0084] Then, a buffer layer 200 is formed by depositing a material of buffer layer 200 on the substrate 100 and the light-shielding portion 320.

[0085] B12. A first semiconductor material is disposed on a substrate and patterned to form a first active portion, the first active portion being located in the display area; a second semiconductor material is disposed on a substrate and patterned to form a second active portion and a third active portion spaced apart, the second active portion being located in the display area and the third active portion being located in the border area.

[0086] or,

[0087] A second semiconductor material is disposed on a substrate and patterned to form a second active portion and a third active portion spaced apart. The second active portion is located in the display area and the third active portion is located in the border area. A first semiconductor material is disposed on a substrate and patterned to form a first active portion. The first active portion is located in the display area.

[0088] The first semiconductor material is the same as the second semiconductor material, and the carrier concentrations of the second active part and the third active part are both greater than the carrier concentration of the first active part.

[0089] Specifically, IZTO semiconductor material is deposited on buffer layer 200, and patterned to form a second metal oxide portion and a third metal oxide portion spaced apart. The second metal oxide portion is located in display area 11. The third metal oxide portion is located in border area 12. Other semiconductor materials may also be used, and are not limited here.

[0090] Then, gold oxide material IZTO is deposited on the buffer layer 200 and patterned to form spaced first metal oxide portions. The first metal oxide portions are located directly above the light-shielding portion 320. The thickness T2 of the second metal oxide portion and the thickness T3 of the third metal oxide portion are both greater than the thickness T1 of the first metal oxide portion. The first semiconductor material can also be other materials, and is not limited here.

[0091] Then, an insulating layer is deposited on the buffer layer 200, the first metal oxide portion, the second metal oxide portion, and the third metal oxide portion; then, a metal layer is formed on the insulating layer.

[0092] Using a beam of yellow light, a first gate 340, a second gate 430, and a third gate 530 are first etched to form spaced-apart gates. Then, using the first gate 340, the second gate 430, and the third gate 530 as self-alignment, a first gate insulating portion 330, a second gate insulating portion 420, and a third gate insulating portion 520 are etched to form spaced-apart gates. The first gate 340 corresponds to the first gate insulating portion 330. The second gate 430 corresponds to the second gate insulating portion 420. The third gate 530 corresponds to the third insulating portion. Then, a full-surface plasma treatment is performed, and the area of ​​the active portion covered by the gates becomes conductive, reducing resistance. The area of ​​the active portion not covered by the gates is not conductive. That is, the first metal oxide portion forms the first active portion 310, the second metal oxide portion forms the second active portion 410, and the third metal oxide portion forms the third active portion 510. The first active portion 310. Both the second active region 410 and the third active region 510 include a channel region and non-channel regions disposed on both sides of the channel region. The non-channel regions are N+ doped.

[0093] Then, an interlayer dielectric layer 600 is formed on the first gate 340, the second gate 430, and the third gate 530. The interlayer dielectric layer 600 has a first via 601, a second via 602, a third via 603, a fourth via 604, a fifth via 605, a sixth via 606, and a seventh via 607. The first via 601 and the second via 602 penetrate the interlayer dielectric layer 600 to expose the first active portion 310. The third via 603 penetrates the interlayer dielectric layer 600 and the buffer layer 200 to expose the light-shielding portion 320. The fourth via 604 and the fifth via 605 penetrate the interlayer dielectric layer 600 to expose the second active portion 410. The sixth via 606 and the seventh via 607 penetrate the third active portion 510 of the interlayer dielectric layer 600.

[0094] Then, a first source 350, a first drain 360, a second source 440, a second drain 450, a third source 540, and a third drain 550 are formed on the interlayer dielectric layer 600 at intervals.

[0095] Then, a passivation layer 700 is applied over the first source 350, the first drain 360, the second source 440, the second drain 450, the third source 540, and the third drain 550.

[0096] In another embodiment, the first active part 310 may be formed first, and then the second active part 410 and the third active part 510 may be formed.

[0097] This application provides an array substrate 10 and a method for fabricating the same. The array substrate 10 includes a display area 11 and a border area 12 surrounding the display area 11. The array substrate 10 includes a substrate 100, a driving transistor 300, a switching transistor 400, and a gate driving transistor 500. The driving transistor 300 and the switching transistor 400 are spaced apart on the substrate 100. The driving transistor 300 and the switching transistor 400 are located in the display area 11. The driving transistor 300 includes a first active portion 310. The switching transistor 400 includes a second active portion 410. The gate driving transistor 500 is located in the border area 12. The gate driving transistor 500 includes a third active portion 510. The materials of the first active portion 310, the second active portion 410, and the third active portion 510 include metal-oxide-semiconductor. The carrier concentrations of the second active portion 410 and the third active portion 510 are both greater than the carrier concentration of the first active portion 310. At the same temperature, carrier concentration is proportional to mobility. Therefore, by setting the carrier concentration of the second active part 410 and the carrier concentration of the third active part 510 to be greater than that of the first active part 310, the mobility of the switching transistor 400 and the gate drive transistor 500 can be improved, while the stability of the drive transistor 300 can be improved, thereby ensuring the transistor performance requirements of different regions in the array substrate 10.

[0098] The above provides a detailed description of an array substrate, its fabrication method, and a display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, characterized by, The array substrate includes a display area and a border area surrounding the display area, and the array substrate includes: substrate; A driving transistor and a switching transistor are disposed on the substrate, the driving transistor and the switching transistor being located in the display area, the driving transistor including a first active portion, and the switching transistor including a second active portion; and A gate driving transistor is disposed on the substrate, the gate driving transistor is located in the border region, and the gate driving transistor includes a third active portion; The first active part, the second active part, and the third active part are all made of the same material, and the carrier concentration of the second active part and the carrier concentration of the third active part are both greater than the carrier concentration of the first active part. The thickness of the second active portion and the thickness of the third active portion are both greater than the thickness of the first active portion, and the materials of the first active portion, the second active portion and the third active portion all include metal oxide semiconductor.

2. The array substrate according to claim 1, characterized in that, The thickness of the second active part is the same as the thickness of the third active part.

3. The array substrate according to claim 1 or 2, characterized in that, The widths of the second active portion and the third active portion are both smaller than the width of the first active portion.

4. The array substrate according to claim 3, characterized in that, The driving transistor, the switching transistor, and the gate driving transistor are disposed on the same layer. The driving transistor is located on the side of the switching transistor away from the gate driving transistor. The first active portion, the second active portion, and the third active portion are disposed on the same layer and spaced apart on the substrate.

5. The array substrate according to claim 4, characterized in that, The thickness of the first active part is 99-999 angstroms, and the thickness of the second active part and the thickness of the third active part are both 100-1000 angstroms.

6. The array substrate according to claim 5, characterized in that, The thickness of the first active part is 150-349 angstroms, and the thickness of the second active part and the thickness of the third active part are 350-1000 angstroms.

7. The array substrate according to claim 6, characterized in that, The materials of the first active part, the second active part, and the third active part all contain at least indium and zinc.

8. A display device, characterized in that, The display device includes an array substrate as described in any one of claims 1-5.

9. A method for fabricating an array substrate, characterized in that, The array substrate includes a display area and a border area surrounding the display area, and the fabrication method includes: Provide a substrate; and A first semiconductor material is disposed on the substrate and patterned to form a first active portion, the first active portion being located in the display area; a second semiconductor material is disposed on the substrate and patterned to form a second active portion and a third active portion spaced apart, the second active portion being located in the display area and the third active portion being located in the border area; or, A second semiconductor material is disposed on the substrate and patterned to form a second active portion and a third active portion spaced apart. The second active portion is located in the display area, and the third active portion is located in the border area. A first semiconductor material is disposed on the substrate and patterned to form a first active portion, which is located in the display area. Wherein, the first semiconductor material and the second semiconductor material are the same, and the carrier concentration of the second active part and the carrier concentration of the third active part are both greater than the carrier concentration of the first active part; The thickness of the second active portion and the thickness of the third active portion are both greater than the thickness of the first active portion, and the materials of the first active portion, the second active portion and the third active portion all include metal oxide semiconductor.

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