Magnetic random access memory cell array and method of manufacturing the same

Abstract

The application provides a magnetic random memory unit array, comprising: a substrate, the substrate comprising a storage array area, a peripheral circuit area and a logic area, each area being formed with a bottom metal line, and the peripheral circuit area being between the storage array area and the logic area; a first dielectric layer on the upper surface of the substrate; a bottom electrode via array in the first dielectric layer of the storage array area and aligned with the bottom metal line of the storage array area, the bottom electrode via array being filled with a conductive metal; a first bottom electrode array on the bottom electrode via array; a second bottom electrode array on the first dielectric layer of the peripheral circuit area; a second dielectric layer surrounding the first bottom electrode array and the second bottom electrode array; a magnetic tunnel junction unit array on the first bottom electrode array; and a pseudo magnetic tunnel junction unit array on the second bottom electrode array. The application can solve the problem of copper diffusion caused by uneven bottom electrode grinding.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of magnetic random access memory technology, and in particular to a magnetic random access memory cell array and a manufacturing method thereof. BACKGROUND

[0002] MRAM (Magnetoresistive Random Access Memory) is considered to be the future solid-state non-volatile memory, which has the characteristics of high speed reading and writing, large capacity and low energy consumption.

[0003] The core component of MRAM is a magnetic tunnel junction (MTJ), which uses the low resistance state and the high resistance state of the MTJ to realize the storage of "0" and "1". The storage array area of the MRAM is generally arranged in an array by a plurality of repeated MTJs. The MTJ is connected to the bottom metal wire through a via hole under the bottom electrode. There is a peripheral circuit area around the storage array area, and a Dummy (dummy pattern) is arranged in the peripheral circuit area. The structure of the Dummy is generally the same as that of the array area. The Dummy is not used as a storage cell, and is mainly used to ensure that the MTJ structure in the array area is not affected by the edge effect and the performance of the MTJ structure is not affected.

[0004] In the MRAM manufacturing process, the bottom electrode of the MTJ generally uses a metal material, which requires high planarization. In the process, chemical mechanical polishing is used to make the bottom electrode as flat as possible to facilitate the growth of the MTJ structure on the bottom electrode. However, referring to Figure 1 Because the polishing rate is large at the edge of the array area, the bottom electrode of the peripheral circuit area is polished through, which causes the copper in the via hole to diffuse out. If the copper diffuses to the array area, it will cause short circuit between the MTJs in the array area. SUMMARY

[0005] To solve the above problems, the present application provides a magnetic random access memory cell array and a manufacturing method thereof, which can solve the problem of copper diffusion caused by uneven polishing of the bottom electrode and further cause short circuit between the MTJs.

[0006] In a first aspect, the present application provides a magnetic random access memory cell array, comprising:

[0007] a substrate, the substrate comprising a storage array area, a peripheral circuit area and a logic area, each area being formed with a bottom metal wire, the peripheral circuit area being between the storage array area and the logic area;

[0008] a first dielectric layer on the upper surface of the substrate;

[0009] a bottom electrode via array in the first dielectric layer of the memory array region and aligned with the bottom metal lines of the memory array region, the bottom electrode via array filled with conductive metal;

[0010] a first bottom electrode array on the bottom electrode via array;

[0011] a second bottom electrode array on the first dielectric layer of the peripheral circuit region;

[0012] a second dielectric layer surrounding the first bottom electrode array and the second bottom electrode array;

[0013] a magnetic tunnel junction cell array on the first bottom electrode array; and

[0014] a dummy magnetic tunnel junction cell array on the second bottom electrode array.

[0015] Optionally, the width of the peripheral circuit region is greater than a set threshold value, the set threshold value being a minimum number of bottom electrode rows needed to be added to ensure that the bottom electrode vias of the memory array region are not affected by metal precipitation caused by uneven chemical mechanical polishing.

[0016] Optionally, the first bottom electrode array is aligned with the bottom metal lines of the memory array region, and the second bottom electrode array is aligned with the bottom metal lines of the peripheral circuit region.

[0017] In a second aspect, the present application provides a magnetic random access memory cell array, comprising:

[0018] a substrate comprising a memory array region, a peripheral circuit region and a logic region, each region formed with bottom metal lines, the peripheral circuit region being between the memory array region and the logic region;

[0019] a first dielectric layer on the top surface of the substrate;

[0020] a bottom electrode via array in the first dielectric layer of the memory array region and aligned with the bottom metal lines of the memory array region, the bottom electrode via array filled with conductive metal;

[0021] a first bottom electrode array on the bottom electrode via array;

[0022] a second bottom electrode array on the first dielectric layer of the peripheral circuit region;

[0023] a third bottom electrode array on the first dielectric layer of the extension region, the extension region being a part of the logic region adjacent to the peripheral circuit region;

[0024] a second dielectric layer surrounding the first bottom electrode array, the second bottom electrode array and the third bottom electrode array;

[0025] a magnetic tunnel junction cell array on the first bottom electrode array; and

[0026] a pseudo magnetic tunnel junction cell array on the second bottom electrode array and the third bottom electrode array, or only on the second bottom electrode array.

[0027] Optionally, the width of the peripheral circuit region is less than a set threshold, the sum of the width of the peripheral circuit region and the width of the extension region is greater than the set threshold, and the set threshold is the minimum number of bottom electrode rows needed to be increased to ensure that the bottom electrode via of the memory array region is not affected by the non-uniformity of chemical mechanical polishing to cause metal precipitation.

[0028] Optionally, the first bottom electrode array is aligned with the bottom metal line of the memory array region, and the second bottom electrode array is aligned with the bottom metal line of the peripheral circuit region.

[0029] In a third aspect, the present application provides a method for manufacturing a magnetic random access memory cell array, comprising:

[0030] providing a substrate, the substrate comprising a memory array region, a peripheral circuit region and a logic region, each region being formed with a bottom metal line, the peripheral circuit region being between the memory array region and the logic region, and the width of the peripheral circuit region being greater than a set threshold, the set threshold being the minimum number of bottom electrode rows needed to be increased to ensure that the bottom electrode via of the memory array region is not affected by the non-uniformity of chemical mechanical polishing to cause metal precipitation;

[0031] depositing a first dielectric layer on the top surface of the substrate;

[0032] forming an array of bottom electrode vias in the first dielectric layer of the memory array region, the array of bottom electrode vias being aligned with the bottom metal line of the memory array region, and filling the array of bottom electrode vias with a conductive metal;

[0033] depositing a bottom electrode layer on the memory array region and the peripheral circuit region, the bottom electrode layer being in contact with the array of bottom electrode vias and the first dielectric layer of the peripheral circuit region;

[0034] patterning the bottom electrode layer to form a first bottom electrode array on the array of bottom electrode vias and a second bottom electrode array on the first dielectric layer of the peripheral circuit region;

[0035] depositing a second dielectric layer;

[0036] planarization processing to completely expose the surface of the first bottom electrode array and the second bottom electrode array and to make the surface flat;

[0037] forming a magnetic tunnel junction cell array on the first bottom electrode array and forming a dummy magnetic tunnel junction cell array on the second bottom electrode array.

[0038] In a fourth aspect, the present application provides a method for manufacturing a magnetic random access memory cell array, comprising:

[0039] providing a substrate, the substrate comprising a memory array region, a peripheral circuit region and a logic region, each region being formed with a bottom metal line, the peripheral circuit region being between the memory array region and the logic region, and the width of the peripheral circuit region being less than a set threshold value, the set threshold value being the minimum number of bottom electrode rows needed to ensure that the bottom electrode via of the memory array region will not be affected by the non-uniform chemical mechanical polishing to cause metal precipitation;

[0040] depositing a first dielectric layer on the top surface of the substrate;

[0041] forming an array of bottom electrode vias in the first dielectric layer of the memory array region in alignment with the bottom metal line of the memory array region, and filling the array of bottom electrode vias with a conductive metal;

[0042] depositing a bottom electrode layer on the memory array region, the peripheral circuit region and an extension region, the extension region being a part of the logic region adjacent to the peripheral circuit region, the sum of the width of the peripheral circuit region and the extension region being greater than the set threshold value, the bottom electrode layer being in contact with the array of bottom electrode vias, the first dielectric layer of the peripheral circuit region and the first dielectric layer of the extension region;

[0043] patterning the bottom electrode layer to form a first bottom electrode array on the array of bottom electrode vias, a second bottom electrode array on the first dielectric layer of the peripheral circuit region and a third bottom electrode array on the first dielectric layer of the extension region;

[0044] depositing a second dielectric layer;

[0045] planarization processing to expose the top surface of the first bottom electrode array, the second bottom electrode array and the third bottom electrode array completely and make the top surface flat;

[0046] forming a magnetic tunnel junction cell array on the first bottom electrode array and forming a dummy magnetic tunnel junction cell array on the second bottom electrode array and the third bottom electrode array, or forming a magnetic tunnel junction cell array on the first bottom electrode array and forming a dummy magnetic tunnel junction cell array only on the second bottom electrode array.

[0047] Optionally, the set threshold value is greater than the width of 10 rows of bottom electrodes.

[0048] Optionally, the thickness of the bottom electrode layer is greater than 10 nm.

[0049] The application provides a magnetic random access memory cell array and a manufacturing method thereof. The bottom interconnection structure of the cell array is optimized. The storage array region comprises a bottom metal line, a via, a bottom electrode and an MTJ. The peripheral circuit region comprises a bottom electrode and an MTJ, and does not comprise a bottom via. The special array structure can protect the array region. Even if the bottom electrode of the peripheral circuit region is ground through during chemical mechanical polishing of the bottom electrode layer, copper diffusion does not occur, and thus the copper diffusion problem caused by grinding through of the bottom electrode can be effectively prevented. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 A schematic diagram of copper diffusion caused by chemical mechanical polishing in the prior art;

[0051] Figure 2 A structural schematic diagram of a magnetic random access memory cell array provided by an embodiment of the application;

[0052] Figures 3A to 3F A structural schematic diagram of a magnetic random access memory cell array provided by an embodiment of the application;

[0053] Figure 4 A structural schematic diagram of a magnetic random access memory cell array provided by an embodiment of the application;

[0054] Figure 5 A structural schematic diagram of a magnetic random access memory cell array provided by an embodiment of the application;

[0055] Figures 6A to 6F A structural schematic diagram of a magnetic random access memory cell array provided by an embodiment of the application;

[0056] Figure 6G A structural schematic diagram of a device manufactured by another embodiment. DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described below in detail with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the application.

[0058] Some embodiments of the application will be described below in detail with reference to the accompanying drawings. In the case of no conflict, the embodiments described below and the features in the embodiments can be combined with each other.

[0059] Figure 2 A structural diagram of a magnetic random access memory cell array provided by an embodiment of the present invention is shown. Figure 2 As shown, the magnetic random access memory (MRM) cell array includes: a substrate 101, a first dielectric layer 102, a bottom electrode via array 103, a first bottom electrode array 1041, a second bottom electrode array 1042, a second dielectric layer 105, a magnetic tunnel junction cell array 1061, and a pseudo magnetic tunnel junction cell array 1062. Those skilled in the art will understand that... Figure 2 The markings 103, 1041, 1042, 1061, and 1062 all represent arrays, not just a single component.

[0060] The substrate 101 includes a memory array region, a peripheral circuit region, and a logic region, each with underlying metal lines, designated 1011, 1012, and 1013 respectively. The peripheral circuit region lies between the memory array region and the logic region. In this embodiment, the width of the peripheral circuit region is greater than a set threshold to prevent the bottom electrode via array of the memory array region from being affected by uneven chemical mechanical polishing (CMP). This set threshold can be understood as follows: during the fabrication of the bottom electrode array, the deposited bottom electrode layer needs to be sufficiently planarized. To ensure that the bottom electrodes of the memory array region are not worn through during planarization, the width of the peripheral circuit region cannot be too small. Therefore, a threshold can be set. If the width of the peripheral circuit region is greater than this threshold, it is considered sufficient; if the width is less than this threshold, it is considered insufficient. It is recommended to refer to the results of actual process verification when setting the threshold. In actual processing, the threshold can be defined as the minimum number of bottom electrode rows required to ensure that the bottom electrode vias of the memory array region are not affected by uneven CMP causing metal precipitation. The threshold is generally obtained through surface defect inspection and is typically greater than the width of 10 bottom electrode rows.

[0061] A first dielectric layer 102 is located on the upper surface of the substrate 101. A bottom electrode via array 103 is located in the first dielectric layer of the memory array region and aligned with the bottom metal lines 1011 of the memory array region. The bottom electrode via array is filled with conductive metal, typically copper (Cu). A first bottom electrode array 1041 is located on the bottom electrode via array 103 and can be aligned with the bottom metal lines 1011 of the memory array region. A second bottom electrode array 1042 is located on the first dielectric layer of the peripheral circuit region and can be aligned with the bottom metal lines 1012 of the peripheral circuit region. A second dielectric layer 105 surrounds the first bottom electrode array 1041 and the second bottom electrode array 1042. A magnetic tunnel junction unit array 1061 is located on the first bottom electrode array 1041. A pseudo magnetic tunnel junction unit array 1062 is located on the second bottom electrode array 1042.

[0062] The magnetic random access memory cell array provided by the embodiment of the present application has a peripheral circuit region with sufficient width to protect the storage array region, the storage array region comprises bottom metal lines+via holes+bottom electrodes+MTJ, and the peripheral circuit region comprises bottom electrodes+MTJ and does not comprise bottom via holes. The special array structure can protect the array region. When the bottom electrode layer is subjected to chemical mechanical polishing, even if the bottom electrode of the peripheral circuit region is polished through, copper diffusion will not occur, and thus the copper diffusion problem caused by the polishing through of the bottom electrode can be effectively prevented.

[0063] In addition, it should be noted that, generally, for a conventional cell array, the bottom via hole is added to the dummy structure of the peripheral circuit region. Before the bottom electrode is formed, the bottom via hole is subjected to chemical mechanical polishing. For the array (including the dummy), the polishing rate of the via hole region is greater than that of the region (dielectric layer) without the via hole, which can cause a certain height difference of the bottom surface of the deposited bottom electrode at the edge of the array. The closer to the edge, the higher the bottom surface. If the height difference is too large, the thickness and performance of the bottom electrode after polishing can be affected, and the metal in the bottom via hole can also be precipitated, affecting the MTJ.

[0064] In the process of the present application, it is actually found that the influence caused by the polishing of the bottom via hole is much smaller than that of the polishing of the bottom electrode, and the height difference and the affected array rows are relatively small. Therefore, reducing the number of bottom via holes basically will not affect the performance of the bottom electrode.

[0065] On the other hand, the embodiment of the present application provides a manufacturing method which can be implemented to manufacture the magnetic random access memory cell array provided by the above embodiment. Specifically, the manufacturing method comprises the following steps:

[0066] Reference Figure 3A A substrate 201 is provided, the substrate 201 comprises a storage array region, a peripheral circuit region and a logic region, each region is formed with a bottom metal line, and is sequentially denoted as 2011, 2012 and 2013. The peripheral circuit region is between the storage array region and the logic region, and the width of the peripheral circuit region is greater than a set threshold. A first dielectric layer 202 is deposited on the upper surface of the substrate 201.

[0067] Reference Figure 3B A bottom electrode via hole array 203 aligned with the bottom metal line 2011 of the storage array region is formed in the first dielectric layer of the storage array region, and a conductive metal is filled in the bottom electrode via hole array 203. The conductive metal is generally copper (Cu).

[0068] Reference Figure 3CA bottom electrode layer 204 is deposited in the memory array region and the peripheral circuit region, which contacts the bottom electrode via array 203 and the first dielectric layer in the peripheral circuit region. The thickness of the bottom electrode layer 204 is greater than 10 nm. The material of the bottom electrode layer 204 is one or a combination of Ta, Ti, TaN and TiN.

[0069] Referring to Figure 3D , the bottom electrode layer 204 is patterned to form a first bottom electrode array 2041 on the bottom electrode via array 203 and a second bottom electrode array 2042 on the first dielectric layer in the peripheral circuit region.

[0070] Referring to Figure 3E , a second dielectric layer 205 is deposited around the first bottom electrode array 2041 and the second bottom electrode array 2042. Then planarization processing is performed to completely expose the surface of the first bottom electrode array 2041 and the second bottom electrode array 2042 and to make the surface flat.

[0071] Referring to Figure 3F , a magnetic tunnel junction cell array 2061 is formed on the first bottom electrode array 2041 and a dummy magnetic tunnel junction cell array 2062 is formed on the second bottom electrode array 2042. This step can be achieved by conventional deposition and etching processes.

[0072] The manufacturing method provided by the above embodiment is suitable for the case where the width of the peripheral circuit region is greater than a certain threshold value. The magnetic random access memory cell array formed thereby can protect the array region. When chemical mechanical polishing is performed on the bottom electrode layer, even if the bottom electrode in the peripheral circuit region is polished through, there will be no problem of copper diffusion, so the problem of copper diffusion caused by polishing through of the bottom electrode can be effectively prevented.

[0073] Figure 4 A structure diagram of a magnetic random access memory cell array provided by an embodiment of the present application is shown. As shown in Figure 4 , the magnetic random access memory cell array comprises a substrate 301, a first dielectric layer 302, a bottom electrode via array 303, a first bottom electrode array 3041, a second bottom electrode array 3042, a third bottom electrode array 3043, a second dielectric layer 305, a magnetic tunnel junction cell array 3061 and a dummy magnetic tunnel junction cell array 3062. Those skilled in the art can understand that, Figure 4 the marks 303, 3041, 3042, 3043, 3061 and 3062 in

[0074] The substrate 301 includes a memory array region, a peripheral circuit region, and a logic region, each of which is formed with a bottom metal line, denoted as 3011, 3012, and 3013 in sequence, and the peripheral circuit region is between the memory array region and the logic region. In this embodiment, the width of the peripheral circuit region is less than a set threshold, and thus the peripheral circuit region is not wide enough to protect the memory array region. In this case, in order to avoid copper diffusion, a part of the logic region must be occupied.

[0075] The first dielectric layer 302 is on the upper surface of the substrate 301. The bottom electrode via array 303 is in the first dielectric layer of the memory array region and is aligned with the bottom metal line 3011 of the memory array region, and the bottom electrode via array is filled with a conductive metal, generally copper (Cu). The first bottom electrode array 3041 is on the bottom electrode via array 303 and can be aligned with the bottom metal line 3011 of the memory array region. The second bottom electrode array 3042 is on the first dielectric layer of the peripheral circuit region and can be aligned with the bottom metal line 3012 of the peripheral circuit region. The third bottom electrode array 3043 is on the first dielectric layer of the extension region, which is a part of the logic region adjacent to the peripheral circuit region. The sum of the widths of the peripheral circuit region and the extension region is greater than the set threshold, so that the bottom electrode via array of the memory array region is not affected by the unevenness of chemical mechanical polishing.

[0076] The second dielectric layer 305 surrounds the first bottom electrode array 3041, the second bottom electrode array 3042, and the third bottom electrode array 3043. The magnetic tunnel junction cell array 3061 is on the first bottom electrode array 3041. The pseudo magnetic tunnel junction cell array 3062 is on the second bottom electrode array 3042 and the third bottom electrode array 3043.

[0077] The magnetic random access memory cell array provided by the embodiment of the present application has a relatively small peripheral circuit region, which is difficult to protect the memory array region, and thus the logic region is extended to obtain an extension region without affecting the logic circuit of the logic region itself. The memory array region includes a bottom metal line + a via + a bottom electrode + an MTJ, and the peripheral circuit region and the extension region include a bottom electrode + an MTJ, but do not include a bottom via. Such a special array structure can protect the array region, and even if the bottom electrode of the peripheral circuit region and the extension region is ground through during chemical mechanical polishing of the bottom electrode layer, copper diffusion will not occur, and thus the problem of copper diffusion caused by grinding of the bottom electrode can be effectively prevented.

[0078] Further, Figure 5 Another structure diagram of a magnetic random access memory cell array is shown. In fact, this structure is an optimization of Figure 4 the structure shown in FIG. 4, and the pseudo magnetic tunnel junction cell on the third bottom electrode array 3043 in the extension region is omitted, which can reduce the resistance-capacitance effect that may be caused and prevent delay interference on the circuit of the logic region.

[0079] In another aspect, the embodiments of the present application provide a manufacturable method for fabricating the magnetic random access memory cell array provided by the embodiments of the present application. Specifically, the method comprises:

[0080] Referring to Figure 6A , a substrate 401 is provided, which includes a memory array region, a peripheral circuit region and a logic region, each of which is formed with a bottom metal line, denoted as 4011, 4012 and 4013 in sequence, the peripheral circuit region is between the memory array region and the logic region, and the width of the peripheral circuit region is less than a set threshold, and a first dielectric layer 402 is deposited on the top surface of the substrate 401.

[0081] Referring to Figure 6B , a bottom electrode via array 403 is formed in the first dielectric layer of the memory array region and aligned with the bottom metal line 4011 of the memory array region, and a conductive metal is filled in the bottom electrode via array 403, which is generally copper (Cu).

[0082] Referring to Figure 6C , a bottom electrode layer 404 is deposited in the memory array region, the peripheral circuit region and an extension region, wherein the extension region is a part of the logic region adjacent to the peripheral circuit region, and the sum of the widths of the peripheral circuit region and the extension region is greater than the set threshold, the bottom electrode layer 404 is in contact with the first dielectric layer of the peripheral circuit region and the first dielectric layer of the extension region as well as the bottom electrode via array 403. The thickness of the bottom electrode layer 404 is greater than 10 nm. The material of the bottom electrode layer 404 is one or a combination of several of Ta, Ti, TaN and TiN.

[0083] Referring to Figure 6D , the bottom electrode layer 404 is patterned to form a first bottom electrode array 4041 on the bottom electrode via array 403, a second bottom electrode array 4042 on the first dielectric layer of the peripheral circuit region and a third bottom electrode array 4043 on the first dielectric layer of the extension region.

[0084] Referring to Figure 6E , a second dielectric layer 405 is deposited around the first bottom electrode array 4041, the second bottom electrode array 4042 and the third bottom electrode array 4043. Then, a planarization process is performed to completely expose the surfaces of the first bottom electrode array 4041, the second bottom electrode array 4042 and the third bottom electrode array 4043 and make the surfaces flat.

[0085] Referring to Figure 6F , a magnetic tunnel junction cell array 4061 is formed on the first bottom electrode array 4041 and a dummy magnetic tunnel junction cell array 4062 is formed on the second bottom electrode array 4042 and the third bottom electrode array 4043. This step can be achieved by conventional deposition and etching processes.

[0086] As another embodiment, as shown in FIG. 4B, the magnetic tunnel junction cell array 4061 can be formed on the first bottom electrode array 4041 and the dummy magnetic tunnel junction cell array 4062 can be formed only on the second bottom electrode array 4042. Figure 6G

[0087] The manufacturing method provided by the above embodiment is suitable for the case where the width of the peripheral circuit region is less than a set threshold value, and the formed magnetic random memory cell array can protect the array region. When the bottom electrode layer is chemically mechanically polished, even if the bottom electrodes of the peripheral circuit region and the extension region are polished through, there will be no copper diffusion problem, so the copper diffusion problem caused by the polishing through of the bottom electrode can be effectively prevented.

[0088] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.​

Claims

1. A magnetic random access memory cell array, characterized in that, include: The substrate includes a memory array region, a peripheral circuit region, and a logic region. Each region has a bottom metal line formed thereon. The peripheral circuit region is located between the memory array region and the logic region. The width of the peripheral circuit region is greater than a set threshold. The set threshold is the minimum number of bottom electrode rows required to ensure that the bottom electrode vias of the memory array region are not affected by uneven chemical mechanical polishing and cause metal precipitation. A first dielectric layer is located on the upper surface of the substrate; A bottom electrode via array is located in the first dielectric layer of the memory array region and aligned with the bottom metal line of the memory array region. The bottom electrode via array is filled with conductive metal. The first bottom electrode array is located on the bottom electrode through-hole array; The second bottom electrode array is located on the first dielectric layer of the peripheral circuit region; A second dielectric layer surrounds the first bottom electrode array and the second bottom electrode array; A magnetic tunnel junction unit array is located on the first bottom electrode array; as well as, A pseudo-magnetic tunnel junction unit array is located on the second bottom electrode array.

2. The magnetic random access memory cell array according to claim 1, characterized in that, The first bottom electrode array is aligned with the bottom metal lines of the memory array region, and the second bottom electrode array is aligned with the bottom metal lines of the peripheral circuit region.

3. A magnetic random access memory cell array, characterized in that, include: The substrate includes a memory array region, a peripheral circuit region, and a logic region, each region having a bottom metal line formed thereon, and the peripheral circuit region being located between the memory array region and the logic region; A first dielectric layer is located on the upper surface of the substrate; A bottom electrode via array is located in the first dielectric layer of the memory array region and aligned with the bottom metal line of the memory array region. The bottom electrode via array is filled with conductive metal. The first bottom electrode array is located on the bottom electrode through-hole array; The second bottom electrode array is located on the first dielectric layer of the peripheral circuit region; The third bottom electrode array is located on the first dielectric layer of the extended region, wherein the extended region is a portion of the logic region adjacent to the peripheral circuit region. A second dielectric layer surrounds the first bottom electrode array, the second bottom electrode array, and the third bottom electrode array; A magnetic tunnel junction unit array is located on the first bottom electrode array; as well as, The pseudo-magnetic tunnel junction unit array is located on the second bottom electrode array and the third bottom electrode array, or only on the second bottom electrode array.

4. The magnetic random access memory cell array according to claim 3, characterized in that, The width of the peripheral circuit area is less than a set threshold, and the sum of the widths of the peripheral circuit area and the expansion area is greater than the set threshold. The set threshold is the minimum number of bottom electrode rows required to ensure that the bottom electrode vias of the storage array area are not affected by uneven chemical mechanical polishing and thus do not cause metal precipitation.

5. The magnetic random access memory cell array according to claim 3, characterized in that, The first bottom electrode array is aligned with the bottom metal lines of the memory array region, and the second bottom electrode array is aligned with the bottom metal lines of the peripheral circuit region.

6. A method for manufacturing a magnetic random access memory (RAM) cell array, characterized in that, include: A substrate is provided, the substrate including a memory array region, a peripheral circuit region and a logic region, each region having a bottom metal line formed thereon, the peripheral circuit region being located between the memory array region and the logic region, and the width of the peripheral circuit region being greater than a set threshold, the set threshold being the minimum number of bottom electrode rows required to ensure that the bottom electrode vias of the memory array region are not affected by uneven chemical mechanical polishing and cause metal precipitation; A first dielectric layer is deposited on the upper surface of the substrate; A bottom electrode via array aligned with the bottom metal lines of the storage array region is formed in the first dielectric layer of the storage array region, and conductive metal is filled in the bottom electrode via array. A bottom electrode layer is deposited in the memory array region and the peripheral circuit region, and the bottom electrode layer is in contact with the bottom electrode via array and the first dielectric layer of the peripheral circuit region; The bottom electrode layer is patterned to form a first bottom electrode array on the bottom electrode via array and a second bottom electrode array on the first dielectric layer of the peripheral circuit region. Deposit a second dielectric layer; Planarization process is performed to fully expose and flatten the surfaces of the first and second bottom electrode arrays. A magnetic tunnel junction array is formed on the first bottom electrode array and a pseudo magnetic tunnel junction array is formed on the second bottom electrode array.

7. A method for manufacturing a magnetic random access memory cell array, characterized in that, include: A substrate is provided, the substrate including a memory array region, a peripheral circuit region and a logic region, each region having a bottom metal line formed thereon, the peripheral circuit region being located between the memory array region and the logic region, and the width of the peripheral circuit region being less than a set threshold, the set threshold being the minimum number of bottom electrode rows required to ensure that the bottom electrode vias of the memory array region are not affected by uneven chemical mechanical polishing and cause metal precipitation; A first dielectric layer is deposited on the upper surface of the substrate; A bottom electrode via array aligned with the bottom metal lines of the storage array region is formed in the first dielectric layer of the storage array region, and conductive metal is filled in the bottom electrode via array. A bottom electrode layer is deposited in the memory array region, the peripheral circuit region, and the extended region. The extended region is a portion of the logic region adjacent to the peripheral circuit region. The sum of the widths of the peripheral circuit region and the extended region is greater than a set threshold. The bottom electrode layer is in contact with the bottom electrode via array, the first dielectric layer of the peripheral circuit region, and the first dielectric layer of the extended region. The bottom electrode layer is patterned to form a first bottom electrode array on the bottom electrode via array, a second bottom electrode array on the first dielectric layer of the peripheral circuit region, and a third bottom electrode array on the first dielectric layer of the extended region. Deposit a second dielectric layer; Planarization process is performed to fully expose and flatten the surfaces of the first bottom electrode array, the second bottom electrode array, and the third bottom electrode array. A magnetic tunnel junction array is formed on the first bottom electrode array and a pseudo magnetic tunnel junction array is formed on the second bottom electrode array and the third bottom electrode array, or a magnetic tunnel junction array is formed on the first bottom electrode array and a pseudo magnetic tunnel junction array is formed only on the second bottom electrode array.

8. The method according to claim 6 or 7, characterized in that, The set threshold is greater than the width of 10 rows of bottom electrodes.

9. The method according to claim 6 or 7, characterized in that, The thickness of the bottom electrode layer is greater than 10 nm.

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