Display substrate, preparation method thereof and display device

Abstract

This disclosure provides a display substrate, its fabrication method, and a display device. The display substrate includes a pixel region and a stretched hole region, the stretched hole region including a hole region and a partition region; the display substrate includes a substrate, a structural layer, and an encapsulation structural layer, the partition region including at least one partition structure surrounding the hole region; the hole region includes a substrate hole disposed on the substrate and a structural hole penetrating the structural layer, the substrate hole and the structural hole being connected, at least a portion of the inner wall of the structural hole being covered by at least one encapsulation material layer in the encapsulation structural layer, and the inner wall of the substrate hole including a substrate material segment not covered by the encapsulation material layer. This disclosure, by forming a substrate material segment not covered by the encapsulation material layer in the substrate hole of the stretched hole, ensures that the peeling interface between the display substrate and the glass substrate consists only of the substrate material, avoiding the situation where the film layer of the display substrate cannot be separated from the glass substrate, and avoiding pull cracks during the peeling process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a preparation method thereof, and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, a flexible display device with an OLED as a light emitting device and a thin film transistor (TFT) for signal control has become a mainstream product in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of protection of the present document.

[0004] The technical problem to be solved by the present disclosure is to provide a display substrate, a preparation method thereof, and a display device to effectively ensure the packaging effect of the display substrate.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a pixel area and a stretch hole area, the pixel area comprising at least one sub-pixel, and the stretch hole area comprising at least one hole area and a partition area surrounding the hole area; the display substrate comprises a substrate, a structure layer disposed on the substrate, and a packaging structure layer disposed on a side of the structure layer away from the substrate, the partition area comprises at least one partition structure, and the partition structure surrounds the hole area; the hole area comprises a substrate hole disposed on the substrate and a structure hole penetrating through the structure layer, the substrate hole and the structure hole are in communication, at least part of the inner wall of the structure hole is covered by at least one encapsulation material layer in the packaging structure layer, and the inner wall of the substrate hole comprises a substrate material segment which is not covered by the encapsulation material layer.

[0006] In an exemplary embodiment, the inner wall of the substrate hole further comprises an encapsulation material segment covered by the encapsulation material layer, and the encapsulation material segment is located on a side of the substrate material segment close to the structure hole.

[0007] In an exemplary embodiment, the substrate hole comprises a through hole penetrating through the substrate, or comprises a blind hole which does not penetrate through the substrate.

[0008] In an exemplary embodiment, the partition structure comprises a first partition layer surrounding the hole region and a second partition layer disposed on a side of the first partition layer away from the substrate, the first partition layer is provided with a first partition hole surrounding the hole region, the second partition layer is provided with a second partition hole surrounding the hole region, and the second partition hole and the first partition hole are in communication to form a partition groove; the second partition layer at the periphery of the second partition hole has a protrusion relative to the side wall of the first partition hole, and the protrusion and the side wall of the first partition hole form a re-entrant structure.

[0009] In an exemplary embodiment, the partition structure is disposed between the structure layer and the encapsulation structure layer.

[0010] In an exemplary embodiment, the opening size of the substrate hole is smaller than the opening size of the structure hole.

[0011] In an exemplary embodiment, the encapsulation structure layer comprises a first encapsulation layer covering the structure layer and the partition structure, and the first encapsulation layer of the hole region is provided with an encapsulation hole in communication with the structure hole.

[0012] In an exemplary embodiment, the inner wall of the encapsulation hole on the substrate is substantially overlapped with the inner wall of the structure hole on the substrate.

[0013] In an exemplary embodiment, the encapsulation structure layer further comprises a second encapsulation layer; the second encapsulation layer is disposed on a side of the first encapsulation layer of the pixel region away from the substrate, or the second encapsulation layer is disposed on a side of the first encapsulation layer of the pixel region and the partition region away from the substrate.

[0014] In an exemplary embodiment, the encapsulation structure layer further comprises a third encapsulation layer as the encapsulation material layer; the third encapsulation layer is disposed on a side of the second encapsulation layer away from the substrate, and the third encapsulation layer covers the inner walls of the structure hole and the encapsulation hole, and the third encapsulation layer does not cover the substrate material segment of the substrate hole.

[0015] In an exemplary embodiment, the third encapsulation layer covers part of the inner wall of the substrate hole, forms an encapsulation material segment covered by the third encapsulation layer in the substrate hole, or the third encapsulation layer does not cover the inner wall of the substrate hole, and the inner wall of the substrate hole is the substrate material segment.

[0016] In an exemplary embodiment, the structure layer of the hole region is provided with a light-emitting block away from the substrate, the light-emitting block is provided with a light-emitting block hole, the light-emitting block hole is in communication with the structure hole, and the third encapsulation layer covers the inner wall of the light-emitting block hole.

[0017] In an exemplary embodiment, the light-emitting block of the hole region is provided with a cathode block away from the substrate side, the first encapsulation layer is arranged on the side of the cathode block away from the substrate, a cathode block hole is arranged on the cathode block, the cathode block hole is in communication with the light-emitting block hole and the encapsulation hole, and the third encapsulation layer covers the inner wall of the cathode block hole.

[0018] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0019] In yet another aspect, the present disclosure also provides a preparation method of a display substrate, the display substrate comprising a pixel region and a stretchable hole region, the pixel region comprising at least one sub-pixel, the stretchable hole region comprising at least one hole region and a partition region surrounding the hole region; the preparation method comprising:

[0020] forming a substrate, a structure layer arranged on the substrate, and an encapsulation structure layer arranged on the structure layer, the partition region comprising at least one partition structure surrounding the hole region;

[0021] forming a stretchable hole in the hole region, the stretchable hole comprising a substrate hole arranged on the substrate and a structure hole penetrating through the structure layer, the substrate hole and the structure hole being in communication, at least part of the inner wall of the structure hole being covered by at least one encapsulation material layer in the encapsulation structure layer, and the inner wall of the substrate hole comprising a substrate material segment not covered by the encapsulation material layer.

[0022] In an exemplary embodiment, the inner wall of the substrate hole further comprises an encapsulation material segment covered by the encapsulation material layer, the encapsulation material segment being located on the side of the substrate material segment close to the structure hole.

[0023] In an exemplary embodiment, the substrate hole comprises a through hole penetrating through the substrate, or a blind hole not penetrating through the substrate.

[0024] In an exemplary embodiment, forming a stretchable hole in the hole region comprises:

[0025] forming an encapsulation structure layer and a transition hole; the encapsulation structure layer comprises a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer as the encapsulation material layer; the transition hole is located in the hole region, the first encapsulation layer and the structure layer in the transition hole are removed, and the third encapsulation layer covers the inner wall of the transition hole;

[0026] etching the transition hole to form a stretchable hole; the stretchable hole comprises the transition hole and a substrate hole arranged on the substrate, the substrate hole and the transition hole being in communication, and the inner wall of the substrate hole comprising a substrate material segment not covered by the third encapsulation layer.

[0027] In an example embodiment, the material of the first and third encapsulation layers comprises inorganic material, and the material of the second encapsulation layer comprises organic material; forming an encapsulation structure layer and a transition hole comprises:

[0028] forming a first encapsulation layer, the first encapsulation layer covering the structure layer and the partition structure;

[0029] forming a transition hole in the hole region by a patterning process, the first encapsulation layer and the structure layer in the transition hole being removed;

[0030] forming a second encapsulation layer, the second encapsulation layer being arranged on the side of the first encapsulation layer in the pixel region and the partition region away from the substrate, or the first organic material layer in the second encapsulation layer being arranged on the side of the first encapsulation layer in the pixel region away from the substrate, and the second organic material layer in the second encapsulation layer being arranged on the side of the first encapsulation layer in the partition region away from the substrate;

[0031] forming a third encapsulation layer as the encapsulation material layer, the third encapsulation layer being arranged on the side of the second encapsulation layer away from the substrate, and the third encapsulation layer covering the inner wall of the transition hole.

[0032] The present disclosure provides a display substrate and a preparation method thereof, and a display device. By forming a substrate material segment not covered by an encapsulation material layer in a substrate hole in a stretched hole, the peeling interface of the display substrate and the glass substrate only has substrate material, avoiding the case that the film layer of the display substrate cannot be separated from the glass substrate, avoiding the occurrence of a pulling crack in the peeling process, and effectively ensuring the encapsulation effect of the display substrate.

[0033] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0035] Figure 1 FIG. 1 is a structural schematic diagram of a display substrate;

[0036] Figure 2 FIG. 2 is a plan structural schematic diagram of a display substrate;

[0037] Figure 3 FIG. 3 is an equivalent circuit schematic diagram of an OLED pixel driving circuit;

[0038] Figure 4 FIG. 4 is a working timing diagram of a pixel driving circuit;

[0039] Figure 5 A cross-sectional structure schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0040] Figure 6 A schematic diagram after forming a pixel driving circuit pattern according to an embodiment of the present disclosure;

[0041] Figure 7 A schematic diagram after forming a second planarization layer and a partition structure pattern according to an embodiment of the present disclosure;

[0042] Figure 8 A schematic diagram after forming an anode pattern according to an embodiment of the present disclosure;

[0043] Figure 9 A schematic diagram after forming a pixel definition layer pattern according to an embodiment of the present disclosure;

[0044] Figure 10 A schematic diagram after forming an organic light-emitting layer and a light-emitting block pattern according to an embodiment of the present disclosure;

[0045] Figure 11 A schematic diagram after forming a cathode and a cathode block pattern according to an embodiment of the present disclosure;

[0046] Figure 12 A schematic diagram after forming a first encapsulation thin film pattern according to an embodiment of the present disclosure;

[0047] Figure 13a and Figure 13b A schematic diagram after forming a transition hole pattern according to an embodiment of the present disclosure;

[0048] Figure 14a and Figure 14b A schematic diagram after forming a second encapsulation layer pattern according to an embodiment of the present disclosure;

[0049] Figure 15a and Figure 15b A schematic diagram after forming a third encapsulation layer pattern according to an embodiment of the present disclosure;

[0050] Figures 16a to 16d A schematic diagram after forming a stretching hole pattern according to an embodiment of the present disclosure.

[0051] Explanation of reference signs:

[0052] 1 - glass carrier plate; 10 - substrate; 11 - first active layer;

[0053] 12 - first gate electrode; 13 - first source electrode; 14 - first drain electrode;

[0054] 15 - connection electrode; 20 - driving structure layer; 21 - first capacitor electrode;

[0055] 22 - second capacitor electrode; 30 - structure layer; 31 - first flat layer;

[0056] 32 - second flat layer; 33 - inorganic layer; 41 - first partition layer;

[0057] 42 - second partition layer; 50 - hole region; 51 - partition region;

[0058] 60 - partition groove; 70 - light emitting structure layer; 71 - anode;

[0059] 72 - pixel definition layer; 73 - organic light emitting layer; 74 - light emitting block;

[0060] 75 - cathode; 76 - cathode block; 80 - encapsulation structure layer;

[0061] 81 - first encapsulation layer; 82 - second encapsulation layer; 83 - third encapsulation layer;

[0062] 91 - first insulating layer; 92 - second insulating layer; 93 - third insulating layer;

[0063] 94 - fourth insulating layer; 100 - pixel region; 101 - transistor;

[0064] 102 - storage capacitor; 200 - stretched hole region; 500 - stretched hole. DETAILED DESCRIPTION

[0065] For the purpose of making the object, technical solutions and advantages of the present disclosure clearer, below the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It can be easily understood by those skilled in the art that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the detailed description of some known functions and known components is omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design

[0066] In the drawings, the size of each constituent element, the thickness of each layer or the area is exaggerated for the sake of clearness in some cases. Therefore, the mode of the present disclosure is not necessarily limited to such a dimension, and the shape and the size of each component in the drawings do not reflect the actual scale. In addition, the drawings schematically show ideal examples, and the mode of the present disclosure is not limited to the shape or the value shown in the drawings.

[0067] In this specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among components, and are not used to denote the number in the order of the sequence.

[0068] In this specification, in order to facilitate the description of the present specification and simplify the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0069] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0070] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0071] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit during operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0072] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can transmit and receive an electrical signal between the connected components. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0073] In this specification, "parallel" means a state where an angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is 80° or more and 100° or less, and thus, a state where an angle of 85° or more and 95° or less is also included.

[0074] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be sometimes interchanged with "a conductive film". Similarly, "an insulating film" can be sometimes interchanged with "an insulating layer".

[0075] "About" in this disclosure means not strictly limited to a boundary, and allows a range of values within process and measurement errors.

[0076] Figure 1 A structure diagram of a display device. As Figure 1As shown, the OLED display device can include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array, and the pixel array can include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emission signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data signal driver can sample the gray value using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row, n can be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide the scan signals having on-pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register, and can generate the scan signals in a manner of sequentially transferring the scan start signal provided in the form of an on-pulse to a next stage circuit under the control of the clock signal, m can be a natural number. The light emission signal driver can generate emission signals to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driver can sequentially provide the emission signals having off-pulse to the light emission signal lines E1 to Eo. For example, the light emission signal driver can be configured in the form of a shift register, and can generate the light emission signals in a manner of sequentially transferring the light emission stop signal provided in the form of an off-pulse to a next stage circuit under the control of the clock signal, o can be a natural number. The pixel array can include a plurality of sub-pixels Pxij. Each sub-pixel Pxij can be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emission signal line, i and j can be natural numbers. The sub-pixel Pxij can refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and connected to the j-th data signal line.

[0077] Currently, flexible OLED displays exhibit uniaxial bending and minimal screen deformation. By creating micro-holes in the display substrate, the tensile strength of the substrate can be improved. Flexible display substrates can employ an island-bridge structure, where light-emitting devices are positioned within the pixel area, with the micro-holes located between the pixel areas, and connecting lines positioned between the pixel areas and the connecting bridge areas between the micro-holes. When an external force is applied to stretch the display substrate, deformation primarily occurs in the micro-hole and connecting bridge areas, while the light-emitting devices in the pixel areas largely maintain their shape, ensuring that the light-emitting devices in the pixel areas are not damaged.

[0078] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2 As shown, the display substrate may include multiple pixel regions spaced apart, and these pixel regions may be arranged in a matrix. In an exemplary embodiment, a pixel region may include at least one pixel unit P. Pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0079] In an exemplary embodiment, the first sub-pixel P1 can be a red (R) sub-pixel, the second sub-pixel P2 can be a green (G) sub-pixel, and the third sub-pixel P3 can be a blue (B) sub-pixel. In an exemplary embodiment, a pixel unit P can include four sub-pixels, such as a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in a pixel unit can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three light-emitting units can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the four light-emitting units can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement; this disclosure does not limit the arrangement.

[0080] In an exemplary embodiment, the display substrate can include a plurality of stretch holes 500 arranged at intervals, the stretch holes 500 being arranged between the pixel regions, and the stretch holes 500 being configured to increase the deformability of the display substrate. In a plane perpendicular to the display substrate, the base and the structure film layer in the stretch holes 500 are removed entirely to form a through-hole structure, or part of the base and the structure film layer in the stretch holes 500 are removed to form a blind hole structure. In a plane parallel to the display substrate, the shape of the stretch holes can include any one or more of the following: an "I" shape, a "T" shape, an "L" shape, and an "H" shape, without being limited by the present disclosure.

[0081] In an exemplary embodiment, the plurality of stretch holes 500 can include first direction stretch holes and second direction stretch holes, the first direction stretch holes being strip-shaped holes extending along a first direction X, the second direction stretch holes being strip-shaped holes extending along a second direction Y, the first direction X intersecting the second direction Y. In an exemplary embodiment, in the first direction X, the first direction stretch holes and the second direction stretch holes are arranged alternately, a first direction stretch hole being arranged between two second direction stretch holes, or a second direction stretch hole being arranged between two first direction stretch holes. In the second direction Y, the first direction stretch holes and the second direction stretch holes are arranged alternately, a first direction stretch hole being arranged between two second direction stretch holes, or a second direction stretch hole being arranged between two first direction stretch holes.

[0082] In an exemplary embodiment, the pixel driving circuit can be of a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T2C structure, etc. Figure 3 An equivalent circuit schematic diagram of a pixel driving circuit is shown in FIG. 1. As shown in FIG. 1, the pixel driving circuit can include seven transistors (a first transistor T1 to a seventh transistor T7), one storage capacitor C, and seven signal lines (a first scan signal line S1, a second scan signal line S2, an emission signal line E, a data signal line D, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS). Figure 3

[0083] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power supply line VDD, and a second end of the storage capacitor C is connected to a second node N2, i.e., the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0084] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.​

[0085] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0086] The control electrode of the third transistor T3 is connected to the second node N2, i.e., the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driver transistor, and the third transistor T3 determines the amount of a drive current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between the control electrode and the first electrode thereof.

[0087] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, or the like, and when the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0088] The control electrode of the fifth transistor T5 is connected to the emission signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the emission signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When the on-level emission signal is applied to the emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a drive current path between the first power supply line VDD and the second power supply line VSS.

[0089] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device.

[0090] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0091] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0092] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the initial signal line INIT extend in the horizontal direction, while the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in the vertical direction.

[0093] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0094] Figure 4 This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 3 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 3 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS). All 7 transistors are P-type transistors.

[0095] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0096] The first stage A1, called reset stage, the signal of the second scan signal line S2 is low level signal, the signals of the first scan signal line S1 and the emitting signal line E are high level signals. The signal of the second scan signal line S2 is low level signal, so that the first transistor T1 is turned on, the signal of the initial signal line INIT is provided to the second node N2, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. The signals of the first scan signal line S1 and the emitting signal line E are high level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light in this stage.

[0097] The second stage A2, called data writing stage or threshold compensation stage, the signal of the first scan signal line S1 is low level signal, the signals of the second scan signal line S2 and the emitting signal line E are high level signals, and the data signal line D outputs data voltage. In this stage, the second end of the storage capacitor C is low level, so that the third transistor T3 is turned on. The signal of the first scan signal line S1 is low level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage in the first electrode is cleared, the initialization is completed, and the OLED does not emit light. The signal of the second scan signal line S2 is high level signal, so that the first transistor T1 is turned off. The signal of the emitting signal line E is high level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.

[0098] The third stage A3, called emitting stage, the signal of the emitting signal line E is low level signal, and the signals of the first scan signal line S1 and the second scan signal line S2 are high level signals. The signal of the emitting signal line E is low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving voltage is provided to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 from the power supply voltage output by the first power supply line VDD, so that the OLED emits light.

[0099] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0100] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0101] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0102] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on the substrate, a light-emitting structure layer disposed on the driving structure layer, and an encapsulation layer disposed on the light-emitting element. The driving structure layer includes a pixel driving circuit, and the light-emitting structure layer includes a light-emitting device, which is connected to the pixel driving circuit.

[0103] Figure 5 This is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the cross-sectional structure at the junction of the pixel region and the stretching hole region. Figure 2 A cross-sectional view along direction AA. The display substrate may include a pixel region 100 and a stretched hole region 200. The pixel region 100 may include at least one sub-pixel, and the stretched hole region 200 may include a hole region 50 and a partition region 51 surrounding the hole region 50. In a plane perpendicular to the display substrate, the display substrate may include a substrate, a structural layer disposed on the substrate, and an encapsulation structural layer disposed on the structural layer. Figure 5 As shown, in an exemplary embodiment, the structural layer of the pixel region 100 may include a driving structure layer 20 disposed on the substrate 10 and a light-emitting structure layer 70 disposed on the side of the driving structure layer 20 away from the substrate. In an exemplary embodiment, the driving structure layer 20 may include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. Figure 5This example uses only one transistor 101 and one storage capacitor 102. The light-emitting structure layer 70 may include an anode 71, a pixel definition layer 72, an organic light-emitting layer 73, and a cathode 75. The anode 71 is connected to the drain electrode of the transistor 101 through a via of the connecting electrode 15. The organic light-emitting layer 73 is connected to the anode 71, and the cathode 75 is connected to the organic light-emitting layer 73. The organic light-emitting layer 73 emits light of the corresponding color under the drive of the anode 71 and the cathode 75. In an exemplary embodiment, the encapsulation structure layer 80 of the pixel area 100 is disposed on the side of the light-emitting structure layer 70 away from the substrate. It may include a first encapsulation layer 81, a second encapsulation layer 82, and a third encapsulation layer 83 stacked together. The first encapsulation layer 81 and the third encapsulation layer 83 may be made of inorganic materials, and the second encapsulation layer 82 may be made of organic materials. The second encapsulation layer 82 is disposed between the first encapsulation layer 81 and the third encapsulation layer 83 to ensure that external moisture cannot enter the light-emitting device.

[0104] In an exemplary embodiment, the aperture region 50 may include a substrate 10 and a structural layer 30 disposed on the substrate 10. The substrate 10 has a base aperture, and the structural layer 30 has a structural aperture penetrating the entire structural layer; the base aperture and the structural aperture are connected. At least part or all of the inner wall of the structural aperture may be covered by at least one encapsulation material layer in the encapsulation structural layer. The inner wall of the base aperture may include a segment of encapsulation material not covered by the encapsulation material layer, or the inner wall of the base aperture may include a base material segment covered by the encapsulation material layer and a segment of encapsulation material not covered by the encapsulation material layer, with the encapsulation material segment located on the side of the base material segment closest to the structural aperture. In an exemplary embodiment, the encapsulation material layer may include a third encapsulation layer 83.

[0105] In an exemplary embodiment, the structural layer 30 of the via region 50 may include any one or more of the following film layers: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a first planarization layer. In an exemplary embodiment, the structural layer 30 of the via region 50 may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a first planarization layer sequentially stacked along a direction away from the substrate.

[0106] In an exemplary embodiment, the base hole may be a through hole that penetrates the entire base 10, or it may be a blind hole that does not completely penetrate the base 10.

[0107] In an exemplary embodiment, the partition region 51 may include a base 10, a structural layer 30 disposed on the base 10, and at least one partition structure disposed on the side of the structural layer 30 away from the base, the partition structure surrounding the hole region 50. In an exemplary embodiment, the partition structure may include a first partition layer 41 surrounding the hole region 50 and a second partition layer 42 disposed on the first partition layer 41. The first partition layer 41 has a first partition hole surrounding the hole region 50, and the second partition layer 42 has a second partition hole surrounding the hole region 50. The second partition hole and the first partition hole communicate to form a partition groove 60 surrounding the hole region 50. In an exemplary embodiment, the second partition layer 42 located around the second partition hole has a protrusion 421 relative to the sidewall of the first partition hole, and the protrusion 421 and the sidewall of the first partition hole form an indented structure.

[0108] In an exemplary embodiment, in the direction away from the hole area 50, the width of the second partition hole is smaller than the width of the first partition hole, and the orthographic projection of the outline of the second partition hole on the substrate is within the range of the orthographic projection of the outline of the first partition hole on the substrate.

[0109] In an exemplary embodiment, the first partition layer may be disposed on the same layer as the second planarization layer in the driving structure layer, and formed simultaneously by the same patterning process.

[0110] In an exemplary embodiment, in the partition area 51, a first encapsulation layer 81 covers the partition structure, a second encapsulation layer 82 is disposed on the side of the first encapsulation layer 81 away from the substrate and fills the partition groove 60, and a third encapsulation layer 83 is disposed on the side of the second encapsulation layer 82 away from the substrate. The first encapsulation layer 81 covering the partition structure means that the first encapsulation layer 81 covers the exposed outer surfaces of the first partition layer 41 and the second partition layer 42, as well as the inner wall of the partition groove 60, forming a complete enclosure of the partition structure.

[0111] In an exemplary embodiment, a first encapsulation hole is provided on the first encapsulation layer 81 in the hole area 50. The first encapsulation hole on the first encapsulation layer 81 is connected to the structural hole on the structural layer 30. The inner wall of the first encapsulation hole is substantially flush with the inner wall of the structural hole. The orthographic projection of the inner wall of the first encapsulation hole on the substrate is substantially overlapping with the orthographic projection of the inner wall of the structural hole on the substrate. The third encapsulation layer 83 covers the inner wall of the first encapsulation hole.

[0112] In an exemplary embodiment, the aperture region 50 further includes a light-emitting block 74, which is disposed on the side of the structural layer 30 away from the substrate. The light-emitting block has a light-emitting hole, which communicates with the structural hole on the structural layer 30. The inner wall of the light-emitting block hole is substantially flush with the inner wall of the structural hole, and the third encapsulation layer 83 covers the inner wall of the light-emitting block hole.

[0113] In an exemplary embodiment, the aperture region 50 further includes a cathode block 76, which is disposed on the side of the light-emitting block 74 away from the substrate, and a first encapsulation layer 81 is disposed on the side of the cathode block 76 away from the substrate. The cathode block 76 has a cathode block hole that communicates with the light-emitting block hole, the first encapsulation hole, and the structural hole. The inner wall of the cathode block hole is substantially flush with the inner walls of the light-emitting block hole, the first encapsulation hole, and the structural hole. A third encapsulation layer 83 covers the inner wall of the cathode block hole.

[0114] In an exemplary embodiment, the opening size of the base hole can be smaller than the opening size of the structural hole.

[0115] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0116] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0117] (1) Preparing a substrate on a glass carrier plate. In one exemplary embodiment, the substrate may include a flexible material layer formed on the glass carrier plate. In another exemplary embodiment, the substrate may include a first flexible material layer and a second flexible material layer stacked on the glass carrier plate. In yet another exemplary embodiment, the substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier plate. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers may be referred to as barrier layers or buffer layers. In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate 1, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then coating another layer of polyimide on the first barrier layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the preparation of the substrate.

[0118] In an exemplary embodiment, an amorphous silicon (a-Si) layer may be disposed between the first barrier layer and the second inorganic material layer, and the substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate.

[0119] In an exemplary embodiment, during the formation of the first barrier layer, inorganic holes can be formed on the first barrier layer by a patterning process, and the positions of the inorganic holes can correspond to the positions of the subsequently formed through holes.

[0120] (2) Fabricating a driving structure layer pattern on the substrate 10. In an exemplary embodiment, the driving structure layer may include transistors and storage capacitors constituting a pixel driving circuit, and the process of fabricating the driving structure layer pattern may include:

[0121] A first insulating film and a semiconductor film are sequentially deposited on a substrate 10. The semiconductor film is patterned by a patterning process to form a first insulating layer 91 on the substrate 10, and a semiconductor layer pattern disposed on the first insulating layer 91. The semiconductor layer pattern includes at least a first active layer 11.

[0122] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned using a patterning process to form a second insulating layer 92 covering the semiconductor layer pattern, and a first metal layer pattern disposed on the second insulating layer 92. The first metal layer pattern includes at least a first gate electrode 12 and a first capacitor electrode 21.

[0123] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer 93 covering the pattern of the first metal layer, and a second metal layer pattern disposed on the third insulating layer 93. The second metal layer pattern includes at least a second capacitor electrode 22, and the position of the second capacitor electrode 22 corresponds to the position of the first capacitor electrode 21.

[0124] Subsequently, a fourth insulating film is deposited, and the fourth insulating film is patterned using a patterning process to form a fourth insulating layer 94 covering the pattern of the second metal layer. Multiple vias are formed on the fourth insulating layer 94. These vias may include a first active via and a second active via. The fourth insulating layer 94, the third insulating layer 93, and the second insulating layer 92 within the first and second active vias are etched away, exposing the source and drain regions at both ends of the first active layer 11, respectively.

[0125] Subsequently, a third metal thin film is deposited and patterned using a patterning process to form a third metal layer pattern on the fourth insulating layer 94. The third metal layer pattern includes at least a first source electrode 13 and a first drain electrode 14. The first source electrode 13 and the first drain electrode 14 are connected to the source and drain regions at both ends of the first active layer 11 through a first active via and a second active via, respectively.

[0126] Subsequently, a first planarization film is coated, and the first planarization film is patterned by a patterning process to form a first planarization layer 31 covering the pattern of the third metal layer. A connection via is formed on the first planarization layer 31. The first planarization layer 31 inside the connection via is removed to expose the surface of the first drain electrode 14.

[0127] Subsequently, a fourth metal thin film is deposited and patterned using a patterning process to form a fourth metal layer pattern on the first planarization layer 31. The fourth metal layer pattern includes at least a connecting electrode 15, which is connected to the first drain electrode 14 via a connecting via. The connecting electrode 15 is configured to connect to the subsequently formed anode, such as... Figure 6 As shown in the figure Figure 2 Sectional view along the AA direction.

[0128] The pixel driving circuit is now complete, illustrated by a transistor and a storage capacitor. In an exemplary embodiment, the first active layer 11, the first gate electrode 12, the first source electrode 13, and the first drain electrode 14 constitute the first transistor 101 of the pixel driving circuit, and the first capacitor electrode 21 and the second capacitor electrode 22 constitute the first storage capacitor 102 of the pixel driving circuit. In an exemplary embodiment, the first transistor 101 may be a driving transistor in the pixel driving circuit.

[0129] In an exemplary embodiment, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second and third insulating layers can be called (GI) layers, and the fourth insulating layer can be called an interlayer insulation (ILD) layer. The first planarization layer can be made of organic materials, such as resin. The first, second, third, and fourth metal layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The active layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0130] In an exemplary embodiment, the stretched hole region 200 may include at least one hole region 50 and a partition region 51 surrounding the hole region 50. After this patterning process, the hole region 50 and the partition region 51 include a substrate 10 and a structural layer 30 disposed on the substrate 10. The structural layer 30 may include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, and a first planarization layer 31 stacked on the substrate 10.

[0131] (3) Forming a second planarization layer and a partition structure pattern. In an exemplary embodiment, forming the second planarization layer and the partition structure pattern may include: first coating a second planarization film on a substrate on which the aforementioned pattern is formed, then depositing an inorganic film on the second planarization film, patterning the inorganic film and the second planarization film using a patterning process, forming a second planarization layer 32 covering the fourth metal layer pattern and an inorganic layer 33 disposed on the second planarization layer 32 in the pixel area, and forming a partition structure pattern in the stretch hole area, such as... Figure 7 As shown,Figure 7 for Figure 2 Sectional view along the AA direction.

[0132] In an exemplary embodiment, an anode via is formed on the inorganic layer 33 and the second planarization layer 32 of the pixel region. The inorganic film and the second planarization film inside the anode via are removed to expose the surface of the connecting electrode 15. The anode via is configured to allow the anode to be formed subsequently to be connected to the connecting electrode 15 through the via.

[0133] In an exemplary embodiment, a partition structure pattern is formed in the partition region 51 in an annular shape surrounding the aperture region 50. The inorganic film and the second planar film on the side of the annular partition structure closest to the aperture region 50 are removed to form a first opening K1, which exposes the surface of the first planar layer 31 of the aperture region 50. The inorganic film and the second planar film on the side of the annular partition structure furthest from the aperture region 50 are removed to form an annular second opening K2 between the partition structure and the second planar layer 32, which exposes the surface of the first planar layer 31.

[0134] In an exemplary embodiment, in a plane perpendicular to the display substrate, the partition structure pattern includes a first partition layer 41 disposed on the side of the first flat layer 31 away from the substrate and a second partition layer 42 disposed on the side of the first partition layer 41 away from the substrate. The annular first partition layer 41 has a first partition hole, and the annular second partition layer 42 has a second partition hole. The annular first partition hole and the annular second partition hole are interconnected, and the first partition hole and the second partition hole form a partition groove 60.

[0135] In an exemplary embodiment, the cross-sectional shape of the first partition layer 41 in a plane perpendicular to the substrate can be trapezoidal, and the width of the first partition layer 41 on the side away from the substrate is smaller than the width of the first partition layer 41 on the side close to the substrate.

[0136] In an exemplary embodiment, the process of forming the partition structure pattern may include: first, coating a layer of photoresist on an inorganic thin film; exposing the photoresist using a mask; developing the photoresist to form a fully exposed area and an unexposed area; removing the photoresist from the fully exposed area and retaining the photoresist from the unexposed area; then etching the inorganic thin film in the fully exposed area to form a ring-shaped second partition layer 42 and a ring-shaped second partition hole disposed on the second partition layer 42; subsequently, further etching the exposed second planar thin film to form a ring-shaped first partition layer 41 and a ring-shaped first partition hole disposed on the first partition layer 41, wherein the first partition hole and the second partition hole are interconnected to form a partition groove 60.

[0137] In an exemplary embodiment, a dry etching process can be used for etching, employing a gas with a high organic / inorganic etching ratio, such as O2, CF4, or CHF3. Because the organic / inorganic etching ratio is high—that is, the etching rate of organic materials is greater than that of inorganic materials—the first partition hole undergoes lateral etching during etching. The first partition hole on the first partition layer 41 extends outward relative to the second partition hole on the second partition layer 42 by a certain distance, forming a partition groove 60 with a lateral etching structure.

[0138] In an exemplary embodiment, in a plane perpendicular to the substrate, the cross-sectional shape of the first partition hole on the first partition layer 41 is an inverted trapezoidal shape, and the width of the upper opening of the first partition hole on the side away from the substrate is greater than the width of the lower opening of the first partition hole on the side closer to the substrate. In an exemplary embodiment, the side of the inverted trapezoidal first partition hole can be arc-shaped.

[0139] In an exemplary embodiment, the second partition layer located around the second partition hole has a protrusion 421 relative to the sidewall of the opening in the first partition hole, and the protrusion 421 and the sidewall of the opening in the first partition hole form an indented structure.

[0140] In an exemplary embodiment, the opening size of the first partition hole on the first partition layer 41 is smaller than the opening size of the second partition hole on the second partition layer 42, and the orthographic projection of the second partition hole on the substrate is within the range of the orthographic projection of the opening of the first partition hole on the substrate. Within the partition groove 60, the second partition layer 42 has an edge (protrusion 421) protruding from the opening of the first partition hole, forming an "eaves" structure. The orthographic projection of the outline of the second partition hole on the substrate is within the range of the orthographic projection of the outline of the opening of the first partition hole on the substrate. In this disclosure, by providing the partition groove 60 with the "eaves" structure, the subsequently vapor-deposited organic light-emitting layer, cathode, and optical coupling layer can be effectively isolated, effectively blocking the intrusion of water and oxygen from the hole area.

[0141] In an exemplary embodiment, the width of the second partition layer 42 protruding from the opening edge of the first partition hole can be approximately 1 μm to 3 μm, that is, the first partition hole is expanded outward by 1 μm to 3 μm relative to the second partition hole.

[0142] In an exemplary embodiment, a first partition layer 41, a second partition layer 42 disposed on the first partition layer 41, a first partition hole disposed on the first partition layer 41, and a second partition hole disposed on the second partition layer 42 constitute a partition structure. The partition structure is formed in the partition region 51 surrounding the hole region 50, and is an annular structure surrounding the hole region 50. Furthermore, the second partition layer 42 facing the first opening K1 and the second opening K2 may have an "eaves" structure protruding from the first partition layer 41.

[0143] In an exemplary embodiment, the second planarization layer may be an organic material, such as resin. The inorganic layer may be any one or more of SiOx, SiNx, and SiON, and may be a single layer, multiple layers, or a composite layer. The inorganic layer may be referred to as a passivation layer (PVX).

[0144] At this point, the driving structure layer is fabricated in the pixel region. In an exemplary embodiment, the driving structure layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, a fourth insulating layer, a third metal layer, a first planarization layer, a fourth metal layer, a second planarization layer, and an inorganic layer, all stacked together.

[0145] After this process, the hole area 50 includes a structural layer 30 disposed on the substrate 10, and the partition area 51 includes a structural layer 30 disposed on the substrate and a partition structure disposed on the side of the structural layer 30 away from the substrate. The partition structure is annular in shape surrounding the hole area 50.

[0146] (4) Forming an anode pattern. In an exemplary embodiment, forming an anode pattern may include: depositing a conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the conductive thin film using a patterning process to form an anode 71 pattern, such as... Figure 8 As shown, Figure 8 for Figure 2 Sectional view along the AA direction.

[0147] In an exemplary embodiment, the anode 71 is disposed on the second planarization layer 32 of the pixel region, and the anode 71 is connected to the connection electrode 15 through an anode via. Since the connection electrode 15 is connected to the first drain electrode of the first transistor 101 through the connection via, the connection between the anode 71 and the first transistor 101 is realized through the connection electrode 15.

[0148] In exemplary embodiments, the conductive thin film can be made of a metallic material or a transparent conductive material. The metallic material can include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals. The transparent conductive material can include indium tin oxide (ITO) or indium zinc oxide (IZO). In exemplary embodiments, the conductive thin film can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0149] After this process, the structure of the hole area 50 and the partition area 51 is basically the same as the structure after the previous patterning process.

[0150] (5) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process, and forming a pixel definition layer 72 pattern in the pixel area, such as... Figure 9 As shown, Figure 9 for Figure 2 Sectional view along the AA direction.

[0151] In an exemplary embodiment, a pixel opening is formed on the pixel definition layer 72, and the pixel definition layer within the pixel opening is removed to expose the surface of the anode 71. In an exemplary embodiment, a spacer pillar pattern can be formed when the pixel definition layer is formed, and the spacer pillars are configured to support the mask in a subsequent vapor deposition process. In an exemplary embodiment, the spacer pillars can be disposed outside the pixel opening, and the pixel definition layer and the spacer pillar pattern can be formed using a half-tone mask in the same patterning process, which is not limited herein.

[0152] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc. In a plane parallel to the display substrate, the shape of the pixel opening may be triangular, rectangular, polygonal, circular, or elliptical, etc. In a plane perpendicular to the display substrate, the cross-sectional shape of the pixel opening may be rectangular or trapezoidal, etc., and this disclosure does not limit the specific shape.

[0153] After this process, the structure of the hole area 50 and the partition area 51 is basically the same as the structure after the previous patterning process.

[0154] (6) Forming an organic light-emitting layer and a light-emitting block pattern. In an exemplary embodiment, forming the organic light-emitting layer and the light-emitting block pattern may include: forming the organic light-emitting layer 73 and the light-emitting block 74 pattern on the substrate on which the aforementioned pattern is formed by vapor deposition or inkjet printing, such as... Figure 10 As shown, Figure 10 for Figure 2 Sectional view along the AA direction.

[0155] In an exemplary embodiment, in the pixel region, an organic light-emitting layer 73 is formed on the pixel definition layer 72 and connected to the anode 71 through a pixel opening.

[0156] In an exemplary embodiment, in the stretching hole area, i.e., the area where the first opening K1, the second opening K2, and the partition structure are located, because the second partition layer 42 has an "eaves" structure protruding from the first partition layer 41, and the inner wall of the partition groove 60 has a side-erosion structure, the organic light-emitting material breaks at the edges of the first opening K1 and the second opening K2, and breaks at the "eaves" structure of the partition groove 60. Light-emitting blocks 74 are formed at the bottom of the partition groove 60, the bottom of the first opening K1 and the second opening K2, and on the second partition layer 42 of the partition structure. The light-emitting blocks 74 are isolated from the organic light-emitting layer 73. This disclosure, by setting a partition structure to disconnect the organic light-emitting layer, can cut off the water and oxygen transmission channel, effectively blocking the intrusion of water and oxygen from the hole area.

[0157] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0158] In an exemplary embodiment, the organic light-emitting layer can be fabricated using the following method. First, an open-faced mask is used to sequentially deposit a hole injection layer and a hole transport layer, forming a common layer of the hole injection and hole transport layers in the pixel region. Then, a fine metal mask is used to deposit an electron blocking layer and a red light-emitting layer on the red sub-pixel, an electron blocking layer and a green light-emitting layer on the green sub-pixel, and an electron blocking layer and a blue light-emitting layer on the blue sub-pixel. The electron blocking and light-emitting layers of adjacent sub-pixels may have a small amount of overlap (e.g., the overlapping portion occupies less than 10% of the area of ​​their respective light-emitting layer patterns), or they may be isolated. Subsequently, an open-faced mask is used to sequentially deposit a hole blocking layer, an electron transport layer, and an electron injection layer, forming a common layer of the hole blocking layer, electron transport layer, and electron injection layer in the pixel region.

[0159] In an exemplary embodiment, the electron blocking layer can serve as the microcavity conditioning layer of the light-emitting device. By designing the thickness of the electron blocking layer, the thickness of the organic light-emitting layer between the cathode and anode can be made to meet the design of the microcavity length. In some exemplary embodiments, the hole transport layer, hole blocking layer, or electron transport layer in the organic light-emitting layer can be used as the microcavity conditioning layer of the light-emitting device, and this disclosure does not limit this to any particular method.

[0160] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped in the host material, with the doping ratio of the guest material ranging from 1% to 20%. Within this doping ratio range, on the one hand, the host material can effectively transfer exciton energy to the guest material to excite it to emit light; on the other hand, the host material "dilutes" the guest material, effectively improving fluorescence quenching caused by intermolecular collisions and energy-based collisions, thereby increasing luminous efficiency and device lifetime. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, i.e., mass percentage. In an exemplary embodiment, the host material and the guest material can be deposited together using a multi-source evaporation process, ensuring uniform dispersion of both materials in the light-emitting layer. The doping ratio can be controlled by adjusting the evaporation rate of the guest material or by controlling the ratio of the evaporation rates of the host material and the guest material during the evaporation process. In an exemplary embodiment, the thickness of the light-emitting layer can be approximately 10 nm to 50 nm.

[0161] In an exemplary embodiment, the hole injection layer may be an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or may be a dopant of a p-type dopant with a strong electron-withdrawing system and a hole transport material. In an exemplary embodiment, the thickness of the hole injection layer may be approximately 5 nm to 20 nm.

[0162] In an exemplary embodiment, the hole transport layer can be made of a material with high hole mobility, such as an aromatic amine compound, whose substituent groups can be carbazole, methyl fluorene, spirofluorene, dibenzothiophene, or furan, etc. In an exemplary embodiment, the thickness of the hole transport layer can be approximately 40 nm to 150 nm.

[0163] In an exemplary embodiment, the hole-blocking layer and the electron transport layer can be aromatic heterocyclic compounds, such as imidazole derivatives like benzimidazole derivatives, imidazopyridine derivatives, and benzimidazolephenanthridine derivatives; azine derivatives like pyrimidine derivatives and triazine derivatives; and compounds containing a nitrogen-containing six-membered ring structure such as quinoline derivatives, isoquinoline derivatives, and phenanthreneroline derivatives (including compounds with phosphine oxide substituents on the heterocycle). In an exemplary embodiment, the thickness of the hole-blocking layer can be approximately 5 nm to 15 nm, and the thickness of the electron transport layer can be approximately 20 nm to 50 nm.

[0164] In an exemplary embodiment, the electron injection layer may be made of an alkali metal or a metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or compounds of these alkali metals or metals. In an exemplary embodiment, the thickness of the electron injection layer may be approximately 0.5 nm to 2 nm.

[0165] After this process, the hole area 50 includes a structural layer 30 disposed on the substrate 10 and a light-emitting block 74 disposed on the side of the structural layer 30 away from the substrate. The partition area 51 includes a structural layer 30 disposed on the substrate 10, a partition structure disposed on the side of the structural layer 30 away from the substrate, a light-emitting block 74 disposed on the side of the second partition layer 42 in the partition structure away from the substrate, and a light-emitting block 74 disposed at the bottom of the partition groove 60 in the partition structure.

[0166] (7) Forming the cathode and cathode block pattern. In an exemplary embodiment, forming the cathode pattern may include: forming the cathode 75 and cathode block 76 pattern on the substrate on which the aforementioned pattern is formed by vapor deposition, such as... Figure 11 As shown, Figure 11 for Figure 2 A cross-sectional view along the AA direction. In an exemplary embodiment, the cathode may be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the aforementioned metals.

[0167] In an exemplary embodiment, the stretchable cathode 75 can be a monolithic structure connected together. In the pixel region, the cathode 75 is connected to the organic light-emitting layer 73, enabling the organic light-emitting layer 73 to be simultaneously connected to both the anode 71 and the cathode 75.

[0168] In an exemplary embodiment, in the stretching hole area, i.e., the area where the first opening K1, the second opening K2, and the partition structure are located, because the second partition layer 42 has an "eaves" structure protruding from the first partition layer 41, and the inner wall of the partition groove 60 has a side-erosion structure, the cathode breaks at the edges of the first opening K1 and the second opening K2, and breaks at the "eaves" structure of the partition groove 60. A cathode block 76 is formed at the bottom of the partition groove 60, the bottom of the first opening K1 and the second opening K2, and on the light-emitting block 74 of the partition structure. The cathode block 76 and the cathode 75 are isolated from each other. This disclosure, by setting the partition structure to disconnect the cathode, can cut off the water and oxygen transmission channel and effectively block the intrusion of water and oxygen from the hole area.

[0169] At this point, the light-emitting structure layer is fabricated in the pixel area. In an exemplary embodiment, the light-emitting structure layer may include an anode 71, an organic light-emitting layer 73, and a cathode 75, with the organic light-emitting layer 73 disposed between the anode 71 and the cathode 75.

[0170] After this process, the hole region 50 includes a structural layer 30 disposed on the substrate 10, a light-emitting block 74 disposed on the side of the structural layer 30 away from the substrate, and a cathode block 76 disposed on the side of the light-emitting block 74 away from the substrate. The partition region 51 includes a structural layer 30 disposed on the substrate 10, a partition structure disposed on the side of the structural layer 30 away from the substrate, a light-emitting block 74 disposed on the side of the second partition layer 42 in the partition structure away from the substrate, a light-emitting block 74 disposed at the bottom of the partition groove 60 in the partition structure, and a cathode block 76 disposed on the side of the light-emitting block 74 away from the substrate.

[0171] In an exemplary embodiment, after forming the cathode and cathode block pattern, the step of forming an optical coupling layer and an optical coupling block pattern may be included. The optical coupling layer may be a continuous integral structure disposed on the cathode, while the optical coupling block is disconnected at the "eaves" structure and disposed on the cathode block. In an exemplary embodiment, the refractive index of the optical coupling layer may be greater than that of the cathode, which is beneficial for light extraction and increases light extraction efficiency. The material of the optical coupling layer may be an organic material, an inorganic material, or a combination of organic and inorganic materials, and may be a single layer, multiple layers, or a composite layer; this disclosure does not limit the specific materials used.

[0172] (8) Forming a first encapsulation layer pattern. In an exemplary embodiment, forming the first encapsulation layer pattern may include: depositing a first encapsulation film 80 on the substrate on which the aforementioned pattern is formed, such as... Figure 12 As shown, Figure 12 for Figure 2 Sectional view along the AA direction.

[0173] In an exemplary embodiment, the first encapsulation film 80 can be deposited using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). In the pixel area, the first encapsulation film 80 is disposed on the side of the cathode 75 away from the substrate. In the area where the first opening K1, the second opening K2, and the partition structure are located, the first encapsulation film 80 covers the light-emitting block 74 and the cathode block 76 on the second partition layer 42, covers the light-emitting block 74 and the cathode block 76 at the bottom of the first opening K1, the second opening K2, and the partition groove 60, and covers the sidewalls of the first opening K1, the second opening K2, and the partition groove 60, forming a wrapping structure that completely covers the partition structure.

[0174] After this process, the hole area 50 includes a structural layer disposed on the substrate 10, a light-emitting block 74 disposed on the side of the structural layer away from the substrate, a cathode block 76 disposed on the side of the light-emitting block 74 away from the substrate, and a first encapsulation film 80 disposed on the side of the cathode block 76 away from the substrate.

[0175] Subsequently, the hole region 50 is etched using a patterning process to form the first encapsulation layer 81 and the transition hole H1 pattern located in the hole region 50, as shown below. Figure 13a andFigure 13b As shown, Figure 13a and Figure 13b for Figure 2 Sectional view along the AA direction.

[0176] In one exemplary embodiment, the first encapsulation film 80, cathode block 76, light-emitting block 74, and structural layer 30 of the aperture region 50 are etched. The first encapsulation layer, cathode block, light-emitting block, first planarization layer, and composite insulating layer in the transition hole H1 are removed. The bottom of the transition hole H1 is located at the interface between the composite insulating layer and the substrate, forming a blind hole structure for the transition hole H1. Figure 13a As shown.

[0177] In an exemplary embodiment, the transition hole H1 may include a first encapsulation hole formed on the first encapsulation layer 81, a cathode block hole formed on the cathode block 76, a light-emitting block hole formed on the light-emitting block 74, and a structural hole formed on the structural layer 30. The first encapsulation hole, cathode block hole, light-emitting block hole, and structural hole are interconnected. In an exemplary embodiment, the inner walls of the first encapsulation hole, cathode block hole, light-emitting block hole, and structural hole are substantially flush, and the orthographic projections of the inner walls of the first encapsulation hole, cathode block hole, light-emitting block hole, and structural hole on the substrate substantially overlap. The structural hole may include a planar hole formed on the first planarization layer and an insulating hole formed on the composite insulating layer. The planar hole and the insulating hole are interconnected.

[0178] In another exemplary embodiment, the first encapsulation film 80, cathode block 76, light-emitting block 74, structural layer 30, and a portion of the substrate 10 in the aperture region 50 are etched. The first encapsulation layer, cathode block, light-emitting block, first planarization layer, composite insulating layer, and a portion of the substrate in the transition aperture H1 are removed. The bottom of the transition aperture H1 is located within the substrate, forming a blind aperture H1, as shown below. Figure 13b As shown.

[0179] In an exemplary embodiment, the transition hole H1 may include a first encapsulation hole formed on the first encapsulation layer 81, a cathode block hole formed on the cathode block 76, a light-emitting block hole formed on the light-emitting block 74, a structural hole formed on the structural layer 30, and a transition base hole formed on a portion of the thickness of the substrate 10. The first encapsulation hole, cathode block hole, light-emitting block hole, structural hole, and transition base hole are interconnected. In an exemplary embodiment, the inner walls of the first encapsulation hole, cathode block hole, light-emitting block hole, structural hole, and transition base hole are substantially flush, and the orthographic projections of the inner wall of the first encapsulation hole, the inner wall of the cathode block hole, the inner wall of the light-emitting block hole, the inner wall of the structural hole, and the transition base hole on the substrate substantially overlap.

[0180] In an exemplary embodiment, the inner wall of the transition hole H1 may include the inner wall of the encapsulation material of the first encapsulation hole, the inner wall of the cathode material of the cathode block hole, the inner wall of the light-emitting material of the light-emitting block hole, the inner wall of the flat material of the flat hole, the inner wall of the insulating material of the insulating hole, and the inner wall of the base material of the transition substrate hole. The inner walls of the encapsulation material and the insulating material may be inorganic materials, the inner walls of the flat material and the inner walls of the base material may be organic materials, the inner wall of the light-emitting material may be a small-molecule organic material, and the inner wall of the cathode material may be a metallic material.

[0181] In an exemplary embodiment, since the etching of the transition hole H1 includes etching of both an inorganic material layer and an organic material layer, and the etching rate of the organic material is greater than that of the inorganic material, the sidewall of the transition hole H1 forms a step at the interface between the substrate 10 and the composite insulating layer 30. The opening of the blind hole on the substrate 10 is extended outward by a certain distance relative to the blind hole on the composite insulating layer, and the composite insulating layer in the inner wall of the transition hole H1 has an "eaves" structure that protrudes from the substrate.

[0182] In an exemplary embodiment, the opening size of the transition base hole on the substrate can be larger than the opening size of the structural hole on the structural layer, and the orthographic projection of the outline of the structural hole on the structural layer onto the glass substrate is within the range of the orthographic projection of the outline of the transition base hole on the substrate onto the glass substrate.

[0183] In an exemplary embodiment, in the partition region 51, the first encapsulation layer 81 covers the exposed outer surface of the partition structure and the inner wall of the partition groove 60, forming a complete encapsulation of the partition structure. The complete encapsulation of the partition structure by the first encapsulation layer 81 ensures the integrity of the encapsulation, effectively isolating water and oxygen from the pore area, and the partition groove forms pinning points for the encapsulation layer, which can prevent peeling failure of the film edge.

[0184] (9) Forming a second encapsulation layer pattern. In an exemplary embodiment, forming the second encapsulation layer pattern may include: forming a second encapsulation film on a substrate on which the aforementioned pattern is formed using processes such as inkjet printing or coating; patterning the second encapsulation film; removing the hole area 50 and the second encapsulation film near the hole area 50; and curing the film to form a second encapsulation layer 82, such as... Figure 14a and Figure 14b As shown, Figure 14a and Figure 14b for Figure 2 Sectional view along the AA direction.

[0185] In an exemplary embodiment, the second encapsulation layer 82 is disposed on the first encapsulation layer 81 outside the hole region 50 and completely fills the partition groove 60, forming an inorganic material that encapsulates the partition structure. The second encapsulation layer 82 in the hole region 50 is removed, exposing the transition hole H1, and the second encapsulation layer 82 in the area near the hole region is removed, exposing the surface of the first encapsulation layer 81.

[0186] In an exemplary embodiment, the second encapsulation layer pattern can be formed using an inkjet printing + coating process. First, an inkjet printing process is used to form a first organic material layer in the pixel area, and then a coating process is used to form a second organic material layer in the isolation area. The second organic material layer covers the outer surface of the partition structure and fills the partition groove. In an exemplary embodiment, the materials of the first organic material layer and the second organic material layer can be the same or different.

[0187] (10) Forming a third encapsulation layer pattern. In an exemplary embodiment, forming the third encapsulation layer pattern may include: depositing a third encapsulation film on the substrate on which the aforementioned pattern is formed to form a third encapsulation layer 83, such as... Figure 15a and Figure 15b As shown, Figure 15a and Figure 15b for Figure 2 Sectional view along the AA direction.

[0188] In an exemplary embodiment, the third encapsulation layer 83 can be deposited using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). In areas other than the aperture region 50, the third encapsulation layer 83 is disposed on the second encapsulation layer 82. In the aperture region 50, the third encapsulation layer 83 covers the inner wall of the transition aperture H1, forming a complete encapsulation of the transition aperture H1.

[0189] In one exemplary embodiment, the third encapsulation layer 83 covering the inner wall of the transition hole H1 means that the third encapsulation layer 83 covers: the inner sidewall of the encapsulation hole, the inner sidewall of the cathode block hole, the inner sidewall of the light-emitting block hole, the inner sidewall of the flat hole, and the inner sidewall and bottom of the insulating hole, such as... Figure 15a As shown. In another exemplary embodiment, the third encapsulation layer 83 covering the inner wall of the transition hole H1 means that the third encapsulation layer 83 covers: the inner wall of the encapsulation hole, the inner wall of the cathode block hole, the inner wall of the light-emitting block hole, the inner wall of the flat hole, the inner wall of the insulating hole, the inner wall of the transition base hole, and the bottom of the transition base hole, as shown. Figure 15b As shown. In this way, the inner walls of both the inorganic and organic materials in the transition hole H1 are covered by the third encapsulation layer 83 of the inorganic material, effectively isolating water and oxygen from the hole area.

[0190] At this point, the encapsulation structure layer is complete. In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer 81, a second encapsulation layer 82, and a third encapsulation layer 83 stacked together. The first and third encapsulation layers may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers, ensuring that external water and oxygen cannot enter the light-emitting structure layer. The second encapsulation layer may be made of resin material, serving to encapsulate each film layer of the display substrate to improve structural stability and flatness. Outside the hole region 50, the encapsulation layer forms a stacked structure of inorganic / organic / inorganic materials. In the hole region 50, the third encapsulation layer (encapsulation material layer) in the encapsulation structure layer completely covers the inner wall of the transition hole H1, ensuring encapsulation integrity and effectively isolating water and oxygen from the hole region and the outside world.

[0191] (11) Forming a stretched hole pattern. In an exemplary embodiment, forming a stretched hole pattern may include: etching the transition hole H1 on the substrate on which the aforementioned pattern is formed using a patterning process to form a stretched hole H2 pattern, such as... Figure 16a , Figure 16b , Figure 16c and Figure 16d As shown, Figure 16a , Figure 16b , Figure 16c and Figure 16d All Figure 2 Sectional view along the AA direction.

[0192] In an exemplary embodiment, the etching process for the stretched hole H2 is essentially performed along the outer surface of the third encapsulation layer 83 covering the transition hole H1. First, the third encapsulation layer 83 at the bottom of the transition hole H1 is etched away to form the third encapsulation hole. Then, the substrate 10 is etched to form the base hole. The base hole, the third encapsulation hole, and the transition hole together form the stretched hole H2. In this exemplary embodiment, forming the stretched hole through the etching process can be understood as creating the third encapsulation hole on the third encapsulation layer and creating the base hole on the substrate. The transition hole, the third encapsulation hole, and the base hole are interconnected. The inner walls of the transition hole, the third encapsulation hole, and the base hole are substantially flush. The orthographic projections of the inner wall of the transition hole, the inner wall of the third encapsulation hole, and the inner wall of the base hole onto the substrate substantially overlap.

[0193] The etched hole H2 formed in this way can include a base material segment not covered by the encapsulation material layer (third encapsulation layer 83) and an encapsulation material segment covered by the encapsulation material layer. The encapsulation material segment is located on the side of the base hole closer to the structural hole, that is, the base material segment is located on the side of the encapsulation material segment closer to the glass substrate 1. This makes the peeling interface between the display substrate and the glass substrate only the base material, effectively avoiding the situation where the display substrate cannot be separated from the glass substrate in the subsequent peeling process, avoiding the occurrence of pulling cracks during the peeling process, and effectively ensuring the encapsulation effect of the display substrate.

[0194] In an exemplary embodiment, the stretch hole can be a blind hole, meaning that the substrate inside the stretch hole is partially removed, and the bottom of the stretch hole exposes the surface of the substrate, such as... Figure 16a and Figure 16b As shown. In one exemplary embodiment, the third encapsulation layer 83 only covers the inner walls of the first encapsulation hole, the cathode block hole, the light-emitting block hole, and the structural hole. The inner walls of the substrate holes are all segments of substrate material not covered by the third encapsulation layer 83, such as... Figure 16a As shown. In another exemplary embodiment, the third encapsulation layer 83 not only covers the inner walls of the first encapsulation hole, the cathode block hole, the light-emitting block hole, and the structural hole, but also covers part of the inner wall of the substrate hole. The inner wall of the substrate hole includes an encapsulation material segment covered by the third encapsulation layer 83 and a substrate material segment not covered by the third encapsulation layer 83. The encapsulation material segment is located on the side of the substrate material segment closer to the structural layer, such as... Figure 16b As shown.

[0195] In an exemplary embodiment, the stretch hole can be a through hole, meaning that the substrate inside the stretch hole is completely removed, and the bottom of the stretch hole exposes the surface of the stripped substrate, such as... Figure 16c and Figure 16d As shown. In one exemplary embodiment, the third encapsulation layer 83 only covers the inner walls of the first encapsulation hole, the cathode block hole, the light-emitting block hole, and the structural hole. The inner walls of the substrate holes are all segments of substrate material not covered by the third encapsulation layer 83, such as... Figure 16c As shown. In another exemplary embodiment, the third encapsulation layer 83 not only covers the inner walls of the first encapsulation hole, the cathode block hole, the light-emitting block hole, and the structural hole, but also covers part of the inner wall of the substrate hole. The inner wall of the substrate hole includes an encapsulation material segment covered by the third encapsulation layer 83 and a substrate material segment not covered by the third encapsulation layer 83. The encapsulation material segment is located on the side of the substrate material segment closer to the structural layer, such as... Figure 16d As shown.

[0196] In an exemplary embodiment, the opening size of the base hole is smaller than the opening size of the structural hole, and the orthographic projection of the opening profile of the base hole onto the base is within the range of the orthographic projection of the opening profile of the structural hole onto the base.

[0197] Alternatively, the inner wall of the base hole may include a base material segment covered by the encapsulation material layer and an encapsulation material segment not covered by the encapsulation material layer, with the encapsulation material segment located on the side of the base material segment closest to the structural hole.

[0198] In an exemplary embodiment, the width of the stretch hole can be approximately 5 μm to 15 μm in a plane parallel to the display substrate.

[0199] In an exemplary embodiment, after the encapsulation structure layer is prepared, a touch structure layer (TSP) can be formed on the encapsulation structure layer. The touch structure layer may include a touch electrode layer, or may include a touch electrode layer and a touch insulating layer, which is not limited herein.

[0200] In subsequent processes, the display substrate can be separated from the glass substrate by laser lift-off process, followed by processes such as attaching a back film and cutting, which are not limited in this disclosure.

[0201] In a display substrate with stretch holes, there is a problem where the film layer cannot be effectively peeled off during the stripping process, leading to encapsulation failure. Research has found that the ineffective peeling of the film layer during stripping is partly due to the presence of residual inorganic encapsulation layers within the stretch holes. Current hole etching processes often fail to completely etch away the structural layers within the hole area, especially inorganic encapsulation layers directly deposited on the glass substrate. This results in some inorganic encapsulation layer remaining at the bottom of the hole area, adhering to the glass substrate. When this residual inorganic encapsulation layer remains at the bottom of the hole area, the strong adhesion between the inorganic encapsulation layer and the glass substrate prevents some of the inorganic encapsulation layer from separating from the glass substrate during the stripping process. The residual inorganic encapsulation layer on the glass substrate causes tensile cracks in the encapsulation layer, ultimately leading to encapsulation failure.

[0202] As can be seen from the structure and fabrication process of the display substrate in the exemplary embodiments of this disclosure, the exemplary embodiments of this disclosure form a transition hole after forming a first encapsulation layer, and then form a stretching hole after covering the inner wall of the transition hole with a third encapsulation layer. A base material segment not covered by the encapsulation material layer is formed in the base hole within the stretching hole, ensuring that the peeling interface between the display substrate and the glass substrate consists only of the base material and no inorganic material. Since the base material can be separated from the glass substrate without damage, the situation where the film layer of the display substrate cannot be separated from the glass substrate is avoided, and pulling cracks during the peeling process are prevented, effectively ensuring the encapsulation reliability of the display substrate. The exemplary embodiments of this disclosure, by setting a partition structure around the partition area of ​​the stretching hole and having the encapsulation structure layer wrap the partition structure, maximize the isolation of water and oxygen from the hole area, improving the encapsulation effect. The fabrication process of the display substrate in the exemplary embodiments of this disclosure has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0203] The structure of the display substrate and its fabrication process as described in this exemplary embodiment are merely illustrative. In the exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased as needed. For example, multiple sequentially nested partition structures can be provided outside the hole area, which is not limited herein.

[0204] This disclosure also provides a method for fabricating a display substrate, the display substrate including a pixel region and a stretched hole region, the pixel region including at least one sub-pixel, and the stretched hole region including at least one hole region and a partition region surrounding the hole region. In an exemplary embodiment, the fabrication method may include:

[0205] A substrate is formed, a structural layer disposed on the substrate and an encapsulation structural layer disposed on the structural layer, wherein the partition region includes at least one partition structure surrounding the aperture region;

[0206] A stretching hole is formed in the hole region. The stretching hole includes a base hole disposed on the substrate and a structural hole penetrating the structural layer. The base hole and the structural hole are connected. At least a portion of the inner wall of the structural hole is covered by at least one encapsulation material layer in the encapsulation structural layer. The inner wall of the base hole includes a segment of substrate material not covered by the encapsulation material layer.

[0207] In an exemplary embodiment, the inner wall of the substrate hole further includes a segment of encapsulation material covered by the encapsulation material layer, the segment of encapsulation material being located on the side of the substrate material segment closer to the structural hole.

[0208] In an exemplary embodiment, the base hole includes a through hole penetrating the base, or a blind hole not penetrating the base.

[0209] In an exemplary embodiment, forming a tension hole in the hole region may include:

[0210] A packaging structure layer and a transition hole are formed; the packaging structure layer includes a first packaging layer, a second packaging layer and a third packaging layer as the packaging material layer; the transition hole is located in the hole area, the first packaging layer and the structure layer in the transition hole are removed, and the third packaging layer covers the inner wall of the transition hole;

[0211] The transition hole is etched to form a stretched hole; the stretched hole includes the transition hole and a base hole disposed on the substrate, the base hole and the transition hole are connected, and the inner wall of the base hole includes a segment of substrate material not covered by the third encapsulation layer.

[0212] In an exemplary embodiment, the materials of the first and third encapsulation layers include inorganic materials, and the material of the second encapsulation layer includes organic materials; forming the encapsulation structure layer and the transition hole may include:

[0213] A first encapsulation layer is formed, which covers the structural layer and the partition structure;

[0214] A transition hole is formed in the hole area by a patterning process, and the first encapsulation layer and structural layer in the transition hole are removed;

[0215] A second encapsulation layer is formed, wherein the second encapsulation layer is disposed on the side of the first encapsulation layer in the pixel area and the partition area away from the substrate; or, the first organic material layer in the second encapsulation layer is disposed on the side of the first encapsulation layer in the pixel area away from the substrate, and the second organic material layer in the second encapsulation layer is disposed on the side of the first encapsulation layer in the partition area away from the substrate.

[0216] A third encapsulation layer is formed as the encapsulation material layer, the third encapsulation layer is disposed on the side of the second encapsulation layer away from the substrate, and the third encapsulation layer covers the inner wall of the transition hole.

[0217] This disclosure provides a method for fabricating a display substrate. By forming a substrate material segment not covered by the encapsulation material layer in the substrate hole of the stretching hole, the peeling interface between the display substrate and the glass substrate consists only of the substrate material. This avoids the situation where the film layer of the display substrate cannot separate from the glass substrate, and prevents pulling cracks during the peeling process, effectively ensuring the encapsulation effect of the display substrate. The display substrate fabrication method of this disclosure has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0218] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0219] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, The display substrate includes a pixel region and a stretched hole region. The pixel region includes at least one sub-pixel, and the stretched hole region includes at least one hole region and a partition region surrounding the hole region. The display substrate includes a substrate, a structural layer disposed on the substrate, and an encapsulation structural layer disposed on the side of the structural layer away from the substrate. The partition region includes at least one partition structure surrounding the hole region. The hole region includes a base hole disposed on the substrate and a structural hole penetrating the structural layer. The base hole and the structural hole are connected. At least a portion of the inner wall of the structural hole is covered by at least one encapsulation material layer in the encapsulation structural layer. The inner wall of the base hole includes a segment of substrate material not covered by the encapsulation material layer. The orthographic projection of the end of the structural hole near the base hole on the plane of the base is located within the orthographic projection of the end of the base hole near the structural hole on the plane of the base. There is a gap between the boundary of the orthographic projection of the end of the structural hole near the base hole on the plane of the base and the boundary of the orthographic projection of the end of the base hole near the structural hole on the plane of the base. The portion of the structural hole near the base hole and the portion of the base hole near the structural hole form a step, and the step is covered by the encapsulation structure layer.

2. The display substrate according to claim 1, characterized in that, The inner wall of the base hole also includes a segment of encapsulation material covered by the encapsulation material layer, the segment of encapsulation material being located on the side of the base material segment closer to the structural hole.

3. The display substrate according to claim 1, characterized in that, The base hole includes a through hole that penetrates the base, or a blind hole that does not penetrate the base.

4. The display substrate according to claim 1, characterized in that, The partition structure includes a first partition layer and a second partition layer disposed on the side of the first partition layer away from the substrate. The first partition layer has a first partition hole surrounding the hole area, and the second partition layer has a second partition hole surrounding the hole area. The second partition hole and the first partition hole communicate to form a partition groove. The second partition layer located around the second partition hole has a protrusion relative to the sidewall of the first partition hole, and the protrusion and the sidewall of the first partition hole form an indented structure.

5. The display substrate according to claim 1, characterized in that, The partition structure is disposed between the structural layer and the encapsulation structural layer.

6. The display substrate according to any one of claims 1 to 5, characterized in that, The encapsulation structure layer includes a first encapsulation layer, which covers the structure layer and the partition structure. An encapsulation hole is provided on the first encapsulation layer in the hole area, and the encapsulation hole communicates with the structure hole.

7. The display substrate according to claim 6, characterized in that, The orthographic projection of the inner wall of the encapsulation hole onto the substrate substantially overlaps with the orthographic projection of the inner wall of the structural hole onto the substrate.

8. The display substrate according to claim 6, characterized in that, The encapsulation structure layer further includes a second encapsulation layer; the second encapsulation layer is disposed on the side of the first encapsulation layer in the pixel area away from the substrate, or the second encapsulation layer is disposed on the side of the first encapsulation layer in the pixel area and the partition area away from the substrate.

9. The display substrate according to claim 8, characterized in that, The encapsulation structure layer further includes a third encapsulation layer as the encapsulation material layer; the third encapsulation layer is disposed on the side of the second encapsulation layer away from the substrate, the third encapsulation layer covers the inner wall of the structural hole and the encapsulation hole, and the third encapsulation layer does not cover the substrate material segment of the substrate hole.

10. The display substrate according to claim 9, characterized in that, The third encapsulation layer covers part of the inner wall of the base hole, forming an encapsulation material segment covered by the third encapsulation layer within the base hole.

11. The display substrate according to claim 9, characterized in that, A light-emitting block is provided on the side of the structural layer of the hole area away from the substrate. The light-emitting block has a light-emitting hole that communicates with the structural hole. The third encapsulation layer covers the inner wall of the light-emitting hole.

12. The display substrate according to claim 11, characterized in that, A cathode block is disposed on the side of the light-emitting block away from the substrate in the aperture area. The first encapsulation layer is disposed on the side of the cathode block away from the substrate. A cathode block hole is disposed on the cathode block. The cathode block hole communicates with the light-emitting block hole and the encapsulation hole. The third encapsulation layer covers the inner wall of the cathode block hole.

13. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 12.

14. A method for preparing a display substrate, characterized in that, The display substrate includes a pixel region and a stretched hole region, the pixel region including at least one sub-pixel, and the stretched hole region including at least one hole region and a partition region surrounding the hole region; the fabrication method includes: A substrate is formed, a structural layer disposed on the substrate and an encapsulation structural layer disposed on the structural layer, wherein the partition region includes at least one partition structure surrounding the aperture region; A stretching hole is formed in the hole area. The stretching hole includes a base hole disposed on the substrate and a structural hole penetrating the structural layer. The base hole and the structural hole are connected. At least a portion of the inner wall of the structural hole is covered by at least one encapsulation material layer in the encapsulation structural layer. The inner wall of the base hole includes a segment of substrate material not covered by the encapsulation material layer. The orthographic projection of the end of the structural hole near the base hole on the plane where the substrate is located is located within the orthographic projection of the end of the base hole near the structural hole on the plane where the substrate is located. There is a gap between the boundary of the orthographic projection of the end of the structural hole near the base hole on the plane where the substrate is located and the boundary of the orthographic projection of the end of the base hole near the structural hole on the plane where the substrate is located. The portion of the structural hole near the base hole and the portion of the base hole near the structural hole form a step, and the step is covered by the encapsulation structural layer.

15. The preparation method according to claim 14, characterized in that, The inner wall of the base hole also includes a segment of encapsulation material covered by the encapsulation material layer, the segment of encapsulation material being located on the side of the base material segment closer to the structural hole.

16. The preparation method according to claim 14, characterized in that, The base hole includes a through hole that penetrates the base, or a blind hole that does not penetrate the base.

17. The preparation method according to any one of claims 14 to 16, wherein a stretched hole is formed in the hole region, comprising: A packaging structure layer and a transition hole are formed; the packaging structure layer includes a first packaging layer, a second packaging layer and a third packaging layer as the packaging material layer; The transition hole is located in the hole area, the first encapsulation layer and the structural layer in the transition hole are removed, and the third encapsulation layer covers the inner wall of the transition hole; The transition hole is etched to form a stretched hole; the stretched hole includes the transition hole and a base hole disposed on the substrate, the base hole and the transition hole are connected, and the inner wall of the base hole includes a segment of substrate material not covered by the third encapsulation layer.

18. The preparation method according to claim 17, characterized in that, The materials of the first and third encapsulation layers include inorganic materials, and the material of the second encapsulation layer includes organic materials; Forming the encapsulation structure layer and transition vias, including: A first encapsulation layer is formed, which covers the structural layer and the partition structure; A transition hole is formed in the hole area by a patterning process, and the first encapsulation layer and structural layer in the transition hole are removed; A second encapsulation layer is formed, wherein the second encapsulation layer is disposed on the side of the first encapsulation layer in the pixel area and the partition area away from the substrate; or, the first organic material layer in the second encapsulation layer is disposed on the side of the first encapsulation layer in the pixel area away from the substrate, and the second organic material layer in the second encapsulation layer is disposed on the side of the first encapsulation layer in the partition area away from the substrate. A third encapsulation layer is formed as the encapsulation material layer, the third encapsulation layer is disposed on the side of the second encapsulation layer away from the substrate, and the third encapsulation layer covers the inner wall of the transition hole.

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