Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device, which comprise a display area and a non-display area, the non-display area is located at the periphery of the display area, comprises adjacent side non-display areas and a bottom non-display area, the side non-display areas are arranged along a first direction with the display area, the bottom non-display area is arranged along a second direction with the display area, the first direction intersects with the second direction; a substrate; a plurality of cascaded shift registers located in the side non-display area; a first binding pad located in the bottom non-display area; a plurality of input signal lines, the first end of the input signal line is electrically connected with the input end of the shift register, the second end of the input signal line is electrically connected with the first binding pad, and the input signal line comprises a first connecting part and a second connecting part connected with each other; the first connecting part is located in the side non-display area and is directly electrically connected with the input end of the shift register, and the second connecting part is located in the display area. The application provides an array substrate, a display panel and a display device, so as to realize narrow frame and improve screen ratio.

Description

TECHNICAL FIELD

[0001] The present application relates to the display technical field, especially to an array substrate, a display panel and a display device. BACKGROUND

[0002] In the prior art display panel technology, there are mainly two mainstream technologies, i.e. liquid crystal display panel and organic self-luminous display panel. The liquid crystal display panel forms an electric field capable of controlling the deflection of liquid crystal molecules by applying a voltage on the pixel electrode and the common electrode in the display panel, thereby controlling the light transmission to realize the display function of the display panel. The organic self-luminous display panel adopts organic electroluminescent material. When an electric current passes through the organic electroluminescent material, the light-emitting material will emit light, thereby realizing the display function of the display panel.

[0003] With the application of display technology in smart wear and other portable electronic devices, the design of electronic products is constantly pursuing the smooth use experience of users, and at the same time, the sensory experience of users is also increasingly pursued. For example, wide viewing angle, high resolution, narrow frame, high screen ratio and other performances have become the selling points of various electronic products. SUMMARY

[0004] The present application provides an array substrate, a display panel and a display device to realize a narrow frame and improve the screen ratio.

[0005] In a first aspect, an array substrate is provided, comprising a display area and a non-display area, the non-display area is located at the periphery of the display area, comprising adjacent side non-display areas and a bottom non-display area, the side non-display areas are arranged along a first direction with the display area, the bottom non-display area is arranged along a second direction with the display area, and the first direction intersects the second direction.

[0006] a substrate;

[0007] a plurality of cascaded shift registers located in the side non-display area;

[0008] a first binding pad located in the bottom non-display area;

[0009] a plurality of input signal lines, a first end of the input signal line is electrically connected with the input end of the shift register, a second end of the input signal line is electrically connected with the first binding pad, and the input signal line comprises a first connecting part and a second connecting part connected with each other; the first connecting part is located in the side non-display area and is directly electrically connected with the input end of the shift register, and the second connecting part is located in the display area.

[0010] In a second aspect, a display panel is provided, comprising the array substrate of the first aspect and a pixel electrode.

[0011] The pixel electrode is located on the side of the second connecting portion away from the substrate in the direction perpendicular to the substrate.

[0012] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel of the second aspect.

[0013] In the array substrate provided by the embodiment of the present application, the second connecting portion in the input signal line is located in the display area, and the second connecting portion in the input signal line does not need to occupy the space of the non-display area, so that the layout path of the input signal line can reduce the frame and improve the screen-to-body ratio. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 A top view structural schematic diagram of an array substrate provided by the embodiment of the present application is shown in FIG. 1.

[0015] Figure 2 A top view structural schematic diagram of an array substrate provided by the embodiment of the present application is shown in FIG. 1. Figure 1 An enlarged schematic diagram of the S1 region in FIG. 1 is shown in FIG. 2.

[0016] Figure 3 A top view structural schematic diagram of another array substrate provided by the embodiment of the present application is shown in FIG. 3.

[0017] Figure 4 A top view structural schematic diagram of another array substrate provided by the embodiment of the present application is shown in FIG. 3. Figure 3 An enlarged schematic diagram of the S2 region in FIG. 3 is shown in FIG. 4.

[0018] Figure 5 A sectional structural schematic diagram along AA' in FIG. 3 is shown in FIG. 5. Figure 4

[0019] A sectional structural schematic diagram of another array substrate provided by the embodiment of the present application is shown in FIG. 6. Figure 6

[0020] A top view structural schematic diagram of another array substrate provided by the embodiment of the present application is shown in FIG. 7. Figure 7

[0021] A top view structural schematic diagram of another array substrate provided by the embodiment of the present application is shown in FIG. 7. Figure 8 Figure 7 An enlarged schematic diagram of the S3 region in FIG. 7 is shown in FIG. 8.

[0022] Figure 9 A sectional structural schematic diagram along BB' in FIG. 7 is shown in FIG. 9. Figure 8

[0023] A sectional structural schematic diagram of another array substrate provided by the embodiment of the present application is shown in FIG. 10. Figure 10

[0024] A top view structural schematic diagram of another array substrate provided by the embodiment of the present application is shown in FIG. 11. Figure 11

[0025] A top view structural schematic diagram of another array substrate provided by the embodiment of the present application is shown in FIG. 11. Figure 12 ​Another schematic view of a cross section of an array substrate according to an embodiment of the present application is provided.

[0026] Figure 13 Another schematic view of a top structure of an array substrate according to an embodiment of the present application is provided.

[0027] Figure 14 Another schematic view of a top structure of an array substrate according to an embodiment of the present application is provided.

[0028] Figure 15 Another schematic view of a top structure of an array substrate according to an embodiment of the present application is provided.

[0029] Figure 16 Another schematic view of a top structure of an array substrate according to an embodiment of the present application is provided.

[0030] Figure 17 A schematic view of a cross section of a display panel according to an embodiment of the present application is provided.

[0031] Figure 18 A schematic view of a display device according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0032] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, rather than all the structures.

[0033] Figure 1 A schematic view of a top structure of an array substrate according to an embodiment of the present application is provided, Figure 2 A schematic view of a top structure of an array substrate according to an embodiment of the present application is provided, Figure 1 A schematic view of a top structure of an array substrate according to an embodiment of the present application is provided, Figure 1 A schematic view of a top structure of an array substrate according to an embodiment of the present application is provided, Figure 2 The array substrate includes a display area 100 and a non-display area 200. The non-display area 200 is located at the periphery of the display area 100, and the non-display area 200 includes adjacent side non-display areas 210 and a bottom non-display area 220. The side non-display areas 210 are arranged along a first direction with the display area 100. The side non-display areas 210 are located at one side of the display area 100 along the first direction. The bottom non-display area 220 is arranged along a second direction with the display area 100, and the bottom non-display area 220 is located at one side of the display area 100 along the second direction. The first direction intersects the second direction.

[0034] The array substrate comprises a substrate 310, a plurality of cascaded shift registers 320, a first binding pad 331 and a plurality of input signal lines 40. The plurality of cascaded shift registers 320 are located on one side of the substrate 310. The plurality of cascaded shift registers 320 are located on the side non-display area 210. The first binding pad 331 is located on the bottom non-display area 220. The first end of the input signal line 40 is electrically connected with the input end of the shift register 320, the second end of the input signal line 40 is electrically connected with the first binding pad 331, the input signal line 40 connects the input end of the shift register 320 with the first binding pad 331, and is used for transmitting the signal of the first binding pad 331 to the input end of the shift register 320.

[0035] Exemplarily, the first binding pad 331 can be electrically connected with a driving chip or a flexible circuit board provided with the driving chip, so as to receive the signal from the driving chip and transmit the signal to the input end of the shift register 320 through the input signal line 40, and drive the shift register 320 to work.

[0036] The input signal line 40 comprises a first connecting part 41 and a second connecting part 42 connected with each other. The first connecting part 41 is located on the side non-display area 210, the first connecting part 41 is directly electrically connected with the input end of the shift register 320, and the second connecting part 42 is located on the display area 100.

[0037] In the array substrate provided by the embodiment of the present application, the second connecting part 42 in the input signal line 40 is located on the display area 100, the second connecting part 42 in the input signal line 40 does not need to occupy the space of the non-display area 200, so that the layout path of the input signal line 40 can reduce the frame and improve the screen-to-body ratio.

[0038] Exemplarily, referring to Figure 1 and Figure 2 , the input signal line 40 comprises a third connecting part 43, the first end of the third connecting part 43 is electrically connected with the second connecting part 42, and the second end of the third connecting part 43 is electrically connected with the first binding pad 331. The third connecting part 43 is located on the bottom non-display area 220.

[0039] Optionally, referring to Figure 1 and Figure 2The display area 100 includes a non-right-angle corner 51, and the side non-display area 210 includes a chamfered area 510, which is adjacent to the non-right-angle corner 51. The chamfered area 510 is located on the periphery of the non-right-angle corner 51. The connection point between the first connecting part 41 and the second connecting part 42 is located in the chamfered area 510. This avoids the situation where the connection point between the first connecting part 41 and the second connecting part 42 is located in the display area 100, and the connection point between the first connecting part 41 and the second connecting part 42 does not occupy space in the display area 100. On the other hand, the space in the chamfered area 510 is relatively small. If the input signal line 40 is placed in the chamfered area 510, that is, the input signal line 40 is placed in the chamfered area 510, but the input signal line 40 does not include the portion located in the display area 100, then the input signal line 40 occupies the space in the chamfered area 510. If other components need to be placed there, only a relatively large border can be set. In this embodiment of the invention, by routing the input signal line 40 around the display area 100, the space occupied by the input signal line 40 in the chamfered area 510 is reduced, thereby reducing the bezel size.

[0040] In one embodiment, the connection point between the first connecting portion 41 and the second connecting portion 42 is located in the display area 100.

[0041] In one embodiment, the display area 100 may also be rectangular in shape, and the display area 100 may include right-angled corners.

[0042] Figure 3 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 4 for Figure 3 Enlarged schematic diagram of region S2 in the middle. Figure 5 For along Figure 4 A schematic diagram of the cross-sectional structure of AA' is shown in the reference diagram. Figures 3-5 The array substrate includes multiple data lines 62 and pixel driving circuitry. Figure 3 (Not shown in the image). Data lines 62 and pixel driving circuitry are both located in display area 100. Multiple data lines 62 extend along a second direction and are arranged along a first direction. Data lines 62 are used for pixel units ( Figure 3 (Not shown in the image) provides data signals. The pixel driving circuit is used to drive the pixel unit to emit light for display. Perpendicular to the substrate 310, the data line 62 is located on the side of the pixel driving circuit 63 away from the substrate 310, and the second connection portion 42 is located on the side of the film layer containing the data line 62 away from the substrate 310. In this embodiment of the invention, the second connection portion 42 is located on the side of the pixel driving circuit 63 and the data line 62 away from the substrate 310. The second connection portion 42 is made of a metal layer other than the pixel driving circuit 63 and the data line 62, so that the second connection portion 42 will not form unwanted electrical connections with the pixel driving circuit 63 and the data line 62.

[0043] Exemplarily, referring to Figures 3-5 The array substrate includes a plurality of scan lines 61 extending along a first direction and arranged along a second direction, located in the display area 100, for providing a scan signal. The plurality of scan lines 61 cross the plurality of data lines 62 to define a plurality of pixel units. The output end of the shift register 320 is electrically connected with the scan line 61 for providing the scan signal to the scan line 61. In other embodiments, the array substrate can further include a light-emitting control signal line, and the output end of the shift register 320 is electrically connected with the light-emitting control signal line for providing a light-emitting control signal to the light-emitting control signal line.

[0044] Exemplarily, referring to Figure 5 The pixel driving circuit 63 includes a thin film transistor 64 including a source electrode 641, a semiconductor layer 642, a gate electrode 643 and a drain electrode 644. The source electrode 641 of the thin film transistor 64 and the drain electrode 644 of the thin film transistor 64 are in the same layer and are located on the side of the gate electrode 643 away from the substrate 310. The film layer where the data line 62 is located is located on the side of the film layer where the source electrode 641 and the drain electrode 644 of the thin film transistor 64 are located away from the substrate 310. The second connection part 42 is located on the side of the film layer where the data line 62 is located away from the substrate 310.

[0045] Exemplarily, referring to Figure 5 The gate electrode 643 of the thin film transistor 64 is located in the first metal layer, the source electrode 641 and the drain electrode 644 of the thin film transistor 64 are located in the second metal layer, the data line 62 is located in the third metal layer, and the second connection part 42 is located in the fourth metal layer. The first metal layer, the second metal layer, the third metal layer and the fourth metal layer are arranged in sequence along the direction away from the substrate 310.

[0046] Exemplarily, referring to Figures 3-5 The first connection part 41 is in the same layer as the source electrode 641 and the drain electrode 644 of the thin film transistor 64, so that the first connection part 41, the source electrode 641 of the thin film transistor 64 and the drain electrode 644 of the thin film transistor 64 can be formed by using the same material and in the same process, thereby saving the process. The first connection part 41 is located in the second metal layer, the second connection part 42 is located in the fourth metal layer, the first connection part 41 and the second connection part 42 are in different layers, and the first connection part 41 and the second connection part 42 are electrically connected through the first connection via hole 71. The first connection via hole 71 is the connection point of the first connection part 41 and the second connection part 42.

[0047] Figure 6 Another cross-sectional structure diagram of an array substrate provided by an embodiment of the present application is shown in FIG. 6. Referring to Figure 6The first connecting part 41 is in the same layer with the data line 62, so that the first connecting part 41 and the data line 62 can be formed by using the same material and in the same process, thereby saving the process procedure. The first connecting part 41 is in the third metal layer, the second connecting part 42 is in the fourth metal layer, the first connecting part 41 and the second connecting part 42 are in different layers, and the first connecting part 41 and the second connecting part 42 are electrically connected through the first connecting via 71.

[0048] Figure 7 Another schematic top view of an array substrate, Figure 8 For Figure 7 An enlarged schematic view of the S3 region in the array substrate, Figure 9 An enlarged schematic view of the S3 region in the array substrate, Figure 8 A schematic view of the cross-sectional structure of BB', referring to Figures 7-9 The array substrate further includes a second binding pad 332 and a data lead-out line 80. The second binding pad 332 is located in the bottom non-display area 220. A first end of the data lead-out line 80 is electrically connected with the data line 62, and a second end of the data lead-out line 80 is electrically connected with the second binding pad 332. The data lead-out line 80 connects the data line 62 and the second binding pad 332, and is used for transmitting a signal of the second binding pad 332 to the data line 62. The second connecting part 42 is arranged in the same layer with the data lead-out line 80, so that the second connecting part 42 and the data lead-out line 80 can be formed by using the same material and in the same process, thereby saving the process procedure. It should be noted that the data lead-out line 80 is arranged in the display area 100, and the data line 62 is led out to the second binding pad 332 in the bottom non-display area 220, so that the fan-out wiring does not need to be arranged in the bottom non-display area 220, the space of the bottom non-display area 220 is reduced, and the frame is reduced. On this basis, the second connecting part 42 is formed by using the metal in the same layer with the data lead-out line 80, without increasing the additional metal layer and the manufacturing process on the array substrate, and the frame is reduced and the screen-to-body ratio is improved.

[0049] Exemplarily, the second binding pad 332 can be electrically connected with a driving chip or a flexible circuit board provided with the driving chip, so as to receive a signal from the driving chip and transmit the signal to the data line 62 through the data lead-out line 80, thereby providing the data signal for the data line 62.

[0050] Optionally, referring to Figures 7-9The second connecting portion 42 is located between the data lead-out line 80 and the non-display region 200. In the first direction, or the reverse direction of the first direction, the data lead-out line 80 is closer to the central axis of the display region 100, the second connecting portion 42 is farther from the central axis of the display region 100, and the distance between the data lead-out line 80 and the central axis of the display region 100 is less than the distance between the second connecting portion 42 and the central axis of the display region 100. The central axis of the display region 100 is parallel to the second direction, and the display region 100 is symmetrical about the central axis of the display region 100. In the embodiment of the present application, since the shift register 320 is located at the periphery of the data line 62, correspondingly, the second connecting portion 42 is arranged at the periphery of the data lead-out line 80 to avoid the intersection of the second connecting portion 42 and the data lead-out line 80 in the same layer.

[0051] Exemplarily, referring to Figure 9 , the data line 62 is located in the third metal layer, the data lead-out line 80 is located in the fourth metal layer, the data line 62 and the data lead-out line 80 are in different layers, and the data line 62 and the data lead-out line 80 are electrically connected through the second connecting via 72. The second connecting via 72 is located in the display region 100. In other embodiments, the second connecting via 72 can also be located in the non-display region 200.

[0052] Figure 10 Another schematic diagram of the cross-sectional structure of the array substrate provided by the embodiment of the present application is provided, referring to Figure 10 The input signal line 40 includes a power signal line. Correspondingly, the first connecting portion 41 includes a first power signal portion 411 and a second power signal portion 412 which are stacked and electrically connected. The first power signal portion 411 and the second power signal portion 412 are electrically connected with at least one second connecting portion 42. Figure 10 In the embodiment of the present application, the first connecting portion 41 includes the first power signal portion 411 and the second power signal portion 412 which are stacked and electrically connected, and the first power signal portion 411 and the second power signal portion 412 are connected in parallel, which is beneficial to reduce the resistance of the power signal line and reduce the voltage drop on the power signal line.

[0053] Exemplarily, referring to Figure 10 The first power signal portion 411 is in the same layer as the data line 62, and the first power signal portion 411 is located in the third metal layer. The second power signal portion 412 is in the same layer as the source electrode 641 and the drain electrode 644 of the thin film transistor 64, and the second power signal portion 412 is located in the second metal layer. The first power signal portion 411 is located on the side away from the substrate 310 of the second power signal portion 412 and is electrically connected with the second power signal portion 412. The first power signal portion 411 is electrically connected with the second connecting portion 42 through the first connecting via 71.

[0054] Exemplarily, the power signal lines include a high-level power signal line (i.e., VHG) and a low-level power signal line (i.e., VGL).

[0055] Optionally, referring to Figure 8 and Figure 10 The first power signal part 411 and the second power signal part 412 are electrically connected with the same second connection part 42. The line width of the first power signal part 411 and the second power signal part 412 is smaller than the line width of the second connection part 42. That is, the line width of the second connection part 42 is larger than the line width of the first power signal part 411, and the line width of the second connection part 42 is larger than the line width of the second power signal part 412. In the embodiment of the present application, by increasing the line width of the second connection part 42, the resistance of the second connection part 42 is reduced, thereby facilitating the reduction of the resistance of the power signal line and the voltage drop on the power signal line.

[0056] Figure 11 Another schematic top view of the array substrate provided by the embodiment of the present application is shown in FIG. 4, which is combined with reference to Figure 10 and Figure 11 The first connection part 41 includes the first power signal part 411 and the second power signal part 412 which are stacked and electrically connected. The first power signal part 411 is electrically connected with one second connection part 42, and the second power signal part 412 is electrically connected with another second connection part 42. The first power signal part 411 and the second power signal part 412 are electrically connected with two different second connection parts 42. Thus, the two second connection parts 42 in the display area 100 are electrically connected with the same first connection part 41, and the two second connection parts 42 electrically connected with the same first connection part 41 are connected, thereby reducing the resistance of the second connection part 42, facilitating the reduction of the resistance of the power signal line and the voltage drop on the power signal line.

[0057] Exemplarily, referring to Figure 11 The second connection part 42 includes the first connection sub-part 421 and the second connection sub-part 422. The first connection sub-part 421 is electrically connected with the first power signal part 411, and the second connection sub-part 422 is electrically connected with the second power signal part 412. The first connection sub-part 421 and the second connection sub-part 422 are electrically connected with the same first connection part 41.

[0058] Figure 12 Another schematic cross-sectional structure of the array substrate provided by the embodiment of the present application is shown in FIG. 5, which is combined with reference to Figure 12The input signal line 40 includes a clock signal line. The first connection part 41 includes a first clock signal part 413 and a second clock signal part 414 which are stacked and electrically connected. The first clock signal part 413 and the second clock signal part 414 are electrically connected with at least one second connection part 42. In the embodiment, the first connection part 41 includes the first clock signal part 413 and the second clock signal part 414 which are stacked and electrically connected. The first clock signal part 413 and the second clock signal part 414 are connected in parallel, which is beneficial to reduce the resistance of the clock signal line and reduce the voltage drop on the clock signal line.

[0059] Exemplarily, referring to Figure 12 The first clock signal part 413 is in the same layer with the data line 62, and the first clock signal part 413 is located in the third metal layer. The second clock signal part 414 is in the same layer with the source 641 and the drain 644 of the thin film transistor 64, and the second clock signal part 414 is located in the second metal layer. The first clock signal part 413 is located on the side of the second clock signal part 414 which is away from the substrate 310, and is electrically connected with the second clock signal part 414. The first clock signal part 413 is electrically connected with the second connection part 42 through the first connection via hole 71.

[0060] Exemplarily, the clock signal line includes a first clock signal line and a second clock signal line. The first clock signal line and the second clock signal line have opposite timing, that is, when the first clock signal line is high, the second clock signal line is low; when the first clock signal line is low, the second clock signal line is high.

[0061] Exemplarily, in an embodiment, the first clock signal part 413 and the second clock signal part 414 are electrically connected with the same second connection part 42. The line width of the first clock signal part 413 and the second clock signal part 414 is smaller than the line width of the second connection part 42.

[0062] Exemplarily, in another embodiment, the first clock signal part 413 is electrically connected with one second connection part 42, and the second clock signal part 414 is electrically connected with another second connection part 42. The first clock signal part 413 and the second clock signal part 414 are electrically connected with two different second connection parts 42. Thus, the two second connection parts 42 in the display area 100 are electrically connected with the same first connection part 41, the two second connection parts 42 which are electrically connected with the same first connection part 41 are connected, the resistance of the second connection part 42 is reduced, which is beneficial to reduce the resistance of the clock signal line and reduce the voltage drop on the clock signal line.

[0063] Exemplarily, referring to Figure 2The second connecting portion 42 includes a first line segment 91 and a second line segment 92 that are interconnected. The first line segment 91 extends along a first direction, and the second line segment 92 extends along a second direction. The first end of the first line segment 91 is directly electrically connected to the first connecting portion 41, and the second end of the first line segment 91 is directly electrically connected to the second line segment 92. The first end of the second line segment 92 is directly electrically connected to the first line segment 91, and the second end of the second line segment 92 is directly electrically connected to the third connecting portion 43. The second connecting portion 42 is L-shaped.

[0064] Figure 13 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 13 The second connecting portion 42 includes a first line segment 91, a second line segment 92, and a third line segment 93. The second line segment 92 extends along a first direction, while the first line segment 91 and the third line segment 93 extend along a second direction. The first line segment 91 connects the second line segment 92 and the third line segment 93. The first end of the third line segment 93 is directly electrically connected to the first connecting portion 41, and the second end of the third line segment 93 is directly electrically connected to the first line segment 91. The first end of the first line segment 91 is directly electrically connected to the third line segment 93, and the second end of the first line segment 91 is directly electrically connected to the second line segment 92. The first end of the second line segment 92 is directly electrically connected to the first line segment 91, and the second end of the second line segment 92 is directly electrically connected to the third connecting portion 43. The second connecting portion 42 is U-shaped.

[0065] Figure 14 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 14The array substrate includes a gate driving circuit 720 and a light emitting control circuit 710, and the gate driving circuit 720 and the light emitting control circuit 710 each include a plurality of cascaded shift registers 320. The gate driving circuit 720 is located between the light emitting control circuit 710 and the display area 100. The input signal line 40 includes a gate driving input signal line 420 and a light emitting control input signal line 410. The input end of the shift register 320 in the gate driving circuit 720 is electrically connected with the gate driving input signal line 420, and the input end of the shift register 320 in the light emitting control circuit 710 is electrically connected with the light emitting control input signal line 410. The second connection part 42 of the light emitting control input signal line 410 is located between the second connection part 42 of the gate driving input signal line 420 and the non-display area 200. In the first direction or the reverse direction of the first direction, the second connection part 42 of the gate driving input signal line 420 is closer to the central axis of the display area 100, and the second connection part 42 of the light emitting control input signal line 410 is farther away from the central axis of the display area 100. The distance between the second connection part 42 of the gate driving input signal line 420 and the central axis of the display area 100 is less than the distance between the second connection part 42 of the light emitting control input signal line 410 and the central axis of the display area 100. In the embodiment of the application, since the light emitting control circuit 710 is located in the periphery of the gate driving circuit 720, correspondingly, the second connection part 42 of the light emitting control input signal line 410 is located in the periphery of the second connection part 42 of the gate driving input signal line 420, so as to avoid the intersection of each second connection part 42 in the same layer.

[0066] Exemplarily, referring to Figure 1 The side non-display area 210 includes a first side non-display area 211 and a second side non-display area 212, and the first side non-display area 211 and the second side non-display area 212 are opposite to each other and are located at opposite sides of the display area 100 respectively. The shift register 320 is located in the first side non-display area 211. The array substrate adopts a single-side driving mode.

[0067] Exemplarily, referring to Figure 1 The array substrate further includes a top non-display area 230, and the top non-display area 230 is opposite to the bottom non-display area 220 and is located at opposite sides of the display area 100 respectively.

[0068] Figure 15 Another top view structural schematic diagram of an array substrate is provided in the embodiment of the application, referring to Figure 15 The shift register 320 is located in the first side non-display area 211 and the second side non-display area 212. Specifically, a part of the shift registers 320 are located in the first side non-display area 211, and another part of the shift registers 320 are located in the second side non-display area 212. The array substrate adopts a double-side driving mode.

[0069] Exemplarily, referring to Figure 1 , the non-right-angle corner 51 comprises an arc shape. The non-right-angle corner 51 is an arc chamfer. In other embodiments, the non-right-angle corner 51 can also comprise other shapes.

[0070] Figure 16 Another schematic top view of an array substrate is provided for an embodiment of the present application, referring to Figure 16 , the non-right-angle corner 51 comprises a broken line shape. The non-right-angle corner 51 is an oblique chamfer.

[0071] Figure 17 A schematic cross-sectional structure of a display panel is provided for an embodiment of the present application, referring to Figure 17 , the display panel comprises an array substrate and a pixel electrode 700. In a direction perpendicular to the substrate 310, the pixel electrode 700 is located on a side of the second connecting portion 42 away from the substrate 310.

[0072] Exemplarily, referring to Figure 17 , the pixel electrode 700 is electrically connected with the drain 644 of the thin film transistor 64, and by turning on or off the thin film transistor 64, whether to provide voltage and / or current to the pixel electrode 700 is controlled, and when the thin film transistor 64 is turned on, by controlling the voltage and / or current provided to the pixel electrode 700, the luminance of the pixel unit (not shown in the figure) where the pixel electrode 700 is located can be controlled. Figure 17

[0073] Exemplarily, the display panel can comprise an organic light-emitting display panel, and the organic light-emitting display panel can further comprise a light-emitting material layer and other well-known structures, which will not be described here.

[0074] Exemplarily, the display panel can comprise a liquid crystal display panel, and the liquid crystal display panel can further comprise a liquid crystal layer and a color resistance and other well-known structures, which will not be described here.

[0075] Figure 18 A schematic view of a display device is provided for an embodiment of the present application, referring to Figure 18 , the display device comprises the display panel in the above embodiments. The display device can be one of a mobile phone, a computer, an electronic paper, a vehicle-mounted display, a wearable device, etc.

[0076] ​Note that the above merely describes preferred embodiments of the present application and the principles of the technology applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, modifications, combinations and substitutions can be made by those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, It includes a display area and a non-display area. The non-display area is located around the display area and includes adjacent side non-display areas and bottom non-display areas. The side non-display areas are arranged with the display area along a first direction, and the bottom non-display areas are arranged with the display area along a second direction. The first direction and the second direction intersect. Substrate; Multiple cascaded shift registers are located in the side non-display area; The first binding pad is located in the bottom edge non-display area; Multiple input signal lines are provided. The first end of each input signal line is electrically connected to the input terminal of the shift register, and the second end of each input signal line is electrically connected to the first bonding pad. Each input signal line includes a first connecting portion and a second connecting portion that are electrically connected. The first connecting portion is located in the side non-display area and is electrically connected to the input terminal of the shift register. The second connecting portion is located in the display area. The display area includes a non-right-angle corner, and the side non-display area includes a chamfered area, which is adjacent to the non-right-angle corner. The connection point between the first connecting part and the second connecting part is located in the chamfered area.

2. The array substrate according to claim 1, characterized in that, It includes multiple data lines and pixel driving circuits, all located in the display area, with the multiple data lines extending along the second direction and arranged along the first direction; Perpendicular to the substrate, the data line is located on the side of the pixel driving circuit away from the substrate, and the second connection portion is located on the side of the film layer where the data line is located away from the substrate.

3. The array substrate according to claim 2, characterized in that, Also includes: The second binding pad is located in the non-display area at the bottom edge; A data lead-out line, wherein a first end of the data lead-out line is electrically connected to the data line, and a second end of the data lead-out line is electrically connected to the second bonding pad; The second connection part is arranged on the same layer as the data lead-out line.

4. The array substrate according to claim 3, characterized in that, The second connection is located between the data lead and the non-display area.

5. The array substrate according to claim 1, characterized in that, The first connection portion includes a first power signal portion and a second power signal portion that are stacked and electrically connected; The first power signal section and the second power signal section are electrically connected to at least one of the second connection sections.

6. The array substrate according to claim 5, characterized in that, The first power signal section and the second power signal section are electrically connected to the same second connection section, and the line width of the first power signal section and the second power signal section is smaller than the line width of the second connection section.

7. The array substrate according to claim 1, characterized in that, The first connection portion includes a first clock signal portion and a second clock signal portion that are stacked and electrically connected; The first clock signal section and the second clock signal section are electrically connected to at least one of the second connection sections.

8. The array substrate according to claim 1, characterized in that, The second connection portion includes a first line segment and a second line segment that are electrically connected to each other, the first line segment extending along the first direction and the second line segment extending along the second direction.

9. The array substrate according to claim 8, characterized in that, The second connecting portion further includes a third line segment, which extends along the second direction, and the first line segment connects the second line segment and the third line segment.

10. The array substrate according to claim 1, characterized in that, It includes a gate driving circuit and a light-emitting control circuit, both of which include multiple cascaded shift registers, with the gate driving circuit located between the light-emitting control circuit and the display area; The input signal lines include gate drive input signal lines and light emission control input signal lines; In the gate driving circuit, the input terminal of the shift register is electrically connected to the gate driving input signal line, and in the light emission control circuit, the input terminal of the shift register is electrically connected to the light emission control input signal line. The second connection portion of the light emission control input signal line is located between the second connection portion of the gate drive input signal line and the non-display area.

11. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-10, and pixel electrodes; Perpendicular to the substrate, the pixel electrode is located on the side of the second connection portion away from the substrate.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

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