Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a semiconductor element. The semiconductor element has a semiconductor layer (1), a first conductive type layer (2), a saturation current suppression layer (3, 4), a current diffusion layer (6), a base region (7), a source region (8), a trench gate structure, an interlayer insulating film (13), a source electrode (14), a drain electrode (15), and a second deep layer (5). The first conductive type layer is provided above the semiconductor layer. The saturation current suppression layer provided above the first conductive type layer includes a first deep layer (4) and a JFET portion (3). The base region is provided above the saturation current suppression layer. The source region and the contact region are provided above the regions. Each trench gate structure has a gate trench (10), a gate insulating film (11), and a gate electrode (12). The second deep layer is provided between the trench gate structures and connected to the first deep layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device including a semiconductor element having a trench gate structure, and also to a method for manufacturing the semiconductor device. This disclosure can be applied to SiC semiconductor devices using silicon carbide (SiC) as the semiconductor material. Background Technology

[0002] JP 2020-109808 A discloses a semiconductor device including a semiconductor element with a trench gate structure that can suppress surge voltage or device breakdown. In this semiconductor device, when the drain voltage rises to a high voltage in the structure (in which a p-type electric field barrier layer is formed below the trench gate structure to obtain a withstand voltage, while simultaneously achieving low saturation current and low on-resistance), the electric field barrier layer is completely depleted. As a result, when the drain voltage rises to a high voltage, the feedback capacitance can be increased, and the change in drain current can be reduced by increasing the capacitance between the gate and drain. Therefore, surge voltage can be reduced and device breakdown caused by surge voltage can be suppressed. Furthermore, the gate insulating film can be protected from the effects of high electric fields by completely depleting the electric field barrier layer. Summary of the Invention

[0003] In the semiconductor device with this structure disclosed in JP 2020-109808 A, since the electric field blocking layer needs to have the same potential as the source potential, a p-type semiconductor for connection is used to connect the region between the base region and the electric field blocking layer to form a trench region at the trench side surface.

[0004] However, as the spacing between two adjacent trenches in the trench structure narrows, the changes in on-resistance and threshold voltage caused by the offset of the formation location of the p-type semiconductor used for connection may increase. The p-type semiconductor used for connection is formed at a predetermined distance from the trench. However, when the p-type semiconductor is formed by, for example, ion implantation, the formation location may be offset. In this case, for example, if the p-type semiconductor used for connection is in contact with the trench side surface, the concentration of p-type impurities in the contact portion becomes higher than the concentration in the base region. Therefore, the area for MOSFET operation varies depending on whether the formation location of the p-type semiconductor is offset and whether the on-resistance Ron fluctuates. Due to the offset of the formation location, the concentration of p-type impurities in the base region increases significantly in the portion where the p-type semiconductor used for connection is formed. Therefore, this leads to an increased change in the threshold voltage Vth.

[0005] The purpose of this disclosure is to provide a semiconductor device that can suppress the increase in on-resistance or threshold voltage, and also to provide a method for manufacturing the semiconductor device.

[0006] According to a first aspect of this disclosure, a semiconductor device includes a semiconductor element. The semiconductor element includes a semiconductor layer, a first conductivity type layer, a saturation current suppression layer, a current dispersing layer, a base region, a source region, a contact region, a trench gate structure, an interlayer insulating film, a source electrode, a drain electrode, and a second deep layer. The semiconductor layer has a first conductivity type or a second conductivity type. The first conductivity type layer is disposed above the semiconductor layer and has a first conductivity type with an impurity concentration lower than that of the semiconductor layer. The saturation current suppression layer is located above the first conductivity type layer. The saturation current suppression layer includes a first deep layer and a JFET portion. The first deep layer has a length direction defined as a first direction, and the first deep layer has a second conductivity type and has a plurality of segments aligned in a stripe pattern. The JFET portion has the same length direction as the first direction and has a first conductivity type. The JFET portion has a plurality of segments aligned in a stripe pattern and arranged alternately with the segments of the first deep layer. The current dispersing layer has a first conductivity type and is disposed above the saturation current suppression layer. The base region has a second conductivity type and is disposed above the current dispersing layer. A source region is disposed above the base region and has a first conductivity type with an impurity concentration higher than that of the first conductivity type layer. A contact region is disposed above the base region at a different location from the source region and has a second conductivity type with an impurity concentration higher than that of the base region. The trench gate structures are aligned in a stripe pattern, and each trench gate structure has a length direction defined as a second direction, which intersects the first direction. Each trench gate structure has a gate trench, a gate insulating film, and a gate electrode. The gate trench penetrates both the source and base regions. The gate insulating film covers the inner wall surface of the gate trench. The gate electrode is disposed above the gate insulating film. An interlayer insulating film covers the gate electrode and includes contact holes for exposing the contact region and the source region. The source electrode is electrically connected to the source region through the contact holes. The drain electrode is disposed on the back side of the semiconductor layer. A second deep layer is disposed between the trench gate structures and connected to the first deep layer. The second deep layer has the same length direction as the second direction. The second deep layer is disposed over the entire region between two adjacent trench gate structures. The width of the second deep layer is greater than or equal to the spacing between two adjacent trench gate structures along the width direction of each trench gate structure.

[0007] The width of the second deep layer is set so that no channel region is intentionally formed in the portion where the second deep layer is formed. By setting the width dimension of the second deep layer as described above, the second deep layer is disposed over the entire region between two adjacent trench gate structures along the width direction of the trench gate structure. Therefore, the intentional formation of a channel region in the portion where the second deep layer is formed can be prevented. In addition, the increase in on-resistance or threshold voltage caused by changes in the area where device operation is performed can be suppressed.

[0008] According to a second aspect of this disclosure, a method for manufacturing a semiconductor device including semiconductor elements. The method includes: preparing a semiconductor layer having a first conductivity type or a second conductivity type; preparing and disposing of a first conductivity type layer over the semiconductor layer; forming a saturation current suppression layer over the first conductivity type layer; forming a current dispersing layer having the first conductivity type over the saturation current suppression layer; forming a base region having the second conductivity type over the current dispersing layer; forming a source region over the base region; forming a contact region at a location different from the source region over the base region; forming trench gate structures aligned with a stripe pattern; forming an interlayer insulating film covering a gate electrode included in each trench gate structure; forming a source electrode electrically connected to the source region through a contact hole; forming a drain electrode at a rear side of the semiconductor layer; and forming at least one second deep layer between a plurality of trench gate structures by implanting ions into the entire region between two adjacent trench gate structures. The first conductivity type layer has a first conductivity type with an impurity concentration lower than that of the semiconductor layer. The saturation current suppression layer includes a first deep layer whose length direction is defined as a first direction and a JFET portion whose length direction is the same as the first direction. The first deep layer has a second conductivity type and has multiple segments aligned in a stripe pattern. The JFET portion has multiple segments aligned in a stripe pattern and arranged alternately with the multiple segments of the first deep layer. The source region has a first conductivity type with an impurity concentration higher than that of the first conductivity type layer. The contact region has a second conductivity type with an impurity concentration higher than that of the base region. Each trench gate structure has a length direction defined as a second direction, which intersects with the first direction. Each trench gate structure includes: a gate trench penetrating the source and base regions; a gate insulating film covering the inner wall surface of the gate trench; and a gate disposed above the gate insulating film. The interlayer insulating film includes contact holes for exposing the contact and source regions. The second deep layer has the same length direction as the second direction. The width of the entire region is greater than or equal to the spacing between two adjacent trench gate structures along the width direction of each trench gate structure. The second deep layer is connected to the first deep layer.

[0009] This manufacturing method allows the second deep layer to be arranged throughout the region between the sidewalls of adjacent gate trenches. Therefore, a semiconductor device can be formed in which a channel region is not intentionally formed in the portion where the second deep layer is formed. Furthermore, increases in on-resistance or threshold voltage due to area variations during device operation can be suppressed. Attached Figure Description

[0010] Other objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a cross-sectional structural diagram of a SiC semiconductor device according to the first embodiment;

[0012] Figure 2 It is shown Figure 1 A perspective cross-sectional view of a portion of the SiC semiconductor device shown;

[0013] Figure 3 This is a top view showing the trench gate structure and the second deep layer layout;

[0014] Figure 4A This is a perspective view of the SiC semiconductor device in the comparative example, showing the state where the width of the second deep layer is relatively narrow;

[0015] Figure 4B Is Figure 4A The perspective view of the SiC semiconductor device in the comparative example shows the state in which the formation location of the second deep layer has shifted;

[0016] Figure 5A It is shown Figure 2 A perspective cross-sectional view of the manufacturing process of the SiC semiconductor device shown;

[0017] Figure 5B It is shown Figure 5A A perspective cross-sectional view of the subsequent manufacturing process of SiC semiconductor devices;

[0018] Figure 5C It is shown Figure 5B A perspective cross-sectional view of the subsequent manufacturing process of SiC semiconductor devices;

[0019] Figure 5D It is shown Figure 5C A perspective cross-sectional view of the subsequent manufacturing process of SiC semiconductor devices;

[0020] Figure 5E It is shown Figure 5D A perspective cross-sectional view of the subsequent manufacturing process of SiC semiconductor devices;

[0021] Figure 5F It is shown Figure 5E A perspective cross-sectional view of the subsequent manufacturing process of SiC semiconductor devices;

[0022] Figure 5G It is shown Figure 5F A perspective cross-sectional view of the subsequent manufacturing process of SiC semiconductor devices;

[0023] Figure 6 This is a top view of the trench gate structure and the second deep layer layout described in the second embodiment;

[0024] Figure 7AThe layout of the trench gate structure and localized high-temperature regions inside the semiconductor chip is shown; and

[0025] Figure 7B This is a top view of a semiconductor chip, showing an example of the layout of a second, deeper layer to avoid localized high temperatures. Detailed Implementation

[0026] The following are the technical elements disclosed herein. Each of these technical elements may be applied independently.

[0027] (First Embodiment)

[0028] The first embodiment is described below. This embodiment describes a SiC semiconductor device using silicon carbide as the semiconductor material as an example. However, this embodiment can also be applied to semiconductor devices made of other semiconductor materials such as silicon (Si).

[0029] In the SiC semiconductor device according to this embodiment, there is Figure 1 and Figure 2 The trench-gate structure shown is an inverting vertical MOSFET formed as a semiconductor device. Those vertical MOSFETs shown in the figures are formed within the cell region of the SiC semiconductor device, and the SiC semiconductor device is constructed around the cell region by forming a voltage-resistance holding structure; however, only the vertical MOSFETs are shown in the figures. Figure 1 and Figure 2 As shown, the X direction is orthogonal to the Y direction, the Y direction is orthogonal to the Z direction, and the Z direction is orthogonal to the X direction. In particular, the width direction perpendicular to the MOSFET can be called the X direction, the length direction perpendicular to the MOSFET that intersects the X direction can be called the Y direction, and the thickness or depth direction perpendicular to the MOSFET (i.e., the normal direction of the XY plane) can be called the Z direction.

[0030] Figure 2 It is a perspective cross-sectional view of a portion of the unit region, but omits a part of the SiC semiconductor device structure to make the layout of each part easier to understand.

[0031] like Figure 1 and Figure 2 As shown, n is made of SiC + Type 1 substrate is used as a semiconductor substrate in SiC semiconductor devices. - Type 2 is formed in n + Above the main surface of substrate 1. - Type 2 contains layers with concentrations below n + In a portion of the drift layer of substrate 1. + Type 1 substrate corresponds to semiconductor layer, n - Type 2 corresponds to the first conductivity type layer.

[0032] In the cell region, an n-type JFET portion 3 (hereinafter referred to as JFET portion 3) and a p-type first deep layer 4 (hereinafter referred to as first deep layer 4) contained in a portion of a drift layer made of SiC are formed on the n-type JFET portion 3. - Above layer 2. - Type 2 in facing n + One side of the substrate 1 is connected to the JFET portion 3.

[0033] JFET portion 3 and the first deep layer 4 are contained within a saturation current suppression layer, both extending along the Y direction (the length direction) and arranged alternately and repeatedly along the X direction. In other words, when from n... + When viewed in the normal direction of the main surface of the substrate 1, at least a portion of the JFET portion 3 and a portion of the first deep layer 4 are shaped into multiple linear shapes, i.e. strips, and arranged alternately.

[0034] In this embodiment, the JFET portion 3 is formed below the first deep layer 4. Therefore, the strip portions of the JFET portion 3 are connected to each other below the first deep layer 4, but each strip portion is arranged between two corresponding segments in the plurality of segments of the first deep layer 4.

[0035] The first deep layer 4 is made of a layer of p-type impurities. The first deep layer 4 has a strip shape. Each segment of the linear shape of the first deep layer 4 has a constant width, and the linear shapes are arranged at equal intervals. The concentration of p-type impurities in the depth direction is constant.

[0036] An n-type current dispersing layer 6 is formed above the JFET portion 3 and the first deep layer 4. The n-type current dispersing layer 6 is contained within a portion of a drift layer made of SiC. The n-type current dispersing layer 6 is a layer that allows the current flowing through the trench perpendicular to the MOSFET to be distributed in the Y direction, as will be described later, and has, for example, a higher current dispersing layer than n... - The n-type impurity concentration is higher in layer 2. However, for the n-type current dispersing layer 6, the impurity concentration is set to be higher than that of the n-type layer. - n-type layer 2 is not required. For example, the impurity concentration of n-type current dispersing layer 6 can be related to n... - The impurity concentration is the same in layer 2.

[0037] In this embodiment, the drift layer consists of n - The drift layer is formed by layer 2, JFET portion 3, and n-type current dispersing layer 6. The structure of the drift layer can be arbitrary. For example, the drift layer can be included in the n-type current dispersing layer. - Type 2 and n + The structure has a buffer layer between the type substrates 1.

[0038] A p-type base region 7 made of SiC is formed above the n-type current dispersion layer 6. + The source region 8 is p-type. The base region 7 is configured to have a lower p-type impurity concentration than the first deep layer 4. Additionally, n... + The source region 8 is configured to have a higher n-type impurity concentration than the n-type current dispersion layer 6.

[0039] Form p + Type contact layer 9, making n + The surface of the p-type source region 8 reaches the p-type base region 7. + The p-type contact layer 9 corresponds to a contact region configured to have a higher p-type impurity concentration than the p-type base region 7. In this embodiment, p + The contact layer 9 includes a coupling layer 9a and a contact portion 9b. The coupling layer 9a is a portion with a linear shape, its length direction being along the X direction. The contact portion 9b is a portion with a linear shape, its length direction being the Y direction intersecting the X direction. A second deep layer 5 is formed below the coupling layer 9a. The second deep layer 5 penetrates the p-type base region 7 and the n-type current dispersing layer 6 to connect to the first deep layer 4. The second deep layer 5, together with the coupling layer 9a, is formed in a linear shape, with the X direction as the longitudinal direction.

[0040] The coupling layer 9a and the second deep layer 5 connect the first deep layer 4 and the source electrode 14 to fix the first deep layer 4 at the source potential. The contact portion 9b sets the p-type base region 7 to the source potential. If the contact portion 9b is connected to the second deep layer 5, the first deep layer 4 can be fixed at the source potential from the contact portion 9b through the p-type base region 7 and the second deep layer 5. In this case, the coupling layer 9a is not necessary. However, the coupling layer 9a is used to connect the second deep layer 5 to the source electrode 14 over a wide area.

[0041] The spacing between the multiple segments forming the coupling layer 9a and the multiple segments forming the second deep layer 5 are arbitrary. However, in this embodiment, the coupling layer 9a and the second deep layer 5 are formed within a set of multiple trench gate structures that serve as a spacing. For example, Figure 3The diagram shows a group of five trench gate structures, in which a second deep layer 5 is disposed, formed as a single space. The width of the coupling layer 9a is arbitrary. However, the width of the coupling layer 9a is set to be shorter than or equal to the spacing between two adjacent trench gate structures. Similar to the second deep layer 5, the coupling layer 9a can also be arranged to fill the entire space between two adjacent trench gate structures. According to the above arrangement, even if misalignment occurs during the formation of the coupling layer 9a, the first deep layer 4 can be stably fixed to the source potential. The width of the second deep layer 5 is set to be greater than or equal to the spacing between two adjacent trench gate structures. In other words, the entire region between two adjacent trench gate structures along the width direction (i.e., the Y direction) of the trench gate structure is set as the width of the second deep layer 5. The width of the second deep layer 5 is set such that n + The region below the p-type source region 8 or coupling layer 9a is formed to the width of the second deep layer 5. The width of the second deep layer 5 is described below. The spacing of the formed contact portions 9b is also arbitrary. However, if the formation spacing is too wide, the distance from a portion of the p-type base region 7 to the contact portion 9b becomes longer. Therefore, the formation spacing is set such that the source potential is reached over the entire p-type base region 7. Since the trench density decreases in the portion where the contact portion 9b is formed, the formation spacing of the contact portion 9b is set to suppress the decrease in trench density.

[0042] Gate trench 10 is formed to penetrate the p-type base region 7 and n-type base region 8. + The p-type source region 8 reaches the n-type current dispersing layer 6. The gate trench 10 has a predetermined width and a predetermined depth. The coupling layer 9a is also disposed on the p-type base region 7 and the n-type current dispersing layer 6. + There are 8 source regions to facilitate contact with the side surface of the gate trench 10. The gate trench 10 is formed in a strip-shaped arrangement, wherein... Figure 2 In this context, the Y direction is defined as the width direction of the gate trench 10, which intersects the length direction of the JFET portion 3 and the first deep layer 4. In this case, the X direction is defined as the length direction of the gate trench 10 intersecting the Y direction, and the Z direction is defined as the depth direction of the gate trench 10. Figures 1 to 2 As shown, the gate trench 10 is formed in a strip shape, wherein the gate trench 10 is arranged at equal intervals along the Y direction, and the p-type base region 7 and n + The p-type source region 8 is interposed between them. However, in the region forming the second deep layer 5, the p-type base region 7 between the gate trenches 10 is replaced by the second deep layer 5.

[0043] For example, the spacing between trench gate structures, in other words, the spacing Pt between the side surfaces of gate trench 10 and adjacent gate trench 10, is arbitrary. The spacing Pt can also be referred to as the distance between the side surfaces of gate trench 10 and adjacent gate trenches. However, the spacing Pt is set to be narrowed to 2 micrometers or less. For example, the spacing Pt is set to 1 micrometer or less. The width Wt of the gate trench 10 is arbitrary. However, the width Wt is set to be less than the distance between the center position of the trench gate structure and the center position of adjacent trench gate structures. For example, the width Wt is set in the range of 0.5 micrometers to 0.8 micrometers. The spacing between two adjacent gate trenches 10 is obtained by subtracting the width Wt from the cell pitch.

[0044] When perpendicular to n + When viewed from the direction of the main surface of the substrate 1, in other words, when viewed from above, the gate trench 10 is formed as a strip. However, the gate trench can also be formed as at least one portion having a strip shape. For example, two adjacent gate trenches 10 having a linear shape can be configured as a group, and the gate trenches 10 can be arranged such that the two ends of the gate trenches 10 are connected in a semi-circular shape.

[0045] When the vertical MOSFET is operating, a portion of the p-type base region 7 located on the side surface of the gate trench 10 is connected to n. + The trench 10 has a source region 8 and an n-type current dispersing layer 6. The inner wall surface of the trench 10 is covered with a gate insulating film 11. A gate electrode 12 made of doped polysilicon is formed on the surface of the gate insulating film 11, and the gate trench 10 is filled with the gate insulating film 11 and the gate electrode 12 to form a trench gate structure. An interlayer insulating film 13 is formed to cover the gate electrode 12. The interlayer insulating film 13 may extend outside the gate trench 10. However, in this embodiment, the interlayer insulating film 13 is disposed inside the gate trench 10, and the gate trench 10 is filled with the gate insulating film 11, the gate electrode 12, and the interlayer insulating film 13.

[0046] like Figure 1 As shown, the source electrode 14, etc., are formed on the n-thickness layer via the interlayer insulating film 13. + The source electrode 14 is made of various metals, such as Ni / Al. Among these metals, at least n-type SiC (specifically n...) is used. +The portion of the source region 8 that contacts the gate electrode 12 (in the case of n-type doping) is made of a metal capable of ohmic contact with n-type SiC. Additionally, among various metals, at least a portion that contacts p-type SiC (specifically, the portion that contacts the p+ type contact layer 9) is made of a metal capable of ohmic contact with p-type SiC. The source electrode 14 is formed on the interlayer insulating film 13 and is electrically insulated from the SiC portion, but it is connected to the n+ type SiC through contact holes formed in the interlayer insulating film 13. + Type source polar region 8 and p + Type 9 electrical contact.

[0047] On the other hand, the electrical connection to n + The drain electrode 15 of the substrate 1 is formed on the n + On the rear surface of substrate 1, an n-channel reverse trench gate vertical MOSFET is provided using this structure. A cell region is formed by placing the aforementioned vertical MOSFET cells.

[0048] The SiC semiconductor device, including the vertical MOSFET constructed as described above, is operated by applying a gate voltage Vg of 20V to the gate electrode 12, for example, with the source voltage Vs at 0V and the drain voltage Vd at 1 to 1.5V. That is, when the gate voltage Vg is applied, the vertical MOSFET performs operation, wherein a channel region is formed in the portion of the p-type base region 7 that contacts the gate trench 10 and current flows between the drain and the source.

[0049] At this point, JFET portion 3 and the first deep layer 4 serve as saturation current suppression layers, and can maintain a low saturation current while achieving a low on-state resistance by providing saturation current suppression. Specifically, since the strip portions of JFET portion 3 and the first deep layer 4 are repeatedly and alternately formed, the following operations are performed.

[0050] First, when the drain voltage Vd is the voltage applied during normal operation, such as 1 to 1.5V, the depletion layer extending from the first deep layer 4 to the JFET portion 3 extends only to a width smaller than the strip portion of the JFET portion 3. Therefore, even though the depletion layer extends into the JFET portion 3, a current path is ensured. If the n-type impurity concentration of the JFET portion 3 is set to be higher than that of the n-type layer 2, the current path can be configured to have low resistance, and low on-resistance can be achieved.

[0051] When the drain voltage Vd becomes higher than the normal operating drain voltage Vd due to a load short circuit, the depletion layer extending from the first deep layer 4 to the JFET portion 3 extends beyond the width of the strip portion of the JFET portion 3. Then, the JFET portion 3 is immediately truncated before the n-type current dispersing layer 6. As a result, a low saturation current can be maintained and the withstand capability of the SiC semiconductor device can be enhanced due to, for example, a load short circuit.

[0052] In this way, the JFET portion 3 and the first deep layer 4 are used as saturation current suppression layers and exhibit saturation current suppression effects, thereby providing SiC semiconductor devices that can achieve low on-state resistance and low saturation current.

[0053] Furthermore, by providing a first deep layer 4 to sandwich the JFET portion 3 in the middle, strip-shaped portions of the JFET portion 3 and the first deep layer 4 are formed alternately and repeatedly. Therefore, even when the drain voltage Vd becomes a high voltage, the strip-shaped portion extending from the bottom to n... - The extension of the depletion layer in n-type layer 2 is also suppressed by the first deep layer 4. Therefore, the extension of the depletion layer into the trench gate structure can be prevented. Thus, an electric field control effect can be exhibited to reduce the electric field applied to the gate insulating film 11, and the cracking of the gate insulating film 11 can be suppressed, thereby obtaining a highly reliable device with high withstand voltage. Furthermore, since the extension of the depletion layer into the trench gate structure can be prevented as described above, the n-type impurity concentration in n-type layer 2 and JFET portion 3 can be relatively high, and low on-resistance can be achieved.

[0054] Therefore, SiC semiconductor devices with low on-resistance and high reliability can be provided.

[0055] The SiC semiconductor device in this embodiment includes a normally-off semiconductor element, wherein when no gate voltage Vg is applied, no current flows between the drain and source because no channel region is formed. JFET portion 3 is normally-on because it is only turned off when the drain voltage Vd is higher than the voltage during normal operation, even when no gate voltage Vg is applied.

[0056] To perform the above operations, the first deep layer 4 needs to be precisely fixed to the source potential. However, in this embodiment, the first deep layer 4 is fixed to the source potential via coupling layer 9a and the second deep layer 5. Therefore, the SiC semiconductor device according to this embodiment can accurately perform the above operations.

[0057] In this embodiment, when the first deep layer 4 is fixed to the source potential, a second deep layer 5 is included. However, it is generally considered that the channel region is formed at the location where the second deep layer 5 is formed. Figure 4AAs shown, the width of the second deep layer 5 is shorter than the spacing Pt between adjacent gate trenches 10, and the p-type base region 7 is reversed at the trench gate structure side surface located on both sides of the second deep layer 5, forming a channel region.

[0058] like Figure 4B As shown, when the formation location of the second deep layer 5 is offset, the changes in on-resistance Ron and threshold voltage Vth increase. As the distance between the gate trenches 10 included in the trench gate structure shortens, the mask for forming the second deep layer 5 via ion implantation is narrowly opened. However, it is difficult to improve processing accuracy and may lead to offset at the formation location of the second deep layer 5. In this case, for example, if the second deep layer 5 contacts the side surface of the gate trench 10, the p-type impurity concentration at the contact portion becomes higher than that in the p-type base region, and no channel region is formed during MOSFET operation. Therefore, the area for performing MOSFET operation varies depending on whether the formation location of the p-type semiconductor is offset and whether the on-resistance Ron fluctuates. Due to the offset in formation location, the concentration of p-type impurities in the p-type base region 7 increases significantly around the portion where the second deep layer 5 is formed. Therefore, this leads to an increase in the change in threshold voltage Vth.

[0059] In this embodiment, the width of the second deep layer 5, in other words, its dimension in the Y direction, is set such that a channel is not intentionally formed in the portion forming the second deep layer 5, and MOSFET operation is not performed in that portion. The width Wp of the second deep layer 5 is set to be greater than or equal to the spacing Pt between the gate trenches 10. By setting the width Wp dimension as described above, the second deep layer 5 is disposed along the Y direction over the entire region between the sidewalls of adjacent gate trenches 10. Therefore, it is possible to prevent the channel region from intentionally forming in the portion forming the second deep layer 5. In addition, it is possible to suppress the increase in on-resistance or threshold voltage caused by the area change due to the MOSFET operation.

[0060] Furthermore, the width Wp of the second deep layer 5 can be set to account for the offset of the formation position of the second deep layer 5. For example, when the second deep layer 5 is formed by ion implantation or the like, the formation position of the second deep layer 5 may be offset due to factors such as mask displacement. Therefore, the width Wp of the second deep layer 5 can be set to a size obtained by adding the offset D of the formation position to the spacing Pt between the gate trenches 10. In other words, the width Wp of the second deep layer 5 can be set to satisfy the mathematical relationship Pt+D. <Wp。

[0061] However, the width WP of the second deep layer 5 must be set to prevent the second deep layer 5 from forming between two specific adjacent gate trenches in the gate trench 10, and to prevent the second deep layer 5 from forming into a section adjacent to two specific adjacent gate trenches in the adjacent gate trench 10. Therefore, the width Wp of the second deep layer 5 is set to be shorter than the sum of the corresponding widths Wt of two gate trenches 10 and the pitch Pt between the adjacent gate trenches 10. In other words, the width Wp can be set to satisfy the mathematical relationship: Wp < Pt + 2Wt. Additionally, considering the deviation amount D of the formation position of the second deep layer 5, the width Wp of the second deep layer 5 can be set to satisfy the mathematical relationship: Wp < Pt + 2Wt – D.

[0062] The misalignment of the formation position of the second deep layer 5 does not refer to the misalignment relative to an alignment mark (not shown) during the formation of the second deep layer 5. It refers to the misalignment of the second deep layer 5 relative to the gate electrode 10. In other words, misalignment may also occur during the formation of the gate trench 10, and both the misalignment of the formation of the second deep layer 5 and the misalignment of the formation of the gate trench 10 affect the offset of the relative position of the second deep layer 5 relative to the gate trench 10. The width Wp of the second deep layer 5 is set based on the maximum value of both the position offset of the formation of the gate trench 10 and the position offset of the formation of the second deep layer 5 as the deviation amount D. However, it is not necessary to consider the deviation amount D as the maximum value of the offset of the formation position. It is sufficient to set the width Wp of the second deep layer 5 considering the deviation amount D.

[0063] Next, reference will be made to Figures 5A to 5G the cross-sectional view of the SiC semiconductor device during the manufacturing process shown to describe the manufacturing method of the SiC semiconductor device of a vertical MOSFET including an n-channel type reverse trench gate structure according to the present embodiment.

[0064] ( Figure 5A process in

[0065] First, an n + -type substrate 1 made of, for example, SiC is prepared as a semiconductor substrate. Then, an n + -type layer 2 made of SiC is formed on the main surface of the n - -type substrate 1 by epitaxial growth using a CVD (chemical vapor deposition) apparatus (not shown). At this time, a so-called epitaxial substrate can be used, in which an n + -type layer 2 is pre-grown on the main surface of the n - -type substrate 1. A JFET portion 3 made of SiC is epitaxially grown on the n - -type layer 2.

[0066] ( Figure 5B process in

[0067] The first deep layer 4 is formed in a predetermined region of the JFET portion 3. After a mask 17 made of an oxide film or the like is formed on the surface of the JFET portion 3, the mask 17 is patterned to open the region where the first deep layer 4 will be formed. Then, p-type impurities are implanted by ions to form the first deep layer 4. After that, the mask 17 is removed.

[0068] Although the first deep layer 4 is formed by ion implantation in this example, it can be formed by methods other than ion implantation. For example, the JFET portion 3 can be selectively and anisotropically etched to form a recessed portion at a location corresponding to the first deep layer 4, a p-type impurity layer can be epitaxially grown on the recessed portion, and then the p-type impurity layer can be planarized at a portion located on the JFET portion 3 to form the first deep layer 4. In this way, the first deep layer 4 can also be formed by epitaxial growth.

[0069] ( Figure 5C (process)

[0070] Subsequently, n-type SiC is epitaxially grown on the JFET portion 3 and the first deep layer 4 using a chemical vapor deposition (CVD) apparatus (not shown) to form an n-type current dispersing layer 5.

[0071] The p-type base region 7 is epitaxially grown on the n-type current dispersive layer 6.

[0072] ( Figure 5D (process)

[0073] A mask 18, made of an oxide film or the like, with an opening at a position corresponding to the second deep layer 5, is positioned above the p-type base region 7. Then, p-type impurities are ion implanted to form the second deep layer 5 using the mask 18. Afterward, the mask 18 is removed.

[0074] ( Figure 5E (process)

[0075] n + The source region 8 is epitaxially grown on the second deep layer 5 and the p-type base region 7.

[0076] ( Figure 5F (process)

[0077] In n + A mask 19 is formed on the source pole region 8, which corresponds to p + The contact layer has an opening at point 9. The p-type contact layer includes a coupling layer 9a and a contact portion 9b. + The p-type contact layer 9 is formed by p-type impurity ion implantation using a mask 19. The mask 19 is then removed.

[0078] ( Figure 5G (process)

[0079] In n + After a mask (not shown) is formed above the source region 8, an opening is formed in the portion of the mask where the gate trench 10 will be formed. Then, the gate trench 10 is formed by performing an anisotropic etching process such as RIE using the mask.

[0080] Subsequently, after mask formation, for example, oxide deposition or thermal oxidation is performed to form gate insulating film 11, such that gate insulating film 11 covers the inner wall surface of gate trench 10 and n + The surface of the source region 8 is then etched. Next, polysilicon doped with p-type or n-type impurities is deposited and then etched back to leave polysilicon in the gate trench 10, thereby forming the gate electrode 12. As a result, the trench gate structure is completed.

[0081] In other words, an interlayer insulating film 13, made of, for example, an oxide film, is formed to cover the surfaces of the gate electrode 12 and the gate insulating film 11. The interlayer insulating film 13 is etched using a mask (not shown) until n is exposed. + Type source polar region 8 and p + The contact layer 9 is formed, and contact holes are formed and the interlayer insulating film 13 inside the gate trench 10 is retained.

[0082] Although not shown in the figure, the following process is performed. Then, after forming an electrode material provided by a laminated structure of, for example, various metals on the surface of the interlayer insulating film 13, the source electrode 14 is formed by patterning the electrode material. Furthermore, a drain electrode 15 is formed on the n... + On the back side of substrate 1. In this way, the SiC semiconductor device according to this embodiment is completed.

[0083] In the SiC semiconductor device according to this embodiment, the width of the second deep layer 5, in other words, its dimension in the Y direction, is set such that a channel is not intentionally formed in the portion where the second deep layer 5 is formed, and MOSFET operation is not performed in that portion. The width Wp of the second deep layer 5 is set to be greater than or equal to the spacing Pt between two adjacent gate trenches 10. By setting the width Wp as described above, the second deep layer 5 is disposed over the entire region between the corresponding sidewalls of two adjacent gate trenches 10 in the Y direction. Therefore, it is possible to prevent the channel region from being intentionally formed in the portion where the second deep layer 5 is formed. In addition, it is possible to suppress the increase in on-resistance or threshold voltage caused by the area change due to the MOSFET operation.

[0084] In addition, the width Wp of the second deep layer 5 is set to be shorter than the sum of the widths Wt of two adjacent gate trenches 10 and the pitch Pt between the two adjacent gate trenches 10. In other words, the width Wp can be set to satisfy the mathematical relationship: Wp < Pt + 2Wt. Therefore, the width Wp of the second deep layer 5 can be set to prevent the second deep layer 5 from being formed into a specific gate trench 10 and to prevent the second deep layer 5 from being formed into an adjacent gate trench 10.

[0085] (Second Embodiment)

[0086] The second embodiment will be described below. This embodiment is a modification in which the layout of the second deep layer 5 is changed with respect to the first embodiment and is similar to the first embodiment except for the modified part, and thus only those parts different from the first embodiment will be described.

[0087] In the first embodiment, each of the plurality of sections of the second deep layer 5 is formed between a set of multiple trench gate structures as one interval. For example, as Figure 3 shown, each of the plurality of sections of the second deep layer 5 is provided between a set of five trench gate structures, so that the formation density of the plurality of sections of the second deep layer 5 within the cell region is uniform. In other words, the plurality of sections of the second deep layer 5 are provided at equal intervals within the cell region.

[0088] On the other hand, in this embodiment, the plurality of sections of the second deep layer 5 are respectively formed in multiple sets of trench gate structures, and the plurality of sections of the second deep layer 5 are arranged at unequal intervals. For example, as Figure 6 shown, the first of the plurality of sections of the second deep layer 5 is placed between a set of three trench gate structures, the second of the plurality of sections of the second deep layer 5 is placed between a set of five trench gate structures, and the third of the plurality of sections of the second deep layer 5 is placed between a set of eight trench gate structures. As described above, the arrangement intervals of the plurality of sections of the second deep layer 5 can be changed.

[0089] (Third Embodiment)

[0090] The third embodiment will be described below. This embodiment is a modification in which the formation position of the second deep layer 5 is changed with respect to the first embodiment and is similar to the first embodiment except for the modified part, and thus only those parts different from the first embodiment will be described.

[0091] As Figure 7AAs shown, in the case of a SiC semiconductor device including a MOSFET with a trench gate structure in the semiconductor chip 100, the center of the cell region tends to have a high temperature, and the temperature gradually decreases as it moves away from the center of the cell region. Heat dissipates towards the outer periphery of the cell region. However, heat is not easily dissipated and concentrates in the center of the cell region. Increasing the density of multiple segments of the second deep layer 5 in the portions where the temperature tends to rise helps to suppress temperature deviations within the cell region. Figure 7B As shown, the first segment of the multiple segments of the second deep layer 5 is arranged in a circular shape at the center of the unit region. Furthermore, the second segment of the multiple segments of the second deep layer 5 and the third segment of the multiple segments of the second deep layer 5 are arranged concentrically around the center of the unit region. The spacing between the multiple segments of the second deep layer 5 widens as they are moved away from the center of the unit region. Even without forming multiple segments of the second deep layer 5, by arranging the multiple segments of the second deep layer 5 according to the temperature distribution, temperature deviations within the unit region can be suppressed, and localized heating can be prevented.

[0092] (Other embodiments)

[0093] While this disclosure has been described with reference to the embodiments described above, it is not limited to those embodiments and includes various modifications and equivalent modifications. Furthermore, although various elements are shown in various combinations and configurations (which are exemplary), other combinations and configurations including more, fewer, or only a single element are also within the spirit and scope of this disclosure.

[0094] In the first embodiment, the first deep layer 4 is formed by forming a first deep layer 4 using an ion implantation layer. In other words, the first deep layer 4 is formed by ion implantation of p-type impurities after the formation of the JFET portion 3. On the other hand, the JFET portion 3 is formed by forming the JFET portion 3 using an ion implantation layer. In other words, it is possible to form the JFET portion 3 using an ion implantation layer. - After the first deep layer 4 is epitaxially grown above the type layer 2, the JFET portion 3 is formed by ion implantation of n-type impurities.

[0095] In the above embodiment, the segment between two adjacent gate trenches 10 is formed as a second deep layer 5. However, a segment spanning three or more consecutive gate trenches 10 can be formed as a second deep layer 5. However, in this case, since the channel region cannot be formed in two or more regions between adjacent gate trenches 10, the current density per unit area can be increased in the structure according to the first embodiment.

[0096] In the above embodiments, the use of SiC as a semiconductor material has been described, but this disclosure can also be applied to semiconductor devices using other semiconductor materials or compound semiconductors such as Si.

[0097] In the above embodiment, the second deep layer 5 is formed by ion implantation from the surface of the p-type base region 7 and the n-type current dispersing layer 6. Additionally, the coupling layer 9a and the contact portion 9b are formed simultaneously. This manufacturing method is particularly effective when using a semiconductor material such as SiC in which the implanted ions have not diffused through thermal treatment. When using a semiconductor material such as silicon (Si) in which the ions diffuse through thermal treatment, the coupling layer 9a and the contact portion 9b can be formed separately, and can be formed by using a material provided in the n-type current dispersing layer 6. + The mask at the surface of the source pole region 8 simultaneously forms a coupling layer 9a and a second deep layer 5.

[0098] In the above embodiments, n is prepared as a semiconductor layer. + Type 1 substrate, and in n + n layers corresponding to the n-type conductivity type are epitaxially grown on substrate 1. - Type 2. However, the above method is merely an example. - Type 2 can be used as a semiconductor substrate, and can be achieved through n - Ions are implanted at the rear surface of layer 2 to form a structure with a higher density than n. - Type 2 is a semiconductor layer with a higher impurity concentration.

[0099] In the above embodiments, as an example, an n-channel vertical MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described. Alternatively, the conductivity type of each element can be reversed to form a p-channel vertical MOSFET. In the above description, the vertical MOSFET is described as an example of a semiconductor element. Alternatively, this disclosure can also be applied to IGBTs having a similar structure. In the case of an n-channel IGBT, in each of the above embodiments, n + The conductivity type of substrate 1 is changed from n-type substrate to p-type substrate, and the structure and manufacturing method are the same as those in each of the above embodiments (except for n-type substrate). + (The conductivity type of substrate 1 changes from an n-type substrate to a p-type substrate). Although a trench gate structure is described as an example in this specification, planar MOSFETs or IGBTs can be used, and other components besides MOSFETs and IGBTs can also be used.

Claims

1. A semiconductor device comprising: Semiconductor devices, including: A semiconductor layer having a first conductivity type or a second conductivity type; A first conductivity type layer is disposed above the semiconductor layer and has a first conductivity type with an impurity concentration lower than that of the semiconductor layer; A saturation current suppression layer, disposed above the first conductivity type layer, includes: A first deep layer, the length direction of which is defined as a first direction, the first deep layer having the second conductivity type and having multiple segments aligned in a stripe pattern, and The JFET portion has a length direction that is the same as the first direction, the JFET portion has the first conductivity type, and the JFET portion has a plurality of segments arranged in a strip pattern and alternately arranged with the plurality of segments of the first deep layer; A current dispersion layer having the first conductivity type is disposed above the saturation current suppression layer; A base region having the second conductivity type and disposed above the current dispersing layer; A source region is disposed above the base region and has a first conductivity type with an impurity concentration higher than that of the first conductivity type layer; A contact region is disposed above the base region at a position different from the source region, and has a second conductivity type with an impurity concentration higher than that of the base region; A plurality of trench gate structures aligned in a stripe pattern, each of the plurality of trench gate structures having a length direction defined as a second direction intersecting the first direction, each of the plurality of trench gate structures comprising: A gate trench that penetrates the source region and the base region. A gate insulating film that covers the inner wall surface of the gate trench, and A gate electrode is disposed above the gate insulating film; An interlayer insulating film covers the gate electrode and includes contact holes for exposing the contact region and the source region; A source electrode, which is electrically connected to the source region through the contact hole; Drain electrode, which is disposed on the rear side of the semiconductor layer; and A second deep layer, disposed between the plurality of trench gate structures and connected to the first deep layer, has the same length direction as the second direction, and has a width greater than or equal to the spacing between two adjacent trench gate structures along the width direction of each of the trench gate structures, and is disposed over the entire region between two adjacent trench gate structures in the trench gate structure. The contact area includes: A contact portion having a linear shape intersecting the second direction and contacting the source electrode to fix the base region at the source potential; and A coupling layer having a linear shape with the same length direction as the second direction, and disposed above the second deep layer and in contact with the source electrode, so as to fix the first deep layer at the source potential through the second deep layer.

2. The semiconductor device according to claim 1, The width of the second deep layer satisfies the mathematical relationship Pt ≤ Wp < Pt + 2Wt, where Wp represents the width of the second deep layer, Pt represents the spacing between two adjacent trench gate structures in the trench gate structure, and Wt represents the width of each of the two adjacent trench gate structures in the trench gate structure.

3. The semiconductor device according to claim 1 or 2, in, The second deeper layer includes multiple segments, and The plurality of segments of the second deep layer are respectively configured for multiple groups consisting of two or more trench gate structures, such that the plurality of segments of the second deep layer are arranged between the trench gate structures at equal intervals.

4. A semiconductor device comprising: Semiconductor devices, including: A semiconductor layer having a first conductivity type or a second conductivity type; A first conductivity type layer is disposed above the semiconductor layer and has a first conductivity type with an impurity concentration lower than that of the semiconductor layer; A saturation current suppression layer, disposed above the first conductivity type layer, includes: A first deep layer, the length direction of which is defined as a first direction, the first deep layer having the second conductivity type and having multiple segments aligned in a stripe pattern, and The JFET portion has a length direction that is the same as the first direction, the JFET portion has the first conductivity type, and the JFET portion has a plurality of segments arranged in a strip pattern and alternately arranged with the plurality of segments of the first deep layer; A current dispersion layer having the first conductivity type is disposed above the saturation current suppression layer; A base region having the second conductivity type and disposed above the current dispersing layer; A source region is disposed above the base region and has a first conductivity type with an impurity concentration higher than that of the first conductivity type layer; A contact region is disposed above the base region at a position different from the source region, and has a second conductivity type with an impurity concentration higher than that of the base region; A plurality of trench gate structures aligned in a stripe pattern, each of the plurality of trench gate structures having a length direction defined as a second direction intersecting the first direction, each of the plurality of trench gate structures comprising: A gate trench that penetrates the source region and the base region. A gate insulating film that covers the inner wall surface of the gate trench, and A gate electrode is disposed above the gate insulating film; An interlayer insulating film covers the gate electrode and includes contact holes for exposing the contact region and the source region; A source electrode, which is electrically connected to the source region through the contact hole; Drain electrode, which is disposed on the rear side of the semiconductor layer; and A second deep layer, disposed between the plurality of trench gate structures and connected to the first deep layer, has the same length direction as the second direction, and has a width greater than or equal to the spacing between two adjacent trench gate structures along the width direction of each of the trench gate structures, and is disposed over the entire region between two adjacent trench gate structures in the trench gate structure. The second deep layer comprises multiple segments, and In this configuration, the first segment of the plurality of segments in the second deep layer is located at the center of the cell region where the semiconductor element is disposed, and one or more remaining segments of the plurality of segments in the second deep layer are concentrically disposed relative to the first segment located at the center.

5. A method for manufacturing a semiconductor device including semiconductor elements, the method comprising: Prepare a semiconductor layer having a first conductivity type or a second conductivity type; A first conductivity type layer is prepared and disposed above the semiconductor layer; The first conductivity type layer has a first conductivity type with an impurity concentration lower than that of the semiconductor layer; A saturation current suppression layer is formed above the first conductivity type layer. The saturation current suppression layer comprises a first deep layer and a JFET portion. The length direction of the first deep layer is defined as a first direction, and the length direction of the JFET portion is the same as the first direction. The first deep layer has the second conductivity type and has multiple segments aligned in a stripe pattern. The JFET portion has multiple segments arranged in a strip pattern and alternately with the multiple segments of the first deep layer; A current dispersion layer having the first conductivity type is formed above the saturated current suppression layer; A base region having the second conductivity type is formed above the current dispersing layer; A source region is formed above the base region. The source region has a first conductivity type with an impurity concentration higher than that of the first conductivity type layer. A contact region is formed above the base region at a location different from the source region. The contact region has a second conductivity type with a higher impurity concentration than the base region; Multiple trench gate structures aligned with a stripe pattern are formed. Each of the trench gate structures has a length direction defined as a second direction intersecting the first direction, and Each of the trench gate structures includes: A gate trench that penetrates the source region and the base region. A gate insulating film that covers the inner wall surface of the gate trench, and A gate electrode is disposed above the gate insulating film; An interlayer insulating film is formed covering the gate electrode. The interlayer insulating film includes contact holes for exposing the contact region and the source region; A source electrode is formed that is electrically connected to the source region through the contact hole; A drain electrode is formed on the rear side of the semiconductor layer; and A second deep layer is formed between the plurality of trench gate structures by implanting ions into the entire region between two adjacent trench gate structures. The second deeper layer has the same length direction as the second direction. Wherein, the width of the second deep layer is greater than or equal to the spacing between two adjacent trench gate structures along the width direction of each of the trench gate structures, and The second deep layer is connected to the first deep layer. The contact area includes: A contact portion having a linear shape intersecting the second direction and contacting the source electrode to fix the base region at the source potential; and A coupling layer having a linear shape with the same length direction as the second direction, and disposed above the second deep layer and in contact with the source electrode, so as to fix the first deep layer at the source potential through the second deep layer.

Images