An adaptive turn-off time control circuit and method

Abstract

A control circuit and method of adaptive off time, the circuit is applied to the PWM unit of voltage converter, and includes light load delay unit and off control unit;Wherein, the light load delay unit, with the off control unit is connected, for providing the off delay of the voltage converter lower tube in the off control unit;The off control unit, based on the inductance current limiting logic in the voltage converter, realizes the conduction and off control of the upper tube and lower tube of the voltage converter.This application provides reasonable working frequency of voltage converter to meet the OOA (Out of Audio) demand, reduces the noise, improves the related performance of voltage converter.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a control circuit and method for adaptive turn-off time. Background Technology

[0002] DC-DC (Direct Current-Direct Current) converters are widely used in integrated circuits as voltage converters that can transform input voltage and effectively output a fixed voltage. Typically, when the voltage converter is in a light-load environment, in order to improve the converter's operating efficiency and save power consumption, a DCM (Discontinuous Conduction Mode) is provided to control the operating state of the power transistors in the voltage converter.

[0003] However, when the voltage converter operates in DCM mode, the converter's operating frequency is relatively low, often accompanied by low-frequency noise audible between 20Hz and 20kHz. To overcome the influence of this low-frequency noise and enable the converter to operate normally under light load conditions at frequencies outside the noise range, this invention provides a novel adaptive turn-off time control circuit. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide an adaptive turn-off time control circuit. This circuit adjusts the turn-off time of the lower transistor in the voltage converter to limit the time interval between the multiple conductions of the upper transistor, thereby further adjusting the operating frequency of the voltage converter to a range beyond the human ear.

[0005] The present invention adopts the following technical solution.

[0006] The first aspect of the present invention relates to an adaptive turn-off time control circuit, which is applied in a voltage converter PWM unit and includes a light load delay unit and a turn-off control unit; wherein, the light load delay unit is connected to the turn-off control unit and is used to provide the turn-off delay of the lower transistor of the voltage converter to the turn-off control unit; the turn-off control unit, based on the inductor current limiting logic in the voltage converter, realizes the turn-on and turn-off control of the upper and lower transistors of the voltage converter.

[0007] Preferably, the light-load delay unit includes an inverter, a first RS flip-flop, a second RS flip-flop, a pulse generator, and a timer; wherein, the input terminal of the inverter is connected to the error comparison voltage of the voltage converter, and the output terminal is connected to the R terminal of the first RS flip-flop; the S terminal of the first flip-flop is connected to the inductor peak signal, and the inverse Q terminal is connected to the R terminal of the second RS flip-flop; the S terminal of the second RS flip-flop is connected to the adaptive turn-off time control signal, and the Q terminal is connected to the input terminal of the pulse generator; the output terminal of the pulse generator is connected to the input terminal of the timer, and the output terminal generates a light-load delay signal.

[0008] Preferably, the error comparison voltage is in a high-level state when the feedback voltage of the voltage converter is greater than the reference voltage, and in a low-level state when the feedback voltage is less than the reference voltage.

[0009] Preferably, the inductor peak signal is output based on the relationship between the magnitude of the inductor current in the voltage converter and the preset maximum inductor current; when the inductor current is equal to the preset maximum inductor current, the inductor peak signal is in a high-level state; when the inductor current is less than the preset maximum inductor current, the inductor peak signal is in a low-level state.

[0010] Preferably, the adaptive turn-off time control signal is generated based on the current duty cycle of the voltage converter; starting from the turn-off of the upper transistor and the turn-on of the lower transistor of the voltage converter, the adaptive turn-off time is calculated based on the current duty cycle, and after the adaptive turn-off time ends, the adaptive turn-off time control signal is set to an instantaneous high level.

[0011] Preferably, when the light load delay signal is high, both the upper and lower transistors of the voltage converter are in the off state; when the light load delay signal is low, the upper and lower transistors of the voltage converter are turned on or off based on the PWM signal output by the turn-off control unit.

[0012] Preferably, the shutdown control unit includes a third RS flip-flop; the S terminal of the third RS flip-flop is connected to the inductor peak signal, the R terminal is connected to the negative inductor current limiting signal, and the Q terminal outputs a PWM signal.

[0013] Preferably, the negative inductor current limiting signal is output based on the relationship between the magnitude of the inductor current in the voltage converter and the preset maximum negative inductor current; when the inductor current is equal to the preset maximum negative inductor current, the inductor peak signal is in a high-level state; when the inductor current is greater than the preset maximum negative inductor current, the inductor peak signal is in a low-level state.

[0014] Preferably, when the PWM signal is high, the upper transistor of the voltage converter is turned on and the lower transistor is turned off; when the PWM signal is low, the upper transistor of the voltage converter is turned off.

[0015] A second aspect of the present invention relates to an adaptive turn-off time control method, which is implemented using an adaptive turn-off time control circuit described in the first aspect of the present invention.

[0016] The beneficial effect of the present invention is that, compared with the prior art, the adaptive turn-off time control circuit of the present invention, by adjusting the turn-off time of the lower transistor in the voltage converter, thereby limiting the time interval between multiple conductions of the upper transistor, further adjusting the operating frequency of the voltage converter to a range beyond the human ear.

[0017] The beneficial effects of the present invention also include:

[0018] 1. The method of the present invention fully considers the adjustment method of the voltage converter by the PWM unit in the prior art. Under the premise of fully adapting to the inductor current limit, turn-off time limit, error voltage limit, etc., it realizes the reasonable operating frequency of the voltage converter that meets the OOA (Out of Audio) requirement, reduces noise, and improves the relevant performance of the voltage converter.

[0019] 2. Because the light-load delay signal generated by the PWM unit in this invention can ensure that the inductor current remains basically zero during the process of the upper and lower transistors being turned off simultaneously, it not only saves output power, but also ensures that the inductor current is not affected by any interference and will not cause overall logic problems in the circuit. This ensures that while improving circuit performance, it will not affect important indicators such as the accuracy and stability of the output voltage. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the circuit structure of a light-load delay unit in an adaptive turn-off time control circuit of the present invention.

[0021] Figure 2 This is a schematic diagram of the circuit structure of the shutdown control unit in the adaptive shutdown time control circuit of the present invention. Detailed Implementation

[0022] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0023] Figure 1 This is a schematic diagram of the circuit structure of the light-load delay unit in an adaptive turn-off time control circuit of the present invention. Figure 2 This is a schematic diagram of the circuit structure of the turn-off control unit in an adaptive turn-off time control circuit of the present invention. Figure 1 and Figure 2As shown, this invention relates to an adaptive turn-off time control circuit. The circuit is applied in a voltage converter PWM unit and includes a light-load delay unit and a turn-off control unit. The light-load delay unit is connected to the turn-off control unit and is used to provide the turn-off delay of the lower transistor of the voltage converter to the turn-off control unit. The turn-off control unit, based on the inductor current limiting logic in the voltage converter, realizes the on and off control of the upper and lower transistors of the voltage converter.

[0024] Understandably, this invention adds a light-load delay unit to the voltage converter in the prior art, and uses this unit to additionally control the state of the lower transistor. The output signal of the light-load delay unit can select a period during the time when the upper transistor is off and the lower transistor is on to ensure that both transistors are off, thus delaying the total on-time of the lower transistor. This lengthens the time for the voltage converter to recover until the upper transistor turns on again, thereby limiting the frequency of the voltage converter to the range of OOA. The duration of the two transistors being off in this invention can be controlled by a pre-set fixed delay, thereby changing the frequency of the circuit accordingly.

[0025] Preferably, the light-load delay unit includes an inverter, a first RS flip-flop, a second RS flip-flop, a pulse generator, and a timer; wherein, the input terminal of the inverter is connected to the error comparison voltage of the voltage converter, and the output terminal is connected to the R terminal of the first RS flip-flop; the S terminal of the first flip-flop is connected to the inductor peak signal, and the inverse Q terminal is connected to the R terminal of the second RS flip-flop; the S terminal of the second RS flip-flop is connected to the adaptive turn-off time control signal, and the Q terminal is connected to the input terminal of the pulse generator; the output terminal of the pulse generator is connected to the input terminal of the timer, and the output terminal generates a light-load delay signal.

[0026] It is understood that in this invention, the light-load delay unit needs to generate the light-load delay signal based on relevant parameters in the prior art, such as the error comparison voltage Vo_H, the inductor peak signal Ipeak, and the adaptive turn-off time control signal OFF.

[0027] First, this invention needs to ensure that the light-load delay signal is generated when the error comparison voltage is high, that is, during the period when the circuit's feedback voltage is higher than the reference voltage, or at least before the error comparison voltage has flipped to a low level. Additionally, it also needs to ensure that the light-load delay signal does not conflict with the peak time of the inductor current; in other words, the light-load delay signal will not occur when the upper transistor is turned on.

[0028] In addition, by adding an adaptive turn-off time control signal, it can be ensured that the circuit has completed the adaptive turn-off time after the upper transistor is turned off. Therefore, the inductor current can be maintained at close to 0A, and the duty cycle of the voltage converter can be extended by controlling the light load delay signal.

[0029] Preferably, the error comparison voltage is in a high-level state when the feedback voltage of the voltage converter is greater than the reference voltage, and in a low-level state when the feedback voltage is less than the reference voltage.

[0030] The feedback voltage Vfb, reference voltage Vref, and the error amplifier used to compare the two can be implemented with reference to existing technologies.

[0031] Preferably, the inductor peak signal is output based on the relationship between the magnitude of the inductor current in the voltage converter and the preset maximum inductor current; when the inductor current is equal to the preset maximum inductor current, the inductor peak signal is in a high-level state; when the inductor current is less than the preset maximum inductor current, the inductor peak signal is in a low-level state.

[0032] Understandably, the inductor peak signal enables real-time sampling of the inductor current while simultaneously designing the maximum inductor current. When the sampled inductor current equals or even exceeds the maximum inductor current, the state of the upper transistor is immediately changed, turning it off and turning it on, thereby reducing the inductor current.

[0033] Therefore, when the inductor current increases instantaneously to the current peak value, an inductor peak signal will be generated. This signal can also indicate the switching time of the upper transistor's on and off states.

[0034] Preferably, the adaptive turn-off time control signal is generated based on the current duty cycle of the voltage converter; starting from the turn-off of the upper transistor and the turn-on of the lower transistor of the voltage converter, the adaptive turn-off time is calculated based on the current duty cycle, and after the adaptive turn-off time ends, the adaptive turn-off time control signal is set to an instantaneous high level state.

[0035] In existing technologies, an adaptive on-time (AOT) control circuit is typically required in such DC-DC converters to prevent premature turn-on of the high-side power transistor due to interference or noise during the period when the inductor current signal decreases in each cycle, thus preventing the DC-DC converter from operating too fast. According to existing technologies, the adaptive on-time can be designed based on the circuit's duty cycle, which is calculated as the ratio of the output voltage to the input voltage. Therefore, the adaptive on-time of the circuit is dynamically designed based on the output voltage and the circuit's duty cycle.

[0036] In order to ensure that the circuit logic in this invention does not affect the confirmation of the adaptive turn-off time in the prior art, an OFF signal is added to the circuit, so that the light load delay signal will not enter the high level state until at least after the adaptive turn-off time has ended, and control the lower transistor to turn off.

[0037] Preferably, when the light load delay signal is high, both the upper and lower transistors of the voltage converter are in the off state; when the light load delay signal is low, the upper and lower transistors of the voltage converter are turned on or off based on the PWM signal output by the turn-off control unit.

[0038] In this circuit, the PWM_ENB signal is the light load delay signal. This signal is generated based on the multiple signals mentioned above, thereby increasing the time period during which the upper and lower transistors are simultaneously turned off while maintaining the original logic of the circuit.

[0039] In one embodiment of the present invention, the simultaneous cutoff time of the upper and lower transistors is 30 μs. This setting allows the inductor current to remain stable for a period of time during its decrease. Simultaneously, during this period, the inductor current will not be too high or too low, thus making it less susceptible to external interference, thereby maintaining circuit stability and adjusting the circuit frequency.

[0040] Preferably, the shutdown control unit includes a third RS flip-flop; the S terminal of the third RS flip-flop is connected to the inductor peak signal, the R terminal is connected to the negative inductor current limiting signal, and the Q terminal outputs a PWM signal.

[0041] In addition, the logic of the shutdown control unit in this invention is similar to that of the PWM signal generation logic in the prior art. Since the inductor current is limited to between the maximum inductor current and the maximum negative inductor current in this invention, the above two related signals are needed to limit the turn-on and turn-off times of the upper and lower transistors.

[0042] Preferably, the negative inductor current limiting signal is output based on the relationship between the magnitude of the inductor current in the voltage converter and the preset maximum negative inductor current; when the inductor current is equal to the preset maximum negative inductor current, the inductor peak signal is in a high-level state; when the inductor current is greater than the preset maximum negative inductor current, the inductor peak signal is in a low-level state.

[0043] Preferably, when the PWM signal is high, the upper transistor of the voltage converter is turned on and the lower transistor is turned off; when the PWM signal is low, the upper transistor of the voltage converter is turned off.

[0044] It is understandable that for a PWM signal, its rising edge is controlled by the time of the maximum negative inductor current, and its falling edge is controlled by the time of the maximum inductor current. By controlling both, the time when the upper transistor is turned on and the lower transistor is turned off can be determined.

[0045] Adding the logic of the light-load delay signal in this invention enables reasonable limitation of the inductor current. It should be noted that if the circuit cannot operate in light-load mode, then under the control of relevant parameters, after the adaptive turn-off time and a 30μs delay, the circuit has entered the next cycle, and the PFM_ENB signal will not be generated normally, thus not affecting the original logic of the circuit.

[0046] A second aspect of the present invention relates to an adaptive turn-off time control method, which is implemented using an adaptive turn-off time control circuit from the first aspect of the present invention.

[0047] The beneficial effect of the present invention is that, compared with the prior art, the adaptive turn-off time control circuit of the present invention, by adjusting the turn-off time of the lower transistor in the voltage converter, thereby limiting the time interval between multiple conductions of the upper transistor, further modifies the operating frequency of the voltage converter to a range beyond the human ear.

[0048] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A control circuit for adaptive turn-off time, characterized in that: The circuit is used in the voltage converter PWM unit and includes a light-load delay unit and a shutdown control unit; wherein, The light-load delay unit is connected to the shutdown control unit and is used to provide the shutdown delay of the lower transistor of the voltage converter to the shutdown control unit. The light-load delay unit includes an inverter, a first RS flip-flop, a second RS flip-flop, a pulse generator, and a timer; wherein, The input terminal of the inverter is connected to the error comparison voltage of the voltage converter, and the output terminal is connected to the R terminal of the first RS flip-flop. The S terminal of the first RS flip-flop is connected to the inductor peak signal, and the Q inverse terminal is connected to the R terminal of the second RS flip-flop. The S terminal of the second RS flip-flop is connected to an adaptive turn-off time control signal, and the Q terminal is connected to the input terminal of the pulse generator; The output terminal of the pulse generator is connected to the input terminal of the timer, and the output terminal of the timer generates a light-load delay signal. The shutdown control unit, based on the inductor current limiting logic in the voltage converter, realizes the on and off control of the upper and lower transistors of the voltage converter.

2. The adaptive turn-off time control circuit according to claim 1, characterized in that: The error comparison voltage is high when the feedback voltage of the voltage converter is greater than the reference voltage, and low when the feedback voltage is less than the reference voltage.

3. The adaptive turn-off time control circuit according to claim 2, characterized in that: The inductor peak signal is output based on the relationship between the magnitude of the inductor current in the voltage converter and the preset maximum inductor current. When the inductor current is equal to the preset maximum inductor current, the inductor peak signal is in a high-level state; When the inductor current is less than the preset maximum inductor current, the inductor peak signal is in a low-level state.

4. The adaptive turn-off time control circuit according to claim 3, characterized in that: The adaptive turn-off time control signal is generated based on the current duty cycle of the voltage converter; Starting from the moment the upper transistor of the voltage converter is turned off and the lower transistor is turned on, the adaptive turn-off time is calculated based on the current duty cycle, and after the adaptive turn-off time ends, the adaptive turn-off time control signal is set to a momentary high level.

5. The adaptive turn-off time control circuit according to claim 4, characterized in that: When the light load delay signal is high, both the upper and lower transistors of the voltage converter are in the off state. When the light load delay signal is low, the upper and lower transistors of the voltage converter are turned on or off based on the PWM signal output by the shutdown control unit.

6. The adaptive turn-off time control circuit according to claim 5, characterized in that: The shutdown control unit includes a third RS trigger; The S terminal of the third RS flip-flop is connected to the peak signal of the inductor, the R terminal is connected to the current limiting signal of the negative inductor, and the Q terminal outputs a PWM signal.

7. The adaptive turn-off time control circuit according to claim 6, characterized in that: The negative inductor current limiting signal is output based on the relationship between the magnitude of the inductor current in the voltage converter and the preset maximum negative inductor current. When the inductor current is equal to the preset maximum negative inductor current, the inductor peak signal is in a high-level state; When the inductor current is greater than the preset maximum negative inductor current, the inductor peak signal is in a low-level state.

8. The adaptive turn-off time control circuit according to claim 7, characterized in that: When the PWM signal is high, the upper transistor of the voltage converter is turned on and the lower transistor is turned off. When the PWM signal is low, the upper transistor of the voltage converter is turned off.

9. A control method for adaptive turn-off time, characterized in that: The method is implemented using an adaptive turn-off time control circuit as described in any one of claims 1-8.

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