Signal transmission method, circuit and memory

Abstract

The present application provides a signal transmission method, circuit and memory, which can, when receiving a first external signal, if the external signal has a narrow pulse, process the first signal and output a second signal that does not include the narrow pulse to the memory for processing; if the external signal does not have a narrow pulse, directly output the first signal to the memory for processing, thereby eliminating the narrow pulse of the external signal received by the memory, so that the narrow pulse of the external signal will not affect the normal processing of the external signal inside the memory, thereby improving the accuracy of the memory in processing the signal.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a signal transmission method, circuit, and memory. Background Art

[0002] Memory is a device commonly used in electronic devices to store data. Taking dynamic random access memory (DRAM) as an example, DRAM uses the principles of semiconductor memory to represent a binary bit (1 or 0) by the amount of charge stored in a capacitor.

[0003] In the existing technology, with the continuous development of semiconductor technology, the operating frequency that DRAM can achieve is getting higher and higher. There are more and more analog and digital devices on the DRAM itself and the platform on which it is located. As a result, the external signals received by the DRAM are easily interfered with by other devices when the DRAM is working, which in turn causes narrow pulses to be generated on the external signals received by the DRAM, affecting the accuracy of the DRAM's subsequent processing of the external signals.

[0004] Therefore, how to eliminate the narrow pulses of the external signal received by the memory is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] The present application provides a signal transmission method, circuit and memory to eliminate narrow pulses of external signals received by the memory.

[0006] In a first aspect, the present application provides a signal transmission circuit, comprising: a signal processing module, which receives an input first signal, processes the first signal according to a preset processing method to obtain a second signal, and uses the second signal as the output signal of the signal processing module; a selection module, which receives the input first signal, the second signal and a control signal, and uses the first signal or the second signal as the output signal of the selection module according to the control signal.

[0007] In an embodiment of the first aspect of the present application, the signal transmission circuit further includes: a control module, which sends the control signal to the selection module.

[0008] In an embodiment of the first aspect of the present application, the signal processing module also receives the control signal; when the control signal corresponds to the first state, the signal processing module processes the first signal according to a preset processing method to obtain a second signal; when the control signal corresponds to the second state, the signal processing module sets the second signal to a fixed value.

[0009] In an embodiment of the first aspect of the present application, the preset processing method includes: when the first signal is a pulse signal, setting the signal between two adjacent pulses in the first signal to a low level.

[0010] In an embodiment of the first aspect of the present application, the signal processing module includes: a shift unit, which shifts the first signal according to a clock cycle of the first signal and outputs it to a latch unit; a latch unit, which latches the received signal and outputs it to a logic processing unit; and a logic processing unit, which outputs the second signal according to the received signal.

[0011] In an embodiment of the first aspect of the present application, the shift unit includes: an N-bit serial shift register, wherein N is a first clock number corresponding to the period of the first signal; an input end of the N-bit serial shift register receives the first signal; the Mth shift register in the N-bit serial shift register outputs a first shift signal after M-bit shift processing to the latch unit; wherein M is a second clock number corresponding to the pulse length of the first signal; and an output end of the N-bit serial shift register outputs a second shift signal after N-bit shift processing to the latch unit.

[0012] In an embodiment of the first aspect of the present application, the latch unit includes: an edge-triggered latch; the first input end of the edge-triggered latch receives the first shift signal, the second input end receives the second shift signal, and the output end is used to output the latched signal to the logic processing unit.

[0013] In an embodiment of the first aspect of the present application, the edge-triggered latch is specifically used to: when the first edge of the first shift signal is detected, output a signal of the first level through the output end before the second edge of the second shift signal is detected; when the second edge of the second shift signal is detected, output a signal of the second level through the output end before the first edge of the first shift signal is detected.

[0014] In an embodiment of the first aspect of the present application, the first level is opposite to the pulse signal level of the first signal; and the second level is the same as the pulse signal level of the first signal.

[0015] In an embodiment of the first aspect of the present application, the signal transmission circuit is applied to the memory to receive a first signal from the outside, and the control module is specifically configured to: when the memory is in a test state, send a control signal corresponding to the first state to the selection module; when the memory is in a normal working state, send a control signal corresponding to the second state to the selection module.

[0016] A second aspect of the present application provides a memory comprising the signal transmission circuit as described in any one of the first aspects of the present application.

[0017] The third aspect of the present application provides a signal transmission method, which can be used to execute the signal transmission circuit provided in the first aspect, including: obtaining a control signal and a first signal; outputting the first signal according to the control signal, or processing the first signal according to a preset processing method to obtain a second signal, and outputting the second signal.

[0018] In an embodiment of the third aspect of the present application, the preset processing method includes: when the first signal is a pulse signal, setting the signal between two adjacent pulses in the first signal to a low level.

[0019] In an embodiment of the third aspect of the present application, the processing of the first signal according to a preset processing method to obtain the second signal includes: performing M-bit shift processing on the first signal to obtain a first shifted signal; wherein M is the second clock number corresponding to the pulse length of the first signal; performing N-bit shift processing on the first signal to obtain a second shifted signal; wherein N is the first clock number corresponding to the period of the first signal; and obtaining the second signal based on the first edge of the first shift signal and the second edge of the second shift signal.

[0020] In an embodiment of the third aspect of the present application, obtaining the second signal based on the first edge of the first shift signal and the first edge of the second shift signal includes: when the first edge of the first shift signal is detected, before the second edge of the second shift signal is detected, a signal of a first level is output through the output end to obtain the second signal, and the first level is opposite to the pulse signal level of the first signal; when the second edge of the second shift signal is detected, before the first edge of the first shift signal is detected, a signal of a second level is output through the output end to obtain the second signal, and the second level is the same as the pulse signal level of the first signal.

[0021] In summary, the signal transmission method, circuit and memory provided by the present application can, when receiving a first external signal, if the external signal has a narrow pulse, output the second signal that does not include the narrow pulse after processing the first signal to the memory for processing; if the external signal does not have a narrow pulse, the first signal will be directly output to the memory for processing, thereby eliminating the narrow pulse of the external signal received by the memory, so that the narrow pulse of the external signal will not affect the normal processing of the external signal inside the memory, thereby improving the accuracy of the memory in processing the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0023] Figure 1 A schematic diagram of an application scenario for this application;

[0024] Figure 2 A schematic diagram of a waveform of an external signal received by the memory;

[0025] Figure 3 A schematic structural diagram of an embodiment of a memory provided by this application;

[0026] Figure 4 A schematic structural diagram of an embodiment of a signal transmission circuit provided by the present application;

[0027] Figure 5 A waveform diagram of an embodiment of a signal processed by the signal processing module provided in this application;

[0028] Figure 6 A schematic structural diagram of another embodiment of the signal transmission circuit provided by the present application;

[0029] Figure 7 A waveform diagram of another embodiment of a signal processed by the signal processing module provided by the present application;

[0030] Figure 8 A schematic structural diagram of another embodiment of the signal transmission circuit provided by the present application;

[0031] Figure 9 A schematic structural diagram of another embodiment of the signal transmission circuit provided by the present application;

[0032] Figure 10 A schematic structural diagram of the shift unit provided in this application;

[0033] Figure 11 This is a schematic diagram of the signal waveforms transmitted by each unit in the signal transmission circuit provided in this application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0035] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] Figure 1 This is a schematic diagram of an application scenario of this application, such as Figure 1 It shows the manner in which the memory 1 receives an external signal, wherein the interface 10 provided in the memory 1 receives the external signal and transmits the received external signal to the memory 1 for processing.

[0037] In some embodiments, the processing unit 11 can be a logic circuit with signal processing capabilities, etc., and the external signal received by the memory 1 can be directly sent to the processing unit 11 in the memory 1, and the processing unit 11 performs subsequent further processing on the external signal. This application does not limit the specific processing of the external signal by the processing unit 11.

[0038] In some embodiments, the interface 10 may be a physical device provided by the memory 1 for receiving external signals, such as a chip, circuit, logic circuit, etc. for receiving signals; in other embodiments, the interface 10 may be a physical device for drawing Figure 1 The virtual module, for example, the processing unit 11 can receive an external signal through one of its pins or connected wires, and the pin or wire for receiving the external signal is in Figure 1 It can be abstracted as interface 10.

[0039] Figure 2 This is a waveform diagram of the external signal received by the memory, where it is assumed that Figure 1 The memory 1 shown is receiving a signal ① sent from an external device connected to the memory 1. Figure 2In the example, signal ① is a standard square wave signal with a period of T. Since signal ① can be understood as the signal actually sent by the external signal without any change or interference, and is also the form that the memory 1 hopes to receive, it can be recorded as the target (Purpose) signal. However, in the actual operation of the memory, the external signal received is easily interfered with by other devices, which in turn causes narrow pulses to be generated on the external signal received by the memory. For example, although the external device gives Figure 1 The memory 1 shown sends signal ①, but the external signal actually received by the memory 1 is signal ② with glitches on the waveform, so that after the internal processing unit 11 of the memory 1 performs smoothing and other processing on signal ②, a signal ③ with narrow pulses is obtained. Finally, the processing unit 11 should have processed signal ①, but due to the problem of receiving the external signal, the processing unit 11 actually processes signal ③. The narrow pulse in signal ③ will affect the normal operation of the processing unit 11 and reduce the accuracy of the processing unit 11 when processing the signal.

[0040] Therefore, the present application also provides a signal transmission method, circuit and memory for eliminating the narrow pulses of external signals received by the memory, so that the narrow pulses of the external signals will not affect the normal processing of the external signals inside the memory, thereby improving the accuracy of the memory in processing signals.

[0041] The following specific embodiments are used to describe the technical solution of the present application in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0042] Figure 3 This is a schematic diagram of the structure of an embodiment of the memory provided by this application, as shown in FIG. Figure 3 The memory shown is Figure 1 On the basis of the illustrated embodiment, a signal transmission circuit 12 is further included between the interface 10 and the processing unit 11, so that the external signal received by the memory 12 through the interface 10 is processed by the signal transmission circuit 12 and then sent to the processing unit 11 inside the memory for subsequent processing.

[0043] Figure 4 This is a schematic diagram of the structure of an embodiment of the signal transmission circuit provided by the present application, as shown in FIG. Figure 4 Shown as Figure 3 A specific implementation of the signal transmission circuit 12 shown in FIG. 1 includes a signal processing module 121 and a selection module 122 .

[0044] Among them, the signal processing module 121 is used to receive an external signal (recorded as a first signal, or recorded as ExternalSignal, etc.), and can be used to process the first signal according to a preset processing method to obtain a second signal (recorded as Internal Signal, etc.), and output the second signal as the output signal of the signal processing module 121 to the selection module 122.

[0045] In some embodiments, the signal processing module 121 can be specifically used to remove the narrow pulse signal between two adjacent pulses in the first signal. This process can also be understood as smoothing the signal between adjacent valid square wave pulse signals in the first signal. For example, Figure 5 This is a waveform diagram of a signal processed by the signal processing module provided in this application, wherein the signal processing module receives 121 as shown in FIG. Figure 5 After the signal ④ shown in the figure is obtained, the first pulse and the second pulse in the signal ④ are kept unchanged. These two pulses are valid pulse signals, and the narrow pulse between the first pulse and the second pulse due to the transmission burr is removed, so that the first pulse and the second pulse are kept at a low level, thereby obtaining the signal ⑤, and outputting the signal ⑤ as the second signal to the selection module 122. It can be understood that, as Figure 5 Taking the pulse signal as a high level as an example, accordingly, if the pulse signal of the first signal is a low level, the signal processing module 121 can also keep the signal between two valid low-level square wave pulses at a high level, thereby obtaining a second signal after eliminating the narrow pulse.

[0046] The selection module 122 can be configured to receive a first signal from an external input of the memory and a second signal from the signal processing module 121. In this case, the selection module 122 can select between the first signal and the second signal, selecting either the first signal or the second signal as the output of the selection module 122. In this case, the output signal of the selection module 122 is also the output signal of the signal transmission circuit 122. The selection module 122 can specifically select between the first signal and the second signal based on a control signal, where the control signal can be sent by the memory control module. In one specific implementation, the selection module 123 can be a data multiplexer (MUX).

[0047] In some embodiments, Figure 6 This is a schematic diagram of the structure of another embodiment of the signal transmission circuit provided by the present application. The control module 123 can be as follows Figure 6In the illustrated example, the control module 123 is provided within the signal transmission circuit 12 and is configured to send a control signal (e.g., TM_Bolck) to the selection module 122, causing the selection module 122 to select and output the first signal or the second signal based on the control signal. Alternatively, in other embodiments, the control module 123 may be provided before the signal transmission circuit 12, such as the processing unit 11 within the memory 1. Alternatively, the control module 123 may be another unit within the memory 1 that is configured to send a control signal to the selection module 122. Alternatively, the control module 123 may be a unit outside the memory 1.

[0048] The selection module 122 can then determine whether to use the first signal or the second signal as the output signal based on the received control signal. For example, when the control signal received by the selection module 122 corresponds to the first state, the received second signal is used as the output signal. When the control signal received by the selection module 122 corresponds to the second state, the received first signal is used as the output signal. The first state and the second state can be different level states of the control signal. For example, the first state can be that the control signal is at a high level, and the second state can be that the control signal is at a low level, etc.

[0049] In some embodiments, the signal processing module 121 may also receive a control signal, and only when the control signal corresponds to the first state, it processes the first signal in a preset manner to obtain the second signal; and when the received control signal corresponds to the second state, since the selection module 122 outputs the first signal, the signal processing module 121 does not need to process the first signal, but can output a fixed value as the second signal, which can reduce redundant calculations and reduce energy consumption.

[0050] In some embodiments, the control module 123 may send control signals of different states to the selection module 122 according to different situations. For example, when the control module 123 determines that the current operating condition meets the trigger condition, indicating that the external signal received by the memory at this time may have a narrow pulse, the control module 123 sends a control signal of the first state to the selection module 122. When the control module 123 determines that the current operating condition does not meet the trigger condition and the possibility of the external signal having a narrow pulse is low, the control module 123 sends a control signal of the second state to the selection module. In another specific implementation scenario, when the memory is in a test state, the control module 123 may send a control signal of the first state to the selection module, and when the memory is in a normal working state, the control module sends a control signal of the second state to the selection module.

[0051] For example, Figure 6 The signal transmission circuit 1 shown receives the signal Figure 5The signal ④ shown is taken as an example. Since there is a narrow pulse in the signal ④ at this time, the control module 123 sends a control signal of the first state to the selection module 122. The signal processing module 121 obtains the signal ⑤ as the second signal input to the selection module 122 according to the signal ④. After the selection module 122 receives the signal ④ and the signal ⑤ at the same time, it uses the signal ⑤ as the output signal of the selection module according to the control signal of the first state.

[0052] Again illustratively, Figure 7 This is a waveform diagram of another embodiment of a signal processed by the signal processing module provided by the present application, Figure 8 This is a structural diagram of another embodiment of the signal transmission circuit provided by the present application. Figure 8 The signal transmission circuit 1 shown receives the signal Figure 7 As shown in the signal ⑥, since there is no narrow pulse in the signal ⑥, the control module 123 sends the control signal of the second state to the selection module 122. The selection module 122 selects the signal ⑥ as the output signal of the selection module according to the control signal of the second state. Figure 8 In the state shown, the signal processing module 121 may not output the second signal to the selection module 122 according to the received control signal.

[0053] In some embodiments, Figure 9 This is a structural diagram of another embodiment of the signal transmission circuit provided by the present application, as shown in FIG. Figure 9 FIG. 1 shows a specific implementation of the signal processing module 121 in the signal transmission circuit 12. Figure 9 The signal processing module 121 shown specifically includes: a shift unit 1211 , a latch unit 1212 and a logic processing unit 1213 .

[0054] The latch unit 1211 is used to receive the first signal and the clock signal, and shift the first signal according to the clock cycle of the first signal, and then output it to the latch unit 1212. In some embodiments, Figure 10 The schematic diagram of the structure of the shift unit provided in this application is as follows: Figure 10 The shift unit 1211 shown specifically includes: an N-bit serial shift register, where N is the first clock number corresponding to the cycle of the first signal. Figure 10 In the figure, a shift register is represented by a square block diagram. Each input terminal D receives the front-end input signal, CLK clock signal, and Q outputs the signal to the next stage. In particular, the input terminal D of the first shift register in the N-bit serial shift register receives the first signal.

[0055] In some embodiments, in addition to outputting a second shift signal that shifts the first signal by N bits to the subsequent latch unit 1212, the output end of the N-bit serial shift register also outputs a first shift signal that shifts the first signal by M bits to the latch unit 1212, where M is the second clock number corresponding to the pulse length of the first signal.

[0056] Combine Figure 11 The above process is described, wherein: Figure 11 This is a schematic diagram of the signal waveform transmitted by each unit in the signal transmission circuit provided in this application, as shown in FIG. Figure 9-10 The shift unit 1211 shown will receive Figure 11 The signal ⑨ shown is used as the clock signal (CLK), and the signal ④ with a narrow pulse is used as the first signal. At the same time, the shift unit 1211 also receives the control signal ⑩ sent by the control module 123 (not shown in FIG. Figure 11 ). Figure 11 In the example shown, the length of the first signal ④ is N clocks N*CLK, and the length of the effective square wave pulse of the first signal ④ is M clocks M*CLK. Figure 11 In the example, M=1 is taken.

[0057] The M=1 shift register in the shift unit 1211 can shift the signal ④ and obtain the signal ⑥ as the first shift signal (recorded as First latch signal, etc.) for output. Figure 10 Since it is a signal output through the nQ output port of the shift register, the level of signal ⑥ is opposite to that of signal ④ and is shifted backward by 1 CLK time. At the same time, the Q output port of the Nth shift register in the shift unit 1211 also outputs a second shift signal (denoted as After shift, etc.), and the second shift signal is Figure 11 From the signal ⑦ in the figure, we can see that the signal ⑦ is shifted backward by N CLK times compared with the signal ④.

[0058] In some embodiments, the latch unit specifically includes: an edge-triggered latch, wherein the edge-triggered latch receives the above-mentioned first shift signal ⑥ and second shift signal ⑦, and the edge-triggered latch specifically generates a signal for removing the narrow pulse based on the states of signal ⑥ and signal ⑦.

[0059] For example, referring to Figure 11, when the edge-triggered latch detects the first edge a of the first shift signal ⑥ (in this embodiment, the first edge is taken as a falling edge as an example, it can also be a rising edge), the edge-triggered latch outputs a signal of the first level through the output terminal (the first level can be a level opposite to the pulse level of the first signal, for example, in this embodiment, the pulse level of the first signal is a high level, then the first level is a low level), and maintains the latch output of the first level before detecting the second edge c of the second shift signal ⑦. Subsequently, when the edge-triggered latch detects the second edge c of the second shift signal ⑦ (in this embodiment, the second edge is taken as a falling edge as an example, it can also be a rising edge), the edge-triggered latch outputs a signal of the second level through the output terminal (the second level can be the same level as the pulse level of the first signal, for example, in this embodiment, the pulse level of the first signal is a high level, then the second level is a high level), and maintains the latch output of the second level before the next detection of the first edge e of the first shift signal ⑥. By analogy, the final latch unit 1212 outputs the following to the logic processing unit 1213: Figure 11 Signal ⑧ is shown.

[0060] Signal ⑧ is processed by the logic processing unit 1213 to obtain signal ⑤. Figure 9 and Figure 11 For example, a “logical AND” operation is performed on signal ⑧ and signal ④ to obtain signal ⑤. Then, the signal ⑤ output by the logic processing unit 1213 is the second signal obtained after being processed by the entire signal processing module 121.

[0061] In summary, the signal transmission circuit provided in the embodiment of the present application can, when receiving a first external signal, if the external signal has a narrow pulse, output the second signal that does not include the narrow pulse after processing the first signal to the memory for processing; if the external signal does not have a narrow pulse, the first signal will be directly output to the memory for processing, thereby eliminating the narrow pulse of the external signal received by the memory, so that the narrow pulse of the external signal will not affect the normal processing of the external signal inside the memory, thereby improving the accuracy of the memory in processing the signal.

[0062] The present application also provides a signal transmission method, which can be Figure 3 The signal transmission circuit 12 in the memory 1 shown is executed. At this time, the signal transmission circuit 12 can be understood as a processor and can execute the signal transmission method by software processing. Specifically, the method includes:

[0063] S1: Obtaining a control signal and a first signal. For the description of the control signal and the first signal, please refer to the above embodiments of the present application and will not be repeated here.

[0064] S2: outputting a first signal according to the control signal, or; processing the first signal according to a preset processing method according to the control signal to obtain a second signal, and outputting the second signal.

[0065] In some embodiments, the preset processing method is to remove the narrow pulse signal between two adjacent pulses in the first signal, for example, by setting the signal between two adjacent pulses in the first signal to a low level. More specifically, processing the first signal according to the preset method to obtain the second signal includes: performing M-bit shifting on the first signal to obtain a first shifted signal, where M is the second clock number corresponding to the pulse length of the first signal; performing N-bit shifting on the first signal to obtain a second shifted signal, where N is the first clock number corresponding to the period of the first signal; and obtaining the second signal based on a first edge of the first shifted signal and a second edge of the second shifted signal.

[0066] In some embodiments, the above process of obtaining the second signal based on the first edge and the second edge specifically includes: when the first edge of the first shift signal is detected, before the second edge of the second shift signal is detected, a first level signal is output through the output end to obtain the second signal, and the first level is opposite to the pulse signal level of the first signal; when the second edge of the second shift signal is detected, before the first edge of the first shift signal is detected, a second level signal is output through the output end to obtain the second signal, and the second level is the same as the pulse signal level of the first signal. The specific process can be referred to as follows Figure 11 The processing process shown will not be repeated here.

[0067] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal transmission circuit, characterized in that: include: a signal processing module that receives a first input signal, processes the first signal according to a preset processing method to obtain a second signal, and uses the second signal as an output signal of the signal processing module; a selection module, which receives the first signal, the second signal, and a control signal as input, and uses the first signal or the second signal as an output signal of the selection module according to the control signal; a control module configured to send the control signal to the selection module; The signal processing module further receives the control signal; When the control signal corresponds to the first state, the signal processing module processes the first signal according to a preset processing method to obtain a second signal; When the control signal corresponds to a second state, the signal processing module sets the second signal to a fixed value; The preset processing methods include: When the first signal is a pulse signal, setting a signal between two adjacent pulses in the first signal to a low level; The signal processing module includes: a shift unit, configured to shift the first signal according to a clock cycle of the first signal and output the shifted signal to a latch unit; A latch unit, which latches the received signal and outputs it to the logic processing unit; A logic processing unit is configured to output the second signal according to the received signal.

2. The circuit according to claim 1, wherein: The shift unit comprises: An N-bit serial shift register, wherein N is the number of first clocks corresponding to the period of the first signal; An input end of the N-bit serial shift register receives the first signal; The M-th shift register in the N-bit serial shift register outputs a first shift signal after M-bit shifting to the latch unit; wherein M is a second clock number corresponding to the pulse length of the first signal; The output end of the N-bit serial shift register outputs a second shift signal after N-bit shift processing to the latch unit.

3. The circuit according to claim 2, characterized in that The latch unit includes: an edge-triggered latch; The first input terminal of the edge-triggered latch receives the first shift signal, the second input terminal receives the second shift signal, and the output terminal is used to output the latched signal to the logic processing unit.

4. The circuit according to claim 3, characterized in that The edge-triggered latch is specifically used for: When a first edge of the first shift signal is detected, before a second edge of the second shift signal is detected, a signal of a first level is output through the output terminal; When the second edge of the second shift signal is detected, a signal of a second level is outputted through the output terminal before the first edge of the first shift signal is detected.

5. The circuit according to claim 4, characterized in that The first level is opposite to the pulse signal level of the first signal; The second level is the same as a pulse signal level of the first signal.

6. The circuit according to any one of claims 1 to 5, characterized in that: The signal transmission circuit is used for the memory to receive a first signal from the outside, and the control module is specifically configured as follows: When the memory is in the test state, sending a control signal corresponding to the first state to the selection module; When the memory is in a normal working state, a control signal corresponding to the second state is sent to the selection module.

7. A memory, characterized in that: The method comprises the signal transmission circuit according to any one of claims 1 to 5.

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