Copper base substrate

Abstract

The copper base substrate of the present invention is a copper base substrate in which a copper substrate, an insulating layer, and a circuit layer are sequentially stacked, the ratio of the thickness (unit: μm) of the insulating layer to the elastic modulus (unit: GPa) of the insulating layer at 100°C is 50 or more, and the elastic modulus of the circuit layer at 100°C is 100 GPa or less.

Description

Technical Field

[0001] This invention relates to a copper substrate.

[0002] This application claims priority based on Japanese Patent Application No. 2020-065163, filed on March 31, 2020, the contents of which are incorporated herein by reference. Background Technology

[0003] Metal substrates are known as substrates for mounting electronic components such as semiconductor devices and LEDs. A metal substrate is a laminate consisting of a metal substrate, an insulating layer, and a circuit layer stacked sequentially. The insulating layer is typically formed of an insulating composition comprising a resin with excellent insulation and voltage resistance, and an inorganic filler with excellent thermal conductivity. Electronic components are mounted on the circuit layer using solder. In this type of metal substrate, heat generated in the electronic components is transferred to the metal substrate via the insulating layer and dissipated from the metal substrate to the outside.

[0004] Regarding metal substrates, if there is a significant difference in the coefficient of thermal expansion between the metal substrate and the electronic components bonded to it via solder, the stress applied to the solder that bonds the electronic components to the circuit layer of the metal substrate due to the switching on / off of the electronic components or thermal cycling caused by the external environment will increase, potentially leading to solder cracks. Therefore, research is underway to reduce the elastic modulus of the insulating layer of the metal substrate in order to mitigate the difference in the coefficient of thermal expansion between the metal substrate and the electronic components using the insulating layer (Patent Documents 1 and 2).

[0005] Patent Document 1: Japanese Patent Application Publication No. 11-87866

[0006] Patent Document 2: Japanese Patent Application Publication No. 2016-111171

[0007] To suppress solder cracking caused by thermal cycling during the installation of electronic components and improve reliability under thermal cycling conditions, reducing the elastic modulus of the insulating layer of the metal substrate to make the insulating layer more deformable, thereby mitigating the thermal stress caused by the expansion of the metal substrate, is effective. However, since there is also stress on the solder caused by the expansion of the circuit layers, improving reliability under thermal cycling solely by reducing the elastic modulus of the insulating layer of the metal substrate has limitations. Summary of the Invention

[0008] The present invention was made in view of the above circumstances, and its object is to provide a metal substrate with excellent reliability in thermal cycling when electronic components are mounted.

[0009] To address the aforementioned issues, the metal substrate of the present invention is a copper substrate having a copper substrate, an insulating layer, and a circuit layer sequentially stacked. The metal substrate is characterized in that the ratio of the thickness (in μm) of the insulating layer to the elastic modulus (in GPa) of the insulating layer at 100°C is 50 or more, and the elastic modulus of the circuit layer at 100°C is 100 GPa or less.

[0010] According to the copper substrate of the present invention, since the ratio of the thickness (in μm) of the insulating layer to the elastic modulus (in GPa) of the insulating layer at 100°C is high, exceeding 50, the insulating layer is easily deformable, and the insulating layer can mitigate the difference in thermal expansion coefficients between the metal substrate and the electronic components caused by thermal cycling. Furthermore, the elastic modulus of the circuit layer at 100°C is low, below 100 GPa, thus reducing the difference in thermal expansion coefficients between the circuit layer and the electronic components caused by thermal cycling. Therefore, the stress applied to the solder that bonds the electronic components to the circuit layer of the copper substrate due to thermal cycling can be reduced. Consequently, the reliability of the copper substrate of the present invention against thermal cycling is improved when electronic components are mounted.

[0011] Here, in the copper substrate of the present invention, the insulating layer may comprise a polyimide resin, a polyamide-imide resin, or a mixture thereof.

[0012] In this case, because the insulating layer contains these resins, the insulation, voltage resistance, chemical resistance and mechanical properties of the copper substrate are improved.

[0013] Furthermore, in the copper substrate of the present invention, the insulating layer may contain inorganic fillers, wherein the average particle size of the inorganic fillers is in the range of 0.1 μm or more and 20 μm or less.

[0014] In this case, since the insulating layer contains the aforementioned inorganic filler, the thermal conductivity and voltage resistance of the copper substrate are improved.

[0015] Furthermore, in the copper substrate of the present invention, the circuit layer may be composed of copper foil, copper alloy foil, aluminum foil, or aluminum alloy foil.

[0016] In this case, since the circuit layer is made of copper foil, copper alloy foil, aluminum foil, or aluminum alloy foil, it has high conductivity, which allows the circuit layer to be thinned.

[0017] According to the present invention, a copper substrate with excellent reliability in thermal cycling when electronic components are mounted can be provided. Attached Figure Description

[0018] Figure 1 This is a schematic cross-sectional view of a copper substrate according to an embodiment of the present invention. Detailed Implementation

[0019] Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

[0020] Figure 1 This is a schematic cross-sectional view of a copper substrate according to an embodiment of the present invention.

[0021] exist Figure 1 In this embodiment, the copper substrate 10 is a laminate consisting of a copper substrate 20, an insulating layer 30, and a circuit layer 40 stacked sequentially. On the circuit layer 40 of the copper substrate 10, terminals 61 of electronic components 60 are mounted using solder 50.

[0022] The copper substrate 20 is a component that forms the base of the copper substrate 10. The copper substrate 20 is made of copper or a copper alloy.

[0023] The insulating layer 30 is used to insulate the copper substrate 20 from the circuit layer 40. The insulating layer 30 is formed of an insulating resin composition comprising an insulating resin 31 and an inorganic filler 32. By forming the insulating layer 30 from an insulating resin composition comprising an insulating resin 31 with high insulating properties and an inorganic filler 32 with high thermal conductivity, the thermal resistance of the entire copper substrate 10 from the circuit layer 40 to the copper substrate 20 can be further reduced while maintaining insulation.

[0024] The insulating resin 31 preferably comprises polyimide resin, polyamide-imide resin, or a mixture thereof. These resins enhance the properties of the copper substrate 10 due to their excellent insulation, voltage resistance, chemical resistance, and mechanical properties.

[0025] The average particle size of the inorganic filler 32 is preferably in the range of 0.1 μm or more and 20 μm or less. Since the average particle size of the inorganic filler 32 is 0.1 μm or more, the thermal conductivity of the insulating layer 30 is improved. Since the average particle size of the inorganic filler 32 is 20 μm or less, the voltage withstand capability of the insulating layer 30 is improved. Furthermore, if the average particle size of the inorganic filler 32 is within the above-mentioned range, the inorganic filler 32 is less likely to form aggregated particles, making it easier to uniformly disperse the inorganic filler 32 in the insulating resin 31. If the inorganic filler 32 is dispersed in the insulating resin 31 as primary particles or similar fine particles without forming aggregated particles, the voltage withstand capability of the insulating layer 30 is improved. From the viewpoint of improving the thermal conductivity of the insulating layer 30, the average particle size of the inorganic filler 32 is preferably in the range of 0.3 μm or more and 20 μm or less.

[0026] The content of inorganic filler 32 in the insulating layer 30 is preferably in the range of 50% by volume or more and 85% by volume or less. Since the content of inorganic filler 32 is 50% by volume or more, the thermal conductivity of the insulating layer 30 is improved. On the other hand, since the content of inorganic filler 32 is 85% by volume or less, the voltage withstand capability of the insulating layer 30 is improved. Furthermore, if the content of inorganic filler 32 is within the above range, it is easier to uniformly disperse the inorganic filler 32 in the insulating resin 31. If the inorganic filler 32 is uniformly dispersed in the insulating resin 31, the mechanical strength of the insulating layer 30 is improved. From the viewpoint of improving the thermal conductivity of the insulating layer 30, the content of inorganic filler 32 is particularly preferably in the range of 50% by volume or more and 80% by volume or less.

[0027] As the inorganic filler 32, alumina (Al2O3) particles, alumina hydrate particles, aluminum nitride (AlN) particles, silicon dioxide (SiO2) particles, silicon carbide (SiC) particles, titanium oxide (TiO2) particles, boron nitride (BN) particles, etc., can be used. Among these fillers, alumina particles are preferred. Alumina particles are more preferably α-alumina particles. The ratio of tap density to true density (tap density / true density) of the α-alumina particles is preferably 0.1 or higher. The tap density / true density is related to the filling density of α-alumina particles in the insulating layer 30. If the tap density / true density is high, the filling density of α-alumina particles in the insulating layer 30 can be increased. If the filling density of α-alumina particles in the insulating layer 30 becomes higher, the spacing of the α-alumina particles in the insulating layer 30 becomes narrower, and pores (gases) are less likely to be generated in the insulating layer 30. The tap density / true density is preferably in the range of 0.2 or higher and 0.9 or lower. Furthermore, α-alumina can be polycrystalline particles, but monocrystalline particles are particularly preferred.

[0028] The ratio (thickness / elastic modulus) of the insulating layer 30 to its elastic modulus at 100°C is 50 or more. Because the thickness / elastic modulus of the insulating layer 30 is high (50 or more), the insulating layer 30 is easily deformable, resulting in high buffering capacity in the thickness direction. Therefore, the insulating layer 30 is more effective in mitigating the difference in thermal expansion rates between the copper substrate 20 and the circuit layer 40 caused by thermal cycling. The thickness / elastic modulus of the insulating layer 30 is preferably in the range of 50 or more and 20,000 or less, more preferably in the range of 50 or more and 2,000 or less, and even more preferably in the range of 50 or more and 200 or less. The elastic modulus of the insulating layer 30 at 100°C is preferably in the range of 0.01 GPa or more and 1 GPa or less, more preferably in the range of 0.01 GPa or more and 0.1 GPa or less. Furthermore, the thickness of the insulating layer 30 is preferably in the range of 10 μm or more and 200 μm or less, and more preferably in the range of 50 μm or more and 200 μm or less.

[0029] The circuit layer 40 is formed in the shape of a circuit pattern. On this circuit layer 40, which is formed in the shape of a circuit pattern, the terminals 61 of the electronic component 60 are joined by solder 50 or the like. The circuit layer 40 can be made of metals such as copper, copper alloy, aluminum, aluminum alloy, or gold. The circuit layer 40 is preferably made of copper foil, copper alloy foil, aluminum foil, or aluminum alloy foil.

[0030] Since the elastic modulus of the circuit layer 40 at 100°C is set to be 100 GPa or less, the stress applied to the solder due to the difference in thermal expansion rates between the circuit layer 40 and the electronic component 60 caused by thermal cycling is reduced. The elastic modulus of the circuit layer 40 at 100°C is preferably in the range of 50 GPa or more and 100 GPa or less. The thickness of the circuit layer 40 is preferably in the range of 20 μm or more and 200 μm or less.

[0031] The thicknesses of the copper substrate 20, insulating layer 30, and circuit layer 40 of the copper substrate 10 can be measured, for example, as follows: The copper substrate 10 is embedded in resin, and its cross-section is exposed by mechanical polishing. Then, the exposed cross-section of the copper substrate is observed using an optical microscope, and the thicknesses of the copper substrate 20, insulating layer 30, and circuit layer 40 are measured.

[0032] The elastic modulus of the copper substrate 20, insulating layer 30 and circuit layer 40 of the copper substrate 10 are values ​​measured at 100°C.

[0033] The elastic modulus (tensile elastic modulus) of the copper substrate 20 and circuit layer 40 of the copper substrate 10 can be measured, for example, by removing the insulating layer 30 of the copper substrate 10 with a solvent, thus separating the copper substrate 20 and the circuit layer 40. The elastic modulus of the obtained copper substrate 20 and circuit layer 40 is measured by dynamic viscoelasticity measurement. The elastic modulus of the insulating layer 30 of the copper substrate 10 can be measured, for example, by removing the copper substrate 20 and circuit layer 40 of the copper substrate 10 by etching, thus separating the insulating layer 30. The elastic modulus of the obtained insulating layer 30 is measured by dynamic viscoelasticity measurement.

[0034] Examples of electronic components 60 mounted on the copper substrate 10 of this embodiment are not particularly limited, and can include semiconductor elements, resistors, capacitors, quartz oscillators, etc. Examples of semiconductor elements include MOSFETs (Metal-oxide-semiconductor field-effect transistors), IGBTs (Insulated Gate Bipolar Transistors), LSIs (Large Scale Integration), LEDs (Light Emitting Diodes), LED chips, and LED-CSPs (LED-Chip-Size Packages).

[0035] The manufacturing method of the copper substrate 10 according to this embodiment will be described below.

[0036] The copper substrate 10 involved in this embodiment can be manufactured, for example, by a method including an insulating layer formation process and a circuit layer lamination process.

[0037] In the insulating layer formation process, an insulating layer 30 is formed on a copper substrate 20 to obtain a copper substrate with an insulating layer. Regarding the thickness of the insulating layer 30 (unit: μm), the insulating layer 30 for measuring elastic modulus is formed on the copper substrate 20, the elastic modulus of the obtained insulating layer 30 is measured, and a thickness is set to be 50 or more for the thickness / elastic modulus ratio. As a method for forming the insulating layer 30, a coating method or an electrodeposition method can be used.

[0038] The coating method is as follows: a coating liquid containing a solvent, an insulating resin, and an inorganic filler is applied to a copper substrate 20 to form a coating layer; then, the coating layer is heated to obtain an insulating layer 30. As the coating liquid, an inorganic filler-dispersed resin material solution can be used, which includes a resin material solution in which the insulating resin is dissolved and an inorganic filler dispersed in the resin material solution. As a method for applying the coating liquid to the substrate surface, spin coating, rod coating, blade coating, roller coating, squeegee coating, mold coating, gravure coating, dip coating, etc., can be used.

[0039] The electrodeposition method is as follows: a copper substrate 20 is immersed in an electrodeposition solution containing insulating resin particles and inorganic fillers; the insulating resin particles and inorganic fillers are electrodeposited on the substrate surface to form an electrodeposited film; then, the obtained electrodeposited film is heated to form an insulating layer 30. As the electrodeposition solution, an electrodeposition solution prepared by adding a poor solvent to the insulating resin material—containing an insulating resin solution and inorganic fillers dispersed in the insulating resin solution—can be used to cause the insulating resin to precipitate as particles.

[0040] In the circuit lamination process, metal foil is laminated on the insulating layer 30 of a copper substrate with an insulating layer. The resulting laminate is heated and pressurized simultaneously to form a circuit layer 40, thereby obtaining a copper substrate 10. The heating temperature of the laminate is, for example, 200°C or higher, more preferably 250°C or higher. The upper limit of the heating temperature is lower than the thermal decomposition temperature of the insulating resin, preferably a temperature 30°C lower than the thermal decomposition temperature. The pressure applied during lamination is, for example, in the range of 1 MPa or higher and 30 MPa or lower, more preferably in the range of 3 MPa or higher and 25 MPa or lower. The lamination time varies depending on the heating temperature or pressure, but is typically 10 minutes or more and 180 minutes or less.

[0041] According to the copper substrate 10 of this embodiment with the structure described above, since the ratio of the thickness (in μm) of the insulating layer 30 to the elastic modulus (in GPa) of the insulating layer 30 at 100°C is high, exceeding 50, the insulating layer 30 is easily deformed. Therefore, the insulating layer 30 can mitigate the difference in thermal expansion rates between the copper substrate 20 and the circuit layer 40 caused by thermal cycling. Furthermore, the elastic modulus of the circuit layer 40 at 100°C is low, below 100 GPa, thus reducing the difference in thermal expansion rates between the circuit layer 40 and the electronic component 60 caused by thermal cycling. Therefore, the stress applied to the solder 50 that bonds the electronic component 60 to the circuit layer 40 of the copper substrate 10 due to thermal cycling can be reduced. Consequently, the reliability of the copper substrate 10 of this embodiment under thermal cycling is improved when the electronic component 60 is mounted.

[0042] Furthermore, in the copper substrate 10 of this embodiment, when the insulating layer 30 comprises polyimide resin, polyamide-imide resin, or a mixture thereof, the insulation, voltage resistance, chemical resistance, and mechanical properties of the copper substrate 10 are improved. Additionally, when the insulating layer 30 comprises inorganic filler 32 and the average particle size of the inorganic filler 32 is in the range of 0.1 μm or more and 20 μm or less, the thermal conductivity and voltage resistance of the copper substrate 10 are improved. Furthermore, when the circuit layer 40 is composed of copper foil, copper alloy foil, aluminum foil, or aluminum alloy foil, due to its high conductivity, the thickness of the circuit layer 40 can be reduced.

[0043] The embodiments of the present invention have been described above, but the present invention is not limited thereto, and appropriate changes can be made without departing from the technical concept of the present invention.

[0044] Example

[0045] [Example 1 of the present invention]

[0046] A solvent-soluble polyimide solution was mixed with α-alumina powder (crystal structure: single crystal, average particle size: 0.7 μm) in a solid material (insulating layer) formed by heating, with the polyimide and α-alumina powder content being 65% by volume. The resulting mixture was diluted with solvent to a polyimide concentration of 5% by mass. Next, the diluted mixture was dispersed using a Star Burst manufactured by SUGINO MACHINE LIMITED by repeatedly subjecting it to high-pressure jetting at 50 MPa for 10 cycles, thereby preparing a coating solution for forming the insulating layer.

[0047] A copper substrate (composition: C1100, tough copper) with a thickness of 1000 μm and dimensions of 30 mm in length and 20 mm in width was prepared. An insulating layer was formed on the surface of this copper substrate by applying an insulating layer coating solution using a rod coating method. Next, the copper substrate with the coated layer was placed on a hot plate and heated from room temperature to 60 °C at a rate of 3 °C / min, and heated at 60 °C for 100 minutes. Then, the temperature was increased to 120 °C at a rate of 1 °C / min, and heated at 120 °C for 100 minutes to dry the coating layer. Next, the copper substrate was heated at 250 °C for 1 minute, and then at 400 °C for 1 minute. Thus, a copper substrate with an insulating layer was produced, on which an insulating layer composed of polyimide resin with dispersed α-alumina single crystal particles was formed. Furthermore, the thickness of the insulating layer was set to 30 μm, the elastic modulus of the insulating layer at 100 °C was set to 0.27 GPa, and the thickness / elastic modulus ratio was set to 110.

[0048] A 70 μm thick copper foil (elastic modulus at 100°C: 75 GPa, GHY5-HA-V2 manufactured by JX Nippon Mining & Metals Corporation) was stacked on the insulating layer of the obtained copper substrate with an insulating layer. Next, while applying a pressure of 5 MPa to the obtained laminate using a carbon clamp, it was heated in a vacuum at a pressing temperature of 300°C for 120 minutes to press the insulating layer and copper foil together. In this way, a copper substrate with a copper substrate, an insulating layer, and copper foil stacked sequentially was produced.

[0049] [Examples 2-4 of this invention, Comparative Examples 1-2]

[0050] Except for changing the thickness and elastic modulus of the insulating layer and the elastic modulus of the circuit layer to the values ​​recorded in Table 1 below, a copper substrate was fabricated in the same manner as in Example 1 of the present invention.

[0051] [evaluate]

[0052] The reliability of the copper substrates obtained in Examples 1-4 and Comparative Examples 1-2 of this invention to thermal cycling was evaluated by the following method. The results are shown in Table 1.

[0053] (Reliability of copper substrate to thermal cycling)

[0054] A 2.5cm x 2.5cm x 100μm solder layer was formed by coating Sn-Ag-Cu solder onto the circuit layer of a copper substrate. A 2.5cm square Si chip was then mounted on this solder layer to fabricate a test specimen. The fabricated test specimen was subjected to 3000 cycles of thermal cycling (each cycle consisting of -40℃ for 30 minutes to 150℃ for 30 minutes). After the thermal cycling, the test specimen was embedded in resin. Samples obtained by grinding the cross-section were observed. Specimens without cracks longer than 5mm in the solder layer were marked "0", while those with cracks longer than 5mm were marked "×".

[0055] [Table 1]

[0056]

[0057] The copper substrates of Examples 1-4 of the present invention, whose ratio of insulating layer thickness (in μm) to elastic modulus (in GPa) (thickness / elastic modulus) and the elastic modulus of circuit layer are within the scope of the present invention, exhibit excellent reliability under thermal cycling. This is because, since the insulating layer's thickness / elastic modulus is within the scope of the present invention, the difference in thermal expansion coefficients between the copper substrate and the electronic components caused by thermal cycling is mitigated by the insulating layer. Furthermore, since the elastic modulus of the circuit layer is within the scope of the present invention, the thermal stress applied to the solder due to the difference in thermal expansion coefficients between the circuit layer and the electronic components is reduced.

[0058] In contrast, although the thickness / elastic modulus of the insulating layer is within the range of the present invention, the copper substrate of Comparative Example 1, whose elastic modulus of the circuit layer exceeds the range of the present invention, exhibits lower reliability under thermal cycling. This is because, since the elastic modulus of the circuit layer exceeds the range of the present invention, the thermal stress applied to the solder increases due to the difference in thermal expansion coefficients between the circuit layer and the electronic components.

[0059] Furthermore, although the elastic modulus of the circuit layer is within the range of the present invention, the copper substrate of Comparative Example 2, whose insulation layer thickness / elastic modulus is less than the range of the present invention, has lower reliability under thermal cycling. This is because, since the insulation layer thickness / elastic modulus is less than the range of the present invention, the thermal stress applied to the solder is not sufficiently mitigated due to the difference in thermal expansion coefficients between the copper substrate and the circuit layer caused by thermal cycling.

[0060] Symbol Explanation

[0061] 10 Copper substrate

[0062] 20 Copper substrate

[0063] 30 Insulation layer

[0064] 31 Insulating Resin

[0065] 32 Inorganic fillers

[0066] 40 circuit layers

[0067] 50 Solder

[0068] 60 Electronic components

[0069] 61 terminal

Claims

1. A copper substrate, formed by sequentially stacking a copper substrate, an insulating layer, and a circuit layer, characterized in that, The ratio of the thickness of the insulating layer to its elastic modulus at 100°C is 50 or greater. The unit of the thickness is μm, and the unit of the elastic modulus is GPa. The elastic modulus of the circuit layer at 100°C is above 50 GPa and below 100 GPa.

2. The copper substrate according to claim 1, characterized in that, The insulating layer comprises a polyimide resin, a polyamide-imide resin, or a mixture thereof.

3. The copper substrate according to claim 1 or 2, characterized in that, The insulating layer contains inorganic fillers, the average particle size of which is greater than 0.1 μm and less than 20 μm.

4. The copper substrate according to claim 1 or 2, characterized in that, The circuit layer is composed of copper foil, copper alloy foil, aluminum foil, or aluminum alloy foil.

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