Clock tree circuit and signal transmission method based on clock tree circuit

Abstract

The present application relates to a clock tree circuit and a signal transmission method based on the clock tree circuit. The circuit includes: a scan chain test mode clock module, the output end of the scan chain test mode clock module is electrically connected to the input end of a clock selection generator; a first functional mode clock module group, the output end of the first functional mode clock module group is electrically connected to the input end of the clock selection generator; a clock selection generator, the input end of the clock selection generator is electrically connected to the output end of the scan chain test mode clock module and the output end of the first functional mode clock module group, respectively, and the output end of the clock selection generator is electrically connected to the input end of a device; the clock selection generator is used to select and generate a functional mode clock and a scan chain test mode clock; a device, the input end of the device is electrically connected to the output end of the clock selection generator. The use of this circuit can reduce the dynamic power consumption of a chip in functional mode.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a clock tree circuit and a signal transmission method based on the clock tree circuit. Background Art

[0002] As a method for detecting circuit defects, scan chain test mode is essential in large-scale integrated circuits and automotive electronics. In systems with microcontroller units (MCUs) and peripherals, functional mode typically features a variety of clock sources, including externally fed pin clocks, high-speed crystal oscillator clocks (HFXO), phase-locked loop clocks (PLL) generated by HFXO, high-speed internal clocks (HFRC), low-speed internal clocks (LFRC), and low-speed crystal oscillator clocks (LFXO). Unlike functional mode, the clock source in scan chain test mode is a single clock, originating from an external chip pin (PAD).

[0003] When the system operates in scan chain test mode, it is necessary to switch the different clock sources used in functional mode to a single clock source to save test time. However, existing clock tree circuits have different timing requirements for functional mode and scan chain test mode. Therefore, to achieve timing closure, existing clock tree circuits introduce numerous buffer units in the back-end clock tree implementation, which increases the chip's dynamic power consumption in functional mode. Summary of the Invention

[0004] Based on this, it is necessary to provide a clock tree circuit and a signal transmission method based on the clock tree circuit that can reduce the dynamic power consumption of the chip in the functional mode to address the above technical problems.

[0005] In a first aspect, the present application provides a clock tree circuit. The circuit includes:

[0006] a scan chain test mode clock module, wherein an output end of the scan chain test mode clock module is electrically connected to an input end of the clock selection generator;

[0007] a first functional mode clock module group, wherein an output end of the first functional mode clock module group is electrically connected to an input end of the clock selection generator;

[0008] a clock selection generator, wherein the input end of the clock selection generator is electrically connected to the output end of the scan chain test mode clock module and the output end of the first functional mode clock module group, respectively, and the output end of the clock selection generator is electrically connected to the input end of the device; the clock selection generator is used to select and generate a functional mode clock and a scan chain test mode clock;

[0009] A device, wherein an input terminal of the device is electrically connected to an output terminal of the clock selection generator.

[0010] In one embodiment, the circuit further comprises:

[0011] a second functional mode clock module group, wherein an output end of the second functional mode clock module group is electrically connected to an input end of the data selector;

[0012] A data selector, wherein the input end of the data selector is electrically connected to the output end of the scan chain test mode clock module and the output end of the second functional mode clock module group respectively, and the output end of the data selector is electrically connected to the input end of the device.

[0013] In one embodiment, the circuit further comprises:

[0014] An asynchronous frequency divider, wherein the input end of the asynchronous frequency divider is electrically connected to the output end of the scan chain test mode clock module, and the output end of the asynchronous frequency divider is electrically connected to the input end of the data selector.

[0015] In one embodiment, the asynchronous frequency divider is configured to shut down the asynchronous frequency divider in response to a power-on instruction of a functional mode.

[0016] In one embodiment, the device includes: a high-speed device and a low-speed device, and the first functional mode clock module group includes: a high-speed clock module group and a low-speed clock module group;

[0017] The output end of the high-speed clock module group is electrically connected to the input end of the clock selection generator; the high-speed clock module group is used to generate a high-speed clock to provide a working clock frequency to the high-speed device;

[0018] The output end of the low-speed clock module group is electrically connected to the input end of the clock selection generator; the low-speed clock module group is used to generate a low-speed clock to provide a working clock frequency to the low-speed device;

[0019] The input end of the clock selection generator is electrically connected to the output end of the high-speed clock module group and the output end of the low-speed clock module group respectively, and the output end of the clock selection generator is electrically connected to the high-speed device and the low-speed device respectively.

[0020] In one embodiment, the device further comprises: a medium-speed device, and the circuit further comprises:

[0021] A synchronous frequency divider, wherein the input end of the synchronous frequency divider is electrically connected to the output end of the clock selection generator, and the output end of the synchronous frequency divider is electrically connected to the input end of the high-speed device, the input end of the medium-speed device and the input end of the low-speed device, respectively, for providing an operating clock frequency to the medium-speed device.

[0022] In one embodiment, the circuit further comprises:

[0023] A pattern generator, wherein the input end of the pattern generator is electrically connected to the output end of the scan chain test mode clock module, and the output end of the pattern generator is electrically connected to the input end of the clock selection generator, for entering the scan chain test mode.

[0024] In one embodiment, the first functional mode clock module group includes: a high-frequency clock module and a non-high-frequency clock module; the high-frequency clock module is the clock source with the highest frequency in the first functional mode clock module group; the clock selection generator includes:

[0025] a first sub-clock selection generator, wherein an input end of the first sub-clock selection generator is electrically connected to an output end of the scan chain test mode clock module and an output end of the high-frequency clock module, respectively, and an output end of the first sub-clock selection generator is electrically connected to an input end of a third sub-clock selection generator;

[0026] a second sub-clock selection generator, wherein an input terminal of the second sub-clock selection generator is electrically connected to an output terminal of the non-high-frequency clock module, and an output terminal of the second sub-clock selection generator is electrically connected to an input terminal of a third sub-clock selection generator;

[0027] A third sub-clock selection generator, wherein the input end of the third sub-clock selection generator is electrically connected to the output end of the first sub-clock selection generator and the output end of the second sub-clock selection generator respectively, and the output end of the third sub-clock selection generator is electrically connected to the input end of the device.

[0028] In one embodiment, the circuit further comprises:

[0029] A clock divider, wherein the input end of the clock divider is electrically connected to the output end of the scan chain test mode clock module, and the output end of the clock divider is electrically connected to the input end of the second sub-clock selection generator.

[0030] In a second aspect, the present application provides a signal transmission method based on a clock tree circuit. The method is applied to the clock tree circuit described in the first aspect above, comprising:

[0031] In the functional mode, in response to a power-on instruction of the functional mode, the first functional mode clock module group generates a first functional mode clock group and sends the first functional mode clock group to the clock selection generator; the clock selection generator sends the first functional mode clock group to the device;

[0032] In the scan chain test mode, in response to the power-on instruction of the scan chain test mode, the scan chain test mode clock module generates a scan chain test mode clock and sends the scan chain test mode clock to the clock selection generator; the clock selection generator sends the scan chain test mode clock to the device.

[0033] The clock tree circuit in scan chain test mode and the signal transmission method based on the clock tree circuit include: a scan chain test mode clock module, the output of which is electrically connected to the input of a clock selection generator; a first functional mode clock module group, the output of which is electrically connected to the input of the clock selection generator; a clock selection generator, the input of which is electrically connected to the output of the scan chain test mode clock module and the output of the first functional mode clock module group, respectively, and the output of which is electrically connected to the input of a device; the clock selection generator is used to select and generate a functional mode clock and a scan chain test mode clock; and a device, the input of which is electrically connected to the output of the clock selection generator. In this way, the scan chain test mode clock and the functional mode clock group have the same path to the main system clock. In scan chain test mode, the main clock maintains the same path as the functional mode system clock. The two modes have the same timing requirements, which reduces the impact on critical timing closure and the number of buffer units introduced in clock tree implementation, thereby reducing the dynamic power consumption of the chip in functional mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a structural diagram of a clock tree circuit in one embodiment;

[0035] Figure 2 is a structural diagram of a clock tree circuit in one embodiment;

[0036] Figure 3 FIG1 is a structural diagram of a clock tree circuit with an AHB bus in one embodiment;

[0037] Figure 4 1 is a flow chart of a signal transmission method based on a clock tree circuit in one embodiment. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0039] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application include direct and indirect connections (couplings) unless otherwise specified. In the description of this application, it should be understood that the orientations or positional relationships indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.

[0040] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0041] In one embodiment, Figure 1 As shown, a clock tree circuit is provided, which includes:

[0042] A scan chain test mode clock module, wherein an output end of the scan chain test mode clock module is electrically connected to an input end of the clock selection generator.

[0043] A first functional mode clock module group, wherein an output end of the first functional mode clock module group is electrically connected to an input end of the clock selection generator.

[0044] A clock selection generator, wherein the input end of the clock selection generator is electrically connected to the output end of the scan chain test mode clock module and the output end of the first functional mode clock module group, respectively, and the output end of the clock selection generator is electrically connected to the input end of the device. The clock selection generator is used to select and generate the functional mode clock and the scan chain test mode clock.

[0045] The device has an input terminal electrically connected to an output terminal of the clock selection generator.

[0046] In an embodiment of the present application, the clock tree circuit is applied to an integrated circuit. It is understood that the integrated circuit can be a mixed-analog integrated circuit. The integrated circuit can be a large-scale chip with a deep submicron process and a microcontroller unit (MCU) and peripherals. For example, the clock tree circuit is applied to a low-power integrated circuit designed for automotive electronics with an MCU and peripherals. The scan chain test mode clock module is used to generate a scan chain test mode clock in scan chain test mode. The scan chain test mode can be a scan mode, and the scan chain test mode clock can be a scan mode clock. The scan chain test mode is used to test digital functional devices. The scan chain test mode clock module can be an external chip pin (PAD). The first functional mode clock module group is a combination of the first functional mode clock modules. The first functional mode clock module group is used to generate a first functional mode clock group in functional mode. The first functional mode clock group may include: an external pin clock, a high-speed crystal oscillator clock (HFXO), a phase-locked loop clock (PLL) generated using the high-speed crystal oscillator clock, a high-speed internal clock (HFRC), a low-speed internal clock (LFRC), and a low-speed crystal oscillator clock (LFXO). The clock selection generator includes at least one data multiplexer (MUX). The device includes a microcontroller unit (MCU) and peripherals. The device may also include static random-access memory (SRAM). Peripherals are hardware devices connected to a computer host that transmit, transfer, and store data and information, and are an important component of a computer system.

[0047] In the aforementioned clock tree circuit, the scan chain test mode clock and the first functional mode clock group are both electrically connected to the input of a clock selection generator, and the output of the clock selection generator is further electrically connected to the input of the device. This allows the scan chain test mode clock and the functional mode clock group to reach the main system clock via the same path. In scan chain test mode, the main clock maintains the same path as the system clock in functional mode. The two modes have identical timing requirements, minimizing the impact on critical timing closure and the difficulty of timing closure. This reduces the number of buffer units required in clock tree implementation, thereby reducing static power consumption and dynamic power consumption in functional mode. Furthermore, this avoids increasing chip area, reducing chip area, and lowering costs. Furthermore, this clock tree circuit can be implemented at the RTL stage of digital circuit design, eliminating the need for synthesis tools. Its structure is highly suitable for porting and legacy applications. Furthermore, the main clock tree structure of this clock tree circuit features a streamlined hierarchy. The scan chain test mode clock path is short, reducing delays at the clock source, further facilitating timing closure and further reducing chip power consumption.

[0048] In one embodiment, the clock tree circuit further includes:

[0049] The second functional mode clock module group has an output terminal electrically connected to the input terminal of the data selector.

[0050] A data selector, wherein the input end of the data selector is electrically connected to the output end of the scan chain test mode clock module and the output end of the second functional mode clock module group respectively, and the output end of the data selector is electrically connected to the input end of the device.

[0051] In an embodiment of the present application, the peripheral has two clock systems, one is the bus read and write register clock (APB_CLK or AHB_CLK) configured by the MCU, and the other is the device's own working clock, which is in an asynchronous relationship with the configuration bus. The second functional mode clock module group is a combination of each second functional mode clock module. The second functional mode clock module group is used to generate a second functional mode clock group in functional mode, that is, to generate the device's own working clock in functional mode. The second functional mode clock group may include: a high speed peripheral clock (HPER_CLK), a low speed peripheral clock (LPER_CLK), and a medium speed peripheral clock (MPER_CLK).

[0052] In the aforementioned clock tree circuit, the scan chain test mode clock and the second functional mode clock group are both electrically connected to the input of the data selector, and the output of the data selector is then electrically connected to the input of the device. This allows the scan chain test mode clock and the functional mode clock group to use the same clock paths to reach the device. This means the clock paths in scan chain test mode and functional mode are identical, and both modes have the same timing requirements. This further reduces the difficulty of timing closure, the need for buffer units, and the chip's static power consumption and dynamic power consumption in functional mode, further reducing chip area and cost.

[0053] In one embodiment, the clock tree circuit further includes:

[0054] An asynchronous frequency divider, wherein the input end of the asynchronous frequency divider is electrically connected to the output end of the scan chain test mode clock module, and the output end of the asynchronous frequency divider is electrically connected to the input end of the data selector.

[0055] In an embodiment of the present application, the asynchronous frequency divider is used to perform asynchronous frequency division processing on the main clock of the scan chain test mode.

[0056] In the aforementioned clock tree circuit, the scan chain test mode clock is electrically connected to the input terminals of the data selector through an asynchronous divider with the second functional mode clock group. This allows asynchronous frequency division of the scan chain test mode master clock in the scan chain test mode to maintain an asynchronous clock relationship in both functional and scan chain test modes, further reducing the difficulty of timing closure and ensuring that critical timing paths are tightly focused. This reduces chip area and both static and dynamic power consumption compared to back-end processing that blindly converges high-speed and low-speed peripherals to the same frequency.

[0057] In one embodiment, the asynchronous frequency divider is configured to shut down the asynchronous frequency divider in response to a power-on instruction of the functional mode.

[0058] In an embodiment of the present application, the power-on instruction of the functional mode is used to instruct to start the functional mode. The asynchronous frequency divider includes: an asynchronous frequency divider gated clock management circuit. The asynchronous frequency divider gated clock management circuit is used to shut down the asynchronous frequency divider in response to the power-on instruction of the functional mode.

[0059] In the clock tree circuit described above, the asynchronous divider is disabled in functional mode. This allows the asynchronous divider to divide the scan chain test mode master clock only in scan chain test mode, without affecting the functional mode. This ensures functional mode stability and avoids increased power consumption.

[0060] In one embodiment, the device includes: a high-speed device and a low-speed device. The first functional mode clock module group includes: a high-speed clock module group and a low-speed clock module group.

[0061] The output end of the high-speed clock module group is electrically connected to the input end of the clock selection generator. The high-speed clock module group is used to generate a high-speed clock and provide a working clock frequency for the high-speed device.

[0062] The output end of the low-speed clock module group is electrically connected to the input end of the clock selection generator. The low-speed clock module group is used to generate a low-speed clock and provide a working clock frequency to the low-speed device.

[0063] The input end of the clock selection generator is electrically connected to the output end of the high-speed clock module group and the output end of the low-speed clock module group respectively, and the output end of the clock selection generator is electrically connected to the high-speed device and the low-speed device respectively.

[0064] In the embodiments of the present application, high-speed devices include high-speed peripherals. High-speed peripherals refer to peripherals such as pulse width generators (PWM), general-purpose input / output (GPIO), and RAM storage areas that operate at the same frequency as the MCU. Low-speed devices include low-speed peripherals. Low-speed peripherals refer to devices such as LPUART (low-speed serial port device), RTC (perpetual clock counter), LPTIMER (low-power timer), and WDT (watchdog timer). The operating clock frequency of low-speed peripherals supports a maximum of 32 kHz and its division by 1 to 4096. The high-speed clock module group is a combination of various high-speed clock modules. The high-speed clock module group may include: a high-speed crystal oscillator clock (HFXO) module, a phase-locked loop clock (PLL) module, and a high-speed internal clock (HFRC) module. The low-speed clock module group is a combination of various low-speed clock modules. The low-speed clock module group may include: a low-speed internal clock (LFRC) module and a low-speed crystal oscillator clock (LFXO) module. The frequency multiple of the high-speed clock and the low-speed clock is not less than 1000. The first functional mode clock module group also includes an external clock module group. The external clock module group is used to generate an external clock group, which includes the debug MCU's protocol clock and the PAD external clock.

[0065] In the aforementioned clock tree circuit, in functional mode, the high-speed clock module group generates a high-speed clock, providing the operating clock frequency for high-speed devices; the low-speed clock module group generates a low-speed clock, providing the operating clock frequency for low-speed devices. This makes chip testing more difficult when the operating frequencies of different devices vary significantly, further increasing the power consumption and chip area differences between this clock tree circuit and other clock tree circuits.

[0066] In one embodiment, the device further comprises: a medium-speed device, and the circuit further comprises:

[0067] A synchronous frequency divider, wherein the input end of the synchronous frequency divider is electrically connected to the output end of the clock selection generator, and the output end of the synchronous frequency divider is electrically connected to the input end of the high-speed device, the input end of the medium-speed device and the input end of the low-speed device respectively, for providing the working clock frequency to the medium-speed device.

[0068] In the present embodiment, medium-speed devices include medium-speed peripherals. In automotive integrated circuits, medium-speed peripherals refer to peripherals such as CAN (Controller Area Network) and SPI (Serial Peripheral Interface), which communicate at frequencies between 1 MHz and 20 MHz. Synchronous frequency dividers are used to divide the high-speed clock group.

[0069] In the above clock tree circuit, the synchronous frequency divider provides the medium-speed device with an operating clock frequency to ensure the normal operation of the medium-speed device.

[0070] In one embodiment, Figure 2 As shown, the clock tree circuit includes:

[0071] A scan chain test mode clock module, wherein an output end of the scan chain test mode clock module is electrically connected to an input end of the clock selection generator and an input end of the asynchronous frequency divider respectively.

[0072] A first functional mode clock module group, wherein an output end of the first functional mode clock module group is electrically connected to an input end of the clock selection generator.

[0073] A clock selection generator, wherein the input end of the clock selection generator is electrically connected to the output end of the scan chain test mode clock module and the output end of the first functional mode clock module group respectively, and the output end of the clock selection generator is electrically connected to the input end of the synchronous divider.

[0074] A synchronous frequency divider, wherein the input end of the synchronous frequency divider is electrically connected to the output end of the clock selection generator, and the output end of the synchronous frequency divider is electrically connected to the input end of the high-speed device, the input end of the medium-speed device and the input end of the low-speed device respectively.

[0075] An asynchronous frequency divider, wherein the input end of the asynchronous frequency divider is electrically connected to the output end of the scan chain test mode clock module, and the output end of the asynchronous frequency divider is electrically connected to the input end of the data selector.

[0076] The second functional mode clock module group includes: a first group, a second group, and a third group. The output of the first group is electrically connected to the input of the first selector. The output of the second group is electrically connected to the input of the second selector. The output of the third group is electrically connected to the input of the third selector.

[0077] The data selector includes: a first selector, a second selector, and a third selector. The first selector has an input electrically connected to the output of the asynchronous frequency divider and the output of the first group, respectively, and the output of the data selector is electrically connected to the input of the high-speed device. The second selector has an input electrically connected to the output of the asynchronous frequency divider and the output of the second group, respectively, and the output of the data selector is electrically connected to the input of the medium-speed device. The third selector has an input electrically connected to the output of the asynchronous frequency divider and the output of the third group, respectively, and the output of the data selector is electrically connected to the input of the low-speed device.

[0078] The high-speed device has an input terminal electrically connected to the output terminal of the synchronous frequency divider and the input terminal of the first selector respectively.

[0079] The medium-speed device has an input terminal electrically connected to the output terminal of the synchronous frequency divider and the input terminal of the second selector respectively.

[0080] The low-speed device has an input terminal electrically connected to the output terminal of the synchronous frequency divider and the input terminal of the third selector respectively.

[0081] In one embodiment, the clock tree circuit further includes:

[0082] A pattern generator, wherein the input end of the pattern generator is electrically connected to the output end of the scan chain test mode clock module, and the output end of the pattern generator is electrically connected to the input end of the clock selection generator, for entering the scan chain test mode.

[0083] In an embodiment of the present application, the pattern generator is used to provide different chips with different ways of entering scan chain test modes.

[0084] In the clock tree circuit described above, the scan chain test mode clock is electrically connected to the input of the clock selection generator via the pattern generator. This provides different chips with different ways to enter the scan chain test mode, further improving the portability and inheritability of the clock tree circuit.

[0085] In one embodiment, the first functional mode clock module group includes: a high-frequency clock module and a non-high-frequency clock module. The high-frequency clock module is the clock source with the highest frequency in the first functional mode clock module group.

[0086] The clock selection generator includes:

[0087] The first sub-clock selection generator, the input end of the first sub-clock selection generator is electrically connected to the output end of the scan chain test mode clock module and the output end of the high-frequency clock module respectively, and the output end of the first sub-clock selection generator is electrically connected to the input end of the third sub-clock selection generator.

[0088] The second sub-clock selection generator has an input terminal electrically connected to the output terminal of the non-high-frequency clock module, and an output terminal electrically connected to the input terminal of the third sub-clock selection generator.

[0089] The third sub-clock selection generator, the input end of the third sub-clock selection generator is electrically connected to the output end of the first sub-clock selection generator and the output end of the second sub-clock selection generator respectively, and the output end of the third sub-clock selection generator is electrically connected to the input end of the device.

[0090] In the embodiment of the present application, the first sub-clock selection generator, the second sub-clock selection generator, and the third sub-clock selection generator can all be data selectors (MUXs). The number of the second sub-clock selection generators is related to the number of the non-high-frequency clock modules.

[0091] In the above clock tree circuit, keeping the paths of the scan chain test mode clock and the system's highest frequency clock source consistent can further reduce the number of clock buffer units in scenario applications, further reduce the chip area, and further reduce the chip's power consumption.

[0092] In one embodiment, the clock tree circuit further includes:

[0093] A clock divider, wherein the input end of the clock divider is electrically connected to the output end of the scan chain test mode clock module, and the output end of the clock divider is electrically connected to the input end of the second sub-clock selection generator.

[0094] In an embodiment of the present application, a clock divider is used to divide the test clock in the scan chain test mode. The number of clock dividers can be the same as the number of first functional mode clock modules electrically connected to the input end of the second sub-clock selection generator. Each clock divider can be configured with a different division ratio. The clock divider can be a synchronous divider or an asynchronous divider. The clock divider is an asynchronous divider, which can reduce the mutual influence between different clocks in the scan chain test mode, avoid increasing the chip area to reduce the mutual influence between different clocks, and further reduce the chip area.

[0095] In the aforementioned clock tree circuit, the scan chain test mode clock is electrically connected to the input of the second sub-clock selection generator via a clock divider. This divides the scan chain test mode clock to maintain the same frequency correspondence as in functional mode, further ensuring that the clock correlation and frequency relationship between the scan chain test mode and functional mode remain consistent in magnitude. This can further reduce the number of clock buffer units in specific application scenarios, further reducing chip area and power consumption.

[0096] In one embodiment, Figure 3 As shown, the clock tree circuit includes:

[0097] The first functional mode clock module group includes a high-speed crystal oscillator clock module 301, a low-speed crystal oscillator clock module 302, a high-speed built-in clock module 303, a low-speed built-in clock module 304, an external clock module 305, and a phase-locked loop clock module 309. The output of the high-speed crystal oscillator clock module 301 is electrically connected to the input of a data selector 308. The output of the low-speed crystal oscillator clock module 302 is electrically connected to the input of a data selector 310. The output of the high-speed built-in clock module 303 is electrically connected to the input of a data selector 311. The output of the low-speed built-in clock module 304 is electrically connected to the input of a data selector 312. The output of the external clock module 305 is electrically connected to the input of a data selector 313. The phase-locked loop clock module 309 has its input electrically connected to the output of the data selector 308, and its output electrically connected to the input of the data selector 314. The output range of the phase-locked loop clock (PLL) output by the phase-locked loop clock module 309 is 72 MHz to 500 MHz.

[0098] The scan chain test mode clock module 306 has an output terminal electrically connected to an input terminal of the pattern generator 307 .

[0099] The pattern generator 307 has an input end electrically connected to the output end of the scan chain test mode clock module 306, and the output end of the pattern generator 307 is electrically connected to the input end of the data selector 308, the input end of the asynchronous divider 324, the input end of the asynchronous divider 325, the input end of the data selector 326, the input end of the data selector 327, the input end of the data selector 330, the input end of the data selector 331, the input end of the clock divider 315, the input end of the clock divider 316, the input end of the clock divider 317, and the input end of the clock divider 318.

[0100] The clock selection generator includes data selectors 308, 310-314. Data selector 308 has its input electrically connected to the output of the high-speed crystal oscillator clock module 301 and the output of the scan chain test mode clock module 306, respectively. Its output is electrically connected to the input of the phase-locked loop clock module 309. Data selector 310 has its input electrically connected to the output of the low-speed crystal oscillator clock module 302 and the output of the clock divider 315, respectively. Its output is electrically connected to the input of data selector 314. Data selector 311 has its input electrically connected to the output of the high-speed built-in clock module 303 and the output of the clock divider 316, respectively. Its output is electrically connected to the input of data selector 314. Data selector 312: The input end of data selector 312 is electrically connected to the output end of low-speed internal clock module 304 and the output end of clock divider 317, respectively. The output end of data selector 312 is electrically connected to the input end of data selector 314. Data selector 313: The input end of data selector 313 is electrically connected to the output end of external clock module 305 and the output end of clock divider 318, respectively. The output end of data selector 313 is electrically connected to the input end of data selector 314. Data selector 314: The input end of data selector 314 is electrically connected to the output end of phase-locked loop clock module 309, the output end of data selector 310, the output end of data selector 311, the output end of data selector 312, and the output end of data selector 313, respectively. The output end of data selector 314 is electrically connected to the input end of synchronous divider 319, the input end of synchronous divider 320, and the input end of system bus to peripheral bus bridge 323, respectively.

[0101] The clock divider includes clock dividers 315-318. The input of clock divider 315 is electrically connected to the output of pattern generator 307, and the output of clock divider 315 is electrically connected to the input of data selector 310. The input of clock divider 316 is electrically connected to the output of pattern generator 307, and the output of clock divider 316 is electrically connected to the input of data selector 311. The input of clock divider 317 is electrically connected to the output of pattern generator 307, and the output of clock divider 317 is electrically connected to the input of data selector 312. The input of clock divider 318 is electrically connected to the output of pattern generator 307, and the output of clock divider 318 is electrically connected to the input of data selector 313.

[0102] The synchronous frequency divider includes synchronous frequency dividers 319 and 320. The input of synchronous frequency divider 319 is electrically connected to the output of data selector 314, and the output of synchronous frequency divider 319 is electrically connected to the input of static random access memory 321. The input of synchronous frequency divider 320 is electrically connected to the output of data selector 314, and the output of synchronous frequency divider 320 is electrically connected to the input of microcontroller unit 322.

[0103] The device includes: a static random access memory 321, a microcontroller unit 322, high-speed peripherals 332-333, low-speed peripherals 334-335, and medium-speed peripherals 336-337. The static random access memory 321 has its input electrically connected to the output of the synchronous frequency divider 319. The microcontroller unit 322 has its input electrically connected to the output of the synchronous frequency divider 320. The high-speed peripherals 332 have their input electrically connected to the output of the system bus to peripheral bus bridge 323 and the output of the data selector 326. The high-speed peripherals 333 have their input electrically connected to the output of the system bus to peripheral bus bridge 323 and the output of the data selector 327. Low-speed peripherals 334: The input end of low-speed peripherals 334 is electrically connected to the output end of the system bus to peripheral bus bridge 323 and the output end of the data selector 328, respectively. Low-speed peripherals 335: The input end of low-speed peripherals 335 is electrically connected to the output end of the system bus to peripheral bus bridge 323 and the output end of the data selector 329, respectively. Medium-speed peripherals 336: The input end of medium-speed peripherals 336 is electrically connected to the output end of the system bus to peripheral bus bridge 323 and the output end of the data selector 330, respectively. Medium-speed peripherals 337: The input end of medium-speed peripherals 337 is electrically connected to the output end of the system bus to peripheral bus bridge 323 and the output end of the data selector 331, respectively.

[0104] The system bus to peripheral bus bridge 323 has an input end electrically connected to an output end of the data selector 314, and an output end electrically connected to an input end of a high-speed peripheral 332, an input end of a high-speed peripheral 333, an input end of a low-speed peripheral 334, an input end of a low-speed peripheral 335, an input end of a medium-speed peripheral 336, and an input end of a medium-speed peripheral 337, respectively.

[0105] The asynchronous frequency divider includes asynchronous frequency dividers 324 and 325. Asynchronous frequency divider 324 has its input electrically connected to the output of pattern generator 307, and its output electrically connected to the input of data selector 328. Asynchronous frequency divider 325 has its input electrically connected to the output of pattern generator 307, and its output electrically connected to the input of data selector 329.

[0106] The data selector 326 has its input terminals electrically connected to the output terminals of the high-speed peripheral clock module 338 and the output terminals of the pattern generator 307 , and its output terminals electrically connected to the input terminals of the high-speed peripheral 332 .

[0107] The data selector 327 has its input terminals electrically connected to the output terminals of the high-speed peripheral clock module 339 and the output terminals of the pattern generator 307 , and its output terminals electrically connected to the input terminals of the high-speed peripheral 333 .

[0108] The data selector 328 has its input electrically connected to the output of the low-speed peripheral clock module 340 and the output of the asynchronous frequency divider 324 , and its output electrically connected to the input of the low-speed peripheral 334 .

[0109] The data selector 329 has its input electrically connected to the output of the low-speed peripheral clock module 341 and the output of the asynchronous frequency divider 325 , and its output electrically connected to the input of the low-speed peripheral 335 .

[0110] The data selector 330 has its input electrically connected to the output of the medium-speed peripheral clock module 342 and the output of the pattern generator 307 , and its output electrically connected to the input of the medium-speed peripheral 336 .

[0111] The data selector 331 has its input electrically connected to the output of the medium-speed peripheral clock module 343 and the output of the pattern generator 307 , and its output electrically connected to the input of the medium-speed peripheral 337 .

[0112] The second functional mode clock module group includes high-speed peripheral clock modules 338-339, low-speed peripheral clock modules 340-341, and medium-speed peripheral clock modules 342-343. The output of high-speed peripheral clock module 338 is electrically connected to the input of data selector 326. The output of high-speed peripheral clock module 339 is electrically connected to the input of data selector 327. The output of low-speed peripheral clock module 340 is electrically connected to the input of data selector 328. The output of low-speed peripheral clock module 341 is electrically connected to the input of data selector 329. The output of medium-speed peripheral clock module 342 is electrically connected to the input of data selector 330. The medium-speed peripheral clock module 343 has an output terminal electrically connected to an input terminal of the data selector 331 .

[0113] Based on the same inventive concept, embodiments of the present application also provide a signal transmission method based on a clock tree circuit for implementing the aforementioned clock tree circuit. The solution provided by this method is similar to the solution described in the aforementioned method. Therefore, the specific limitations in the following embodiments of one or more signal transmission methods based on a clock tree circuit can be found in the above-mentioned limitations on clock tree circuits and will not be further elaborated here.

[0114] In one embodiment, Figure 4 As shown, a signal transmission method based on a clock tree circuit is provided. The method is applied to any clock tree circuit in the above clock tree circuits, and the method includes the following steps:

[0115] Step 401: In the functional mode, in response to a functional mode power-on instruction, the first functional mode clock module group generates a first functional mode clock group and sends the first functional mode clock group to a clock selection generator. The clock selection generator sends the first functional mode clock group to the device.

[0116] In an embodiment of the present application, in functional mode, in response to a functional mode power-on instruction, the first functional mode clock module group generates a first functional mode clock group. The first functional mode clock module group then sends the first functional mode clock group to a clock selection generator. The clock selection generator then sends the first functional mode clock group to the device.

[0117] Step 402: In the scan chain test mode, in response to a scan chain test mode power-on instruction, the scan chain test mode clock module generates a scan chain test mode clock and sends the scan chain test mode clock to the clock selection generator. The clock selection generator sends the scan chain test mode clock to the device.

[0118] In an embodiment of the present application, in scan chain test mode, in response to a scan chain test mode power-on instruction, a scan chain test mode clock module generates a scan chain test mode clock. The scan chain test mode clock module then transmits the scan chain test mode clock to a clock selection generator. The clock selection generator then transmits the scan chain test mode clock to the device.

[0119] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0120] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A clock tree circuit, characterized in that: The circuit comprises: a scan chain test mode clock module, wherein an output end of the scan chain test mode clock module is electrically connected to an input end of the clock selection generator; a first functional mode clock module group, wherein an output end of the first functional mode clock module group is electrically connected to an input end of the clock selection generator; a clock selection generator, wherein the input end of the clock selection generator is electrically connected to the output end of the scan chain test mode clock module and the output end of the first functional mode clock module group, respectively, and the output end of the clock selection generator is electrically connected to the input end of the device; the clock selection generator is used to select and generate a functional mode clock and a scan chain test mode clock; a device, an input terminal of the device being electrically connected to an output terminal of the clock selection generator; a second functional mode clock module group, wherein an output end of the second functional mode clock module group is electrically connected to an input end of the data selector; A data selector, wherein the input end of the data selector is electrically connected to the output end of the scan chain test mode clock module and the output end of the second functional mode clock module group respectively, and the output end of the data selector is electrically connected to the input end of the device.

2. The circuit according to claim 1, wherein: The circuit further comprises: An asynchronous frequency divider, wherein the input end of the asynchronous frequency divider is electrically connected to the output end of the scan chain test mode clock module, and the output end of the asynchronous frequency divider is electrically connected to the input end of the data selector.

3. The circuit according to claim 2, characterized in that The asynchronous frequency divider is used to shut down the asynchronous frequency divider in response to a power-on instruction of a functional mode.

4. The circuit according to claim 1, wherein: The device includes: a high-speed device and a low-speed device, and the first functional mode clock module group includes: a high-speed clock module group and a low-speed clock module group; The output end of the high-speed clock module group is electrically connected to the input end of the clock selection generator; the high-speed clock module group is used to generate a high-speed clock to provide a working clock frequency to the high-speed device; The output end of the low-speed clock module group is electrically connected to the input end of the clock selection generator; the low-speed clock module group is used to generate a low-speed clock to provide a working clock frequency to the low-speed device; The input end of the clock selection generator is electrically connected to the output end of the high-speed clock module group and the output end of the low-speed clock module group respectively, and the output end of the clock selection generator is electrically connected to the high-speed device and the low-speed device respectively.

5. The circuit according to claim 4, characterized in that The device further includes: a medium-speed device, and the circuit further includes: A synchronous frequency divider, wherein the input end of the synchronous frequency divider is electrically connected to the output end of the clock selection generator, and the output end of the synchronous frequency divider is electrically connected to the input end of the high-speed device, the input end of the medium-speed device and the input end of the low-speed device, respectively, for providing an operating clock frequency to the medium-speed device.

6. The circuit according to claim 1, wherein: The circuit further comprises: A pattern generator, wherein the input end of the pattern generator is electrically connected to the output end of the scan chain test mode clock module, and the output end of the pattern generator is electrically connected to the input end of the clock selection generator, for entering the scan chain test mode.

7. The circuit according to claim 1, wherein: The first functional mode clock module group includes: a high-frequency clock module and a non-high-frequency clock module; the high-frequency clock module is the clock source with the highest frequency in the first functional mode clock module group; the clock selection generator includes: a first sub-clock selection generator, wherein an input end of the first sub-clock selection generator is electrically connected to an output end of the scan chain test mode clock module and an output end of the high-frequency clock module, respectively, and an output end of the first sub-clock selection generator is electrically connected to an input end of a third sub-clock selection generator; a second sub-clock selection generator, wherein an input terminal of the second sub-clock selection generator is electrically connected to an output terminal of the non-high-frequency clock module, and an output terminal of the second sub-clock selection generator is electrically connected to an input terminal of a third sub-clock selection generator; A third sub-clock selection generator, wherein the input end of the third sub-clock selection generator is electrically connected to the output end of the first sub-clock selection generator and the output end of the second sub-clock selection generator respectively, and the output end of the third sub-clock selection generator is electrically connected to the input end of the device.

8. The circuit according to claim 7, characterized in that The circuit further comprises: A clock divider, wherein the input end of the clock divider is electrically connected to the output end of the scan chain test mode clock module, and the output end of the clock divider is electrically connected to the input end of the second sub-clock selection generator.

9. The circuit according to claim 7, characterized in that The second functional mode clock module group includes: a first group, a second group and a third group; the output end of the first group is electrically connected to the input end of the first selector, the output end of the second group is electrically connected to the input end of the second selector; the output end of the third group is electrically connected to the input end of the third selector.

10. A signal transmission method based on a clock tree circuit, characterized in that: The method is applied to the clock tree circuit according to any one of claims 1 to 9, comprising: In the functional mode, in response to a power-on instruction of the functional mode, the first functional mode clock module group generates a first functional mode clock group and sends the first functional mode clock group to the clock selection generator; the clock selection generator sends the first functional mode clock group to the device; In the scan chain test mode, in response to the power-on instruction of the scan chain test mode, the scan chain test mode clock module generates a scan chain test mode clock and sends the scan chain test mode clock to the clock selection generator; the clock selection generator sends the scan chain test mode clock to the device.

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