Memory management method, device, memory manager, equipment and storage medium

Abstract

The embodiments of the present application disclose a memory management method, apparatus, memory manager, device and storage medium, which relate to the field of memory management. The method comprises: determining a memory slice according to the business type corresponding to different business data; adjusting the slice capacity of the memory slice based on the interruption frequency of the memory slice during business processing, wherein the interruption frequency refers to the frequency at which the memory usage of the memory slice is greater than the memory waterline, and the memory waterline is the threshold value for triggering an interruption of the memory slice. The method provided in the embodiments of the present application can reasonably adjust the slice capacity of the memory slice corresponding to different business types through a dynamic memory management mechanism, thereby improving memory utilization.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of memory management, and in particular to a memory management method, apparatus, memory manager, device, and storage medium. Background Art

[0002] The proper use of memory has a significant impact on the power consumption and chip area of ​​the terminal. The memory usage includes different types of business data.

[0003] In related technologies, memory is partitioned according to different service types. This partitioning process is based on the maximum amount of memory required by each service. With this approach, the accumulated memory required by each service can occupy a large amount of memory space, which can easily lead to memory waste. Summary of the Invention

[0004] The present invention provides a memory management method, apparatus, memory manager, device, and storage medium. The technical solution is as follows:

[0005] In one aspect, an embodiment of the present application provides a memory management method, the method comprising:

[0006] Determine the memory area based on the business type corresponding to different business data;

[0007] Based on the interruption frequency of the memory slice during business processing, the slice capacity of the memory slice is adjusted, wherein the interruption frequency refers to the frequency at which the memory usage of the memory slice is greater than the memory waterline, and the memory waterline is the threshold value for triggering an interruption of the memory slice.

[0008] On the other hand, an embodiment of the present application provides a memory management device, the device comprising:

[0009] The memory partitioning module is used to determine the memory area according to the business type corresponding to different business data;

[0010] A memory adjustment module is used to adjust the slice capacity of the memory slice based on the interruption frequency of the memory slice during business processing, wherein the interruption frequency refers to the frequency at which the memory usage of the memory slice is greater than the memory waterline, and the memory waterline is the threshold value for the memory slice to trigger an interrupt.

[0011] On the other hand, an embodiment of the present application provides a memory manager, which includes a programmable logic circuit and / or program instructions, and is used to implement the memory management method described in the above aspects when the memory manager is running.

[0012] On the other hand, an embodiment of the present application provides a computer device, which includes a processor and a memory, wherein the memory includes a memory and a memory manager as described in the above aspects.

[0013] On the other hand, an embodiment of the present application provides a computer storage medium, wherein the computer-readable storage medium stores at least one program code, and the program code is loaded and executed by a processor to implement the memory management method as described in the above aspects.

[0014] In another aspect, embodiments of the present application provide a computer program product or computer program, comprising computer instructions stored in a computer-readable storage medium. A processor of a terminal reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the terminal to perform the memory management method provided in various optional implementations of the aforementioned aspects.

[0015] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0016] In an embodiment of the present application, the memory manager in the computer device first determines the memory slices for storing different business data based on the business types corresponding to the different business data. Afterwards, the slice capacity of each memory slice can be dynamically adjusted according to the frequency at which the memory usage is greater than the memory waterline during business processing, which can increase the slice capacity of the memory slice with a higher interruption frequency and reduce the slice capacity of the memory slice with a lower interruption frequency. Compared with the method of estimating the memory capacity by maximizing the use of memory for business planning in the related art, in an embodiment of the present application, the slice capacity of the memory slice corresponding to different business types can be reasonably adjusted through a dynamic memory management mechanism, thereby improving memory utilization and helping to save memory space. And because the slice capacity is adjusted based on the interruption frequency, the frequent triggering of interrupts can be reduced, thereby helping to reduce power consumption and improving the efficiency of batch processing of business data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A flowchart of a memory management method provided by an exemplary embodiment of the present application is shown;

[0019] Figure 2 A schematic diagram of a memory area provided by an exemplary embodiment of the present application is shown;

[0020] Figure 3 A flowchart of a memory management method provided by another exemplary embodiment of the present application is shown;

[0021] Figure 4 A schematic diagram of adjusting the slice capacity of a memory slice provided by an exemplary embodiment of the present application is shown;

[0022] Figure 5 A flowchart of a memory management method provided by another exemplary embodiment of the present application is shown;

[0023] Figure 6 A schematic diagram of adjusting the slice capacity of a memory slice provided by another exemplary embodiment of the present application is shown;

[0024] Figure 7 A schematic diagram of adjusting the slice capacity of a memory slice provided by another exemplary embodiment of the present application is shown;

[0025] Figure 8 A structural block diagram of a memory management device provided by an embodiment of the present application is shown;

[0026] Figure 9 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0028] In this document, "plurality" refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0029] Memory usage includes business data, and all business data of different business types requires memory. Related technologies estimate the maximum amount of memory used for each business type, and then determine the total amount of memory based on this maximum amount. This approach accumulates the maximum amount of memory used by each business type, resulting in a large amount of memory space. However, in actual use, not all businesses may utilize the maximum amount of memory, resulting in memory waste.

[0030] Therefore, in an embodiment of the present application, a memory management method is provided to achieve dynamic memory management during business processing. The memory usage corresponding to different businesses can be adjusted in real time based on the actual memory usage, thereby saving memory usage. The method provided in the embodiment of the present application can be applied to computer devices. The computer device can be a mobile terminal device such as a smartphone, tablet computer, laptop computer, etc., or it can be a desktop computer, projection computer, etc., which is not limited in the embodiment of the present application.

[0031] Please refer to Figure 1 , which shows a flow chart of a memory management method provided by an exemplary embodiment of the present application. This embodiment takes the method executed by a memory manager in a computer device as an example to illustrate the process, which includes the following steps:

[0032] Step 101: Determine a memory area according to the business type corresponding to different business data.

[0033] Typically, when storing business data of different business types, memory blocks are divided into different slices to store different types of business data. Therefore, in one possible implementation, the memory manager can perform a preliminary segmentation of the memory to obtain different memory slices. Different memory slices are used to store business data of different business types.

[0034] Optionally, during the initial partitioning process, the memory manager can evenly partition the memory to obtain memory slices for storing business data corresponding to each business type. Alternatively, the slices can be partitioned based on the characteristics of different business types. During the partitioning process, a larger memory slice can be allocated for frequently used businesses, while a smaller memory slice can be allocated for less frequently used businesses.

[0035] Indicative, such as Figure 2 As shown, taking the division of memory slices into service types 1, 2, and 3 as an example, three memory slices are obtained. Among them, the first memory slice 201 is used to store service data of service type 1, the second memory slice 202 is used to store service data of service type 2, and the third memory slice 203 is used to store service data of service type 3.

[0036] Step 102, based on the interruption frequency of the memory slice during business processing, adjust the slice capacity of the memory slice, wherein the interruption frequency refers to the frequency at which the memory usage of the memory slice exceeds the memory waterline, and the memory waterline is the threshold value for triggering an interruption of the memory slice.

[0037] Each memory slice is assigned a memory watermark. This watermark is the threshold at which a memory slice triggers an interrupt. This watermark can be the maximum capacity of a memory slice, or it can be an intermediate value of the capacity of a memory slice, i.e., less than the maximum capacity. This embodiment does not limit this.

[0038] When the memory usage of a memory slice exceeds the memory waterline, an interrupt is triggered to allow the processor to process the data in the memory slice in a timely manner. However, if the interrupt is triggered frequently, it will increase the power consumption of the terminal and affect the efficiency of business batch processing.

[0039] Therefore, in one possible implementation, the capacity of the memory slice is adjusted based on the interrupt frequency of the memory slice to reduce the probability of frequent interrupt triggering. The memory manager keeps statistics on the interrupt frequency of each memory slice and updates the corresponding interrupt frequency when an interrupt is triggered.

[0040] After the interruption frequency of each memory slice is obtained, the slice capacity of the memory slice is adjusted based on the interruption frequency of each memory slice.

[0041] In one possible implementation, when the interrupt frequency is high, the memory manager may increase the slice capacity of the corresponding memory slice, so that the maximum amount of memory allowed to be used by the corresponding memory slice increases accordingly, which can effectively reduce the interrupt frequency. During the slice capacity adjustment process of the memory slice, the total memory capacity remains unchanged. Therefore, when the slice capacity of a memory slice is increased, the slice capacity of another memory slice is reduced accordingly. In order to reduce the impact of the slice capacity adjustment on other business processing, after determining the memory slice that needs to be increased, it is also necessary to determine the memory slice whose capacity can be reduced based on the interrupt frequency. If there is a memory slice that allows capacity reduction, the slice capacity of the memory slice is adjusted. Optionally, when the interrupt frequency is low, it indicates that the memory usage of the corresponding memory slice may be low. Therefore, the slice capacity of the memory slice with a low interrupt frequency can be reduced to improve memory utilization.

[0042] That is, in the embodiments of the present application, after initially dividing the memory slices for different services, the slice capacity of each memory slice is dynamically adjusted based on the actual usage of the memory slice during service processing. During service processing, different services correspond to different memory usage. There may be services with high memory requirements, while there may also be services with low memory requirements. Therefore, by rationally adjusting the slice capacity of the memory slices corresponding to different services, memory utilization can be improved and memory waste can be avoided.

[0043] In summary, in the embodiment of the present application, the memory manager in the computer device first determines the memory slices for storing different business data based on the business types corresponding to the different business data. Afterwards, the slice capacity of each memory slice can be dynamically adjusted according to the frequency at which the memory usage is greater than the memory waterline during business processing, which can increase the slice capacity of the memory slice with a higher interruption frequency and reduce the slice capacity of the memory slice with a lower interruption frequency. Compared with the method of estimating the memory capacity of the memory to maximize the use of memory in the related art, in the embodiment of the present application, the slice capacity of the memory slice corresponding to different businesses can be reasonably adjusted through the dynamic memory management mechanism, thereby improving memory utilization and helping to save memory space. And because the slice capacity is adjusted based on the interruption frequency, the frequent triggering of interrupts can be reduced, thereby helping to reduce power consumption and improve the efficiency of batch processing of business data.

[0044] During the data processing process, data may need to be moved from one node to another for processing. In this process, different memory nodes need to be set up to realize the movement of data. In one possible implementation, the memory can be divided into different memory nodes, and then the memory nodes are partitioned to obtain different memory partitions. In the process of node partitioning of the memory, the memory capacity required for the memory node can be determined first, and then the node partitioning can be performed based on the memory capacity. When partitioning each memory node, a preliminary division can also be performed based on the frequency of business use, and preliminary and reasonable planning of the memory can be performed. The following will be explained with exemplary embodiments.

[0045] Please refer to Figure 3 , which shows a flowchart of a memory management method provided by another exemplary embodiment of the present application. This embodiment takes the method executed by a memory manager in a computer device as an example to illustrate the process, which includes the following steps:

[0046] Step 301: divide the memory into nodes to obtain memory nodes, and memory migration occurs between different memory nodes.

[0047] In this embodiment, the memory manager first partitions the memory into nodes, thereby obtaining different memory nodes. In one possible implementation, the memory manager partitions the nodes based on whether memory migration is required for processed data. When memory migration is required, a memory node is configured to store the migrated data. This means that memory migration occurs between different memory nodes.

[0048] For example, consider the data processing of a modem chip. After the physical layer receives data from the network, it performs a series of data processing. After the data is processed, it is moved to the protocol layer, where it is then processed by the various processing layers within the protocol layer. When data is moved between the physical and protocol layers, the data in the physical layer's corresponding memory must be moved to the protocol layer's corresponding memory, which means memory transfer occurs. Therefore, the physical layer and protocol layer each correspond to a memory node. The protocol layer includes various processing layers such as MAC / RLC / PDCP / SDAP, and each processing layer within the protocol layer can access and process data in the same memory node. Therefore, when each processing layer within the protocol layer processes data, there is no memory transfer. The protocol layer can be considered a single node, corresponding to only one memory node.

[0049] During the partitioning process, the memory manager can determine the memory capacity required for each memory node, and then partition the memory into nodes based on the memory capacity required for each memory node. After the partitioning, the memory capacity of each memory node remains unchanged. In one possible implementation, the method for partitioning the memory into nodes may include steps 301a-301c (not shown in the figure):

[0050] Step 301a, based on the first data rate and the second data rate, determine the processing time of each data node for processing received data, where the data node refers to a node that processes memory node data, the first data rate refers to the rate at which the data node receives data, and the second data rate refers to the rate at which the data node processes data.

[0051] When the memory manager performs memory partitioning, it first determines the required content capacity of the corresponding memory node and then creates individual memory nodes based on the memory capacity. For each memory node, there is a data node that processes the data within it. In one possible implementation, memory capacity can be calculated based on the processing time of each data node. The processing time of a data node for processing received data refers to the unit time it takes to process received data.

[0052] Alternatively, when the data receiving rate is fast and the data processing rate is slow, the processing time is longer and the amount of memory required is greater. On the other hand, when the data receiving rate is the same as or slower than the data processing rate, the data can be processed promptly, the processing time is shorter, and therefore the amount of memory required is also smaller. Specifically, the processing time can be determined based on the ratio of the data node's data receiving rate (first data rate) to the data node's data processing rate (second data rate), thereby determining the content capacity based on the processing time.

[0053] For example, the data node is used as the protocol layer. The data rate supported by the protocol layer, i.e., the rate at which data is received, is 8G / s. When the corresponding CPU data processing rate is 4G / s, the processing time required for the CPU to process the data is 2s.

[0054] Step 301b: Determine the memory capacity required by each data node based on the processing time and the first data rate.

[0055] After the processing time is determined, the product of the processing time and the first data rate of received data can be determined as the memory capacity required by each data node.

[0056] Illustratively, when the first data rate of the data node is r and the processing time is t, the required memory capacity is r*t.

[0057] Step 301c: Based on the memory capacity required by each data node, the memory is divided into nodes to obtain memory nodes.

[0058] After determining the memory capacity required by each data node, the memory manager divides the memory into individual memory nodes based on the content capacity required by each node. This means that the memory capacity is determined based on each node's actual data processing capabilities, and node division is performed to maximize memory utilization.

[0059] Step 302 : partition the memory node based on the service usage frequency of the service type to obtain memory slices corresponding to different service types, wherein the service usage frequency is positively correlated with the slice capacity of the memory slice.

[0060] After obtaining each memory node, the memory manager divides the memory into sections. In one possible implementation, the terminal can count the service usage frequencies of different service types and then divide the memory nodes into sections based on the service usage frequencies. The higher the service usage frequency, the larger the memory section capacity can be allocated.

[0061] Optionally, services can be sorted by frequency of use, and the corresponding memory shards can be allocated based on the sorted service types. The memory manager can pre-set the memory shards corresponding to service types of different orders, and then partition the memory nodes based on the memory shards.

[0062] For example, taking the classification of five business types as an example, the proportion of memory slices corresponding to business types in different orders can be shown in Table 1:

[0063] Table 1

[0064] order Proportion 1 50％ 2-3 20％ 4-5 5％

[0065] After the memory slices are divided, the memory manager will set up a memory description table and a memory management table for each memory slice to facilitate the management of the memory slices.

[0066] The memory description table may be shown in Table 2:

[0067] Table 2

[0068] Description_0 Description_1 … Description_n …

[0069] Description_i represents the memory description of the i-th business unit within the memory slice, including its starting address and size. A business unit is the smallest memory unit that can be processed at any one time during business processing. Business units of different business types have different sizes; that is, the number of smallest memory units contained in a business unit varies for different business types. For example, business type 1 uses three smallest memory units to form a business unit, while business type 2 uses two smallest memory units to form a business unit.

[0070] The memory management table is shown in Table 3:

[0071] Table 3

[0072]

[0073]

[0074] Among them, In_data_base_address indicates the starting address of the memory slice, In_total_depth indicates the slice capacity of the memory slice, In_filled_depth indicates the used slice capacity (the number of stored business units), In_read_pointer indicates the pointer position of the data to be processed, In_write_pointer indicates the pointer position of the stored data, In_full indicates that the memory is full, In_empty indicates that the memory is empty (that is, no data is stored), Watermark_threshold indicates the threshold value of the memory watermark that triggers the processing interrupt after the memory is used to a certain amount, and enable indicates that the memory is enabled.

[0075] Step 303: Read the interrupt frequency of the memory slice from the interrupt frequency statistics table. The interrupt frequency statistics table stores the interrupt frequency of the memory slice corresponding to each service type. The interrupt frequency is updated when an interrupt is triggered.

[0076] In a possible implementation, in addition to the above-mentioned memory description table and memory management table, the memory manager is also provided with an interrupt frequency statistics table corresponding to the memory nodes, as shown in Table 4:

[0077] Table 4

[0078] InterruptFrequency_1 … InterruptFrequency_n ThresholdH ThresholdL

[0079] Among them, InterruptFrequency_i represents the interrupt frequency of the interrupt triggered by the memory slice i corresponding to the service type i.

[0080] During business processing, the memory manager counts the frequency of interrupts triggered by each memory slice and updates the interrupt frequency in the frequency statistics table in real time.

[0081] In a possible implementation, the memory manager may obtain the interrupt frequency in real time, and thereby adjust the slice capacity of the memory slice according to changes in the interrupt frequency.

[0082] Step 304: When the interrupt frequency of the memory slice is greater than the first frequency threshold, determine the memory slice as the first memory slice.

[0083] In one possible implementation, a pre-set first frequency threshold is stored in the memory manager. When the interrupt frequency of a memory slice exceeds the first frequency threshold, it indicates that the memory usage in the memory slice has exceeded the memory waterline a significant number of times, and therefore, the slice capacity of the corresponding memory slice needs to be increased. This memory slice can be determined as the first memory slice to be increased.

[0084] Optionally, the first frequency threshold may be stored in an interruption frequency statistics table, as shown in Table 4, which stores ThresholdH, indicating a high threshold of the interruption frequency, ie, the first frequency threshold.

[0085] Step 305: When the interrupt frequency of the memory slice is less than the second frequency threshold, the memory slice is determined as the second memory slice, and the first frequency threshold is greater than the second frequency threshold.

[0086] After determining the first memory area, the memory manager needs to determine a second memory area that can be reduced to avoid affecting the corresponding business processing process.

[0087] The memory manager stores a pre-set second frequency threshold, which is a low threshold for interrupt frequency and is lower than the first frequency threshold. When the interrupt frequency of a memory slice is less than the second frequency threshold, it indicates that the memory usage in the memory slice has rarely exceeded the memory waterline. Accordingly, the memory usage is relatively low, and the slice capacity of the corresponding memory slice can be reduced. Therefore, the memory slice can be determined as the second memory slice, which is a memory slice that can be reduced.

[0088] Optionally, the second frequency threshold may be stored in an interruption frequency statistics table, as shown in Table 4, which stores ThresholdL, indicating a lower threshold of the interruption frequency, ie, the second frequency threshold.

[0089] Step 306: Increase the slice capacity of the first memory slice and decrease the slice capacity of the second memory slice.

[0090] In one possible implementation, when a first memory slice and a second memory slice exist in a memory node, the memory manager adjusts the slice capacity of the memory slice to ensure that when the slice capacity of the memory slice is increased, it avoids affecting other business processing processes.

[0091] Optionally, the memory manager may increase the slice capacity of the first memory slice and decrease the slice capacity of the second memory slice, where the increased slice capacity is the same as the decreased slice capacity.

[0092] Indicative, such as Figure 4 As shown, when the interruption frequency of business type 2 is lower than the second frequency threshold and the interruption frequency of business type 3 is higher than the third frequency threshold, the slice capacity of business type 2 is reduced from the first capacity 401 to the second capacity 402, and the slice capacity of business type 3 is increased from the third capacity 403 to the fourth capacity 404, without the need to increase the memory capacity of the memory node.

[0093] The specific adjustment process can be referred to the following embodiment, which will not be described in detail in this embodiment.

[0094] In this embodiment, during the node division process, the required memory capacity is determined based on the node's data receiving rate and data processing rate, so that different nodes are divided according to the memory capacity required by each node. Compared with the related art method of accumulating memory capacity by estimating the maximum usage based on different business types, the maximum memory capacity can be planned based on the node's actual data processing capability, thereby improving memory utilization.

[0095] Furthermore, during the initial partitioning process, the initial partitioning is performed based on the frequency of service usage. Larger memory slices are allocated for frequently used services, which can reduce the need for subsequent frequent slice capacity adjustments. Furthermore, in this embodiment, the slice capacity of the memory slices is adjusted only after both the first and second memory slices are detected. By reducing the memory slices for inactive services and increasing the slice capacity for active services, the memory capacity of the memory node can be maintained unchanged. Only the proportion of memory slices for different service types is adjusted, which can reduce the impact on service processing.

[0096] During the process of adjusting the slice capacity of a memory slice, there may not be other memory slices between the first memory slice and the second memory slice. In this case, the slice capacity of the first memory slice and the second memory slice can be directly adjusted. In another possible case, there may be other memory slices. In this case, the other memory slices need to be moved to achieve the memory slice capacity adjustment. The following is an exemplary embodiment to illustrate.

[0097] like Figure 5 As shown, the above step 306 may include the following steps:

[0098] Step 306a: If there is no third memory area between the first memory area and the second memory area, adjust the adjacent start address and end address between the first memory area and the second memory area.

[0099] After the address adjustment, the distance between the first start address and the first end address of the first memory area increases, and the distance between the second start address and the second end address of the second memory area decreases.

[0100] In one possible case, after determining the first memory slice and the second memory slice, the memory manager may first determine whether there is a third memory slice between the first memory slice and the second memory slice. If there is no third memory slice, only adjacent addresses need to be adjusted.

[0101] Optionally, when the starting address (first starting address) of the first memory slice is adjacent to the ending address (second ending address) of the second memory slice, the first starting address of the first memory slice and the second ending address of the second memory slice can be adjusted, while the ending address (first ending address) of the first memory slice and the starting address (second starting address) of the second memory slice remain unchanged. Figure 6 As shown, the second starting address and the second ending address of the second memory slice are 1-20, while the first starting address and the first ending address of the first memory slice are 21-50. During the slice capacity adjustment process, the second ending address and the first starting address can be reduced simultaneously. After adjustment, the second starting address and the second ending address of the second memory slice are 1-15, while the first starting address and the first ending address of the first memory slice are 16-50, thereby increasing the slice capacity of the first memory slice and reducing the slice capacity of the second memory slice.

[0102] Optionally, when the first end address of the first memory slice is adjacent to the first start address of the second memory slice, the first end address of the first memory slice and the second start address of the second memory slice may be adjusted. The first end address and the second start address may be increased simultaneously while keeping the first start address and the second end address unchanged, thereby increasing the slice capacity of the first memory slice and reducing the slice capacity of the second memory slice.

[0103] Step 306b: When a third memory slice exists between the first memory slice and the second memory slice, determine a minimum migration path, where the number of third memory slices is the smallest.

[0104] In another possible case, there may be another third memory slice between the first memory slice and the second memory slice. In this case, during the slice capacity adjustment process, the third memory slice needs to be moved, that is, the starting address of the third memory slice (third starting address) and the ending address of the third memory slice (third ending address) need to be adjusted.

[0105] In one possible implementation, when a third memory slice exists, there may be different migration paths. The memory manager may determine the minimum migration path, thereby adjusting the slice capacity using the minimum migration path to improve adjustment efficiency. Determining the minimum migration path may include the following steps:

[0106] Step 1: Determine the number of slices in the third memory slice under different migration paths.

[0107] In a possible implementation, the memory manager may determine the number of slices of the third memory slice that need to be passed through under various migration paths.

[0108] Schematically, when the memory blocks corresponding to the memory nodes are 1-100, they include memory slice one (1-10), memory slice two (11-40), memory slice three (41-60), memory slice four (61-80), memory slice five (81-90) and memory slice six (91-100).

[0109] The first memory slice is memory slice 2, and the second memory slice is memory slice 4. Under the first migration path, the migration order can be memory slice 2, memory slice 3, memory slice 4, and the number of slices in the third memory slice is 1. Under the second migration path, the migration order can be memory slice 2, memory slice 1, memory slice 6, memory slice 5, and memory slice 4, and the number of slices in the third memory slice is 3.

[0110] Step 2: Determine the migration path corresponding to the minimum number of areas as the minimum migration path.

[0111] In a possible implementation, the memory manager may determine the migration path corresponding to the minimum number of slices as the minimum migration path, thereby adjusting the memory slices in a manner with the least slice adjustment amount, thereby improving adjustment efficiency.

[0112] Step 306c: Based on the minimum migration path, increase the slice capacity of the first memory slice and decrease the slice capacity of the second memory slice.

[0113] In one possible implementation, after determining the minimum migration path, the slice capacity of the first memory slice may be increased and the slice capacity of the second memory slice may be decreased based on the minimum migration path. This method may include the following steps:

[0114] Step 1: adjusting the first start address or the first end address of the first memory area according to the adjustment sequence indicated by the minimum shift path, so that the distance between the first start address and the first end address increases after the address adjustment.

[0115] In one possible implementation, the memory manager may sequentially adjust the first memory slice, the third memory slice, and the second memory slice according to the minimum migration path. The adjustment may be performed starting from the first memory slice or the second memory slice. This embodiment does not limit this.

[0116] During the adjustment process, from the first memory slice to the second memory slice, one of the first start address or the first end address of the first memory slice remains unchanged, and one of the second start address or the second end address of the second memory slice remains unchanged.

[0117] In the case where the first memory slice is used as the starting point, when the first starting address of the first memory slice remains unchanged, the second ending address of the second memory slice remains unchanged after the adjustment. And when the first ending address of the first memory slice remains unchanged, the second starting address of the second memory slice remains unchanged.

[0118] When the second memory slice is used as the starting point, when the second starting address of the second memory slice remains unchanged, the first ending address of the first memory slice remains unchanged, and when the second ending address of the second memory slice remains unchanged, the first starting address of the second memory slice remains unchanged.

[0119] That is, during the adjustment of the first memory area, only one of the first start address and the first end address needs to be adjusted.

[0120] Step 2: Adjust the third starting address and the third ending address of the third memory area, and the distance between the third starting address and the third ending address after the address adjustment remains unchanged.

[0121] During the adjustment of the third memory slice, the slice capacity of the third memory slice remains unchanged. Therefore, when the third starting address and the third ending address of the third memory slice need to be adjusted, the distance between the adjusted third starting address and the third ending address remains unchanged.

[0122] In one possible implementation, the first memory slice can be used as the starting point, or the second memory slice can be used as the starting point. When the first memory slice is used as the starting point, after the adjustment of the first memory slice is completed, the third starting address and the third ending address of the third memory slice are sequentially adjusted, and then the second memory slice is adjusted. When the second memory slice is used as the starting point, after the adjustment of the second memory slice is completed, the third starting address and the third ending address of the third memory slice are sequentially adjusted.

[0123] Step three: adjusting the second starting address or the second ending address of the second memory area, so that the distance between the second starting address and the second ending address is reduced after the address adjustment.

[0124] In a possible implementation, during the adjustment of the second memory area, only one of the second start address and the second end address needs to be adjusted.

[0125] Indicative, such as Figure 7 As shown, when under the minimum migration path, the address of the first memory slice is 11-40, the address of the third memory slice is 41-60, and the address of the second memory slice is 61-80, taking the adjustment starting point as the first memory slice as an example, the addresses of the adjusted memory slices are the first memory slice (11-45), the third memory slice (46-65), and the second memory slice (66-80).

[0126] In one possible scenario, the second memory slices obtained by the memory manager may include at least two memory slices, meaning there are at least two memory slices that can be reduced in size. In this case, to minimize the amount of adjustment, a second memory slice may be selected from the at least two second memory slices based on the minimum migration path between the slices.

[0127] Optionally, before increasing the slice capacity of the first memory slice and reducing the slice capacity of the second memory slice, when at least two second memory slices are included, a minimum migration path between the at least two second memory slices and the first memory slice is determined.

[0128] That is, when determining that at least two second memory slices are obtained, the memory manager determines the minimum migration path between each second memory slice and the first memory slice, and then reduces the second memory slice corresponding to the shortest minimum migration path.

[0129] Illustratively, when there are two third memory slices between the minimum migration path of the second memory slice A and the first memory slice, and there is one third memory slice between the minimum migration path of the second memory slice B and the first memory slice, the second memory slice B may be determined as the memory slice to be reduced. The memory manager reduces the memory capacity of the second memory slice B.

[0130] In this embodiment, when adjusting the slice capacity of a memory slice, if a third memory slice exists between a first and a second memory slice, the memory manager can select the minimum migration path for adjustment, thereby improving adjustment efficiency. Furthermore, if multiple second memory slices exist, one of the second memory slices can be selected based on the minimum migration path between each second memory slice and the first memory slice, further improving adjustment efficiency and minimizing the impact on business processing.

[0131] During the area capacity adjustment process, the amount of memory units required for the increased business type can be adjusted. The above step 306 may include the following steps:

[0132] Step 1: Determine the amount of memory units required to be added to the first memory area corresponding to the service type. The memory unit amount is the number of minimum memory units in the memory node.

[0133] In a possible implementation, the memory manager first determines the amount of memory units required to be added to the first memory slice corresponding to the service type, that is, the minimum number of memory units required to be added.

[0134] Optionally, the required increased amount of memory units may be determined based on a fixed ratio, for example, by increasing the current slice capacity of the first memory slice by 5%, and determining 5% of the slice capacity of the first slice as the increased amount of memory units.

[0135] Alternatively, the amount of memory units added can be dynamically adjusted based on the number of times the interrupt frequency exceeds the first frequency threshold. The more times the interrupt frequency exceeds the first frequency threshold, the more memory units are added, until the upper limit of memory unit increase is reached. For example, the first time the interrupt frequency exceeds the first frequency threshold, the amount of memory units added can be increased by 5%, and the second time the interrupt frequency exceeds the first frequency threshold, the amount of memory units added can be increased by 8%, until the upper limit of memory unit increase is 20%.

[0136] Step 2: Based on the amount of memory cells, increase the slice capacity of the first memory slice.

[0137] The memory manager increases the slice capacity of the first memory slice according to the memory unit quantity, and the minimum number of memory units included in the adjusted first memory slice is the sum of the minimum number of memory units included in the first memory slice before adjustment and the memory unit quantity.

[0138] Step three: based on the amount of memory cells, reduce the slice capacity of the first memory slice.

[0139] The memory manager reduces the slice capacity of the second memory slice according to the memory unit quantity, and the minimum number of memory units included in the adjusted second memory slice is the difference between the minimum number of memory units included in the second memory slice before adjustment and the memory unit quantity.

[0140] In the above method, the slice capacity is adjusted directly according to the amount of memory units required to increase the business type. However, since the business unit sizes corresponding to different business types are different, that is, the number of minimum memory units that can be processed at a single time is different. For example, the business unit size of the first business corresponding to the first memory slice is 3 minimum memory units, and the business unit size of the second business corresponding to the second memory slice is 2 minimum memory units. When the first business needs to increase by 3 business units, 9 minimum memory units need to be added. If the 9 minimum memory units of the second business are reduced, there will be a single minimum memory unit in the second memory slice, which cannot form the business unit of the second business. Memory fragmentation will appear in the second memory slice, resulting in memory waste. Therefore, in another possible implementation, the memory adjustment granularity can be set, and adjustments can be made based on the memory adjustment granularity. This method may include the following steps:

[0141] Step 1: Obtain the business unit size of each memory slice. The business unit size refers to the number of units of the smallest memory unit that is processed at a single time during business processing.

[0142] In one possible implementation, the memory manager can obtain the business unit size of each business type corresponding to each memory slice in the memory node, thereby determining the memory adjustment granularity based on the business unit size. The memory adjustment granularity refers to the adjustment base unit during slice capacity adjustment, that is, the minimum base number of memory units to be adjusted. The final adjusted slice capacity is an integer multiple of the memory adjustment granularity.

[0143] Alternatively, during each adjustment process, the memory manager can obtain the business unit size of the business type corresponding to each memory slice in the migration path (including the business unit size corresponding to the first memory slice, the second memory slice, and the third memory slice), and thus determine the memory adjustment granularity based on the business unit size of the memory slice adjusted in the migration path.

[0144] Step 2: Determine the lowest common multiple of the sizes of each business unit as the memory adjustment granularity. The memory adjustment granularity refers to the baseline number of the minimum memory units adjusted during the slice capacity adjustment process. The adjusted slice capacity is an integer multiple of the memory adjustment granularity.

[0145] In one possible implementation, the memory manager may determine the lowest common multiple of the business unit sizes as the memory adjustment granularity. For example, if the business unit sizes include 2 and 3, 6 may be determined as the memory adjustment granularity. During the slice capacity adjustment process, adjustments must be made based on the 6 smallest memory units.

[0146] Step three: based on the memory adjustment granularity, increase the slice capacity of the first memory slice and reduce the slice capacity of the second memory slice.

[0147] After determining the memory adjustment granularity, the memory manager can increase the slice capacity of the first memory slice and reduce the slice capacity of the second memory slice based on the memory adjustment granularity. Among them, the amount of memory units to be increased can be determined first. When the increased amount of memory units is an integer multiple of the memory adjustment granularity, the slice capacity can be adjusted directly based on the increased amount of memory units. For example, if the memory adjustment granularity is 6 and the amount of memory units to be increased is 12, the slice capacity can be adjusted based on 12. When the increased amount of memory units is not an integer multiple of the memory adjustment granularity, an integer multiple of the memory adjustment granularity that is greater than the amount of memory units needs to be determined as the adjusted slice capacity. For example, when the amount of memory units to be increased is 15, the adjusted slice capacity can be determined to be 18, and the memory manager increases the first memory slice by 18 minimum memory units and reduces the second memory slice by 18 memory units.

[0148] Since the memory adjustment granularity is the lowest common multiple of the sizes of each business unit, memory fragmentation can be effectively avoided when different businesses correspond to different business unit sizes.

[0149] In this embodiment, during the adjustment process, the memory adjustment granularity is determined based on the size of each business unit, and the slice capacity of the memory slice is adjusted based on the memory adjustment granularity, which can avoid the generation of memory fragmentation during the adjustment process and avoid memory waste.

[0150] Please refer to Figure 8 , which shows a structural block diagram of a memory management device provided by an embodiment of the present application. Figure 8 As shown, the device may include:

[0151] The memory partitioning module 801 is used to determine the memory area according to the business type corresponding to different business data;

[0152] The memory adjustment module 802 is used to adjust the slice capacity of the memory slice based on the interruption frequency of the memory slice during business processing, wherein the interruption frequency refers to the frequency at which the memory usage of the memory slice is greater than the memory waterline, and the memory waterline is the threshold value for triggering an interruption of the memory slice.

[0153] Optionally, the memory adjustment module 802 is further configured to:

[0154] When the interrupt frequency of the memory slice is greater than a first frequency threshold, determining the memory slice as a first memory slice;

[0155] In a case where the interrupt frequency of the memory slice is less than a second frequency threshold, determining the memory slice as a second memory slice, and the first frequency threshold is greater than the second frequency threshold;

[0156] The slice capacity of the first memory slice is increased, and the slice capacity of the second memory slice is decreased.

[0157] Optionally, the memory adjustment module 802 is further configured to:

[0158] In the case that there is no third memory slice between the first memory slice and the second memory slice, the adjacent start address and end address between the first memory slice and the second memory slice are adjusted, wherein the distance between the first start address and the first end address of the first memory slice after the address adjustment is increased, and the distance between the second start address and the second end address of the second memory slice is reduced.

[0159] Optionally, the memory adjustment module 802 is further configured to:

[0160] If a third memory slice exists between the first memory slice and the second memory slice, determining a minimum migration path, wherein the number of the third memory slice is the smallest under the minimum migration path;

[0161] Based on the minimum migration path, the slice capacity of the first memory slice is increased, and the slice capacity of the second memory slice is reduced.

[0162] Optionally, the memory adjustment module 802 is further configured to:

[0163] Adjusting the first start address or the first end address of the first memory slice according to the adjustment order indicated by the minimum shift path, so that the distance between the first start address and the first end address increases after the address adjustment;

[0164] Adjusting a third starting address and a third ending address of the third memory area, wherein the distance between the third starting address and the third ending address after the address adjustment remains unchanged;

[0165] The second starting address or the second ending address of the second memory area is adjusted, and the distance between the second starting address and the second ending address after the address adjustment is reduced.

[0166] Optionally, the memory adjustment module 802 is further configured to:

[0167] Determining the number of slices of the third memory slice under different migration paths;

[0168] The shifting path corresponding to the minimum number of the areas is determined as the minimum shifting path.

[0169] Optionally, the memory adjustment module 802 is further configured to:

[0170] In the case where at least two second memory slices are included, determining a minimum migration path between the at least two second memory slices and the first memory slice;

[0171] The second memory area corresponding to the minimum shift path with the shortest path is reduced.

[0172] Optionally, the memory adjustment module 802 is further configured to:

[0173] Determine the amount of memory units required to be added to the first memory slice corresponding to the service type, where the amount of memory units is the number of minimum memory units in the memory node;

[0174] increasing a slice capacity of the first memory slice based on the amount of memory cells;

[0175] Based on the memory cell quantity, a slice capacity of the first memory slice is reduced.

[0176] Optionally, the memory adjustment module 802 is further configured to:

[0177] Obtaining a business unit size of each of the memory slices, where the business unit size refers to the number of minimum memory units that can be processed at a single time during business processing;

[0178] Determining the least common multiple of the sizes of the service units as a memory adjustment granularity, wherein the memory adjustment granularity refers to a base number of minimum memory units adjusted during a slice capacity adjustment process, and the adjusted slice capacity is an integer multiple of the memory adjustment granularity;

[0179] Based on the memory adjustment granularity, the slice capacity of the first memory slice is increased, and the slice capacity of the second memory slice is reduced.

[0180] Optionally, the memory partitioning module 801 is further configured to:

[0181] Divide the memory into nodes to obtain memory nodes, and move memory between different memory nodes;

[0182] Based on the service usage frequency corresponding to the service type, the memory node is partitioned to obtain memory slices corresponding to different service types, wherein the service usage frequency is positively correlated with the slice capacity of the memory slice.

[0183] Optionally, the memory partitioning module 801 is further configured to:

[0184] Determining, based on a first data rate and a second data rate, a processing time for each data node to process received data, wherein the data node is a node that processes memory node data, the first data rate is a rate at which the data node receives data, and the second data rate is a rate at which the data node processes data;

[0185] determining a memory capacity required by each of the data nodes based on the processing time and the first data rate;

[0186] Based on the memory capacity required by each of the data nodes, the memory is divided into nodes to obtain the memory nodes.

[0187] Optionally, the device further includes:

[0188] The frequency acquisition module is used to read the interrupt frequency of the memory slice from the interrupt frequency statistics table, wherein the interrupt frequency statistics table stores the interrupt frequency of the memory slice corresponding to each service type, and the interrupt frequency is updated when the interrupt is triggered.

[0189] In summary, in an embodiment of the present application, the memory manager in the computer device first determines the memory slices corresponding to the different business data based on the business types corresponding to the different business data. Afterwards, the slice capacity of each memory slice can be dynamically adjusted according to the frequency at which the memory usage is greater than the memory waterline during business processing, which can increase the slice capacity of the memory slice with a higher interruption frequency and reduce the slice capacity of the memory slice with a lower interruption frequency. Compared with the method of estimating the memory capacity by maximizing the use of memory for business planning in the related art, in an embodiment of the present application, the slice capacity of the memory slice corresponding to different business types can be reasonably adjusted through a dynamic memory management mechanism, thereby improving memory utilization and helping to save memory space. And because the slice capacity is adjusted based on the interruption frequency, the frequent triggering of interrupts can be reduced, thereby helping to reduce power consumption and improving the efficiency of batch processing of business data.

[0190] It should be noted that the apparatus provided in the above embodiments is merely exemplified by the division of the above functional modules. In actual applications, the above functions can be distributed among different functional modules as needed, that is, the internal structure of the apparatus can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments are based on the same concept. The implementation process is detailed in the method embodiments and will not be repeated here.

[0191] Please refer to Figure 9 , which shows a structural block diagram of a computer device 900 provided by an exemplary embodiment of the present application. The computer device 900 in the present application may include one or more of the following components: a processor 910 and a memory 920.

[0192] The processor 910 may include one or more processing cores. The processor 910 utilizes various interfaces and circuits to connect various components within the electronic device 900. It executes instructions, programs, code sets, or instruction sets stored in the memory 920, as well as accesses data stored in the memory 920, to perform various functions of the electronic device 900 and process data. Optionally, the processor 910 may be implemented using at least one of the following hardware forms: a digital signal processing (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 910 may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU primarily processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing content displayed on the display; and the modem handles wireless communications. It is understood that the modem may not be integrated into the processor 910 and may be implemented separately via a baseband chip.

[0193] The memory 920 may include a memory 921 and a memory manager 922. The memory 921 includes a random access memory (RAM) and may also include a read-only memory (ROM). Optionally, the memory 920 includes a non-transitory computer-readable storage medium. The memory 921 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 921 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc. The operating system may be an Android system (including a system deeply developed based on the Android system), an iOS system developed by Apple (including a system deeply developed based on the iOS system), or other systems. The data storage area may also store data created by the computer device 900 during use (such as a phone book, audio and video data, chat history data, etc.).

[0194] The memory 920 may further include a memory manager 922 . The memory manager 922 includes programmable logic circuits and / or program instructions for managing the memory of the computer device 900 .

[0195] In addition, those skilled in the art will appreciate that the structure of the computer device 900 shown in the above figures does not limit the computer device 900. The computer device may include more or fewer components than shown, or may combine certain components or arrange the components differently. For example, the computer device 900 may also include a radio frequency circuit, a camera component, a sensor, an audio circuit, a wireless fidelity (WiFi) component, a power supply, a Bluetooth component, and other components, which will not be described in detail here.

[0196] The present application also provides a computer-readable storage medium, which stores at least one instruction, at least one program, code set or instruction set. The at least one instruction, the at least one program, the code set or instruction set is loaded and executed by a processor to implement the memory management method provided by any of the above exemplary embodiments.

[0197] An embodiment of the present application provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the memory management method provided in the above-mentioned optional implementation.

[0198] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0199] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A memory management method, characterized in that: The method comprises: Determine the memory area based on the business type corresponding to different business data; Counting the interrupt frequency of each memory slice, where the interrupt frequency refers to the frequency at which the memory usage of the memory slice exceeds the memory watermark, where the memory watermark is the threshold at which the memory slice triggers an interrupt, and the processor processes data in the memory slice when the memory slice triggers an interrupt; Based on the interruption frequency of the memory slice during business processing, the slice capacity of the memory slice is adjusted to reduce the probability of the memory slice triggering an interruption, wherein the memory adjustment granularity used during the adjustment is the lowest common multiple of the business unit sizes of the business types corresponding to the various memory slices, the business unit size refers to the number of units of the minimum memory unit processed in a single time during business processing, the memory adjustment granularity refers to the baseline number of the minimum memory units adjusted during the slice capacity adjustment process, and the adjusted slice capacity is an integer multiple of the memory adjustment granularity.

2. The method according to claim 1, characterized in that The adjusting the slice capacity of the memory slice based on the interrupt frequency of the memory slice during the service processing includes: When the interrupt frequency of the memory slice is greater than a first frequency threshold, determining the memory slice as a first memory slice; In a case where the interrupt frequency of the memory slice is less than a second frequency threshold, determining the memory slice as a second memory slice, and the first frequency threshold is greater than the second frequency threshold; The slice capacity of the first memory slice is increased, and the slice capacity of the second memory slice is decreased.

3. The method according to claim 2, characterized in that The increasing the slice capacity of the first memory slice and reducing the slice capacity of the second memory slice include: In the case that there is no third memory slice between the first memory slice and the second memory slice, the adjacent start address and end address between the first memory slice and the second memory slice are adjusted, wherein the distance between the first start address and the first end address of the first memory slice after the address adjustment is increased, and the distance between the second start address and the second end address of the second memory slice is reduced.

4. The method according to claim 2, characterized in that The increasing the slice capacity of the first memory slice and reducing the slice capacity of the second memory slice include: If a third memory slice exists between the first memory slice and the second memory slice, determining a minimum migration path, wherein the number of the third memory slice is the smallest under the minimum migration path; Based on the minimum migration path, the slice capacity of the first memory slice is increased, and the slice capacity of the second memory slice is reduced.

5. The method according to claim 4, characterized in that The increasing the slice capacity of the first memory slice and decreasing the slice capacity of the second memory slice based on the minimum migration path includes: Adjusting the first start address or the first end address of the first memory slice according to the adjustment order indicated by the minimum shift path, so that the distance between the first start address and the first end address increases after the address adjustment; Adjusting a third starting address and a third ending address of the third memory area, wherein the distance between the third starting address and the third ending address after the address adjustment remains unchanged; The second starting address or the second ending address of the second memory area is adjusted, and the distance between the second starting address and the second ending address after the address adjustment is reduced.

6. The method according to claim 4, characterized in that Determining the minimum shift path includes: Determining the number of slices of the third memory slice under different migration paths; The shifting path corresponding to the minimum number of the areas is determined as the minimum shifting path.

7. The method according to claim 4, characterized in that Before increasing the slice capacity of the first memory slice and reducing the slice capacity of the second memory slice, the method further includes: In the case where at least two second memory slices are included, determining a minimum migration path between the at least two second memory slices and the first memory slice; The reducing the slice capacity of the second memory slice includes: The second memory area corresponding to the minimum shift path with the shortest path is reduced.

8. The method according to any one of claims 2 to 7, characterized in that: The increasing the slice capacity of the first memory slice and reducing the slice capacity of the second memory slice include: Determine the amount of memory units required to be added to the first memory slice corresponding to the service type, where the amount of memory units is the number of minimum memory units in the memory node; increasing a slice capacity of the first memory slice based on the amount of memory cells; Based on the memory cell quantity, a slice capacity of the first memory slice is reduced.

9. The method according to any one of claims 1 to 7, characterized in that: Before determining the memory slices according to the service types corresponding to the different service data, the method further includes: Divide the memory into nodes to obtain memory nodes, and move memory between different memory nodes; Determining the memory area according to the business type corresponding to different business data includes: Based on the service usage frequency corresponding to the service type, the memory node is partitioned to obtain memory slices corresponding to different service types, wherein the service usage frequency is positively correlated with the slice capacity of the memory slice.

10. The method according to claim 9, characterized in that The memory is divided into nodes to obtain memory nodes, including: Determining, based on a first data rate and a second data rate, a processing time for each data node to process received data, wherein the data node is a node that processes memory node data, the first data rate is a rate at which the data node receives data, and the second data rate is a rate at which the data node processes data; determining a memory capacity required by each of the data nodes based on the processing time and the first data rate; Based on the memory capacity required by each of the data nodes, the memory is divided into nodes to obtain the memory nodes.

11. The method according to any one of claims 1 to 7, characterized in that: Before adjusting the slice capacity of the memory slice based on the interrupt frequency of the memory slice during the service processing, the method further includes: The interrupt frequency of the memory slice is read from an interrupt frequency statistics table, where the interrupt frequency statistics table stores the interrupt frequency of the memory slice corresponding to each of the service types.

12. A memory management device, characterized in that: The device comprises: The memory partitioning module is used to determine the memory area according to the business type corresponding to different business data; a memory adjustment module, configured to count the interrupt frequency of each of the memory slices, where the interrupt frequency refers to the frequency at which the memory usage of the memory slice exceeds the memory watermark, where the memory watermark is the threshold at which the memory slice triggers an interrupt, and the processor processes data in the memory slice when the memory slice triggers an interrupt; Based on the interruption frequency of the memory slice during business processing, the slice capacity of the memory slice is adjusted to reduce the probability of the memory slice triggering an interruption, wherein the memory adjustment granularity used during the adjustment is the lowest common multiple of the business unit sizes of the business types corresponding to the various memory slices, the business unit size refers to the number of units of the minimum memory unit processed in a single time during business processing, the memory adjustment granularity refers to the baseline number of the minimum memory units adjusted during the slice capacity adjustment process, and the adjusted slice capacity is an integer multiple of the memory adjustment granularity.

13. A memory manager, characterized in that: The memory manager includes a programmable logic circuit and / or program instructions, and is used to implement the memory management method according to any one of claims 1 to 11 when the memory manager is running.

14. A computer device, characterized in that: The computer device comprises a processor and a memory, wherein the memory comprises a memory and a memory manager as claimed in claim 13 .

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one program code, and the program code is loaded and executed by a processor to implement the memory management method according to any one of claims 1 to 11.

16. A computer program product, characterized in that The computer program product includes computer instructions, which are stored in a computer-readable storage medium. A processor reads and executes the computer instructions from the computer-readable storage medium to implement the memory management method according to any one of claims 1 to 11.

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