A method for detecting memory data failure and a related device

Abstract

The application discloses a method for detecting memory data faults and a related device thereof, and is applied to the storage field. The method comprises the following steps: detecting whether the data stored in the first memory space is faulty in a patrol cycle, the patrol cycle is a cycle for detecting the DDR5 memory, the first memory space belongs to the DDR5 memory, the data comprises N data bits, and N is greater than or equal to 1. In the patrol process, when it is detected that the data is faulty, the fault information corresponding to the faulty data is obtained from a memory mode register, the fault information at least comprises a memory address corresponding to the faulty data, wherein the memory mode register is located in the DDR5 memory, the memory mode register is used for saving the mapping relationship between the data stored in the first memory space and the memory address, and the fault information is sent to an OS or a BMC. In the application, the position of the faulty data stored in the perception DDR5 memory is accurately positioned, the data faults are detected, and no additional hardware circuit is needed, so that the cost is reduced.

Description

Technical Field

[0001] This application relates to the field of storage, and more particularly to a method and related equipment for detecting memory data faults. Background Technology

[0002] With the rapid development of computing power in the technology industry, the capacity of memory is getting larger and larger. For double data rate synchronous dynamic random access memory (DDR SDRAM), facing higher capacity, faster speed and smaller process technology, the possibility of unit errors in memory arrays will increase, and the failure rate will also be higher.

[0003] DDR5 reduces the defect rate of memory chips and ensures data accuracy under high speed and high density by using on-die error correcting codes (ECC). Specifically, it uses additional ECC memory to detect and correct errors before data is sent to the central processing unit (CPU). However, because the system lacks an additional bus for transmitting ECC data, it cannot detect ECC errors detected by on-die ECC, meaning the system cannot detect memory failures. A current technology adds hardware circuitry to provide an alarm signal to the memory controller when an ECC error exceeds a threshold, allowing the system to detect a memory failure. However, while alarm signals can detect the occurrence of a failure, they cannot pinpoint its exact location, and hardware implementation increases costs. Summary of the Invention

[0004] This application provides a method and related equipment for detecting memory data faults, applicable to the DDR5 memory field. It can accurately pinpoint the severity and precise location of data faults in the memory without requiring additional hardware circuitry, thus reducing costs and making it suitable for a wider range of applications.

[0005] Firstly, a method for detecting memory data faults is provided, the method comprising:

[0006] During the inspection cycle, the system checks whether the data stored in the first memory space has been faulty. This inspection cycle is the cycle for checking DDR5 memory. The first memory space is DDR5 memory, and its data includes N data bits, where N is greater than or equal to 1.

[0007] Furthermore, during the inspection process, when a data fault is detected, the fault information corresponding to the faulty data is obtained from the memory mode register. The fault information includes at least the memory address corresponding to the faulty data. The memory mode register is used to manage DDR5 memory and to store the mapping relationship between the data to be inspected and the memory address.

[0008] Then, the fault information is sent to the operating system (OS) or baseboard management controller (BMC).

[0009] In the embodiments of this application, when it is determined that at least one data in the first memory space has failed during the inspection cycle, fault information including at least the memory address of the faulty data is obtained and sent to the OS or BMC. This can accurately locate the severity and precise location of the data fault in memory, without the need to add additional hardware circuits, thus reducing costs and making it suitable for more application scenarios.

[0010] In one possible implementation of the first aspect, the value of the inspection cycle and a first memory space are configured in the basic input output system (BIOS) or BMC, and the first memory space is less than or equal to the data storage space of DDR5 memory.

[0011] In the embodiments of this application, the value of the first inspection cycle and the first memory space are configured in multiple ways, which increases the application scenarios of the solution and improves the selectivity of the solution.

[0012] In one possible implementation of the first aspect, when a fault is detected in the first data, the inspection is stopped, and at least the first memory address corresponding to the first data is obtained from the memory mode register. The first data is the data stored in the aforementioned first memory space.

[0013] In the embodiments of this application, a specific implementation method is described for obtaining the corresponding fault information when there is a data fault during the inspection process, thereby improving the reliability of the solution.

[0014] In one possible implementation of the first aspect, after obtaining at least the first memory address corresponding to the first data from the memory mode register, the second data in the first memory space is continued to be inspected, and the second data is the remaining data to be inspected in the first memory space.

[0015] In the embodiments of this application, when there is faulty data, after obtaining the fault information of the faulty data, the remaining data to be inspected can be continued to ensure that the data of the entire first memory space is inspected, thus guaranteeing the reliability of the memory data.

[0016] In one possible implementation of the first aspect, during the inspection cycle, a piece of data and its corresponding first checksum are acquired from the first memory space each time. Then, a corresponding second checksum is obtained based on the acquired data. If the first checksum and the second checksum are different, it is determined that the data is faulty; or, if the first checksum and the second checksum are the same, it is determined that the data is fault-free.

[0017] The embodiments of this application demonstrate a specific implementation method for detecting whether the detection data has failed, thereby increasing the reliability of the solution.

[0018] In one possible implementation of the first aspect, when a faulty data is detected, the faulty data is corrected to obtain the target data, and the target data is written to the memory address of the faulty data.

[0019] In the embodiments of this application, the faulty data is corrected to obtain the target data, and the target data is written to the memory address of the faulty data, thereby further ensuring that the data stored in the DDR5 memory remains accurate.

[0020] In one possible implementation of the first aspect, the number of faults is obtained, which is the number of faults that occurred within the current inspection cycle, and then the value of the inspection cycle is adjusted based on the number of faults.

[0021] In the embodiments of this application, the value of the inspection cycle can be flexibly adjusted. When the number of failures is high, the inspection frequency can be increased, which can more accurately and in real time monitor the possibility of data failure, ensure the reliability of the data in memory, and improve the flexibility of the solution.

[0022] In one possible implementation of the first aspect, after at least two inspection cycles, a fault-free address range in the first memory space within the first memory space is obtained, and the memory space in the first memory space that does not include the fault-free address range is determined to be the second memory space, i.e., the second memory space is smaller than the first memory space. Furthermore, in the next inspection cycle, it is detected whether the data stored in the second memory space has experienced a fault.

[0023] In the embodiments of this application, the second memory space is detected within the inspection cycle. That is, after a certain number of inspection cycles, the data of addresses that have not experienced faults are no longer inspected, which can improve inspection efficiency and reduce the occupation of device resources.

[0024] In one possible implementation of the first aspect, after inspecting the second memory space within a certain number of inspection cycles, the data in the first memory space is checked again in the next inspection cycle to see if a fault has occurred.

[0025] In one implementation, the number of times can be at least two or more, and the specific number can be determined according to the actual situation. For example, the fault frequency of the detection results of the aforementioned multiple inspection cycles. When there are many faults, all data in the first memory space can be detected after three or five times in the inspection cycle. When there are few faults, all data in the first memory space can be detected after 10 or more times in the inspection cycle.

[0026] In the embodiments of this application, all data in the first memory space is checked again to ensure the overall fault-free operation of the DDR5 memory as much as possible and improve the reliability of memory data.

[0027] In one possible implementation of the first aspect, the fault information further includes a current row address error count and / or a current column address error count. The current row address error count indicates the number of times an error occurred at the memory address of the faulty data in the row, and the current column address error count indicates the number of times an error occurred at the memory address of the faulty data in the column.

[0028] In the embodiments of this application, the memory address of the faulty data in the first memory space, as well as the current row address error count and / or the current column address error count, are obtained. This allows for accurate location of the severity and precise position of the memory fault without the need for additional hardware circuitry, reducing costs and making it suitable for more application scenarios.

[0029] In one possible implementation of the first aspect, after obtaining the fault information, the fault information is sent to the target device, so that the target device determines the target address based on the fault information. The target device stores a large fault data of DDR5 memory data.

[0030] In the embodiments of this application, sending fault information to the target device enriches the fault big data and can improve the accuracy and precision of fault risk prediction.

[0031] In one possible implementation of the first aspect, the target device determines the target address based on the fault information. The target device can predict the risk of faults in the data of other DDR5 memory associated with the target device at the same target address based on the target address, and can simultaneously perform memory repair isolation on the target address of the remaining DDR5 memory.

[0032] In the embodiments of this application, the target device predicts that other DDR5 memory of the same type have the same risk through the target address and takes measures to increase the application scenarios and improve the overall work efficiency of the application scenarios, reduce the workload of fault inspection of individual DDR5 memory data, and ensure the reliability of memory data as much as possible.

[0033] In one possible implementation of the first aspect, memory repair isolation is either hard isolation repair or soft isolation repair.

[0034] In the embodiments of this application, the multiple memory repair isolation methods increase the application scenarios of the solution and reflect the selectivity and flexibility of the solution.

[0035] Secondly, a processing apparatus is provided, the processing apparatus comprising:

[0036] The processing unit is used to detect whether the data stored in the first memory space has failed during the inspection cycle. The inspection cycle is the cycle for detecting DDR5 memory. The first memory space is DDR5 memory, and its data includes N data bits, where N is greater than or equal to 1.

[0037] The acquisition unit is used to acquire the fault information corresponding to the faulty data from the memory mode register when a fault is detected during the inspection process. The fault information includes at least the memory address corresponding to the faulty data. The memory mode register is used to manage DDR5 memory and to store the mapping relationship between the data to be inspected and the memory address.

[0038] The transmitting unit is used to send fault information to the operating system (OS) or the baseboard management controller (BMC).

[0039] In the embodiments of this application, when it is determined that at least one data in the first memory space has failed during the inspection cycle, fault information including at least the memory address of the faulty data is obtained and sent to the OS or BMC. This can accurately locate the severity and precise location of the data fault in memory, without the need to add additional hardware circuits, thus reducing costs and making it suitable for more application scenarios.

[0040] In one possible implementation of the second aspect, the processing unit is further configured in the BIOS or BMC to configure the value of the inspection cycle and the first memory space, wherein the first memory space is less than or equal to the data storage space of the DDR5 memory.

[0041] In the embodiments of this application, the value of the first inspection cycle and the first memory space are configured in multiple ways, which increases the application scenarios of the solution and improves the selectivity of the solution.

[0042] In one possible implementation of the second aspect, the acquisition unit is specifically used to stop the inspection when a fault is detected in the first data, and to acquire at least the first memory address corresponding to the first data from the memory mode register, wherein the first data is the data stored in the aforementioned first memory space.

[0043] In the embodiments of this application, a specific implementation method is described for obtaining the corresponding fault information when there is a data fault during the inspection process, thereby improving the reliability of the solution.

[0044] In one possible implementation of the second aspect, after the processing unit obtains at least the first memory address corresponding to the first data from the memory mode register, it is also used to continue to inspect the second data in the first memory space, which is the remaining data to be inspected in the first memory space.

[0045] In the embodiments of this application, when there is faulty data, after obtaining the fault information of the faulty data, the remaining data to be inspected can be continued to ensure that the data of the entire first memory space is inspected, thus guaranteeing the reliability of the memory data.

[0046] In one possible implementation of the second aspect, the acquisition unit is further configured to acquire, during the inspection cycle, a piece of data in the first memory space and the first check code corresponding to that data each time.

[0047] Then the processing unit is specifically used to obtain the corresponding second check code based on the acquired data, and to determine that the data is faulty based on the difference between the first check code and the second check code corresponding to the data, or to determine that the data is fault-free based on the same first check code and the second check code corresponding to the data.

[0048] The embodiments of this application demonstrate a specific implementation method for detecting whether the detection data has failed, thereby increasing the reliability of the solution.

[0049] In one possible implementation of the second aspect, when the processing unit detects a fault in the data, it is also used to correct the faulty data to obtain the target data.

[0050] The sending unit is also used to write target data to the memory address of the faulty data.

[0051] In the embodiments of this application, the faulty data is corrected to obtain the target data, and the target data is written to the memory address of the faulty data, thereby further ensuring that the data stored in the DDR5 memory remains accurate.

[0052] In one possible implementation of the second aspect, the acquisition unit is also used to acquire the number of faults, which is the number of faults that occur within the current inspection cycle.

[0053] The processing unit is then used to adjust the inspection cycle value based on the number of failures.

[0054] In the embodiments of this application, the value of the inspection cycle can be flexibly adjusted. When the number of failures is high, the inspection frequency can be increased, which can more accurately and in real time monitor the possibility of data failure, ensure the reliability of the data in memory, and improve the flexibility of the solution.

[0055] In one possible implementation of the second aspect, the acquisition unit is also used to acquire the fault-free address range in the first memory space within at least two inspection cycles after at least two inspection cycles.

[0056] The processing unit is also configured to determine that the memory space in the first memory space excluding the fault-free address range is the second memory space, i.e., the second memory space is smaller than the first memory space. Furthermore, in the next inspection cycle, it is configured to detect whether the data stored in the second memory space has experienced a fault.

[0057] In the embodiments of this application, the second memory space is detected within the inspection cycle. That is, after a certain number of inspection cycles, the data of addresses that have not experienced faults are no longer inspected, which can improve inspection efficiency and reduce the occupation of device resources.

[0058] In one possible implementation of the second aspect, after the processing unit inspects the second memory space within a certain number of inspection cycles, it is also used to check again in the next inspection cycle whether the data in the first memory space has failed.

[0059] In one implementation, the number of times can be at least two or more, and the specific number can be determined according to the actual situation. For example, the fault frequency of the detection results of the aforementioned multiple inspection cycles. When there are many faults, all data in the first memory space can be detected after three or five times in the inspection cycle. When there are few faults, all data in the first memory space can be detected after 10 or more times in the inspection cycle.

[0060] In the embodiments of this application, all data in the first memory space is checked again to ensure the overall fault-free operation of the DDR5 memory as much as possible and improve the reliability of memory data.

[0061] In one possible implementation of the second aspect, the fault information further includes a current row address error count and / or a current column address error count. The current row address error count indicates the number of times an error occurred at the memory address of the faulty data in the row, and the current column address error count indicates the number of times an error occurred at the memory address of the faulty data in the column.

[0062] In the embodiments of this application, the memory address of the faulty data in the first memory space, as well as the current row address error count and / or the current column address error count, are obtained. This allows for accurate location of the severity and precise position of the memory fault without the need for additional hardware circuitry, reducing costs and making it suitable for more application scenarios.

[0063] In one possible implementation of the second aspect, after obtaining the fault information, the sending unit is also used to send the fault information to the target device, so that the target device can determine the target address based on the fault information. The target device stores a large fault data of DDR5 memory data.

[0064] In the embodiments of this application, sending fault information to the target device enriches the fault big data and can improve the accuracy and precision of fault risk prediction.

[0065] In one possible implementation of the second aspect, memory repair isolation is either hard isolation repair or soft isolation repair.

[0066] In the embodiments of this application, the multiple memory repair isolation methods increase the application scenarios of the solution and reflect the selectivity and flexibility of the solution.

[0067] Thirdly, another computing device is provided, which may include a processor coupled to a memory for storing instructions, wherein the processor executes the instructions in the memory to cause the computing device to perform the method described in the first aspect of this application or any possible implementation thereof.

[0068] Fourthly, another computing device is provided, including a processor for executing a computer program (or computer-executable instructions) stored in memory, which, when executed, causes the methods of the first aspect and various possible implementations of the first aspect to be performed.

[0069] In one possible implementation, the processor and memory are integrated together;

[0070] In another possible implementation, the aforementioned memory is located outside the computing device.

[0071] The computing device also includes a communication interface for communicating with other devices, such as sending or receiving data and / or signals. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0072] The fifth aspect provides a computer-readable storage medium including computer-readable instructions that, when executed on a computer, cause the method described in the first aspect of this application and any possible implementation thereof to be performed.

[0073] In a sixth aspect, a computer program product is provided, including computer-readable instructions that, when executed on a computer, cause the method described in the first aspect of this application or any possible implementation thereof to be performed. Attached Figure Description

[0074] Figure 1 This is a schematic diagram of the on-die ECC module in DDR5;

[0075] Figure 2a A schematic diagram of the architecture of a computing device provided in an embodiment of this application;

[0076] Figure 2b A schematic diagram of the structure of DDR5 memory and memory mode register provided in an embodiment of this application;

[0077] Figure 3a A schematic diagram of a method for detecting memory data faults provided in an embodiment of this application;

[0078] Figure 3b A schematic diagram illustrating a faulty detection data provided in an embodiment of this application;

[0079] Figure 4a A schematic diagram of data stored in DDR5 memory provided in an embodiment of this application;

[0080] Figure 4b A schematic diagram illustrating an application scenario provided in this application embodiment;

[0081] Figure 5 This is another schematic diagram illustrating an application scenario used in the embodiments of this application;

[0082] Figure 6 A schematic diagram of the processing apparatus provided in the embodiments of this application.

[0083] Figure 7 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0084] This application provides a method and related equipment for detecting memory data faults, applicable to the storage field. This method can accurately pinpoint the severity and precise location of memory faults without requiring additional hardware circuitry, thus reducing costs and making it suitable for a wider range of applications.

[0085] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0086] Before introducing the embodiments of this application, a brief explanation will be given on reducing the basic failure rate of DDR5 memory chips and enabling the system to detect memory chip failures in the current storage field, so as to facilitate the subsequent understanding of the embodiments of this application.

[0087] DDR5 memory utilizes on-die ECC error correction to reduce memory chip latency and ensure data accuracy under high speed and high density conditions. Please refer to [link / reference] for details. Figure 1 , Figure 1 This diagram illustrates the on-die ECC module in DDR5 memory chips. The on-die ECC module consists of an ECC parity generator, a synthesis generator, a synthesis decoder, and a correction module. When data is written to memory, the ECC parity generator calculates an 8-bit checksum (ECC1) for every 128 bits of data. The data and ECC1 are then written to the memory array. When data is read from memory, the synthesis generator generates a new checksum (ECC2) from the read data. The stored ECC1 is compared with ECC2. If no error is found, the data in memory is sent out. If an error occurs, the synthesis decoder identifies the erroneous bit and instructs the correction module to correct the error. The corrected data is then sent out, but it is not written back to the memory array.

[0088] Because the aforementioned DDR5 system lacks an additional bus for transmitting ECC data, it cannot detect ECC errors detected by on-die ECC, thus failing to detect memory failures. Currently, to enable system detection of memory failures, hardware circuitry is added to DDR5 dual in-line memory modules (DIMMs) using on-die ECC to detect ECC errors in the memory. When the number of ECC errors exceeds a threshold, an alarm signal is sent to the memory controller, using ECC error code counting for predictive alarms to allow the system to detect memory failures. However, predictive alarms using ECC error code counting only detect memory failures; they cannot accurately pinpoint the extent and precise location of the memory failure, and the added hardware circuitry increases costs.

[0089] To address the aforementioned problems, this application provides a method and related equipment for detecting memory data faults, applicable to devices in the storage field. The method includes: detecting whether data stored in a first memory space has a fault within a patrol cycle. This patrol cycle is the cycle for detecting DDR5 memory. The first memory space is DDR5 memory, and its data includes N data bits, where N is greater than or equal to 1. During the patrol process, when a faulty data is detected, fault information corresponding to the faulty data is obtained from a memory mode register. This fault information includes at least the memory address corresponding to the faulty data. The memory mode register is located within the DDR5 memory and is used to store the mapping relationship between the data to be patrolled and the memory address. The fault information is then sent to the OS or BMC. In this application's implementation, when at least one piece of data in the first memory space is determined to be faulty within the patrol cycle, fault information including at least the memory address of the faulty data is obtained and sent to the OS or BMC. This accurately locates the severity and precise location of data faults in memory without requiring additional hardware circuitry, reducing costs and making it suitable for more application scenarios.

[0090] To better understand the embodiments of this application, the method for detecting memory data faults provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings. Those skilled in the art will recognize that, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0091] First, to facilitate understanding of the subsequent embodiments, a computing device architecture for applying the method for detecting memory data faults provided in the embodiments of this application will be briefly described. Please refer to [link / reference] for details. Figure 2a , Figure 2a An architectural diagram of a computing device provided in an embodiment of this application specifically includes:

[0092] A central processing unit (CPU) 204, a BMC 203 or an OS 205, and at least one DDR5 memory 202 are included. The DDR memory 202 and the BMC 203 are connected to the CPU 204. The CPU 204 is used to detect whether data stored in a first memory space has failed during a patrol cycle. This patrol cycle is the cycle for detecting the DDR5 memory 202, and the first memory space belongs to the DDR5 memory 202. The data includes N data bits, where N is greater than or equal to 1.

[0093] Furthermore, during the inspection process, when a data fault is detected, CPU204 retrieves the fault information corresponding to the faulty data from the memory mode register. This fault information includes at least the memory address corresponding to the faulty data. The memory mode register manages the DDR5 memory 202 and stores the mapping relationship between data stored in the first memory space and memory addresses. For details, please refer to [link to relevant documentation]. Figure 2b , Figure 2b This is a schematic diagram of the structure of DDR5 memory and memory mode register provided in an embodiment of this application. The CPU 204 includes at least one memory mode register 2041, which is connected to the DDR5 memory. The memory mode register 2041 supports the CPU 204 in managing the DDR5 memory. Specifically, the CPU 204 performs read and write operations on the DDR5 memory, as well as other operations such as inspection, through the instructions supported by the memory mode register 2041. In one possible implementation, the memory mode register 2041 is located within the integrated memory controller (IMC) of the CPU 204.

[0094] After obtaining the fault information, CPU204 is also used to send the fault information to BMC203 or OS205.

[0095] In the embodiments of this application, the CPU is used to determine that the data stored in the first memory space has failed during the inspection cycle, and to obtain fault information and send it to the BMC or OS. The fault information includes a fault address indicating the location of the faulty data in the first memory space, so as to accurately locate the precise location of the fault and detect the data failure in the DDR5 memory storage without adding additional hardware circuits, reducing costs and making it suitable for more application scenarios.

[0096] In one possible implementation, the computing device further includes a basic input / output system (BIOS) 201. The BIOS 201 and BIOS 203 are connected to the CPU 204.

[0097] Before inspecting the first memory space of the DDR5 memory, in one implementation, the inspection cycle value and the first memory space are configured in the BIOS201 or BMC203, and the first memory space is less than or equal to the data storage space of the DDR5 memory. It is understood that the inspection cycle value and the first memory space can also be configured in the OS205 of the computing device or in the application layer. Specifically, the first memory space can be configured by setting any two addresses in the DDR memory as the start address and the end address, respectively. In one implementation, the size of the first memory space is equal to the data storage space of the DDR5 memory; the specific implementation is not limited here.

[0098] In one implementation, the CPU 204 can invoke the BMC 203 or BIOS 201 to detect whether the data stored in the first memory space is faulty during the inspection cycle. During the inspection, when a faulty data is detected, the CPU 204 retrieves the fault information corresponding to the faulty data from the memory mode register 2041. In other implementations, the CPU 204 can also invoke the OS 205 or an application layer to detect whether the data stored in the first memory space is faulty during the inspection cycle. During the inspection, when a faulty data is detected, the CPU 204 retrieves the fault information corresponding to the faulty data from the memory mode register 2041. It is understood that the specific implementation can be determined based on actual needs, and no particular limitation is made here.

[0099] In one implementation, the CPU 204 also sends fault information to the BMC 203 or OS 205. This allows it to detect a data fault in the DDR5 memory. The BMC 203 or OS 205 can then act as a fault diagnosis system, obtaining fault characteristics based on the fault information and instructing the CPU 204 to perform memory isolation and repair on the memory address of the faulty data.

[0100] It should be noted that, in another possible implementation, BIOS 201 is used to detect whether the data stored in the first memory space has failed during the inspection cycle. During the inspection, when a data failure is detected, BIOS 201 obtains the corresponding fault information from the memory mode register 2041. In another implementation, BIOS 201 also sends the obtained fault information to BMC 203 or OS 205, making the external system aware that the DDR5 memory data has failed. In one possible implementation, BMC 203 or OS 205 obtains fault characteristics based on the fault information and notifies CPU 204 to perform memory isolation repair based on the fault characteristics.

[0101] In one possible implementation, BMC203 is used to detect whether the data stored in the first memory space has failed during the inspection cycle. During the inspection, when a data failure is detected, BMC203 obtains the corresponding fault information from the memory mode register 2041. This allows external parties to perceive that the DDR5 memory data has failed. In another implementation, BMC203 also obtains fault characteristics based on the fault information and notifies CPU204 to perform memory isolation repair based on these characteristics.

[0102] Among the aforementioned implementation methods, different approaches are used to detect whether data in the first memory space has failed during the inspection cycle, and when a failure occurs, the fault information of the failed data is obtained. This expands the applicable application scenarios of the solution, demonstrating its diversity and selectivity.

[0103] Specifically, the following are examples Figure 2a The method for detecting memory data faults provided in this application, implemented using a computing device, is described in detail as an example. Please refer to [link / reference needed] for details. Figure 3a , Figure 3a A schematic diagram of a method for detecting memory faults provided in an embodiment of this application, specifically including:

[0104] 301. During the inspection cycle, check whether the first memory space has a fault.

[0105] Specifically, the CPU checks whether a fault has occurred in the first memory space during the inspection cycle. The inspection cycle is the configured cycle for inspecting the entire first memory space to check for faults.

[0106] For example, the CPU calls the BIOS, BMC, OS, or application to check whether the data stored in the first memory space has failed during the inspection cycle. Alternatively, the BIOS, BMC, OS, or application can check whether the data stored in the first memory space has failed during the inspection cycle. It is understood that the specific method can be determined based on actual needs, and no particular limitation is made here.

[0107] Specifically, based on the inspection cycle, the memory space of the DDR5 memory (which includes at least the first memory space) is cyclically inspected to achieve real-time detection of DDR5 memory faults and improve the reliability of DDR5 memory.

[0108] In one implementation, the inspection cycle and a first memory space, which is less than or equal to the data storage space of DDR5 memory, can be configured in the BIOS, BMC, OS, or application.

[0109] For example, the inspection cycle can be a period of 30 minutes, 1 hour, 6 hours, 20 hours or other time units, and there is no specific limitation here.

[0110] The first memory space can be based on Figure 2a The addresses of the data storage space in the DDR5 memory are configured. For example, any two addresses in the data storage space of the DDR5 memory can be defined as the start address and the end address of the first memory space, respectively. In one implementation, the first memory space can be the data storage space of the entire DDR5 memory. In other cases, it can be smaller than the data storage space in the DDR5 memory space. The specifics are not limited here.

[0111] In the embodiments of this application, the inspection cycle and the first memory space are configured in the application layer of the BIOS, BMC, OS, or computing device, demonstrating the diversity and selectivity of the solution. Furthermore, implementing this solution in software can minimize implementation costs.

[0112] To facilitate understanding of this solution, the following explanation will use the example of the BIOS detecting whether a fault has occurred in the first memory space during the inspection cycle.

[0113] In one possible implementation, during the inspection cycle, a piece of data and its corresponding first checksum are retrieved from the first memory space each time. Then, a corresponding second checksum is obtained based on the retrieved data. If the first checksum and the second checksum are different, it is determined that the data is faulty; or, if the first checksum and the second checksum are the same, it is determined that the data is fault-free.

[0114] For example, the BIOS can use an error check scrub (ECS) to traverse all data in the entire first memory space to detect whether the data stored in the first memory space has been faulty. Specifically, the ECS can be used to read data from within memory, correct single-bit errors, and then write the corrected data bits back to the memory array, ensuring the accuracy of the data stored in memory.

[0115] For an example, please refer to the specific implementation process of this ECS. Figure 3b Let's take BIOS as an example to understand. Figure 3b This is a schematic diagram illustrating a faulty detection data provided in an embodiment of this application. Specifically, it is as follows:

[0116] S1. Obtain a data item and its corresponding first verification code.

[0117] Specifically, each time the BIOS retrieves a piece of data from the first memory space and a first checksum, for example, the data is 128 bits (i.e., N=128) and the first checksum is 8 bits. It can be understood that in other application scenarios, the data can be 64 bits (i.e., N=64). In actual situations, the number of N bits included in the data can be determined according to the specific circumstances, which is not limited here.

[0118] S2. Obtain the second verification code based on the data.

[0119] Then, the BIOS calculates the second checksum based on the 128 bits of data obtained, which is a new 8-bit checksum. Specifically, the aforementioned first checksum is based on the data written to the DDR5 memory. Therefore, the BIOS re-obtains the second checksum based on the 128 bits of data obtained from the first memory space, using the same method as the first checksum. See the description above. Figure 1 The ECC description in the example is similar, and will not be repeated here.

[0120] S3. If the first verification code and the second verification code are different, it is determined that the data is faulty, or if they are the same, it is determined that the data is not faulty.

[0121] Specifically, the BIOS compares the new 8-bit parity bit (the second checksum) with the acquired 8-bit parity bit (the first checksum). When they match, there is no ECS error, meaning the 128 bits of the data are fault-free. However, when they do not match, there is an ECS error, indicating a data failure. When an ECS error occurs, the DDR5 memory's mode register (MR) records relevant information, such as the memory address of the faulty data, the current row address error count (the number of times an error occurs in the current row of the faulty data's memory address), and / or the current column address error count (the number of times an error occurs in the current column of the faulty data's memory address), etc. It's understood that other fault-related information may also be present, but details will not be elaborated here. Specifically, using DDR5 memory as an example, the MR register has 256 registers, MR0-MR255, each consisting of eight operands.

[0122] It should be noted that in one implementation, the BIOS can traverse the entire first memory space once or multiple times during the inspection cycle. In practice, this can be determined according to specific requirements, and no specific limit is made here.

[0123] It should be noted that the above example only illustrates the BIOS inspection of the first memory space. In other application scenarios, the specific implementation of BMC, OS or CPU inspection of the first memory space is similar to that of BIOS inspection of the first memory space, and will not be elaborated here.

[0124] During the inspection process, when a data fault is detected, the fault information corresponding to the faulty data is obtained from the memory mode register. This fault information includes at least the memory address corresponding to the faulty data. The memory mode register is located in DDR5 memory and is used to store the mapping relationship between data stored in the first memory space and memory addresses. Specifically, step 302 is as follows:

[0125] 302. When a data fault is detected, obtain the fault information corresponding to the faulty data.

[0126] In one possible implementation, when a fault is detected in the first data, the inspection is stopped, and at least the first memory address corresponding to the first data is obtained from the memory mode register. The first data is the data stored in the aforementioned first memory space.

[0127] For ease of understanding, the following explanation will still use the BIOS as an example to illustrate how to obtain fault information corresponding to fault data. Please refer to [link / reference needed] for details. Figure 4a , Figure 4a This is a schematic diagram illustrating data stored in DDR5 memory according to an embodiment of this application. The first data and / or the second data are stored in DDR5 memory; specific storage locations are not limited here.

[0128] When the BIOS determines that the first data in the first memory space has failed, i.e., an ECS error is detected, the BIOS will trigger a system management interrupt (SMI) to stop the inspection, and obtain the fault information corresponding to the first data from the memory mode register based on the first data that has been detected as faulty. Specifically, at least the first memory address of the first data is obtained. For example, the BIOS can obtain the first memory address corresponding to the first data that has been detected as faulty from the MR16 register to the MR19 register.

[0129] In the embodiments of this application, a specific implementation method is described for obtaining the corresponding fault information when there is a fault in the data during the inspection process, thereby improving the reliability of the solution.

[0130] In one possible implementation, after obtaining at least the first memory address corresponding to the first data from the memory mode register, the system continues to inspect the second data in the first memory space, which is the remaining data to be inspected in the first memory space.

[0131] For example, after obtaining the first memory address of the first data, the BIOS continues to inspect the second data, which may be the remaining data to be inspected in the first memory space. In one implementation, the second data may be the next bit of data in the first memory space after the first data, or it may be other data to be inspected at intervals; the specifics are not limited here.

[0132] During the inspection cycle, the BIOS uses the ECS to check all data in the first memory space for faults. When faulty data is found, the BIOS obtains the fault information and continues to check the remaining data. Even when the currently checked data is fault-free, the remaining data continues to be checked. This ensures that the entire first memory space is inspected, guaranteeing the reliability of the memory data.

[0133] In the embodiments of this application, after executing steps 301 and 302, the memory address of the faulty data in the first memory space can be obtained, thereby accurately locating the precise location of the memory fault without adding additional hardware circuitry, reducing costs and making it suitable for more application scenarios.

[0134] In one implementation, the fault information, in addition to the memory address corresponding to the faulty data, may also include at least one of the current row address error count or the current column address error count. For example, when an ECS error is detected, the BIOS can obtain the memory address corresponding to the faulty data from registers MR16 to MR19, and / or obtain the current row address error count and / or the current column address error count from register MR20. It is understood that the BIOS can also obtain fault information corresponding to other faulty data; specific details are not limited here.

[0135] In the embodiments of this application, the memory address of the faulty data in the first memory space, as well as the current row address error count and / or the current column address error count, are obtained. This allows for accurate location of the severity and precise location of the memory fault without the need for additional hardware circuitry, reducing costs and making it suitable for more application scenarios.

[0136] In one possible implementation, when a data fault is detected, the faulty data is corrected to obtain the target data, and then the target data is written to the memory address of the faulty data. For an example, please refer to [link to example]. Figure 3b Steps S4 and S5 in the example:

[0137] S4. Correct the faulty data to obtain the target data.

[0138] The BIOS uses ECS to correct single-bit errors in faulty data, thereby obtaining the target data. Specifically, the erroneous bits can be flipped to correct the error, resulting in correct, fault-free data.

[0139] S5. Write the target data to the memory address of the faulty data.

[0140] ECS also supports writing the corrected data bits back to the memory array, ensuring the accuracy of the data stored in memory. Therefore, the BIOS can use ECS to write the corrected target data to the memory address of the faulty data in the first memory space, thus guaranteeing the accuracy of the data stored in DDR5 memory.

[0141] In one possible implementation, the number of failures is obtained, which is the number of failures that occurred within the current inspection cycle. The inspection cycle value is then adjusted based on this failure count. Subsequent inspections continue within the newly set inspection cycle.

[0142] For example, the BIOS can adjust the inspection cycle value based on the number or frequency of faults. Specifically, the BIOS determines the corresponding inspection cycle value based on whether the number of faults detected in the current inspection cycle meets a set threshold. Different thresholds for the number of faults correspond to different inspection cycle values. For example, a threshold of 20 corresponds to an inspection cycle of 24 hours, a threshold of 50 corresponds to an inspection cycle of 6 hours, and so on. It is understood that this is only an example for understanding the embodiments of this application. In actual practice, the threshold for the number of faults and the corresponding inspection cycle value can be determined according to specific needs, and are not limited here.

[0143] In one implementation, the BIOS can generate an alarm if the number of failures within the current inspection cycle meets a threshold. This alarm alerts the user, who can then adjust the inspection cycle value based on the alarm. And / or the user can also take measures to repair the faulty data based on the alarm.

[0144] In the embodiments of this application, the value of the inspection cycle can be flexibly adjusted. When the number of failures is high, the inspection frequency can be increased, which can more accurately and in real time monitor the possibility of data failure, improve the reliability of the data in memory, and enhance the flexibility of the solution.

[0145] In one possible implementation, after at least two inspection cycles, a fault-free address range within the first memory space is obtained within those two inspection cycles. The memory space within the first memory space that does not include this fault-free address range is determined to be the second memory space, meaning the second memory space is smaller than the first memory space. Then, in the next inspection cycle, it is checked whether the data stored in the second memory space has experienced a fault.

[0146] For example, after the BIOS has traversed all data in the first memory space via the ECS for at least two inspection cycles, the BIOS determines the fault-free address range of the data that did not experience any faults during those two inspection cycles based on the results of the two ECS inspections. For instance, if the starting address of the first memory space is 0x00 and the ending address is 0xdf, and the fault-free address range in the first inspection cycle includes 0x00 to 0x3f and 0x80 to 0xdf, and the fault-free address range in the second inspection cycle includes 0x00 to 0x4f and 0x90 to 0xdf, then the second memory space is determined to be 0x3f to 0x90. Then, in subsequent inspection cycles, the BIOS checks whether the data stored in the second memory space has experienced any faults, similar to the aforementioned checks for faults in the data stored in the first memory space; details will not be elaborated here.

[0147] It should be noted that the aforementioned example of determining the second memory space is only used to illustrate the embodiments of this application and does not substantially limit the solution. It is understood that in actual situations, the second memory space can be determined according to specific circumstances, and no specific limitation is made here.

[0148] In the embodiments of this application, the second memory space is detected within the inspection cycle. That is, after a certain number of inspection cycles, the data of addresses that have not experienced faults are no longer inspected, which can improve inspection efficiency and reduce the occupation of device resources.

[0149] In one implementation, after inspecting the second memory space within a certain number of inspection cycles, the data in the first memory space is checked again for faults in the next inspection cycle. In another implementation, the "certain number of inspection cycles" can be at least two, and the specific number can be determined based on actual conditions. For example, considering the fault frequency of the aforementioned multiple inspection cycles, if there are many faults, all data in the first memory space can be checked after three or five inspection cycles; if there are few faults, all data in the first memory space can be checked after 10 or more inspection cycles. It is understood that the specific requirements can be determined, and no particular limitation is made here. Furthermore, re-checking all data in the first memory space can ensure the overall fault-free operation of the DDR5 memory as much as possible, improving the reliability of the memory data.

[0150] When the aforementioned inspection is performed by the BMC or OS and fault information is obtained, the severity and precise location of data faults in memory are accurately located, thereby detecting data faults in DDR5 memory without the need for additional hardware circuitry, reducing costs and making it suitable for more application scenarios.

[0151] When the CPU or BIOS obtains fault information during the inspection, it also needs to send the fault information to the BMC or OS, as described in step 303:

[0152] 303. Send fault information to BMC or OS.

[0153] For example, after obtaining fault information, the BIOS also sends fault information to the BMC or OS, so that the system can detect that the data stored in the DDR5 memory has failed and can determine the specific location of the faulty data.

[0154] In one possible implementation, the BMC or OS can also serve as a fault diagnosis system, performing memory repair and isolation on the memory address of the faulty second plastic after analyzing and processing the received fault information.

[0155] For example, please refer to Figure 4b The application scenarios shown are as follows: Figure 4b This is a schematic diagram illustrating an application scenario provided in this application embodiment. The BIOS sends the acquired fault information to the fault diagnosis system and can also transmit this fault information to the target device for fault diagnosis and prediction of fault feature information. The target device includes a fault big data training center, or the fault diagnosis system can send fault information to the target device; the specifics are not limited here. The fault big data training center in the target device uses a machine learning fault prediction and inference algorithm based on a large amount of operational data to complete fault feature research, define a fault feature model, and then output fault severity and / or fault feature models, etc., to the fault diagnosis system.

[0156] For example, the target device can be a database, a server, or other computer device capable of running large-scale data algorithms; the specific method is not limited here. The fault diagnosis system then instructs the CPU to perform hard isolation repair based on the fault characteristics. In one implementation, memory isolation repair can be hard isolation repair or soft isolation repair; the specific method is not limited here. For example, the CPU cuts off the power or signal to the memory address of the faulty data, or the fault diagnosis system instructs the CPU to perform soft isolation repair through the OS based on the fault characteristics, such as defining the memory address of the faulty data as inaccessible or marking the memory address as faulty. It is understood that other methods can achieve the same purpose; the specific method is not limited here.

[0157] In one possible implementation, after obtaining the fault information, the BIOS also sends the fault information to the target device, enabling the target device to determine the target address based on the fault information. The target device stores a large fault data of DDR5 memory data.

[0158] For example, the target device determines the target address based on fault information. Based on this target address, the target device can predict that other DDR5 memory modules associated with it at the same target address have a risk of data failure. Simultaneously, it can perform memory repair isolation on the target addresses of the remaining DDR5 memory modules. The predicted associated DDR5 memory modules belong to the same product category as the DDR5 memory modules that sent the fault information. In this embodiment, the target device predicts the same risk for other DDR5 memory modules of the same type based on the target address and takes measures, increasing the application scenarios and improving the overall efficiency of the application, reducing the workload of fault inspection for individual DDR5 memory data, and ensuring the reliability of memory data as much as possible.

[0159] In the embodiments of this application, the BMC or OS, as a fault diagnosis system, accurately determines the location of the faulty data based on the fault information and performs memory isolation repair, thereby avoiding risky memory areas as much as possible and ensuring the reliability of data storage.

[0160] It should be noted that the above example of BIOS is only used to illustrate the embodiments of this application. It is understood that the specific implementation of this solution by CPU, BMC or OS is similar to the example of BIOS, and will not be repeated here.

[0161] In this embodiment, during the inspection cycle, it is detected whether the data stored in the first memory space has a fault. During the inspection process, when a fault is detected, the fault information corresponding to the faulty data is obtained from the memory mode register and sent to the BMC or OS. The fault information includes the memory address corresponding to the faulty data, so as to accurately locate the precise location of the fault and perceive the fault in the DDR5 stored data. This does not require the addition of additional hardware circuits, reducing costs and making it suitable for more application scenarios.

[0162] The following example of a specific application scenario to illustrate the implementation of this solution will help to further understand the method provided in this application.

[0163] For ease of understanding, the BIOS will still be used as an example below. Please refer to [link / reference needed] for details. Figure 5 , Figure 5 This is another schematic diagram illustrating an application scenario implemented in an embodiment of this application. It includes:

[0164] First, execute step 501. Figure 2aThe BMC, BIOS, OS, or application in the computing device are configured with a 24-hour (h) inspection cycle. The BIOS then executes step 502 to check for ECS errors in the data stored in the first memory space within the inspection cycle. In step 503, the BIOS determines if an ECS error exists. If no ECS error exists, step 502 continues to inspect the first memory space until the entire first memory space has been traversed. If an ECS error exists, the BIOS executes step 504 to stop the inspection and obtains the values ​​from registers MR16 to MR20, acquiring fault information including the memory address corresponding to the faulty data, the current row address error count, and / or the current column address error count. Step 502 then continues to inspect the remaining data in the first memory space until the entire data stored in the first memory space has been traversed. The BIOS also executes step 505 to send the fault information obtained by the BIOS to the BMC, causing the BMC to execute step 506 to obtain fault characteristics based on the fault information through a fault big data training center, and then notify the CPU to perform memory isolation repair based on the fault characteristics.

[0165] In this application scenario, the BIOS inspects the entire first memory space through the ECS, thereby obtaining fault information and sending it to the BMC. This ensures the accuracy of data under high speed and high density in real time, and can accurately locate the precise location of faulty data without the need for additional hardware circuitry, reducing costs. Furthermore, it achieves memory isolation repair, avoiding risky memory areas as much as possible, and ensuring the reliability of data storage.

[0166] like Figure 6 As shown in the illustration, this application also provides a processing apparatus applied in a computing device. Please refer to the following for details. Figure 6 , Figure 6 This is a schematic diagram of a processing apparatus provided in an embodiment of this application. In one possible implementation, the processing apparatus 600 may include components that perform the methods described in the above embodiments. Figure 3a The module or unit corresponding to each implementation method / operation / step / action can be a hardware circuit, software, or a combination of hardware circuit and software. In one possible implementation, the processing device 600 may include: an acquisition unit 601, a processing unit 602, and a sending unit 603. The processing unit 602 can be used to perform the step of detecting whether the data stored in the first memory space has a fault during the inspection cycle, as in the above method embodiment. The acquisition unit 601 can be used to perform the step of acquiring the fault information corresponding to the faulty data from the memory mode register, as in the above method embodiment. The sending unit 603 can be used to perform the step of sending the fault information to the BMC or OS, as in the above method embodiment.

[0167] In other possible designs, the acquisition unit 601, processing unit 602, and sending unit 603 described above can execute the methods / operations / steps / actions in various possible implementations of the energy storage device in the above method embodiments one by one.

[0168] In one possible design, the processing unit 602 is further configured in the BIOS or BMC to configure the value of the inspection cycle and the first memory space before detecting whether a fault has occurred in the first memory space during the inspection cycle. The first memory space is less than or equal to the data storage space of the DDR5 memory.

[0169] In one possible design, the processing unit 602 is specifically used to stop the inspection when a fault is detected in the first data, and to obtain at least the first memory address corresponding to the first data from the memory mode register, wherein the first data is the data stored in the first memory space.

[0170] In one possible design, the processing unit 602, after stopping the inspection when a fault is detected in the first data and obtaining at least the first memory address corresponding to the first data from the memory mode register, is also used to continue inspecting the second data in the first memory space, which is the data to be inspected.

[0171] In one possible design, the acquisition unit 601 is further configured to acquire one piece of data and the corresponding first check code in the first memory space each time during the inspection cycle.

[0172] The processing unit 602 obtains the corresponding second check code based on the data, and then determines that the data is faulty based on the difference between the first check code and the second check code corresponding to the data, or determines that the data is fault-free based on the same first check code and the second check code corresponding to the data.

[0173] In one possible design, the processing unit 602, when a fault is detected in the data, is also used to correct the faulty data to obtain the target data.

[0174] The aforementioned sending unit 603 is also used to write target data to the memory address of the faulty data.

[0175] In one possible design, the acquisition unit 601 is also used to acquire the number of faults, which is the number of faults that occurred within the current inspection cycle.

[0176] The processing unit 602 is also used to adjust the value of the inspection cycle based on the number of faults.

[0177] In one possible design, the aforementioned acquisition unit 601, after at least two inspection cycles, is also used to acquire the fault-free address range in the first memory space within at least two inspection cycles.

[0178] The aforementioned processing unit 602 is also used to determine the memory space in the first memory space that does not include the fault-free address range as the second memory space, and to detect whether the data stored in the second memory space has been faulted in the next inspection cycle.

[0179] In one possible design, the aforementioned fault information also includes a current row address error count and / or a current column address error count, wherein the current row address error count indicates the number of times an error occurred in the row of the faulty data's memory address, and the current column address error count indicates the number of times an error occurred in the column of the faulty data's memory address.

[0180] In one possible design, the sending unit 603 is also used to send fault information to the target device, so that the target device can determine the target address based on the fault information. The target device stores a large fault data of DDR5 memory.

[0181] Please refer to the above description for the beneficial effects of the various designs and processing devices described in this application. Figure 3a The beneficial effects of the various implementation methods corresponding to each other in the Chinese method embodiments will not be elaborated here.

[0182] It should be noted that, Figure 6 The information interaction and execution process between the modules / units in the processing device of the corresponding embodiment are the same as those in this application. Figure 3a The corresponding method embodiments are based on the same concept, and the details can be found in the descriptions of the method embodiments shown above in this application, which will not be repeated here.

[0183] Furthermore, the functional modules or units in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module or unit. The integrated modules or units described above can be implemented in hardware or as software functional modules.

[0184] The following describes another computing device provided in the embodiments of this application. Please refer to [link to relevant documentation]. Figure 7 , Figure 7This is a schematic diagram of a computing device provided in an embodiment of this application. Specifically, the computing device 700 includes a CPU 701, a memory 702, and DDR5 memory 703, wherein the memory 702 can be temporary storage or persistent storage. The program stored in the memory 702 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the computing device 700. Furthermore, the CPU 701 may be configured to communicate with the memory 702 and execute a series of instruction operations in the memory 702 on the computing device 700.

[0185] In this embodiment, CPU701 is used to: detect whether data stored in a first memory space has a fault during a patrol cycle. This patrol cycle is the cycle for detecting DDR5 memory. The first memory space is DDR5 memory, and its data includes N data bits, where N is greater than or equal to 1. During the patrol process, when a faulty data is detected, fault information corresponding to the faulty data is obtained from the memory mode register. This fault information includes at least the memory address corresponding to the faulty data. The memory mode register is located within the DDR5 memory and is used to store the mapping relationship between the data to be patrolled and the memory address. Fault data is also sent to the BMC or OS. This achieves accurate positioning of the severity and precise location of data faults in memory, thereby detecting data faults in the DDR5 memory without adding additional hardware circuitry, reducing costs and making it suitable for more application scenarios.

[0186] The method for detecting memory data faults provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method for detecting memory data faults and its core ideas. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

[0187] This application also provides a computer-readable storage medium including computer-readable instructions that, when executed on a computer, cause the computer to perform any of the implementations shown in the foregoing method embodiments.

[0188] This application also provides a computer program product, which includes a computer program or instructions that, when run on a computer, cause the computer to perform any of the implementation methods shown in the foregoing method embodiments.

[0189] This application also provides a chip or chip system, which may include a processor. The chip may also include a memory (or storage module) and / or a transceiver (or communication module), or the chip may be coupled to a memory (or storage module) and / or a transceiver (or communication module), wherein the transceiver (or communication module) can be used to support the chip in wired and / or wireless communication, and the memory (or storage module) can be used to store a program or a set of instructions, which the processor can call to implement the operations performed by a terminal or network device in any of the above-described method embodiments or any possible implementations of the method embodiments. The chip system may include the above-described chip, or may include the above-described chip and other discrete devices, such as a memory (or storage module) and / or a transceiver (or communication module).

[0190] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the accompanying drawings of the device embodiments provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0191] This application also provides a computer-readable storage medium including computer-readable instructions that, when executed on a computer, cause the computer to perform any of the implementations shown in the foregoing method embodiments.

[0192] This application also provides a computer program product, which includes a computer program or instructions that, when run on a computer, cause the computer to perform any of the implementation methods shown in the foregoing method embodiments.

[0193] This application also provides a chip or chip system, which may include a processor. The chip may also include a memory (or storage module) and / or a transceiver (or communication module), or the chip may be coupled to a memory (or storage module) and / or a transceiver (or communication module), wherein the transceiver (or communication module) can be used to support the chip in wired and / or wireless communication, and the memory (or storage module) can be used to store a program or a set of instructions, which the processor can call to implement the operations performed by a terminal or network device in any of the above-described method embodiments or any possible implementations of the method embodiments. The chip system may include the above-described chip, or may include the above-described chip and other discrete devices, such as a memory (or storage module) and / or a transceiver (or communication module).

[0194] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, training device, or network device, etc.) to execute the methods of the various embodiments of this application.

Claims

1. A method for detecting memory data faults, characterized in that, include: During the inspection cycle, one piece of data and its corresponding first check code are retrieved from the first memory space each time. The inspection cycle is the cycle for inspecting DDR5 memory, and the first memory space belongs to DDR5 memory; the data includes N data bits, where N is greater than or equal to 1. Based on the data, the corresponding second verification code is obtained; If the first check code and the second check code corresponding to the data are different, it is determined that the data is faulty. Alternatively, if the first check code and the second check code corresponding to the data are the same, it is determined that the data is fault-free; During the inspection process, when a fault is detected in the data, the fault information corresponding to the faulty data is obtained from the memory mode register. The fault information includes at least the memory address corresponding to the faulty data. The memory mode register is used to manage the DDR5 memory and to store the mapping relationship between the data stored in the first memory space and the memory address. The fault information is sent to the operating system (OS) or the baseboard management controller (BMC).

2. The method according to claim 1, characterized in that, Before detecting whether a fault has occurred in the first memory space during the inspection cycle, the method further includes: Configure the value of the inspection cycle and the first memory space in the Basic Input / Output System BIOS or BMC; the first memory space is less than or equal to the data storage space of the DDR5 memory.

3. The method according to claim 1 or 2, characterized in that, During the inspection process, when a data fault is detected, the fault information corresponding to that data is obtained from the memory mode register, including: When a fault is detected in the first data, the inspection is stopped, and at least the first memory address corresponding to the first data is obtained from the memory mode register; the first data is the data stored in the first memory space.

4. The method according to claim 3, characterized in that, After stopping the inspection when a fault is detected in the first data and obtaining at least the first memory address corresponding to the first data from the memory mode register, the method further includes: Continue inspecting the second data within the first memory space, where the second data is the data to be inspected.

5. The method according to claim 1 or 2, characterized in that, The method further includes: The number of faults is the number of faults that occurred within the current inspection cycle. The inspection cycle value is adjusted based on the number of failures.

6. The method according to claim 1 or 2, characterized in that, After at least two of the aforementioned inspection cycles, the method further includes: Obtain the fault-free address range in the first memory space within at least two of the aforementioned inspection cycles; The memory space in the first memory space excluding the fault-free address range is determined as the second memory space; During the next inspection cycle, the system checks whether the data stored in the second memory space has malfunctioned.

7. The method according to claim 1 or 2, characterized in that, The fault information also includes a current row address error count; and / or a current column address error count, wherein the current row address error count indicates the number of times an error occurs in the row of the memory address of the faulty data, and the current column address error count indicates the number of times an error occurs in the column of the memory address of the faulty data.

8. The method according to claim 1 or 2, characterized in that, After obtaining the fault information in the memory mode register, the method further includes: The fault information is sent to the target device, enabling the target device to determine the target address based on the fault information; the target device stores a large fault data set containing the data.

9. A computing device, characterized in that, include: The processor and DDR5 memory, the processor being coupled to the memory for storing instructions, the processor executing the instructions to perform the method as described in any one of claims 1-8.

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