Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a first display area, a second display area, a third display area and a first fan-out area, the first fan-out area is located between the third display area and the second display area and between the first display area and the second display area; a plurality of first light emitting elements arranged in the first display area; and a plurality of first pixel circuits located in the third display area, each first pixel circuit comprising a first connection point, the first connection point being electrically connected to at least one first light emitting element through a first connection line, each first pixel circuit comprising a first preset transistor, the first preset transistor comprising a first channel, wherein in at least one first pixel circuit adjacent to the first fan-out area, the first connection point is located on a side of the first channel away from the first fan-out area. According to the display panel of the embodiment of the application, the wiring structure of the local area in the display panel is optimized, and the problem of insufficient wiring space of the first fan-out area is alleviated.

Description

[0001] This application is a divisional application of the application with the application date of June 3, 2021, the application number of 202110628931.6, and the title of "Display panel and display device". TECHNICAL FIELD

[0002] The present application relates to the field of display, in particular to a display panel and a display device. BACKGROUND

[0003] In electronic devices including display panels, the pursuit of high screen-to-body ratio with better visual experience has become one of the trends of current display technology development.

[0004] Taking mobile phones, tablet computers and the like as examples, in the current full-screen scheme, the display panel includes a first display area, a second display area and a third display area, the first display area is multiplexed as a photosensitive element integration area, the second display area is a normal display area, and the third display area is used to accommodate pixel circuits driving light emitting elements of the first display area. Photosensitive elements such as front-facing cameras and infrared sensing elements can be arranged at the back of the first display area of the display panel, and light can pass through the first display area to reach the photosensitive elements, thereby realizing corresponding functions such as front-facing photography and infrared sensing.

[0005] In the current display panel, there are many wires at the junction between the third display area and the second display area, making it difficult to design the wires. SUMMARY

[0006] The present application provides a display panel and a display device, which optimizes the wiring structure of the local area in the display panel.

[0007] In one aspect, the present application provides a display panel, comprising: a first display area, a second display area, a third display area and a first fan-out area, the third display area is located at least one side of the first display area along a first direction, the second display area at least partially surrounds the first display area and the third display area, the light transmittance of the first display area is greater than that of the second display area, the first fan-out area is located between the third display area and the second display area and between the first display area and the second display area along a second direction, the second direction intersects the first direction; a plurality of first light emitting elements arranged in the first display area; and a plurality of first pixel circuits located in the third display area, each first pixel circuit comprising a first connection point, the first connection point being electrically connected to at least one first light emitting element through a first connection line, each first pixel circuit comprising a first preset transistor, the first preset transistor comprising a first channel, wherein in at least one first pixel circuit adjacent to the first fan-out area, the first connection point is located on a side of the first channel facing away from the first fan-out area.

[0008] In another aspect, an embodiment of the present application provides a display device comprising the display panel according to any one of the preceding aspects.

[0009] According to the display panel of the embodiment of the present application, in at least one first pixel circuit adjacent to the first fan-out area, the first connection point is located at the side of the first channel away from the first fan-out area, so that the first connection line corresponding to the connection point extends at the side of the first pixel circuit away from the first fan-out area, reducing the space occupation of the first connection line to the first fan-out area, facilitating the arrangement of other signal lines in the first fan-out area, and alleviating the problem of insufficient wiring space in the first fan-out area. BRIEF DESCRIPTION OF DRAWINGS

[0010] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings, in which like references denote like features, and in which:

[0011] Figure 1 is a top view schematic diagram of a display panel according to an embodiment of the present application;

[0012] Figure 2 is Figure 1 is a partial enlarged schematic diagram of the Q1 region in FIG. 1;

[0013] Figure 3 is an equivalent circuit schematic diagram of a first pixel circuit in a display panel according to an embodiment of the present application;

[0014] Figure 4 is a circuit structure schematic diagram of a first pixel circuit in a display panel according to an embodiment of the present application;

[0015] Figure 5 is a structure schematic diagram of a semiconductor layer of a first pixel circuit in a display panel according to an embodiment of the present application;

[0016] Figure 6 is a structure schematic diagram of a first metal layer of a first pixel circuit in a display panel according to an embodiment of the present application;

[0017] Figure 7 is a structure schematic diagram of a capacitor metal layer of a first pixel circuit in a display panel according to an embodiment of the present application;

[0018] Figure 8 is a structure schematic diagram of a second metal layer and a first connection point of a first pixel circuit in a display panel according to an embodiment of the present application;

[0019] Figure 9 is a layer structure schematic diagram of a display panel according to an embodiment of the present application;

[0020] Figure 10 is a schematic diagram of a layer structure of a display panel according to an alternative embodiment of the present application;

[0021] Figure 11 is a schematic diagram of a layer structure of a display panel according to another alternative embodiment of the present application;

[0022] Figure 12 is a schematic diagram of a top view of a display panel according to another embodiment of the present application;

[0023] Figure 13 is Figure 12 is a schematic diagram of a partial enlargement of a Q2 region;

[0024] Figure 14 is Figure 12 is a schematic diagram of another partial enlargement of a Q2 region;

[0025] Figure 15 is a schematic diagram of an equivalent circuit of a second pixel circuit in a display panel according to another embodiment of the present application;

[0026] Figure 16 is a schematic diagram of a circuit structure of a second pixel circuit in a display panel according to another embodiment of the present application;

[0027] Figure 17 is a schematic diagram of a structure of a semiconductor layer of a second pixel circuit in a display panel according to an embodiment of the present application;

[0028] Figure 18 is a schematic diagram of an equivalent circuit of a third pixel circuit in a display panel according to another embodiment of the present application;

[0029] Figure 19 is a schematic diagram of a circuit structure of a third pixel circuit in a display panel according to another embodiment of the present application;

[0030] Figure 20 is a schematic diagram of a structure of a semiconductor layer of a third pixel circuit in a display panel according to an embodiment of the present application;

[0031] Figure 21 is a schematic diagram of a top view of a display panel according to yet another embodiment of the present application;

[0032] Figure 22 is Figure 21 is a schematic diagram of a partial enlargement of a Q3 region;

[0033] Figure 23 is Figure 21 is a schematic diagram of another partial enlargement of a Q3 region;

[0034] Figure 24 is Figure 21 is a partial enlarged schematic view of the Q3 region in the display panel;

[0035] Figure 25 is a circuit structure schematic view of a first pixel circuit in a display panel according to another embodiment of the present application;

[0036] Figure 26 is a top view schematic view of a display panel according to another embodiment of the present application;

[0037] Figure 27 is Figure 26 is a partial enlarged schematic view of the Q4 region in the display panel;

[0038] Figure 28 is Figure 27 is a partial enlarged schematic view of the Q5 region in the display panel;

[0039] Figure 29 is a structure schematic view of a semiconductor layer of a first pixel circuit and a second pixel circuit in a display panel according to another embodiment of the present application;

[0040] Figure 30 is a structure schematic view of a first metal layer of a first pixel circuit and a second pixel circuit in a display panel according to another embodiment of the present application;

[0041] Figure 31 is a structure schematic view of a capacitor metal layer of a first pixel circuit and a second pixel circuit in a display panel according to another embodiment of the present application;

[0042] Figure 32 is a structure schematic view of a second metal layer of a first pixel circuit and a second pixel circuit in a display panel according to another embodiment of the present application. DETAILED DESCRIPTION

[0043] The features and exemplary embodiments of the various aspects of the present application will be described in detail below with reference to the drawings. To make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are configured only to explain the present application and are not configured to limit the present application. The present application can be implemented without some of the specific details by those skilled in the art. The following description of the embodiments is merely to provide a better understanding of the present application by showing examples of the present application.

[0044] It should be noted that, in the present document, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0045] It should be understood that when describing the structure of a component, when a layer, a region is referred to as being "on" or "above" another layer, another region, it can mean directly on or above the other layer, the other region, or other layers or regions are also included between it and the other layer, the other region. And if the component is turned over, the layer, the region will be "under" or "below" the other layer, the other region.

[0046] An embodiment of the present application provides a display panel, Figure 1 is a top view schematic diagram of a display panel according to an embodiment of the present application, Figure 2 is Figure 1 is a partial enlarged schematic diagram of a Q1 region in

[0047] The display panel 100 includes a first display area DA1, a second display area DA2, a third display area DA3, and a first fan-out area FA1. The third display area DA3 is located at least one side of the first display area DA1 along a first direction X, the second display area DA2 at least partially surrounds the first display area DA1 and the third display area DA3, the light transmittance of the first display area DA1 is greater than that of the second display area DA2, the first fan-out area FA1 is located between the third display area DA3 and the second display area DA2 and between the first display area DA1 and the second display area DA2 along a second direction Y, and the second direction Y intersects the first direction X. In some embodiments, the display panel 100 further includes a non-display area NA, and the non-display area NA at least partially surrounds the first display area DA1, the second display area DA2, and the third display area DA3.

[0048] The display panel 100 further includes a plurality of first light emitting elements 111 and a plurality of first pixel circuits 121. The plurality of first light emitting elements 111 are arranged in the first display area DA1. The plurality of first pixel circuits 121 are located in the third display area DA3. Each first pixel circuit 121 includes a first connection point P1, the first connection point P1 is electrically connected to at least one first light emitting element 111 through a first connection line CL1, each first pixel circuit 121 includes a first preset transistor, and the first preset transistor includes a first channel C1. In the embodiment, in at least one first pixel circuit 121 adjacent to the first fan-out area FA1, the first connection point P1 is located on a side of the first channel C1 away from the first fan-out area FA1.

[0049] According to the display panel 100 of the embodiment of the present application, in at least one first pixel circuit 121 adjacent to the first fan-out area FA1, the first connection point P1 is located on the side of the first channel C1 away from the first fan-out area FA1, so that the first connection line CL1 corresponding to the connection point extends on the side of the first pixel circuit 121 away from the first fan-out area FA1, reducing the space occupation of the first connection line CL1 on the first fan-out area FA1, facilitating the arrangement of other signal lines in the first fan-out area FA1, and relieving the problem of insufficient wiring space in the first fan-out area FA1.

[0050] Optionally, the first connection line CL1 can be a light-transmitting conductive connection line such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). Of course, in order to balance the light transmittance of the first display area DA1 and the resistance of the first connection line CL1, the part of the first connection line CL1 located in the first display area DA1 can be made of a light-transmitting conductive material, and the part located in the third display area DA3 can be made of a metal material with lower resistivity, which will not be described herein again. In addition, in order to improve the diffraction phenomenon of the first display area DA1, the part of the first connection line CL1 located in the first display area DA1 can be designed as a curved trace, and the first light emitting element 111 located in the first display area DA1 can be designed as a circular or circular-like shape. Herein, the first connection point P1 is a connection point capable of directly connecting with the first connection line CL1, and the driving circuit is transmitted to the first light emitting element 111 through the first connection point P1 and the first connection line CL1.

[0051] The embodiment of the present application takes the display panel 100 as an example of an Organic Light Emitting Diode (OLED) display panel, i.e., the first light emitting element 111 is an OLED light emitting element. It can be understood that the display panel 100 of the embodiment of the present application can also be a self-luminous display panel capable of being driven in an Active Matrix (AM) mode, which is similar to the OLED display panel.

[0052] In the embodiment, the term "pixel circuit" refers to the smallest repeating unit of the circuit structure for driving the corresponding light emitting element to emit light. The pixel circuit can be a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, etc. Herein, the "2T1C circuit" refers to a pixel circuit including 2 thin film transistors (T) and 1 capacitor (C), and other "7T1C circuit", "7T2C circuit", etc. are similar. The pixel circuit includes a driving transistor, and in the embodiment, the first preset transistor is the driving transistor of the first pixel circuit 121.

[0053] Optionally, the display panel 100 further comprises a plurality of second light emitting elements 112 and a plurality of second pixel circuits 122. The second pixel circuits 122 are located in the second display area DA2, and each second pixel circuit 122 is electrically connected with at least one second light emitting element 112.

[0054] The display panel 100 can further comprise a plurality of first signal lines 140, the first signal lines 140 connecting the plurality of first pixel circuits 121 and the plurality of second pixel circuits 122. At least one first signal line 140 comprises a first sub-signal line 141, a second sub-signal line 142, and a third sub-signal line 143. The first sub-signal line 141 extends in the third display area DA3 along the second direction Y and is electrically connected with the plurality of first pixel circuits 121. The second sub-signal line 142 extends in the second display area DA2 along the second direction Y and is electrically connected with the plurality of second pixel circuits 122. The third sub-signal line 143 extends in the first fan-out area FA1 and is electrically connected with the first sub-signal line 141 and the second sub-signal line 142.

[0055] In the embodiment, in at least one first pixel circuit 121 adjacent to the first fan-out area FA1, the first connection point P1 is located on the side of the first channel C1 facing away from the first fan-out area FA1, reducing the space occupation of the first connection line CL1 to the first fan-out area FA1, and facilitating the arrangement of the third sub-signal line 143 of the first signal line 140 in the first fan-out area FA1.

[0056] The first signal line 140 comprises at least one of a data line, a reference voltage signal line, or a power supply line. The third sub-signal line 143 of the first signal line 140 extends in the first fan-out area FA1 and is electrically connected with the first sub-signal line 141 and the second sub-signal line 142, so that a column of first pixel circuits 121 in the third display area DA3 and a column of second pixel circuits 122 in the second display area DA2 share one first signal line 140, for example, the first signal line 140 is a data line, used for transmitting a data signal for controlling the gray scale of the light emitting element, thereby realizing the supply of the data signal of the first pixel circuit 121. The first fan-out area FA1 has more wiring space, facilitating the arrangement of the third sub-signal line 143 in the first fan-out area FA1.

[0057] In some embodiments, the plurality of first pixel circuits 121 are arranged as a plurality of rows along the second direction Y, and in each row of first pixel circuits R1, the plurality of first pixel circuits 121 are arranged along the first direction X. Optionally, in at least one row of first pixel circuits R1 adjacent to the first fan-out area FA1, the first connection point P1 of each first pixel circuit 121 is located on a side of the first channel C1 facing away from the first fan-out area FA1. For example, one or two rows of first pixel circuits R1 adjacent to the first fan-out area FA1 can be configured as described above for the first connection point P1. For another example, all rows of first pixel circuits R1 can be configured as described above for the first connection point P1, i.e., in the present embodiment, the first connection point P1 of each first pixel circuit 121 is located on a side of the first channel C1 facing away from the first fan-out area FA1. When at least one row of first pixel circuits R1 adjacent to the first fan-out area FA1 is configured as described above, the first connection line CL1 corresponding to the at least one row of first pixel circuits R1 is located on a side of the at least one row of first pixel circuits R1 facing away from the first fan-out area FA1, thereby reducing the space occupation of the first connection line CL1 on the first fan-out area FA1 to a greater extent and relieving the problem of insufficient wiring space of the first fan-out area FA1 to a greater extent.

[0058] It should be noted that in the above embodiments, in each row of first pixel circuits R1, the plurality of first pixel circuits 121 are arranged along the first direction X. In an actual display panel, other circuit structures can be included in the same row as at least one row of first pixel circuits R1, for example, the display panel 100 further includes third pixel circuits in the same row as at least one row of first pixel circuits R1, and the third pixel circuits are configured to drive the third light emitting elements in the third display area DA3 to emit light. For another example, the display panel 100 further includes virtual pixel circuits in the same row as at least one row of first pixel circuits R1, and the virtual pixel circuits can be pixel circuits having the same or similar circuit structure as the first pixel circuit 121 but being unable to drive the light emitting elements to emit light, e.g., the pixel circuits are missing some film layers or structures, or the pixel circuits are not electrically connected to the light emitting elements. In some optional manners, virtual light emitting elements can also be included in the same row as at least one row of first pixel circuits R1, e.g., the virtual light emitting elements are provided with an anode, a pixel definition layer opening, a light emitting material, and a cathode but are not provided with a corresponding pixel circuit, or the virtual light emitting elements are missing one or more of the anode, the pixel definition layer opening, the light emitting material, and the cathode. When the display panel 100 includes the third pixel circuits and / or the virtual pixel circuits and / or the virtual light emitting elements in the same row as at least one row of first pixel circuits R1, the third pixel circuits and / or the virtual pixel circuits can be arranged between the first pixel circuits 121 or can be arranged on one side of the plurality of first pixel circuits 121.

[0059] Optionally, the first pixel circuit 121 includes a first node N1 configured to transmit a driving current to the first light emitting element 111, and the first node N1 is located on one side of the first channel C1.

[0060] Figure 3 is a schematic diagram of an equivalent circuit of a first pixel circuit in a display panel according to an embodiment of the present application, Figure 4 is a schematic diagram of a circuit structure of a first pixel circuit in a display panel according to an embodiment of the present application.

[0061] In the embodiment, the first pixel circuit 121 is taken as an example of a 7T1C circuit, i.e., the first pixel circuit 121 includes seven transistors M1 to M7 and a storage capacitor Cst. A reference voltage line signal line YL is used to provide a reference voltage signal Vref for resetting a preset node Nc of the first pixel circuit 121. For the first pixel circuit 121 in the current row, a first scan line SL1_1 is used to provide a first scan signal S1, a second scan line SL2 is used to provide a second scan signal S2, and a first scan line SL1_2 of the next row can be connected to the second scan line SL2 of the current row, thereby providing the second scan signal S2 for the current row and providing the first scan signal S1 for the first pixel circuit 121 in the next row. An emission control line EML is used to provide an emission control signal Emit. In some embodiments, the display panel 100 can further include a data line DL used to provide a data signal Data, and a power supply line VL used to provide a power supply signal PVDD. In the embodiment, the transistor M4 is a double-gate transistor, and thus includes two sub-transistors. The part of the semiconductor layer between the two sub-transistors can be doped with impurities to have conductivity. In the embodiment, the first pixel circuit 121 further includes a shielding line (or shielding structure) PL, which can be in the same layer as the reference voltage line signal line YL and electrically connected to the power supply line VL, thereby having a constant voltage. The shielding line PL has a positive projection on the semiconductor layer, and shields at least part of the semiconductor layer between the two sub-transistors of the transistor M4. Since the shielding line PL has a constant voltage, it can reduce signal interference of the transistor M4 caused by other signal lines.

[0062] The first pixel circuit 121 can be configured to include at least one semiconductor layer and multiple conductive layers, e.g., metal layers. In the embodiment, the first pixel circuit 121 includes at least a semiconductor layer, a first metal layer, a capacitor metal layer, and a second metal layer. In some embodiments, the first pixel circuit 121 can further include other conductive layers, e.g., a third metal layer.

[0063] Figure 5 is a schematic diagram of a structure of a semiconductor layer of a first pixel circuit in a display panel according to an embodiment of the present application, Figure 6 is a schematic diagram of a structure of a first metal layer of a first pixel circuit in a display panel according to an embodiment of the present application, Figure 7 is a schematic diagram of a structure of a capacitor metal layer of a first pixel circuit in a display panel according to an embodiment of the present application,Figure 8 is a structural diagram of a second metal layer and a first connection point of a first pixel circuit in a display panel according to an embodiment of the present application, Figure 8 in which, in addition to the second metal layer, a structure layer related to the first connection point is also shown.

[0064] As Figures 3 to 8 , among the plurality of transistors M1 to M7 of the first pixel circuit 121, there are the driving transistor M3, the first light-emitting control transistor M1, and the second light-emitting control transistor M6. The driving transistor M3 can transmit a driving current to the first light-emitting element 111. The gate of the driving transistor M3 is connected to the aforementioned preset node Nc, which is connected to one plate of the storage capacitor Cst. The gates of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are connected to the light-emitting control line EML. The first light-emitting control transistor M1 is connected between the power supply line VL and the driving transistor M3, and the second light-emitting control transistor M6 is connected between the driving transistor M3 and the anode of the first light-emitting element 111. The first node N1 is located between the second light-emitting control transistor M6 and the anode of the first light-emitting element 111.

[0065] Optionally, in the storage capacitor Cst, the plate electrically connected to the power supply line VL is electrically connected to the plate of the same layer of the adjacent first pixel circuit 121, so as to reduce the voltage drop of the power supply line VL.

[0066] As Figure 4 and Figure 5 , in this embodiment, the first preset transistor is the driving transistor M3 of the first pixel circuit 121, and the first channel C1 is the channel of the driving transistor M3 of the first pixel circuit 121. As Figure 4 , in this embodiment, the first node N1 is specifically the position of the first via when the second light-emitting control transistor M6 is connected to the anode of the first light-emitting element 111. As Figure 4 , Figure 5 and Figure 8 , in this embodiment, the first node N1 is the position of the via connecting the second metal layer and the semiconductor layer when the second light-emitting control transistor M6 is connected to the anode of the first light-emitting element 111. The via at the position of the first node N1 can be electrically connected to the anode of the first light-emitting element 111 through other conductive structures, for example, can be electrically connected to the anode of the first light-emitting element 111 through the conductive structure located in the third metal layer.

[0067] As Figure 2 , Figure 4In the embodiment, in the at least one first pixel circuit 121, the first node N1 is located at a side of the first channel C1 facing the first fan-out area FA1, and the first connection point P1 is electrically connected to the first node N1 through the second connection line CL2. According to the display panel 100 of the embodiment, when the first node N1 is located at the side of the first channel C1 facing the first fan-out area FA1, the first node N1 is electrically connected to the first connection point P1 on the side away from the first fan-out area FA1 through the second connection line CL2, and the first connection line CL1 occupies the position is transferred without changing the original structure of the first pixel circuit 121 and the order of the signal lines, and the first connection line CL1 originally arranged on the side facing the first fan-out area FA1 is arranged on the side away from the first fan-out area FA1. Therefore, the display panel 100 realizes the space accommodation of the first connection line CL1 in the first fan-out area FA1 with a small change in the circuit structure, and facilitates the arrangement of the first signal line 140 in the first fan-out area FA1.

[0068] Figure 9 is a schematic diagram of a layer structure of a display panel according to an embodiment of the present application. As shown in Figures 4 to 9 In the embodiment, the first pixel circuit 121 includes a semiconductor layer B1, a first metal layer J1, a capacitor metal layer JC, a second metal layer J2, and a third metal layer J3. The first node N1 is the position of the first via when the anode of the first light emitting element 111 is connected from the second light emitting control transistor M6. In the embodiment, the first node N1 is the position of the via connecting the second metal layer J2 and the semiconductor layer B1 when the anode of the first light emitting element 111 is connected from the second light emitting control transistor M6. In the embodiment, at least part of the second connection line CL2 is located in the third metal layer J3, and at least part of the first connection line CL1 is in the same layer as the anode of the first light emitting element 111. At this time, the first connection point P1 is the position of the via connecting the first connection line CL1 and the second connection line CL2, i.e., the position of the via connecting the layer where the anode is located and the third metal layer J3.

[0069] Figure 10 is a schematic diagram of a layer structure of a display panel according to an alternative embodiment of the present application, Figure 11 is a schematic diagram of a layer structure of a display panel according to another alternative embodiment of the present application.

[0070] As shown in Figure 10 The first pixel circuit 121 includes a semiconductor layer B1, a first metal layer J1, a capacitor metal layer JC, and a second metal layer J2. The first node N1 is the position of the first via when the anode of the first light emitting element 111 is connected from the second light emitting control transistor M6. In Figure 10In the relevant embodiments, the first node N1 is the location of the via connecting the second metal layer J2 and the semiconductor layer B1 when the second light-emitting control transistor M6 is connected to the anode of the first light-emitting element 111. Figure 10 In the relevant embodiments, at least a portion of the second connecting line CL2 is located in the second metal layer J2, and at least a portion of the first connecting line CL1 is in the same layer as the anode of the first light-emitting element 111. At this time, the first connection point P1 is the location of the via connecting the first connecting line CL1 and the second connecting line CL2, that is, the location of the via connecting the anode layer and the second metal layer J2.

[0071] like Figure 11 The first pixel circuit 121 includes a semiconductor layer B1, a first metal layer J1, a capacitor metal layer JC, a second metal layer, and a third metal layer J3. The first node N1 is the location of the first via when connecting from the second light-emitting control transistor M6 to the anode of the first light-emitting element 111. Figure 11 In the relevant embodiments, the first node N1 is the location of the via connecting the third metal layer J3 and the semiconductor layer B1 when the second light-emitting control transistor M6 is connected to the anode of the first light-emitting element 111. Figure 11 In the relevant embodiments, at least a portion of the second connecting line CL2 is located in the third metal layer J3, and at least a portion of the first connecting line CL1 is in the same layer as the anode of the first light-emitting element 111. At this time, the first connection point P1 is the location of the via connecting the first connecting line CL1 and the second connecting line CL2, that is, the location of the via connecting the anode layer and the third metal layer J3.

[0072] Figure 12 This is a top view schematic diagram of a display panel provided according to another embodiment of the present invention. Figure 13 and Figure 14 yes Figure 12 A partially enlarged schematic diagram of region Q2. In this embodiment, the display panel 100 further includes a plurality of second light-emitting elements 112, a plurality of third light-emitting elements 113, a plurality of second pixel circuits 122, a plurality of third pixel circuits 123, and a plurality of first signal lines 140. The plurality of second light-emitting elements 112 are arranged in the second display area DA2. The plurality of third light-emitting elements 113 are arranged in the third display area DA3. The second pixel circuits 122 are located in the second display area DA2. Each second pixel circuit 122 is electrically connected to at least one second light-emitting element 112. The third pixel circuits 123 are located in the third display area DA3. Each third pixel circuit 123 is electrically connected to at least one third light-emitting element 113.

[0073] At least one first signal line 140 includes a first sub-signal line 141, a second sub-signal line 142, and a third sub-signal line 143. The first sub-signal line 141 extends along the second direction Y in the third display area DA3 and is electrically connected to a plurality of first pixel circuits 121. The second sub-signal line 142 extends along the second direction Y in the second display area DA2 and is electrically connected to a plurality of second pixel circuits 122. The third sub-signal line 143 extends in the first fan-out area FA1 and is electrically connected to the first sub-signal line 141 and the second sub-signal line 142.

[0074] like Figure 14 In some embodiments, each second pixel circuit 122 includes a second preset transistor, the second preset transistor including a second channel C2, and the second pixel circuit 122 including a second node N2 for transmitting drive current to the second light-emitting element 112, the second node N2 being located on one side of the second channel C2.

[0075] In this embodiment, the equivalent circuit and circuit structure of the first pixel circuit 121 are the same as those of the second pixel circuit 121. Figure 3 and Figure 4 The embodiments shown are basically the same, and the first pixel circuit 121 will not be described in detail here.

[0076] Figure 15 This is an equivalent circuit diagram of the second pixel circuit in a display panel according to another embodiment of the present invention. Figure 16 This is a schematic diagram of the circuit structure of a second pixel circuit in a display panel according to another embodiment of the present invention. The second pixel circuit 122 includes at least a semiconductor layer, a first metal layer, a capacitor metal layer, and a second metal layer. Figure 17 This is a schematic diagram of the semiconductor layer of the second pixel circuit in a display panel according to an embodiment of the present invention.

[0077] In this embodiment, the second pixel circuit 122 is a 7T1C circuit, which includes seven transistors M1 to M7 and a storage capacitor Cst. The equivalent circuit and circuit structure of the second pixel circuit 122 are similar to those of the first pixel circuit 121. The differences will be described below, while the similarities will not be detailed.

[0078] Please refer to Figures 15 to 17 In this embodiment, the second preset transistor is the driving transistor M3 of the second pixel circuit 122, and the second channel C2 is the channel of the driving transistor M3 of the second pixel circuit 122. Figure 16 and Figure 17In the embodiment, the second node N2 is specifically a position of a first via when the second light-emitting control transistor M6 is connected to the anode of the second light-emitting element 112. In the embodiment, the second node N2 is a position of a via connecting the second metal layer and the semiconductor layer when the second light-emitting control transistor M6 is connected to the anode RE2 of the second light-emitting element 112. The via at the position of the second node N2 can be electrically connected to the anode RE2 of the second light-emitting element 112 through other conductive structures, for example, can be electrically connected to the anode RE2 of the second light-emitting element 112 through the conductive structure CS2 in the third metal layer.

[0079] In the embodiment, the orientation of the first node N1 relative to the first channel C1 in the first pixel circuit 121 is the same as the orientation of the second node N2 relative to the second channel C2 in the second pixel circuit 122. Therefore, the arrangement order of the plurality of signal lines used for transmitting signals to the first pixel circuit 121 and the second pixel circuit 122 is basically unchanged, and the wiring structure of the display panel 100 does not need to be greatly changed.

[0080] As shown in FIG. 1, the display panel 100 includes a plurality of first pixel circuits 121, a plurality of second pixel circuits 122, and a plurality of third pixel circuits 123. Figure 14 In some embodiments, at least one third pixel circuit 123 includes a third connection point P3, and the third light-emitting element 113 is electrically connected to the third pixel circuit 123 through the third connection point P3. Each third pixel circuit 123 includes a third preset transistor including a third channel C3. In at least one third pixel circuit 123 adjacent to the first fan-out area FA1, the third connection point P3 is located on a side of the third channel C3 facing away from the first fan-out area FA1. When the third pixel circuit 123 and the third light-emitting element 113 need to be connected through a connection line, the third connection point P3 is located on a side of the third channel C3 facing away from the first fan-out area FA1, which can reduce the space occupation of the connection line connected to the third pixel circuit 123 to the first fan-out area FA1, and further improve the flexibility of other wirings in the first fan-out area FA1.

[0081] In some embodiments, the plurality of first pixel circuits 121 and the plurality of third pixel circuits 123 are arranged as a plurality of rows along the second direction Y, and in each row of the first pixel circuits and the third pixel circuits R2, the plurality of first pixel circuits 121 and the plurality of third pixel circuits 123 are arranged along the first direction X. In the embodiment, in at least one row of the first pixel circuits and the third pixel circuits R2 adjacent to the first fan-out area FA1, the first connection point P1 of each first pixel circuit 121 is located on a side of the first channel C1 facing away from the first fan-out area FA1, and the third connection point P3 of each third pixel circuit 123 is located on a side of the third channel C3 facing away from the first fan-out area FA1, thereby more greatly reducing the space occupation of the first connection line CL1 and the connection line connected to the third pixel circuit 123 to the first fan-out area FA1, and more relieving the problem of insufficient wiring space in the first fan-out area FA1.

[0082] In the actual display panel, the display panel can include other circuit structures in the same row as the at least one row of first pixel circuits and third pixel circuits R2. For example, the display panel 100 further includes a virtual pixel circuit in the same row as the at least one row of first pixel circuits and third pixel circuits R2. The virtual pixel circuit can be a pixel circuit having the same or similar circuit structure as the first pixel circuit 121 and not electrically connected to the light emitting element. The virtual pixel circuit can be arranged between the first pixel circuit 121 and / or the third pixel circuit 123, or can be located on one side of all the first pixel circuits 121 and / or the third pixel circuits 123.

[0083] In some embodiments, the third pixel circuit 123 includes a third node N3 for transmitting a driving current to the third light emitting element 113. The third node N3 is located on one side of the third channel C3, and the third connection point P3 is electrically connected to the third node N3 through a third connection line.

[0084] Figure 18 is an equivalent circuit schematic diagram of a third pixel circuit in a display panel according to another embodiment of the present application, Figure 19 is a circuit structure schematic diagram of a third pixel circuit in a display panel according to another embodiment of the present application. The third pixel circuit 123 includes at least a semiconductor layer, a first metal layer, a capacitor metal layer, and a second metal layer. Figure 20 is a structure schematic diagram of a semiconductor layer of a third pixel circuit in a display panel according to an embodiment of the present application.

[0085] In this embodiment, the third pixel circuit 123 is a 7T1C circuit including seven transistors M1 to M7 and a storage capacitor Cst. The equivalent circuit and the circuit structure of the third pixel circuit 123 are similar to those of the first pixel circuit 121. Differences will be described below, and the same parts will not be described in detail.

[0086] Please refer to Figures 18 to 20 In this embodiment, the third preset transistor is the driving transistor M3 of the third pixel circuit 123, and the third channel C3 is the channel of the driving transistor M3 of the third pixel circuit 123. As shown in Figure 19 and Figure 20In this embodiment, the third node N3 is specifically the location of the first via when connecting the second light-emitting control transistor M6 to the anode of the third light-emitting element 113. In this embodiment, the third node N3 is the location of the via connecting the second metal layer and the semiconductor layer when connecting the second light-emitting control transistor M6 to the anode RE3 of the third light-emitting element 113. The via at the location of the third node N3 can be electrically connected to the anode RE3 of the third light-emitting element 113 through other conductive structures; for example, it can be electrically connected to the anode RE3 of the third light-emitting element 113 through a conductive structure CS3 located in the third metal layer.

[0087] Figure 21 This is a top view schematic diagram of a display panel provided according to another embodiment of the present invention. Figure 22 , Figure 23 as well as Figure 24 yes Figure 21 A partially enlarged schematic diagram of region Q3. In this embodiment, the first pixel circuit 121 includes a first node N1 for transmitting driving current to the first light-emitting element 111. The first node N1 is located on one side of the first channel C1. In at least one of the first pixel circuits 121, the first connection point P1 coincides with the first node N1. At this time, the first node N1 is located on the side of the first channel C1 away from the first fan-out area FA1, reducing the space occupied by the first connection line CL1 on the first fan-out area FA1, and facilitating the arrangement of the third sub-signal line 143 of the first signal line 140 in the first fan-out area FA1. In this embodiment, it is no longer necessary to set the second connection line CL2, thereby avoiding the signal influence caused by the overlap of the second connection line CL2 and the wires in the first pixel circuit 121 when the second connection line CL2 is set, and reducing the possibility of uneven display in the display panel 100.

[0088] In this embodiment, the equivalent circuit of the first pixel circuit 121 is... Figure 3 The illustrated embodiment is similar. Figure 25 This is a schematic diagram of the circuit structure of the first pixel circuit in a display panel according to another embodiment of the present invention. In this embodiment, the circuit structure of the first pixel circuit 121 is basically equivalent to that of... Figure 12 The circuit structure of the illustrated embodiment is mirrored, wherein the two are mirrored about a plane perpendicular to the second direction Y.

[0089] In this embodiment, the equivalent circuit and circuit structure of the second pixel circuit 122 are the same as those of the second pixel circuit 122. Figure 15 and Figure 16 The implementation methods shown are similar and will not be described in detail again.

[0090] In the present embodiment, the orientation of the first node N1 relative to the first channel C1 in the first pixel circuit 121 is opposite to the orientation of the second node N2 relative to the second channel C2 in the second pixel circuit 122. In the present embodiment, the circuit structure of the first pixel circuit 121 is substantially equivalent to the mirror image of the circuit structure of the second pixel circuit 122, where both are mirrored about a plane perpendicular to the second direction Y.

[0091] As Figure 24 In some embodiments, the display panel 100 further comprises a second fan-out area FA2. The second fan-out area FA2 is located between the third display area DA3 and the first display area DA1 along the first direction X. The display panel 100 further comprises a plurality of second signal lines 150. At least one second signal line 150 comprises a fourth sub-signal line 151, a fifth sub-signal line 152, and a sixth sub-signal line 153. The fourth sub-signal line 151 extends in the third display area DA3 along the first direction X and is electrically connected to the plurality of first pixel circuits 121. The fifth sub-signal line 152 extends in the second display area DA2 along the first direction X and is electrically connected to the plurality of second pixel circuits 122. The sixth sub-signal line 153 extends in the second fan-out area FA2 and is electrically connected to the first sub-signal line 141 and the second sub-signal line 142.

[0092] A row of pixel circuits (including the first pixel circuit 121 and / or the third pixel circuit 123) in the third display area DA3 shares a second signal line 140 with a row of second pixel circuits 122 in the second display area DA2, achieving signal supply for the first pixel circuit 121 and / or the third pixel circuit 123 in the third display area DA3.

[0093] In some embodiments, each first pixel circuit 121 is electrically connected with N second signal lines 150, where N is an integer greater than or equal to 2; and the arrangement order of N fourth sub-signal lines 151 along the second direction Y is opposite to that of N fifth sub-signal lines 152 in the N second signal lines 150 corresponding to each first pixel circuit 121. The second signal lines 150 include at least one of a scan line, a reference voltage signal line, or an emission control line. For example, each first pixel circuit 121 corresponds to four second signal lines 150, which are a first scan line SL1, a second scan line SL2, an emission control line EML, and a reference voltage signal line YL. By setting a second fan-out area FA2, the N fourth sub-signal lines 151 and the N fifth sub-signal lines 152 can be exchanged by N sixth sub-signal lines 153 in the second fan-out area FA2 to achieve the change in the arrangement order along the second direction Y. In an example, a row of first pixel circuits 121 and third pixel circuits 123 share four second signal lines 150 with a corresponding row of second pixel circuits 122, and the four second signal lines 150 have different arrangement orders in different display areas. In the third display area DA3, along the second direction Y from top to bottom, the four fourth sub-signal lines 151 are the first scan line SL1, the reference voltage signal line YL, the emission control line EML, and the second scan line SL2 in sequence. In the second display area DA2, along the second direction Y from top to bottom, the four fifth sub-signal lines 152 are the second scan line SL2, the emission control line EML, the reference voltage signal line YL, and the first scan line SL1 in sequence, which is opposite to the arrangement order of the four fourth sub-signal lines 151.

[0094] In some embodiments, the display panel 100 includes a plurality of wiring layers, and each wiring layer is provided with a patterned conductive structure, which can be a metal material or a semiconductor material. Optionally, in the N second signal lines 150 corresponding to each first pixel circuit 121, at least two of the N sixth sub-signal lines 153 are respectively in different wiring layers, so as to avoid signal interference between the sixth sub-signal lines 153 transmitting different signals, and achieve the change in the arrangement order of the N second signal lines 150 along the second direction Y.

[0095] Figure 26 is a top view schematic diagram of a display panel according to another embodiment of the present application, Figure 27 is Figure 26 is a partial enlarged schematic view of a Q4 region in Figure 28 is Figure 27 is a partial enlarged schematic view of a Q5 region in

[0096] In the present embodiment, the equivalent circuit and the circuit structure of the second pixel circuit 122 are the same as those of the first pixel circuit 121. Figure 15 andFigure 16 The illustrated embodiment is similar, and will not be described in detail.

[0097] The equivalent circuit of the first pixel circuit 121 in this embodiment is similar to that in the above embodiment. Figure 3 The illustrated embodiment is similar to the above embodiment, and the difference is that the circuit structure of the first pixel circuit 121 in this embodiment is not equivalent to that in the above embodiment. Figure 12 The circuit structure of the first pixel circuit 121 in this embodiment is a mirror image of that in the above embodiment, i.e., the circuit structure of the first pixel circuit 121 in this embodiment is different from that in the above embodiment. Figure 25 The illustrated embodiment is similar to the above embodiment, and the difference is that the circuit structure of the first pixel circuit 121 in this embodiment is not equivalent to that in the above embodiment.

[0098] In this embodiment, the first pixel circuit 121 and the second pixel circuit 122 each include at least a semiconductor layer, a first metal layer, a capacitor metal layer, and a second metal layer.

[0099] Figure 29 FIG. 6 is a structural diagram of a semiconductor layer of a first pixel circuit and a second pixel circuit in a display panel according to another embodiment of the present application, Figure 30 FIG. 7 is a structural diagram of a first metal layer of a first pixel circuit and a second pixel circuit in a display panel according to another embodiment of the present application, Figure 31 FIG. 8 is a structural diagram of a capacitor metal layer of a first pixel circuit and a second pixel circuit in a display panel according to another embodiment of the present application, Figure 32 FIG. 9 is a structural diagram of a second metal layer of a first pixel circuit and a second pixel circuit in a display panel according to another embodiment of the present application.

[0100] In this embodiment, the width-length ratio of the driving transistor M3 of the first pixel circuit 121 is different from that of the driving transistor M3 of the second pixel circuit 122, and specifically, the width-length ratio of the driving transistor M3 of the first pixel circuit 121 is greater than that of the driving transistor M3 of the second pixel circuit 122.

[0101] The greater the width-length ratio of the driving transistor M3 of the first pixel circuit 121 is designed, the stronger the driving capability is. When each first pixel circuit 121 needs to be connected to a plurality of first light emitting elements 111 of the same color, the working efficiency and performance of the first pixel circuit 121 can be ensured, and the display effect can be guaranteed. In other embodiments, when the number of the second light emitting elements 112 connected to the second pixel circuit 122 is greater, the width-length ratio of the driving transistor M3 of the second pixel circuit 122 can also be increased, which will not be described in detail here. The second pixel circuit 123 can also adjust the above parameters according to the number of the third light emitting elements 113 connected thereto, which will not be described in detail here.

[0102] As shown in FIG. 1, Figure 27 and Figure 28In some embodiments, the display panel 100 further includes a plurality of second signal lines 150. At least one second signal line 150 includes a fourth sub-signal line 151, a fifth sub-signal line 152, and a sixth sub-signal line 153. The fourth sub-signal line 151 extends along the first direction X in the third display area DA3 and is electrically connected with the plurality of first pixel circuits 121. The fifth sub-signal line 152 extends along the first direction X in the second display area DA2 and is electrically connected with the plurality of second pixel circuits 122. The sixth sub-signal line 153 extends in the second fan-out area FA2 and is electrically connected with the first sub-signal line 141 and the second sub-signal line 142. Each first pixel circuit 121 is electrically connected with N second signal lines 150, where N is an integer greater than or equal to 2; and the arrangement order of the N fourth sub-signal lines 151 along the second direction Y is opposite to the arrangement order of the N fifth sub-signal lines 152 along the second direction Y.

[0103] By providing the second fan-out area FA2, the N fourth sub-signal lines 151 and the N fifth sub-signal lines 152 can be transposed by the corresponding N sixth sub-signal lines 153 in the second fan-out area FA2 to achieve the change of the arrangement order along the second direction Y. For example, in the present embodiment, a row of first pixel circuits 121 and third pixel circuits 123 share a plurality of second signal lines 150 with a corresponding row of second pixel circuits 122, and the plurality of second signal lines 150 have different arrangement orders in different display areas. In the second display area DA2, along the second direction Y from top to bottom, the plurality of fourth sub-signal lines 151 are in turn the reference voltage signal line YL, the first scan line SL1_1, the shielding line PL, the second scan line SL2, the light-emitting control line EML, the reference voltage signal line YL, and the first scan line SL1_2. In the third display area DA3, along the second direction Y from top to bottom, the plurality of fifth sub-signal lines 152 are in turn the first scan line SL1_2, the reference voltage signal line YL, the light-emitting control line EML, the second scan line SL2, the shielding line PL, the first scan line SL1_1, and the reference voltage signal line YL, which is opposite to the arrangement order of the plurality of fourth sub-signal lines 151.

[0104] In the embodiment, the plurality of fourth sub-signal lines 151 and the plurality of fifth sub-signal lines 152 are distributed in the first metal layer and the capacitor metal layer. Each of the plurality of sixth sub-signal lines 153 has at least a portion located in the second metal layer, so that the fourth sub-signal line 151 and the corresponding fifth sub-signal line 152 are electrically connected through wire changing. In some other embodiments, the display panel further includes a third metal layer, and each of the plurality of sixth sub-signal lines 153 has at least a portion located in the third metal layer, or the plurality of sixth sub-signal lines 153 are distributed in the second metal layer and the third metal layer. By configuring at least a portion of the plurality of sixth sub-signal lines 153 in a layer different from the fourth sub-signal line 151 and the fifth sub-signal line 152, signal interference between the plurality of sixth sub-signal lines 153 transmitting different signals can be avoided, and the arrangement order of the N second signal lines 150 along the second direction Y can be changed.

[0105] The display device includes the display panel 100 of any of the foregoing embodiments. The display panel 100 includes a first display area DA1, a second display area DA2, a third display area DA3, and a first fan-out area FA1. The third display area DA3 is located at least on one side of the first display area DA1 along a first direction X. The second display area DA2 at least partially surrounds the first display area DA1 and the third display area DA3. The first display area DA1 has a light transmittance greater than that of the second display area DA2. The first fan-out area FA1 is located between the third display area DA3 and the second display area DA2 and between the first display area DA1 and the second display area DA2 along a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0106] The display panel 100 further includes a plurality of first light emitting elements 111 and a plurality of first pixel circuits 121. The plurality of first light emitting elements 111 are arranged in the first display area DA1. The plurality of first pixel circuits 121 are located in the third display area DA3. Each of the plurality of first pixel circuits 121 includes a first connection point P1 electrically connected to at least one of the plurality of first light emitting elements 111 through a first connection line CL1. Each of the plurality of first pixel circuits 121 includes a first preset transistor including a first channel C1. In the embodiment, at least one of the plurality of first pixel circuits 121 adjacent to the first fan-out area FA1 has the first connection point P1 located on a side of the first channel C1 away from the first fan-out area FA1.

[0107] According to the display device provided by the embodiment of the present application, in the display panel 100, in at least one first pixel circuit 121 adjacent to the first fan-out area FA1, the first connecting point P1 is located on the side of the first channel C1 away from the first fan-out area FA1, so that the first connecting line CL1 corresponding to the connecting point extends on the side of the first pixel circuit 121 away from the first fan-out area FA1, the space occupation of the first connecting line CL1 to the first fan-out area FA1 is reduced, the arrangement of other signal lines in the first fan-out area FA1 is facilitated, and the problem of insufficient wiring space in the first fan-out area FA1 is solved.

[0108] The embodiments described above are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obvious modifications and alterations are possible by persons skilled in the art. The embodiments were chosen and described in order to provide the best teachings to the skilled person in the art. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, The display device comprises: a first display area, a second display area, a third display area, and a first fan-out area and a second fan-out area, the third display area is located at least one side of the first display area along a first direction, the second display area at least partially surrounds the first display area and the third display area, the light transmittance of the first display area is greater than that of the second display area, the first fan-out area is located between the third display area and the second display area and between the first display area and the second display area along a second direction, the second direction intersects the first direction, and the second fan-out area is located between the third display area and the first display area along the first direction; a plurality of first light emitting elements arranged in the first display area; a plurality of second light emitting elements arranged in the second display area, and a plurality of third light emitting elements arranged in the third display area; a plurality of first pixel circuits located in the third display area, each of the first pixel circuits comprises a first connection point, the first connection point is electrically connected to at least one of the first light emitting elements through a first connection line, each of the first pixel circuits comprises a first preset transistor, the first preset transistor comprises a first channel, and in at least one of the first pixel circuits adjacent to the first fan-out area, the first connection point is located on a side of the first channel away from the first fan-out area; a plurality of second pixel circuits located in the second display area, each of the second pixel circuits is electrically connected to at least one of the second light emitting elements, and a plurality of third pixel circuits located in the third display area, each of the third pixel circuits is electrically connected to at least one of the third light emitting elements; a plurality of second signal lines, at least one of the second signal lines comprises a fourth sub-signal line, a fifth sub-signal line and a sixth sub-signal line, the fourth sub-signal line extends in the third display area along the first direction and is electrically connected to a plurality of the first pixel circuits, the fifth sub-signal line extends in the second display area along the first direction and is electrically connected to a plurality of the second pixel circuits, and the sixth sub-signal line extends in the second fan-out area and is electrically connected to the fourth sub-signal line and the fifth sub-signal line. The plurality of first pixel circuits are arranged in multiple rows along the second direction, and in each row of the first pixel circuits, the plurality of first pixel circuits are arranged along the first direction.

2. The display panel of claim 1, wherein, In at least one row of the first pixel circuits adjacent to the first fan-out area, the first connection point of each of the first pixel circuits is located on a side of the first channel away from the first fan-out area. The first connection point of each of the first pixel circuits is located on a side of the first channel away from the first fan-out area.

3. The display panel of claim 1, wherein, The first pixel circuit comprises a first node for transmitting a driving current to the first light emitting element, and the first node is located on one side of the first channel.

4. The display panel of claim 1, wherein, The first pixel circuit comprises a driving transistor, a first light emitting control transistor and a second light emitting control transistor; wherein, 5. The display panel of claim 4, wherein, ​ One pole of the second light-emitting control transistor is electrically connected to the anode of the first light-emitting element through the first node.

6. The display panel of claim 5, wherein, The first pixel circuit includes a first reset transistor electrically connected to the first node, and the first node is disposed between the first reset transistor and the second light-emitting control transistor along the second direction.

7. The display panel of claim 5, wherein, The first pixel circuit includes a second reset transistor electrically connected to the gate of the driving transistor, and the first connection point is disposed on the side of the second reset transistor away from the first node along the second direction.

8. The display panel of claim 4, wherein, In at least one of the first pixel circuits, the first connection point coincides with the first node.

9. The display panel of claim 4, wherein, In at least one of the first pixel circuits, the first node is located on the side of the first channel facing the first fan-out area, and the first connection point is electrically connected to the first node through a second connection line.

10. The display panel of claim 9, wherein, The first connection line extends along the first direction, the second connection line extends along the second direction, and the first connection line and the second connection line intersect at the first connection point.

11. The display panel of claim 9, wherein, At least part of the first connection line and the anode of the first light-emitting element are disposed in the same layer.

12. The display panel of claim 9, wherein, The first connection line is electrically connected to the second connection line through a via, and the first connection point includes the via.

13. The display panel of claim 1, wherein, The first preset transistor includes a driving transistor of the first pixel circuit.

14. The display panel of claim 1, wherein, The second display area includes a second pixel circuit, and the width-length ratio of the driving transistor of the first pixel circuit is greater than the width-length ratio of the driving transistor of the second pixel circuit.

15. The display panel of claim 1, wherein, The third display area includes a plurality of first pixel circuits, a plurality of third pixel circuits, and a plurality of third light-emitting elements, and the third pixel circuit is electrically connected to at least one of the third light-emitting elements. Along the first direction, the third pixel circuit is disposed between two first pixel circuits.

16. The display panel of claim 1, wherein, The first signal line is disposed in the first fan-out area along at least part of the first direction.

17. The display panel of claim 1, wherein, The first signal line includes a first sub-signal line disposed in the third display area, the first sub-signal line extending along the second direction; the first signal line includes a second sub-signal line disposed in the second display area, the second sub-signal line extending along the second direction; the first signal line includes a third sub-signal line disposed in the first fan-out area, the third sub-signal line extending in the first fan-out area; and The first sub-signal line is electrically connected to the second sub-signal line through the third sub-signal line.

18. The display panel of claim 4, wherein, Further comprising: A plurality of first signal lines, at least one of the first signal lines includes a first sub-signal line, a second sub-signal line, and a third sub-signal line, the first sub-signal line extending in the third display area along the second direction and being electrically connected to a plurality of first pixel circuits, the second sub-signal line extending in the second display area along the second direction and being electrically connected to a plurality of second pixel circuits, and the third sub-signal line extending in the first fan-out area and being electrically connected to the first sub-signal line and the second sub-signal line.

19. The display panel of claim 18, wherein, The first signal line comprises at least one of a data line, a reference voltage signal line, or a power supply line.

20. The display panel of claim 18, wherein, Each of the second pixel circuits comprises a second preset transistor comprising a second channel, and each of the second pixel circuits comprises a second node for transmitting a driving current to the second light emitting element, the second node being located at one side of the second channel.

21. The display panel of claim 20, wherein, The first node in the first pixel circuit is opposite to the second node in the second pixel circuit with respect to the orientation of the first channel and the second channel.

22. The display panel of claim 20, wherein, The first node in the first pixel circuit is the same as the second node in the second pixel circuit with respect to the orientation of the first channel and the second channel.

23. The display panel of claim 18, wherein, At least one of the third pixel circuits comprises a third connection point through which the third light emitting element is electrically connected to the third pixel circuit, and each of the third pixel circuits comprises a third preset transistor comprising a third channel. In at least one of the third pixel circuits adjacent to the first fan-out area, the third connection point is located at a side of the third channel facing away from the first fan-out area.

24. The display panel of claim 23, wherein, The first pixel circuits and the third pixel circuits are arranged in multiple rows along the second direction, and in each row of the first pixel circuits and the third pixel circuits, the first pixel circuits and the third pixel circuits are arranged along the first direction. In at least one of the first pixel circuits and the third pixel circuits adjacent to the first fan-out area, the first connection point of each of the first pixel circuits is located at a side of the first channel facing away from the first fan-out area, and the third connection point of each of the third pixel circuits is located at a side of the third channel facing away from the first fan-out area.

25. The display panel of claim 23, wherein, The third pixel circuit comprises a third node for transmitting a driving current to the third light emitting element, the third node being located at one side of the third channel, and the third connection point is electrically connected to the third node through a third connection line.

26. The display panel of claim 1, wherein, Each of the first pixel circuits is electrically connected to N second signal lines, N being an integer greater than or equal to 2. In the N second signal lines corresponding to each of the first pixel circuits, the arrangement order of the N fourth sub-signal lines along the second direction is opposite to the arrangement order of the N fifth sub-signal lines along the second direction.

27. The display panel of claim 1, wherein, The second signal line comprises at least one of a scan line, a reference voltage signal line, or a light emitting control line.

28. A display device comprising: The display panel comprises any one of the display panels according to any one of claims 1 to 27.

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