A silicon carbide IGBT device and a method of manufacturing the same

Abstract

The application provides a silicon carbide IGBT device and a manufacturing method thereof, and the device structure comprises an emitter metal, an emitter ohmic contact, a P+ contact region, an N+ contact region, a P-type base region, an N-type charge storage layer, a P-type shielding region, an N-type drift region, an N-type buffer layer, a P+ substrate, a collector ohmic contact, a collector metal, a polysilicon gate, a gate dielectric, and a P-type shielding region Schottky contact. The application adopts a trench silicon carbide IGBT device structure, and the P-type shielding region at the bottom of the trench is connected with the Schottky contact electrode. When the device is turned on, the Schottky contact improves the potential of the P-type shielding region, thereby inhibiting the holes from being collected by the emitter, enhancing the conductance modulation effect of the drift region, and reducing the on-state voltage drop; when the device is turned off, the P-type shielding region can shield the electric field aggregation at the trench gate chamfer, preventing the device from being broken down in advance; meanwhile, due to the introduction of the Schottky contact, the gate area is reduced, thereby reducing the gate charge, improving the switching speed, and reducing the turn-off loss.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically a silicon carbide IGBT device and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC), as a typical representative of wide-bandgap semiconductor materials, possesses excellent physical and electrical properties such as a wide bandgap, high critical breakdown electric field, high thermal conductivity, and high electron saturation drift velocity. Wide-bandgap silicon carbide power electronic devices have broken through the performance limits of traditional silicon-based devices in terms of voltage withstand capability, operating frequency, and conversion efficiency, making silicon carbide devices promising for applications in high-voltage, high-power, and high-temperature power electronics.

[0003] Silicon carbide (SiC) IGBTs (Insulated Gate Bipolar Transistors) combine the advantages of simple drive circuitry and strong bipolar on-state conduction capability of MOS field-controlled structures. Compared to SiC MOSFETs of the same voltage rating, SiC IGBTs have lower specific on-resistance, making them suitable for applications with voltage ratings above 10kV, such as high-voltage direct current (HVDC) transmission systems in smart grids. SiC IGBTs are mainly available in planar gate and trench gate types. Planar gate SiC IGBTs exhibit a JFET effect in the adjacent P-well region, significantly increasing their forward voltage drop. Trench gate SiC IGBTs eliminate the JFET effect, increasing channel density and further enhancing carrier concentration in the drift region. Compared to planar gate SiC IGBTs, trench gate SiC IGBTs are more conducive to compact cell design, effectively increasing channel density and significantly reducing forward voltage drop without increasing switching losses.

[0004] When the device is in the blocking state, the electric field strength of the gate oxide layer at the bottom of the trench in a trench silicon carbide IGBT is much higher than that in silicon carbide, which greatly tests the device's withstand voltage reliability. Therefore, a shielding layer is usually added to the bottom of the trench to weaken the electric field of the gate oxide layer. The shielding layer has two states: floating and grounded. In the floating state, the shielding layer potential is modulated by the gate and collector voltages, which enhances the conductivity modulation effect and reduces the forward conduction voltage, but it cannot effectively protect the gate oxide layer. In the grounded state, the electric field strength of the trench gate oxide layer can be effectively reduced, but in the conducting state, it accelerates the extraction of holes from the emitter in the drift region, resulting in a weakened conductivity modulation effect and an increased forward voltage drop. Summary of the Invention

[0005] This invention proposes a silicon carbide IGBT device and its manufacturing method. A Schottky contact is introduced in the middle of the trench gate to connect the emitter metal to the P-type shielding region. By raising the potential of the P-type shielding region through the Schottky barrier, holes find it more difficult to pass through the P-type shielding region compared to traditional trench gate IGBTs, thereby enhancing the conductivity modulation effect and reducing the on-state voltage drop. Furthermore, the on-state voltage drop of the IGBT can be controlled by controlling the Schottky barrier. Moreover, when the device is in the blocking state, the P-type shielding region at the bottom of the trench not only suppresses the electric field accumulation at the chamfer of the trench gate but also protects the Schottky contact interface integrated at the bottom of the trench, preventing premature breakdown of the device. Simultaneously, the introduction of the Schottky contact reduces the gate area, thereby reducing the gate charge, improving the switching speed, and reducing turn-off losses.

[0006] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0007] A silicon carbide IGBT device, comprising:

[0008] A P+ substrate 10, an N-type buffer layer 9 above the P+ substrate 10, an N-type drift region 8 above the N-type buffer layer 9, an N-type charge storage layer 6 above the N-type drift region 8, a P-type base region 5 above the N-type charge storage layer 6, a P+ contact region 3 and an N+ contact region 4 above the P-type base region 5, a trench between the P-type base regions 5, the trench including a gate dielectric 14 and a polysilicon gate 13 inside the gate dielectric 14, a P-type shielding region 7 at the bottom of the middle of the trench, a P-type shielding region Schottky contact 15 formed at the top of the P-type shielding region 7, an emitter ohmic contact 2 formed above the N+ contact region 4 and the P+ contact region 3, a portion of emitter metal 1 deposited above the emitter ohmic contact 2, a portion of emitter metal 1 deposited in the middle of the gate dielectric 14 above the P-type shielding region Schottky contact 15, a collector ohmic contact 11 formed below the P+ substrate 10, and a collector metal 12 deposited below the collector ohmic contact 11.

[0009] As a preferred embodiment, the gate dielectric 14 is silicon dioxide (SiO2).

[0010] As a preferred embodiment, the P+ contact region 3, N+ contact region 4, P-type base region 5, and P-type shielding region 7 are all formed by multiple ion implantations.

[0011] As a preferred embodiment, the materials of P+ contact region 3, N+ contact region 4, P-type base region 5, N-type charge storage layer 6, P-type shielding region 7, N-type drift region 8, N-type buffer layer 9, and P+ substrate 10 are all silicon carbide.

[0012] The present invention also provides a method for manufacturing the silicon carbide IGBT device, comprising the following steps:

[0013] Step 1: Sequentially epitaxially form an N-type buffer layer, an N-type voltage blocking layer, and an N-type charge storage layer on a P+ substrate;

[0014] Step 2: Aluminum ions are injected to form a P-type base region;

[0015] Step 3: Inject aluminum ions to form a P+ contact region;

[0016] Step 4: Inject nitrogen ions to form an N+ contact region and activate annealing;

[0017] Step 5: Etch gate trenches;

[0018] Step 6: Inject aluminum ions into the bottom of the trench to form a P-type shielding area;

[0019] Step 7: Thermal oxidation is performed in the trench to form a gate oxide layer, followed by annealing in a nitric oxide atmosphere;

[0020] Step 8: Deposit polycrystalline silicon;

[0021] Step 9: Etch polysilicon and deposit silicon dioxide isolation layer;

[0022] Step 10: Deposit emitter and collector metals, and anneal to form ohmic contacts;

[0023] Step 11: Etch the silicon dioxide isolation layer to form Schottky contact holes, deposit metal and then anneal to form Schottky contacts;

[0024] Step 12: Deposit aluminum or copper as the metal electrode of the device.

[0025] The beneficial effects of this invention are as follows: This invention introduces a Schottky contact in the middle of the trench gate to connect the emitter metal to the P-type shielding region. When the device is forward-biased, the Schottky contact increases the potential of the P-type shielding region, thereby suppressing hole collection by the emitter, enhancing the conductivity modulation effect of the drift region, and reducing the on-state voltage drop. When the device is off, the P-type shielding region can shield the electric field accumulation at the chamfer of the trench gate, preventing premature device breakdown. Simultaneously, the introduction of the Schottky contact reduces the gate area, thereby reducing the gate charge, increasing the switching speed, and reducing turn-off losses. Attached Figure Description

[0026] Figure 1 A schematic diagram of a traditional silicon carbide IGBT device with a shielding layer;

[0027] Figure 2 This is a schematic diagram of a silicon carbide IGBT device structure according to Embodiment 1 of the present invention;

[0028] Figure 3 This is a schematic diagram of the sequential epitaxial formation of an N-type buffer layer, an N-type voltage blocking layer, and an N-type charge storage layer on a P+ substrate layer according to Embodiment 2 of the present invention.

[0029] Figure 4 This is a schematic diagram of the formation of a P-type base region by implanting aluminum ions in Embodiment 2 of the present invention;

[0030] Figure 5 This is a schematic diagram of the formation of a P+ contact region by implanting aluminum ions in Embodiment 2 of the present invention;

[0031] Figure 6 This is a schematic diagram of the formation of an N+ contact region by implanting nitrogen ions and activating annealing in Embodiment 2 of the present invention;

[0032] Figure 7 This is a schematic diagram of the etched gate trench in Embodiment 2 of the present invention;

[0033] Figure 8 This is a schematic diagram of the formation of a P-type shielding area by injecting aluminum ions at the bottom of the trench in Embodiment 2 of the present invention;

[0034] Figure 9 This is a schematic diagram of the generation of a gate oxide layer by thermal oxidation in the trench in Embodiment 2 of the present invention, followed by annealing in a nitric oxide atmosphere;

[0035] Figure 10 This is a schematic diagram of polycrystalline silicon deposition in Embodiment 2 of the present invention;

[0036] Figure 11 This is a schematic diagram of etching polysilicon and depositing a silicon dioxide isolation layer in Embodiment 2 of the present invention;

[0037] Figure 12 This is a schematic diagram of the deposition of emitter and collector metals and the annealing to form an ohmic contact in Embodiment 2 of the present invention.

[0038] Figure 13 This is a schematic diagram of etching a silicon dioxide isolation layer to form a Schottky contact hole, depositing metal, and then annealing to form a Schottky contact in Embodiment 2 of the present invention.

[0039] Figure 14 This is a schematic diagram of deposited aluminum or copper as the metal electrode of the device in Embodiment 2 of the present invention.

[0040] In the figure: 1 is the emitter metal, 2 is the emitter ohmic contact, 3 is the P+ contact region, 4 is the N+ contact region, 5 is the P-type base region, 6 is the N-type charge storage layer, 7 is the P-type shielding region, 8 is the N-type drift region, 9 is the N-type buffer layer, 10 is the P+ substrate, 11 is the collector ohmic contact, 12 is the collector metal, 13 is the polysilicon gate, 14 is the gate dielectric, and 15 is the P-type shielding region Schottky contact. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Example

[0043] This embodiment provides a silicon carbide IGBT device, such as Figure 2 As shown:

[0044] A P+ substrate 10, an N-type buffer layer 9 above the P+ substrate 10, an N-type drift region 8 above the N-type buffer layer 9, an N-type charge storage layer 6 above the N-type drift region 8, a P-type base region 5 above the N-type charge storage layer 6, a P+ contact region 3 and an N+ contact region 4 above the P-type base region 5, a trench between the P-type base regions 5, the trench including a gate dielectric 14 and a polysilicon gate 13 inside the gate dielectric 14, a P-type shielding region 7 at the bottom of the middle of the trench, a P-type shielding region Schottky contact 15 formed at the top of the P-type shielding region 7, an emitter ohmic contact 2 formed above the N+ contact region 4 and the P+ contact region 3, a portion of emitter metal 1 deposited above the emitter ohmic contact 2, a portion of emitter metal 1 deposited in the middle of the gate dielectric 14 above the P-type shielding region Schottky contact 15, a collector ohmic contact 11 formed below the P+ substrate 10, and a collector metal 12 deposited below the collector ohmic contact 11.

[0045] Preferably, the gate dielectric 14 is silicon dioxide (SiO2).

[0046] Preferably, the P+ contact region 3, N+ contact region 4, P-type base region 5, and P-type shielding region 7 are all formed by multiple ion implantations.

[0047] Preferably, the materials of P+ contact region 3, N+ contact region 4, P-type base region 5, N-type charge storage layer 6, P-type shielding region 7, N-type drift region 8, N-type buffer layer 9, and P+ substrate 10 are all silicon carbide.

[0048] The working principle of this example is as follows:

[0049] When a silicon carbide IGBT device is forward-biased, the Schottky barrier raises the potential of the P-type shielding region, making it more difficult for holes to pass through the P-type shielding region compared to traditional trench IGBTs. This enhances the conductivity modulation effect, reduces the on-state voltage drop, and the on-state voltage drop can be adjusted by controlling the Schottky barrier. During reverse breakdown, the P-type shielding region at the bottom of the trench connects to the emitter, which not only suppresses the electric field accumulation at the chamfer of the trench gate but also protects the Schottky contact interface integrated at the bottom of the trench, preventing premature breakdown of the device. At the same time, the introduction of Schottky contacts reduces the gate area, thereby reducing the gate charge, improving the switching speed, and reducing turn-off losses.

[0050] Example 2

[0051] like Figures 3-14 As shown, this embodiment provides a method for fabricating a silicon carbide IGBT device, including the following steps:

[0052] Step 1: Sequentially epitaxially form an N-type buffer layer, an N-type voltage blocking layer, and an N-type charge storage layer on a P+ substrate, such as... Figure 3 As shown;

[0053] Step 2: Aluminum ions are implanted to form a P-type base region, such as... Figure 4 As shown;

[0054] Step 3: Inject aluminum ions to form a P+ contact region, such as Figure 5 As shown;

[0055] Step 4: Inject nitrogen ions to form an N+ contact region and activate annealing, such as... Figure 6 As shown;

[0056] Step 5: Etch the gate trench, such as... Figure 7 As shown;

[0057] Step 6: Inject aluminum ions into the bottom of the trench to form a P-type shielding area, such as... Figure 8 As shown;

[0058] Step 7: Thermally oxidize the gate oxide layer within the trench to form an oxide layer, followed by annealing in a nitric oxide atmosphere, as shown below. Figure 9 As shown;

[0059] Step 8: Deposit polycrystalline silicon, such as... Figure 10 As shown;

[0060] Step 9: Etch polysilicon and deposit a silicon dioxide insulating layer, such as... Figure 11 As shown;

[0061] Step 10: Deposit emitter and collector metals, and anneal to form ohmic contacts, such as... Figure 12 As shown;

[0062] Step 11: Etch the silicon dioxide isolation layer to form Schottky contact holes, deposit metal, and then anneal to form Schottky contacts, such as... Figure 13 As shown;

[0063] Step 12: Deposit aluminum or copper as the metal electrode for the device, such as... Figure 14 As shown.

[0064] The device has a gate dielectric layer as the gate electrode, a P+ substrate as the collector electrode, and P+ and N+ contact regions as emitters.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A silicon carbide IGBT device, characterized in that... include: A P+ substrate (10), an N-type buffer layer (9) above the P+ substrate (10), an N-type drift region (8) above the N-type buffer layer (9), an N-type charge storage layer (6) above the N-type drift region (8), a P-type base region (5) above the N-type charge storage layer (6), a P+ contact region (3) and an N+ contact region (4) above the P-type base region (5), and a trench between the P-type base regions (5). The trench includes a gate dielectric (14) and a polysilicon gate (13) inside the gate dielectric (14). A P-type base region is provided at the bottom of the middle of the trench. The P-type shielding region (7) forms a P-type shielding region Schottky contact (15) on top. An emitter ohmic contact (2) is formed above the N+ contact region (4) and the P+ contact region (3). A portion of the emitter metal (1) is deposited above the emitter ohmic contact (2), and a portion of the emitter metal (1) is deposited in the middle of the gate dielectric (14) above the P-type shielding region Schottky contact (15). A collector ohmic contact (11) is formed below the P+ substrate (10), and collector metal (12) is deposited below the collector ohmic contact (11).

2. The silicon carbide IGBT device according to claim 1, characterized in that: The gate dielectric (14) is silicon dioxide (SiO2).

3. A silicon carbide IGBT device according to claim 1, characterized in that: The P+ contact region (3), N+ contact region (4), P-type base region (5), and P-type shielding region (7) are all formed by multiple ion implantations.

4. A silicon carbide IGBT device according to claim 1, characterized in that: The materials of P+ contact region (3), N+ contact region (4), P-type base region (5), N-type charge storage layer (6), P-type shielding region (7), N-type drift region (8), N-type buffer layer (9), and P+ substrate (10) are all silicon carbide.

5. A method for manufacturing a silicon carbide IGBT device according to any one of claims 1 to 4, characterized in that... Includes the following steps: Step 1: Sequentially epitaxially form an N-type buffer layer, an N-type voltage blocking layer, and an N-type charge storage layer on a P+ substrate; Step 2: Aluminum ions are injected to form a P-type base region; Step 3: Inject aluminum ions to form a P+ contact region; Step 4: Inject nitrogen ions to form an N+ contact region and activate annealing; Step 5: Etch gate trenches; Step 6: Inject aluminum ions into the bottom of the trench to form a P-type shielding area; Step 7: Thermal oxidation is performed in the trench to form a gate oxide layer, followed by annealing in a nitric oxide atmosphere; Step 8: Deposit polycrystalline silicon; Step 9: Etch polysilicon and deposit silicon dioxide isolation layer; Step 10: Deposit emitter and collector metals, and anneal to form ohmic contacts; Step 11: Etch the silicon dioxide isolation layer to form Schottky contact holes, deposit metal and then anneal to form Schottky contacts; Step 12: Deposit aluminum or copper as the metal electrode of the device.

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