Self-clamping split insulated gate bipolar transistor and manufacturing method thereof

Abstract

The application belongs to the technical field of power semiconductor devices, and relates to a self-clamp split insulated gate bipolar transistor and a manufacturing method thereof. The application is characterized in that a diode is connected in series between a split polysilicon gate (11) and a floating P region (12), the cathode of the diode is connected with the split polysilicon gate (11), the anode of the diode is connected with the floating P region (12), a capacitor is connected in series between the split gate (11) and the emitter metal (1), and the floating P region (12) is clamped by an active region to obtain a higher potential at the time of IGBT turn-off. The potential makes the diode open, thereby charging the capacitor and making the capacitor obtain a stable potential. The split gate (11) is connected with the capacitor, so that the split gate also has a stable potential, the potential attracts the electrons near the split gate to accumulate to form an electron accumulation layer, the accumulation layer improves the injection efficiency of the channel, further improves the drift region conductance modulation effect, and reduces the forward conduction voltage drop of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to a self-clamping split gate bipolar transistor and a manufacturing method thereof. BACKGROUND

[0002] The emergence of electric energy has promoted the rapid development of modern social science and technology, and how to more efficiently handle electric energy has always been a popular topic of scientific research all over the world. Efficient use of electric energy highly depends on power electronic systems, and the core electronic components of various power electronic systems are semiconductor power devices. Semiconductor power devices are widely used in various household appliances, various industrial equipment and other fields dominated by electric power. In the 21st century, global warming has attracted more and more attention, and energy saving and emission reduction and improvement of energy utilization efficiency are becoming increasingly important. Today, the proportion of clean and renewable energy is increasing, and society has higher expectations for energy conversion efficiency, and higher requirements for the performance of power semiconductor devices, which are the core of energy control.

[0003] As a new generation of power electronic devices, the insulated gate bipolar transistor (IGBT) combines the advantages of field effect transistor (MOSFET) and bipolar junction transistor (BJT), and has the advantages of MOSFET easy to drive, low input impedance, fast switching speed, and the advantages of BJT large on-state current density, low on-state voltage drop, small loss and good stability. Thus developed into one of the core electronic components in modern power electronic circuits, and is widely used in transportation, power grid, communication, household appliances and aerospace fields. The use of IGBT greatly improves the performance of power electronic systems.

[0004] Since the invention of IGBT, people have been committed to improving the performance of IGBT. After more than 20 years of development, several generations of IGBT device structures have been proposed, and the performance of the device has been steadily improved. The traditional trench IGBT (such as Figure 1 ) changes the gate from a horizontal planar MOS to a vertical trench MOS structure, which not only improves the power density and structural design space, but also eliminates the adverse effects of the JFET region and the latch-up effect caused by the parasitic NPN. The shield gate trench IGBT (such as Figure 2 ) based on the trench IGBT has a lower gate capacitance, so it has a faster switching speed and lower switching loss. Moreover, compared with the high peak electric field at the bottom of the traditional trench gate structure, the SGT structure has the advantage of optimizing the electric field to increase the withstand voltage, so the SGT-IGBT has greater application value in high-reliability high-performance application fields. Figure 2A cell structure of a conventional SGT-IGBT device is shown. The IGBT is an insulated gate controlled structure, and its gate forms a channel while attracting electrons in the non-channel area through the gate voltage to form an electron accumulation layer, further reducing the forward conduction voltage drop. However, in the SGT-IGBT, since the shield gate is connected to the emitter, it cannot attract electrons to form an electron accumulation layer, and the channel electron injection efficiency is reduced, so the conductance modulation effect is weaker than that of the conventional trench IGBT, and the forward conduction voltage drop is increased. SUMMARY

[0005] To reduce the on-state voltage drop of the device and improve the performance of the device, the present application provides a self-clamping split IGBT, and a structure diagram is shown as Figure 3 The structure draws a potential in the floating P region 12, charges the capacitor through the diode when the IGBT is blocked, and uses the voltage on the capacitor to provide a self-clamping potential for the split gate (SG) when the IGBT is turned on, so that an electron accumulation is formed under the split gate 11 trench, thereby enhancing the forward conduction capability of the IGBT device. Its equivalent circuit is shown as Figure 4 At the same time, the split gate 11 forms an internal field plate structure when it is blocked, optimizes the peak electric field at the bottom of the trench, and improves the forward voltage resistance capability of the IGBT. And the existence of the split gate 11 weakens the capacitive effect between the gate and the collector, accelerates the switching speed of the IGBT, reduces the switching loss of the device, and further optimizes the characteristics of the device.

[0006] The technical scheme of the present application is:

[0007] A self-clamping split insulated gate bipolar transistor, comprising a collector metal (10), a P-type collector region 9, an N-type electric field blocking layer 8, an N-drift region 7 and an active region which are sequentially stacked from bottom to top; the active region comprises a P-type base region 4 and a P region 20 located at both ends of the upper surface of the N-drift region 7, a trench gate structure located between the P-type base region 4 and the P region 20, a floating P region 12 located between the trench gate structure and the trench emitter structure, the trench gate structure is in contact with the P-type base region 4, and the trench emitter structure is in contact with the P region 20, and the lower surface junction depths of the trench gate structure, the floating P region 12 and the trench emitter structure are greater than the lower surface junction depths of the P-type base region 4 and the P region 20;

[0008] The upper surface of the P-type base region 4 is provided with a P+ emitter region 2 and an N+ emitter region 3 in parallel, wherein the N+ emitter region 3 is located on the side close to the trench gate structure, and a first metal 1-1 is provided on the upper surfaces of the P+ emitter region 2 and the N+ emitter region 3;

[0009] The trench gate structure comprises a trench gate 5, a split gate 11 and a first gate oxide layer 6-1, wherein the split gate 11 is located directly below the trench gate 5 and is separated by the first gate oxide layer 6-1, and the trench gate 5, the split gate 11 and the P-type base region 4, the floating P region 12 and the N-drift region 7 are also separated by the first gate oxide layer 6-1;

[0010] The upper layer of the floating P region 12 has a P+ ohmic contact region 15 adjacent to the trench emitter structure; the P+ ohmic contact region 15 is in contact with the trench emitter structure, the upper surface of the P+ ohmic contact region 15 has a second metal 17, the upper surface of the floating P region 12 adjacent to the second metal 17 has a field oxide layer 13, the field oxide layer 13 is in contact with the second metal 17 but has a spacing with the trench gate structure, and a polysilicon diode is provided on the upper surface of the field oxide layer 13; the polysilicon diode comprises a polysilicon diode P+ region 18 and a polysilicon diode N+ region 19, and the polysilicon diode P+ region 18 is in contact with the second metal 17;

[0011] The trench emitter structure comprises a trench emitter 14 and a second gate oxide layer 6-2, wherein the second gate oxide layer 6-2 separates the trench emitter 14 from the floating P region 12, the P+ ohmic contact region 15, the P region 20 and the N-drift region 7; the upper surface of the trench emitter 14 has a third metal 1-2;

[0012] The upper surface of the P region 20 has an N+ contact region 16, and the N+ contact region 16 is in contact with the second gate oxide layer 6-2; the third metal also covers the upper surface of the N+ contact region 16;

[0013] The split gate 11 is electrically connected to the polysilicon diode N+ region 19, and a capacitor C is connected in series between the split gate 11 and the first metal 1-1, so that the potential of the floating P region 12 is charged to the capacitor C, and self-clamping of the split gate is realized.

[0014] In the above scheme, the potential of the floating P region 12 is charged to the capacitor through the polysilicon diode PN junction, the capacitor voltage is raised, and self-clamping of the split gate is realized. This structure can improve the forward conduction characteristics on the basis of the traditional split gate structure, and is compatible with the control circuit of the traditional IGBT.

[0015] Further, the P region 20 and the N+ contact region 16 also have an N-BL buried layer 21, which introduces an N-BL buried layer into the P region of the clamping PN junction to form a clamping PMOS structure. The structure can provide a hole extraction channel during the off process, ensuring the clamping of the floating P region while improving the off extraction speed of the device and further improving the dynamic characteristics of the device.

[0016] Further, the trench width of the trench emitter structure is smaller than that of the trench gate structure, and the junction depth of the trench emitter structure is smaller than that of the trench gate structure, that is, the bottom of the trench emitter structure has a spacing from the bottom of the floating P region 12, while the bottom of the trench gate structure is flush with the bottom of the floating P region 12. The emitter trench etching window is reduced, and the trench depth can be further reduced while being fabricated synchronously with the gate trench, and the floating P region and the clamping P region are fabricated through the same process step, thereby saving the process step.

[0017] Further, the trench emitter 14 is split into a first trench emitter 14-1 and a second trench emitter 14-2, and the first trench emitter 14-1 is in a symmetrical structure with the trench gate 5 and the second trench emitter 14-2 is in a symmetrical structure with the split gate 11. The emitter trench is split into two, the thickness of the emitter 14-2 at the bottom of the trench is consistent with the thickness of the split gate electrode 11, and the thickness of the emitter 14-1 at the top is consistent with the thickness of the trench gate electrode 5. This scheme has better process consistency, and the emitter trench and the gate trench are symmetrical, which can be realized through uniform process steps.

[0018] Further, the trench gate structure is adjacent to a shallow trench gate structure in the part of the upper layer of the floating P region 12, and the width and the junction depth of the shallow trench gate structure are smaller than those of the trench gate structure; the shallow trench gate structure and the trench gate structure have a spacing therebetween, and the gate of the trench gate structure is connected to the upper surface of the floating P region 12 between the shallow trench gate structure and the trench gate structure through a metal. The shallow trench structure is introduced on the right side of the trench gate 5 by using the load effect, and is connected to the SG, and the metal connection is formed between the narrow channel top end formed by the metal pair and the top of the shallow trench SG, thereby improving the integration and realizing the controllable PN junction.

[0019] Further, the N-drift region 7 further has a P column 23, and the P column 23 and the N-drift region 7 form an N / P column super-junction drift region. The P column 23 is realized by trenching and filling, and the concentrations of the two are similar, and the doping concentration is set to 1×10 14 cm -3 -5×10 16 cm -3 , the column width is 2-12 μm, and the drift region thickness is reduced by 20-30% according to the voltage requirement. The introduction of the super-junction structure is beneficial to improve the voltage resistance and compromise performance of the device, and the drift column region which is laterally exhausted assists the expansion of the longitudinal depletion layer when the device switches, thereby further improving the switching speed of the device.

[0020] Further, the N-type field stop layer 8 is formed by hydrogen implantation, and the number of hydrogen implantation is set to four times, and 1×10 12 cm -3 -1×1015 cm -3 The implantation dose is in the range of 1012-1014cm-2 and the implantation energy is in the range of 20-200keV. The hydrogen implantation process is suitable for forming the deep implantation of the IGBT instead of the high-temperature pre-diffusion process because of the advantages of large implantation depth at low energy and low annealing temperature.

[0021] Further, the collector region P region 9 also has an N region 24 arranged side by side with the collector region P region 9, and the N region 24 is located below the P region 20. The introduction of the partial N region 24 in the collector region P region 9 realizes the RC-IGBT structure, so that the diode in the IGBT module is also integrated into the IGBT structure. The introduction of the collector region N region integrates the diode in the IGBT module into the IGBT structure, and improves the module integration.

[0022] Further, the material of the structure includes silicon, silicon carbide, gallium nitride, gallium oxide, diamond and the like.

[0023] The manufacturing method of the self-clamping split insulated gate bipolar transistor includes:

[0024] Step 1: select an N-type lightly doped FZ silicon wafer with a certain thickness and concentration as the N-drift region 7 of the device; grow a field oxide layer, as shown in Figure 12 ;

[0025] Step 2: photoetching, implanting P-type impurities by high-temperature ion implantation and annealing to manufacture the floating P region 12 of the device, and growing a pre-oxidation layer on the surface of the silicon wafer, as shown in Figure 13 ;

[0026] Step 3: etching the field oxide to form an active region by photoetching, as shown in Figure 14 ;

[0027] Step 4: etching the trench by photoetching, and growing a sacrificial oxide for removing surface contamination after etching, and then forming the gate oxide layer 6-1, 6-2 by thermal oxidation, as shown in Figure 15 ;

[0028] Step 5: depositing N-doped polysilicon, and etching by photoetching to form the gate polysilicon 5, 14 and the substrate 19 of the polysilicon PN diode, as shown in Figure 16 ;

[0029] Step 6: first, forming an oxidation shielding layer a by thermal oxidation, etching the oxide layer on the surface of 5 and the upper polysilicon in 5 by photoetching to form the SGT gate polysilicon 11, forming an oxidation isolation layer by thermal oxidation and then depositing to form the polysilicon gate 5, and forming the gate electrode by metal connection, as shown inFigure 17 、 18 as shown in Fig. 2;

[0030] Step 7: Photolithography, high temperature ion implantation of P-type impurities and annealing to form P-type base region 4 and 20 of the device, as shown in Fig. 3; Figure 20

[0031] Step 8: High temperature ion implantation of N-type impurities and annealing to form N+ emitter region 3 of the device, as shown in Fig. 4; Figure 21

[0032] Step 9: High temperature ion implantation of P-type impurities and annealing to form P+ emitter region 2, floating P-ohmic contact region 15, P region 18 in the polycrystalline PN junction and P+ region 16 of the device, as shown in Fig. 5; Figure 22

[0033] Step 10: Al metal deposition to form emitter electrode 1-1 and metal connection 17 connecting polycrystalline diode P region 18 and floating P-ohmic contact region 15, metal 1-2 connecting emitter 14, as shown in Fig. 6; Figure 23

[0034] Step 11: Turn over the silicon wafer, thin the silicon wafer, high energy ion implantation of N-type impurities on the back of the silicon wafer, ion implantation of P-type impurities and annealing to form N-type field stop layer 8 and P-type collector region 9 on the lower surface, as shown in Fig. 7; Figure 24

[0035] Step 12: Metal deposition on the back of the silicon wafer to form metal collector 10 on the lower surface of P-type collector region 9. Thus, the self-clamping split IGBT of the present application is prepared, as shown in Fig. 8. Figure 25

[0036] For simplicity of description, the above device structure and preparation method are described by taking N-channel IGBT device as an example, but the present application is also applicable to the preparation of P-channel IGBT device.

[0037] The principle of the present application is described by taking N-channel self-clamping split IGBT as an example:

[0038] When the gate electrode 5 is connected to high potential higher than the threshold voltage of the device, the collector 10 is connected to high potential, and the emitter 1-1, 1-2 is connected to low potential, the device works in the on state, the P+ collector region 9 injects holes into the N- drift region 7, and the N+ emitter region 3 injects electrons into the N- drift region 7, the existence of electron-hole pairs causes the occurrence of conductance modulation effect in the drift region.

[0039] ​​​​​​The polycrystalline silicon diode structure P region 18 is connected with the floating P ohmic contact region 15 above the floating P region 12 through the metal 17, the potential below the floating P region 12 is clamped by the reverse-biased PN junction formed by the P-type base region 20 and the N-drift region 1, the potential charges the integrated capacitor through the PN diode, since the diode can maintain the charge amount on the capacitor and the floating P region has a relatively stable clamping voltage, so that the N region 19 of the diode is kept at a stable value, and the N region 19 of the diode is connected with the SG gate 11, so the SG gate also has a stable potential, which attracts the electrons near the SG gate to accumulate to form an electron accumulation layer, which improves the injection efficiency of the channel, further enhances the drift region conductance modulation effect, and reduces the forward conduction voltage drop of the device.

[0040] The beneficial effects of the present application are: the present application utilizes the potential of the floating P region to provide a bias potential for the split gate 11, thereby forming an electron accumulation ability below the trench, enhancing the conductance modulation effect, thereby enhancing the forward conduction capability of the device. Compared with the traditional split gate structure, the introduction of the self-clamping structure is beneficial to simultaneously improving the conduction capability and switching performance of the device, eliminating the negative effects brought by the split gate, improving the switching loss and switching speed, and also optimizing the forward conduction capability of the device, improving the compromise characteristics between the forward conduction voltage drop and the off-state loss of the device.

[0041] The gate oxide layer 6 around the split polycrystalline silicon gate 11 is not limited by the threshold voltage design, so its thickness can be further increased to improve the voltage resistance and oxide layer reliability of the device, and improve the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 It is a schematic diagram of the cell structure of a traditional trench gate IGBT;

[0043] Figure 2 It is a schematic diagram of the cell structure of a traditional shield gate trench IGBT;

[0044] Figure 3 It is a schematic diagram of the self-clamping split IGBT cell structure provided by embodiment 1 of the present application;

[0045] Figure 4 It is an equivalent circuit diagram of the self-clamping split IGBT cell structure provided by embodiment 1 of the present application;

[0046] Figure 5 It is a schematic diagram of the IGBT cell structure with a PMOS clamping structure provided by embodiment 2 of the present application;

[0047] Figure 6 It is a schematic diagram of the IGBT cell structure with a shallow trench emitter provided by embodiment 3 of the present application;

[0048] Figure 7 is a schematic diagram of an IGBT cell structure with emitter trench and gate trench symmetry provided by embodiment 4 of the present application;

[0049] Figure 8 is a schematic diagram of an IGBT cell structure with internal anti-type layer diode structure with shallow trench provided by embodiment 5 of the present application;

[0050] Figure 9 is a schematic diagram of an IGBT cell structure with N-drift replaced by higher concentration N / P column super junction structure provided by embodiment 6 of the present application.

[0051] Figure 10 is a schematic diagram of an IGBT cell structure with thick FS layer of hydrogen implantation between N-drift and P+ collector provided by embodiment 7 of the present application;

[0052] Figure 11 is a schematic diagram of an IGBT cell structure with back collector RC structure provided by embodiment 8 of the present application.

[0053] Figures 12-25 is a schematic diagram of a device structure obtained in a step of a manufacturing method flow of the present application. DETAILED DESCRIPTION

[0054] The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0055] Embodiment 1

[0056] A self-clamping split insulated gate bipolar transistor, the cell structure of which is as shown in Figure 3As shown, it comprises: collector metal 10, P-type collector region 9, N-type electric field stop layer 8, N-drift region 7, gate oxide layer 6-1, 6-2, P-type base region 4, N+emitter region 3, floating P region 12, polycrystalline diode N+region 19 and P+region 18, floating P region and polycrystalline diode contact metal 17, floating P region 12 and metal 17 connected ohmic contact clamping diode structure P+ohmic contact region 15, P region 20, trench gate structure 5, separate gate structure 11, trench emitter 14 and emitter metal 1-2, and P+region 2 contact metal 1-1; collector metal 10 is located on the back of P-type collector region 9, N-type electric field stop layer 8 is located on the front of P-type collector region 9, and N-drift region 7 is located on the front of N-type electric field stop layer 8; P-type base region 4 is located above N-drift region 7 and on one side of trench gate 11; P-type floating region 12 is located between trench gate 5 and trench emitter 14; polycrystalline diode 18 and 19 are located above P-type floating region 12 and are separated by field oxide layer 13, and metal 17 connects polycrystalline diode P+region 18 and P-type floating region 12; N+emitter region 3 is located on the top layer of P-type base region 4 and is separated from N-drift region 7 by P-type base region 4; the self-clamping PN junction structure is located above N-drift region 7 and on one side of emitter trench 14, P region 20 and N+region 16 are located above the drift region, N+region 16 is in ohmic contact with metal 1-2, and metal 1-2 is connected to the emitter. This structure connects separate gate 11 and polycrystalline diode N+region 19 through module packaging, and simultaneously packages capacitor C into the module, so that C is connected in series between separate gate 11 and emitter metal 1-1.

[0057] In this embodiment, the doping concentration of P-type base region 4 is 3×10 16 cm -3 ~2×10 17 cm -3 , and the depth is 3~3.5μm; the doping concentration of N+emitter region 3 is 5×10 18 cm -3 ~1×10 21 cm -3 , and the depth is 0.2~0.5μm; the thickness of gate dielectric layer 6-1, 6-2 is 80~120nm; the depth of trench gate electrode 5 is 4~6μm; the depth of separate gate electrode 11 is 0.5~2μm; the depth of trench emitter 14 is 5~8μm; the doping concentration of N-drift region 7 is 5×10 12 cm -3 ~2×10 14 cm -3 , and the thickness is 60~700μm; the doping concentration of N-type electric field stop layer 8 is 5×10 15 cm -3 ~5×10 16 cm -3The thickness is 5~20μm; the doping concentration of the P-type collector region 9 is 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The thickness is 0.5~5μm; the cell width is 20~40μm.

[0058] Example 2

[0059] An embodiment of a self-clamped split insulated gate bipolar transistor, such as Figure 5 As shown, based on Example 1, an N-BL buried layer is introduced into the P region of the clamped PN junction to form a clamped PMOS structure. This structure can provide a hole extraction channel during the turn-off process, which improves the turn-off extraction speed of the device while ensuring the clamping of the floating P region, and further enhances the dynamic characteristics of the device.

[0060] Example 3

[0061] An embodiment of a self-clamped split insulated gate bipolar transistor, such as Figure 6 As shown, based on Example 1, the emitter trench etching window is reduced, and its trench depth can be further reduced while being fabricated simultaneously with the gate trench. At the same time, the floating P region and the clamped P region are fabricated through the same process step, saving process steps.

[0062] Example 4

[0063] An embodiment of a self-clamped split insulated gate bipolar transistor, such as Figure 7 As shown, based on Example 1, the emitter trench is split into two. The thickness of the emitter 14-2 at the bottom of the trench is the same as the thickness of the separate gate electrode 11, which is 0.5~2μm. The thickness of the emitter 14-1 at the top is the same as the thickness of the trench gate electrode 5, which is 4~6μm.

[0064] Compared with Example 1, this scheme has better process consistency, and the emitter trench and gate trench are symmetrical, which can be achieved through a unified process step.

[0065] Example 5

[0066] An embodiment of a self-clamped split insulated gate bipolar transistor, such as Figure 8 As shown, based on Example 4, a shallow trench structure is introduced on the right side of the trench gate 5 using the load effect, and it is connected to the SG. The top of the narrow channel formed by the metal pair is connected to the top of the shallow trench SG, which improves the integration and realizes the controllability of the PN junction.

[0067] Example 6

[0068] A self-clamping split-gate bipolar transistor embodiment, on the basis of embodiment 1, injects N-type impurities with high injection energy in the process step of P-base region 4 through the process of high-energy ion implantation, thereby forming a carrier storage layer, further enhancing the accumulation of holes and injection of electrons in the drift region, enhancing the conductance modulation effect, and improving the on-state characteristics of the device.

[0069] Embodiment 7

[0070] A self-clamping split-gate bipolar transistor embodiment, as shown in Figure 9 , on the basis of embodiment 4, replaces the N-drift region 7 with a higher concentration of N / P column super junction structure, the N column 7 is the substrate, and the P column 23 is realized by trench filling single crystal silicon or multiple epitaxial ion implantation, both of which have similar concentrations, and the doping concentration is set to 1×10 14 cm -3 -2×10 16 cm -3 , the column width is 2-12 μm, and the drift region thickness is reduced by 20-30% according to the voltage withstand requirement.

[0071] Compared with embodiment 1, the introduction of the super junction structure is beneficial to improve the voltage withstand and compromise performance of the device, and the laterally exhausted drift column region assists the extension of the longitudinal depletion layer during device switching, further improving the switching speed of the device.

[0072] Embodiment 8

[0073] A self-clamping split-gate bipolar transistor embodiment, as shown in Figure 10 , on the basis of embodiment 4, introduces a thick FS layer 8 with hydrogen implantation between the N-drift region and the P+ collector region. The hydrogen implantation process has the advantages of large implantation depth at low energy and low annealing temperature, and is very suitable for replacing the high-temperature pre-diffusion process to form the deep implantation of the IGBT. The number of back high-energy H implantation is set to four, and the implantation dose is selected in the range of 1×10 12 cm -3 -1×10 15 cm -3 , and the implantation energy is selected as 20-200 keV.

[0074] Compared with embodiment 1, the N-drift region formed by the hydrogen-implanted field stop layer has a more gentle concentration gradient at the NN-junction of the N+ FS layer, which can effectively increase the dynamic avalanche tolerance of the device.

[0075] Embodiment 9

[0076] A self-clamping split-gate bipolar transistor embodiment, as shown in Figure 11As shown, on the basis of embodiment 1, a part of N region 24 is introduced in the collector region P region 9 to realize RC-IGBT structure, so as to integrate the diode in the IGBT module into the IGBT structure. The N region 24 is realized by back injection, and the doping concentration is 1x1018cm-3. 17 cm -3 ~1x1018 19 cm -3 .

[0077] Compared with embodiment 1, the introduction of the collector region N region integrates the diode in the IGBT module into the IGBT structure, and improves the module integration.

Claims

1. A self-clamp split insulated gate bipolar transistor, comprising, from bottom to top, a collector metal (10), a P-type collector region (9), an N-type electric field stop layer (8), an N-drift region (7), and an active region; the active region comprises P-type base regions (4) and P regions (20) at both ends of the upper surface of the N-drift region (7), a trench gate structure between the P-type base regions (4) and the P regions (20), a floating P region (12) between the trench gate structure and the trench emitter structure, the trench gate structure being in contact with the P-type base regions (4), the trench emitter structure being in contact with the P regions (20), and the lower surfaces of the trench gate structure, the floating P region (12), and the trench emitter structure having a deeper junction depth than the lower surfaces of the P-type base regions (4) and the P regions (20); the upper surfaces of the P-type base regions (4) are provided with P+ emitter regions (2) and N+ emitter regions (3) side by side, the N+ emitter regions (3) being located on the side close to the trench gate structure, and the upper surfaces of the P+ emitter regions (2) and the N+ emitter regions (3) having a first metal (1-1); the trench gate structure comprises a trench gate (5), a split gate (11), and a first gate oxide layer (6-1), the split gate (11) being located directly below the trench gate (5) and being separated from the trench gate (5) by the first gate oxide layer (6-1), and the trench gate (5) and the split gate (11) being separated from the P-type base regions (4), the floating P region (12), and the N-drift region (7) by the first gate oxide layer (6-1); the upper layer of the floating P region (12) has a P+ ohmic contact region (15) adjacent to the trench emitter structure; the P+ ohmic contact region (15) is in contact with the trench emitter structure, the upper surface of the P+ ohmic contact region (15) has a second metal (17), the upper surface of the floating P region (12) adjacent to the second metal (17) has a field oxide layer (13), the field oxide layer (13) is in contact with the second metal (17) but has a spacing from the trench gate structure, and a polysilicon diode is provided on the upper surface of the field oxide layer (13); the polysilicon diode comprises a polysilicon diode P+ region (18) and a polysilicon diode N+ region (19), and the polysilicon diode P+ region (18) is in contact with the second metal (17); the trench emitter structure comprises a trench emitter (14) and a second gate oxide layer (6-2), the second gate oxide layer (6-2) separating the trench emitter (14) from the floating P region (12), the P+ ohmic contact region (15), the P regions (20), and the N-drift region (7); the upper surface of the trench emitter (14) has a third metal (1-2); the upper surface of the P regions (20) has an N+ contact region (16), the N+ contact region (16) being in contact with the second gate oxide layer (6-2); and the third metal also covers the upper surface of the N+ contact region (16). The split gate (11) is electrically connected with the polysilicon diode N+ region (19), and a capacitor C is connected in series between the split gate (11) and the first metal (1-1), so that the potential of the floating P region (12) is charged by the capacitor C, and self-clamping of the split gate is realized.

2. The self-clamped punch-through IGBT of claim 1, wherein: The P region (20) and the N+ contact region (16) further have an N-BL buried layer (21), so as to form a clamping PMOS structure, and a hole extraction channel is provided in the off process, so as to improve the off extraction speed of the device while ensuring clamping of the floating P region (12).

3. The self-clamped punch-through IGBT of claim 1, wherein: The trench width of the trench emitter structure is smaller than the trench width of the trench gate structure, and the junction depth of the trench emitter structure is smaller than the junction depth of the trench gate structure, that is, the bottom of the trench emitter structure is spaced apart from the bottom of the floating P region (12), and the bottom of the trench gate structure is flush with the bottom of the floating P region (12).

4. The self-clamped punch-through IGBT of claim 1, wherein: The trench emitter (14) is split into a first trench emitter (14-1) and a second trench emitter (14-2), and the first trench emitter (14-1) and the trench gate (5) and the second trench emitter (14-2) and the split gate (11) are in a symmetrical structure.

5. The self-clamped punch-through IGBT of claim 1, wherein: The floating P region (12) has a shallow trench gate structure adjacent to the trench gate structure on the upper layer of the floating P region (12), and the width and the junction depth of the shallow trench gate structure are smaller than those of the trench gate structure; the shallow trench gate structure and the trench gate structure are spaced apart, and the gate of the trench gate structure is connected to the upper surface of the floating P region (12) between the shallow trench gate structure and the trench gate structure by a metal.

6. The self-clamped punch-through IGBT of claim 1, wherein: The N-drift region (7) further has a P column (23), and the P column (23) and the N-drift region (7) form an N / P column super-junction drift region.

7. The self-clamped punch-through IGBT of claim 1, wherein: The N-type electric field stop layer (8) is formed by hydrogen implantation, the number of hydrogen implantation is set to four times, respectively using 1 x 10 12 cm -3 -1 x 10 15 cm -3 The implantation dose is in the range of 20-200 keV, and the implantation energy is in the range of 20-200 keV.

8. The self-clamped punch-through IGBT of claim 1, wherein: The collector region P region (9) further has an N region (24), and the N region (24) is arranged side by side with the collector region P region (9), and the N region (24) is located below the P region (20).

9. A method for fabricating a self-clamp-off split-gate bipolar transistor as claimed in claim 1, wherein, The method comprises the following steps: Step 1: according to the requirements, an N-type lightly doped FZ silicon wafer with a set thickness and concentration is selected as the N-drift region (7) of the device, and a field oxide layer is grown on the surface thereof; Step 2: a floating P region (12) of the device is made by high-temperature ion implantation of P-type impurities and annealing through a photolithography process, and a pre-oxidation layer is grown on the surface of the silicon wafer; Step 3: the field oxide is etched by photolithography to form an active region; Step 4: a trench is etched by photolithography, and a sacrificial oxide is grown to remove surface contamination after etching, and then a first gate oxide layer (6-1) and a second gate oxide layer (6-2) are formed by thermal oxidation; Step 5: N-doped polysilicon is deposited, and etched by photolithography to form a trench gate structure, a trench emitter structure and a polysilicon diode substrate; Step 6: an oxidation shielding layer is first formed by thermal oxidation, the oxide layer on the surface of the trench gate structure and the upper layer polysilicon in the trench gate structure are etched by photolithography, a split gate electrode (11) is formed at the bottom of the trench gate structure, an oxidation isolation layer is formed by thermal oxidation, and then metal connection is performed to form a trench gate (5). Step 7: Photolithography, high temperature ion implantation of P-type impurities and annealing to form P-type base region (4) and P region (20) of the device; Step 8: High temperature ion implantation of N-type impurities and annealing to form N+ emitter region (3) of the device; Step 9: High temperature ion implantation of P-type impurities and annealing to form P+ emitter region (2), P+ ohmic contact region (15), P region (18) in the polysilicon diode, P+ region (16) on P region (20) of the device; Step 10: Al metal deposition to form first metal (1-1) and second metal (17) connecting P+ region (18) in the polysilicon diode and P+ ohmic contact region (15), and third metal (1-2) connecting trench emitter (14); Step 11: Flip the silicon wafer, thin the silicon wafer, high energy ion implantation of N-type impurities and ion implantation of P-type impurities and annealing to form N-type field stop layer (8) and P-type collector region (9) on the back of the silicon wafer; Step 12: Metal deposition on the back of the silicon wafer to form collector metal (10) on the lower surface of P-type collector region (9).

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