A method for manufacturing a heterojunction solar cell

Abstract

The present invention belongs to the field of solar cell technology and relates to a method for manufacturing a heterojunction solar cell. The method comprises the following steps: A) texturing a semiconductor substrate on both sides; B) forming a tunneling oxide layer on the surface of the semiconductor substrate; C) forming an N-type polysilicon layer on the tunneling oxide layer; D) forming a mask layer on the N-type polysilicon layer on the light-facing side of the semiconductor substrate; and E) performing a plasma treatment on the backlight side of the semiconductor substrate. The present invention aims to provide a method for manufacturing a heterojunction solar cell that is relatively simple and maintains the advantages of the high conductivity and low equipment investment cost of the N-type polysilicon layer while also preserving the technical characteristics of the heterojunction, such as good passivation and high open-circuit voltage.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells and relates to a method for manufacturing a heterojunction solar cell. Background Art

[0002] Heterojunction solar cells are becoming increasingly popular in the photovoltaic industry due to their advantages such as high conversion efficiency, low process temperature, high stability and low attenuation rate. They are the future development direction of high-conversion-efficiency solar cells.

[0003] Heterojunction technology has a simple process flow, high conversion efficiency and high comprehensive power generation. Its attenuation rate is much lower than that of PERC cells, and it has great development potential. However, the amorphous silicon or microcrystalline silicon plate PECVD coating equipment it uses is relatively expensive, and the overall equipment cost does not have a significant advantage over PERC cells. It is necessary to improve production technology and further reduce investment in equipment fixed assets to achieve the goal of greater market competitiveness of comprehensive investment. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for manufacturing a heterojunction solar cell, which has a relatively simple process and maintains the advantages of high conductivity and low equipment investment cost of the N-type polysilicon layer, while maintaining the technical characteristics of good passivation and high open circuit voltage of the heterojunction.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] A method for manufacturing a heterojunction solar cell comprises the following steps:

[0007] A, double-sided texturing of semiconductor substrate;

[0008] B, forming a tunnel oxide layer on the surface of the semiconductor substrate;

[0009] C, forming an N-type polysilicon layer on the tunnel oxide layer;

[0010] D. forming a mask layer on the N-type polysilicon layer on the light-facing surface of the semiconductor substrate;

[0011] E, plasma treatment is performed from the backlight side of the semiconductor substrate.

[0012] Compared with the prior art, the advantages of the present invention are:

[0013] 1. TOPCON technology, which consists of a light-side tunneling oxide layer and an N-type polysilicon layer, has the characteristics of good passivation effect and excellent conductivity, which not only ensures the open circuit voltage of the battery but also improves the battery fill factor;

[0014] 2. Plasma treatment is performed on the backlight side of the semiconductor substrate, which not only solves the problem that the tunneling oxide layer and N-type polysilicon layer formed on the velvet surface are not as passivated as those formed on the polished surface, thus ensuring the passivation effect of the battery, but also protects the backlight side of the semiconductor substrate by utilizing the N-type polysilicon layer and tunneling oxide layer on the backlight side to be removed later;

[0015] 3. The deposition of the silicon nitride mask layer on the smooth surface not only prevents the N-type polysilicon layer from being corroded by the solution in the hot alkaline solution, but also plays the role of annealing and hydrogen injection in the process, further improving the passivation effect of the N-type polysilicon layer;

[0016] 4. The process introduced by the present invention not only removes the N-type polysilicon layer and tunnel oxide layer on the backlight surface, but also naturally eliminates the wrap-around plating generated on the backlight surface during the preparation process, thus avoiding the main factors of yield fluctuation and process complexity of pure TOPCON technology;

[0017] 5. In the present invention, the photo-facing silicon nitride mask layer is not retained in the final structure, but is replaced by a transparent conductive film layer, thereby avoiding damage caused by laser ablation or high-temperature reaction of the slurry, and having good integration with the subsequent heterojunction process;

[0018] 6. The use of P-type oxygen-doped microcrystalline silicon layer ensures conductivity while widening the optical band gap, overcoming the disadvantage of severe light absorption of P-type amorphous silicon layer;

[0019] 7. Since the N-type amorphous silicon layer or N-type microcrystalline silicon layer of the traditional heterojunction is replaced by a tunnel oxide layer and an N-type polycrystalline silicon layer, the equipment investment of the plate-type PECVD is reduced, and the total cost of the heterojunction equipment can be greatly reduced.

[0020] 8. The introduction of an N-type oxygen-containing microcrystalline silicon layer on the TOPCON film layer widens the optical band gap on the front side, compensates for the problem that the TOPCON film layer easily absorbs light on the front side, and ensures the short-circuit current. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic structural diagram of an embodiment of a high-efficiency heterojunction solar cell in the present invention;

[0022] Figure 2 is a schematic cross-sectional view of a silicon wafer after double-sided texturing and cleaning in an embodiment of the present invention;

[0023] Figure 3 is a schematic cross-sectional view after a tunnel oxide layer and a first intrinsic polysilicon layer are sequentially formed on the surface of a silicon wafer in an embodiment of the present invention;

[0024] Figure 4 This is a schematic cross-sectional view of a silicon wafer according to an embodiment of the present invention after a first intrinsic polycrystalline layer is converted into an N-type polycrystalline silicon layer by high-temperature diffusion and a phosphorus silicon glass layer is formed on its surface;

[0025] Figure 5 is a schematic cross-sectional view after the phosphosilicate glass layer on the surface of the silicon wafer is removed in an embodiment of the present invention;

[0026] Figure 6 is a schematic cross-sectional view after a silicon nitride protective layer is deposited on the front side of a silicon wafer in an embodiment of the present invention;

[0027] Figure 7 is a schematic cross-sectional view after the back film layer and the pyramid velvet surface of the silicon wafer are removed by polishing and cleaning in an embodiment of the present invention;

[0028] Figure 8 is a schematic cross-sectional view after the silicon nitride protective layer on the front side of the silicon wafer is removed in an embodiment of the present invention;

[0029] Figure 9 is a schematic cross-sectional view after a second intrinsic amorphous silicon layer and a P-type oxygen-doped microcrystalline silicon layer are sequentially deposited on the back side of a silicon wafer in an embodiment of the present invention;

[0030] Figure 10 is a schematic cross-sectional view after a transparent conductive layer is deposited on the front and back sides of a silicon wafer in an embodiment of the present invention;

[0031] Figure 11 is a schematic cross-sectional view after metal gate electrodes are formed on the front and back surfaces of a silicon wafer in an embodiment of the present invention;

[0032] Figure 12 This is a flow chart of the production of a high-efficiency heterojunction solar cell in the present invention;

[0033] Figure 13 This is a schematic structural diagram of an embodiment of a high-efficiency heterojunction solar cell in the present invention;

[0034] Figure 14 It is a structural schematic diagram of an embodiment of a high-efficiency heterojunction solar cell in the present invention.

[0035] Explanation of reference numerals: 1. Silicon wafer, 2. Tunneling oxide layer, 3. First intrinsic polysilicon layer, 4. N-type polysilicon layer, 5. Phosphosilicate glass layer, 6. Silicon nitride protective layer, 7. Second intrinsic amorphous silicon layer, 8. P-type oxygen-doped microcrystalline silicon layer, 81. First non-oxygen-containing microcrystalline layer, 82. Oxygen-containing microcrystalline layer, 83. Second non-oxygen-containing microcrystalline layer, 9. Transparent conductive layer, 10. Metal gate electrode, 11a. Oxygen-containing microcrystalline layer, 11b. Non-oxygen-containing microcrystalline layer. DETAILED DESCRIPTION

[0036] A method for manufacturing a heterojunction solar cell comprises the following steps:

[0037] A, double-sided texturing of semiconductor substrate;

[0038] B, forming a tunnel oxide layer on the surface of the semiconductor substrate;

[0039] C, forming an N-type polysilicon layer on the tunnel oxide layer;

[0040] D. forming a mask layer on the N-type polysilicon layer on the light-facing surface of the semiconductor substrate;

[0041] E, plasma treatment is performed from the backlight side of the semiconductor substrate.

[0042] A method for manufacturing a heterojunction solar cell, which further comprises the following steps:

[0043] F, removing the N-type polysilicon layer and the tunnel oxide layer on the backlight surface of the semiconductor substrate;

[0044] G, remove the mask layer;

[0045] H, forming a second intrinsic amorphous silicon layer on the backlight surface of the semiconductor substrate;

[0046] I. Forming a P-type oxygen-doped microcrystalline silicon layer on the second intrinsic amorphous silicon layer.

[0047] J, forming a first conductive film layer on the N-type polycrystalline silicon layer, and forming a second conductive film layer on the P-type oxygen-doped microcrystalline silicon layer;

[0048] K, forming a first metal electrode on the first conductive film layer, and forming a second metal electrode on the second conductive film layer.

[0049] The specific method of step B is to perform double-sided texturing on the semiconductor substrate using an alkaline solution, with the texturing time being 8-40 minutes and the texturing temperature being 65° C.-85° C.

[0050] The specific method of step B is to form a tunneling oxide layer on the surface of the semiconductor substrate using a nitric acid oxidation process, an ozone oxidation process, a vacuum plasma assisted oxidation process or a thermal oxidation process.

[0051] In step B, the thermal oxidation process is oxidation by introducing oxygen, oxidation by a mixture of oxygen and nitrogen, or oxidation by using atmospheric oxygen at 550-650°C.

[0052] The specific method of step C is to form a first intrinsic polysilicon layer on the tunneling oxide layer, and use a diffusion annealing process to dope the first intrinsic polysilicon layer with phosphorus to form an N-type polysilicon layer and a phosphosilicate glass layer, and then use a fluorine-containing acidic solution to remove the phosphosilicate glass layer; or, use an LPCVD process to introduce a phosphorus source into the atmosphere for in-situ doping growth to form an N-type polysilicon layer.

[0053] In step C, the first intrinsic polysilicon layer is grown by LPCVD process, or prepared by PECVD process for amorphous silicon layer and microcrystalline silicon layer and then subjected to high temperature annealing, or prepared by PVD sputtering silicon target material for silicon thin film and then subjected to high temperature annealing.

[0054] In a preferred embodiment, the specific method of step B and step C is to place the semiconductor substrate into a tubular LPCVD device and thermally oxidize it at 550-650°C for 30 minutes to form a tunneling oxide layer; then evacuate the device and introduce the reaction gas to grow the first intrinsic polysilicon layer, the growth temperature is controlled between 500-650°C, the gas pressure is controlled between 5-10000 Pa, and the thickness of the grown first intrinsic polysilicon layer is 10-50 nm; then, a diffusion annealing process is used to dope the first intrinsic polysilicon layer with phosphorus to form an N-type polysilicon layer and a phosphosilicate glass layer, and then a fluorine-containing acidic solution is used to remove the phosphosilicate glass layer.

[0055] The diffusion annealing process in step C is to use a diffusion temperature of 780° C. to 950° C. to dope the first intrinsic polysilicon layer with boron, and the square resistance after diffusion is 20-200Ω / □.

[0056] The specific method of step D is to deposit at least one film layer of silicon nitride, silicon oxynitride, and silicon oxide on the N-type polysilicon layer by plasma chemical vapor deposition or high-temperature chemical vapor deposition technology to form a mask layer.

[0057] In one embodiment, an N-type microcrystalline silicon stack deposition step is further performed between Step C and Step D, specifically as follows: an N-type microcrystalline silicon stack is formed on the N-type polycrystalline silicon layer, wherein the N-type microcrystalline silicon stack comprises one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers. In the N-type microcrystalline stack, the total thickness of the oxygen-containing microcrystalline layers is 5-20 nm, and the total thickness of the non-oxygen-containing microcrystalline layers is 5-20 nm. The N-type microcrystalline stack comprises the non-oxygen-containing microcrystalline layers and the oxygen-containing microcrystalline layers stacked sequentially from the light-facing side to the backlight side, with the corresponding film thickness ratio being (0.5-1.5):1.

[0058] The thickness of the mask layer is 30-150 nm.

[0059] The plasma treatment in step E involves ionizing hydrogen or a gas mixture containing hydrogen, and then penetrating the surface of the semiconductor substrate from the backlight side to perform plasma treatment on the surface. The gas mixture containing hydrogen can be a mixture of hydrogen and nitrogen in any ratio, a mixture of hydrogen and ammonia in any ratio, or a mixture of hydrogen and argon in any ratio. Plasma treatment is performed on the backlight side of the semiconductor substrate primarily by utilizing the ionized hydrogen molecules to penetrate the semiconductor substrate to repair the defect state density between the interface of the semiconductor substrate facing the light side and the tunneling oxide layer, thereby improving the overall passivation level.

[0060] The specific method of step F is to remove the N-type polysilicon layer and the tunnel oxide layer using an alkaline solution for 1 to 10 minutes at a temperature of 65° C. to 85° C. The specific method of step G is to remove the mask layer using a fluorine-containing acidic solution.

[0061] The thickness of the tunneling oxide layer is 1-2 nm; the thickness of the N-type polysilicon layer is 10-50 nm; and the thickness of the P-type oxygen-doped microcrystalline silicon layer is 10-30 nm.

[0062] The specific method of step I is to form a P-type oxygen-doped microcrystalline silicon layer composed of one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers by plasma-enhanced chemical vapor deposition or hot-filament chemical vapor deposition. In a preferred embodiment, a first non-oxygen-containing microcrystalline layer, an oxygen-containing microcrystalline layer, and a second non-oxygen-containing microcrystalline layer are sequentially deposited on the second intrinsic amorphous silicon layer.

[0063] In the step I, each film layer of the P-type oxygen-doped microcrystalline silicon layer is deposited by using a process method in which the ratio of the P-type doping gas to silane is increased step by step.

[0064] The present invention is described in detail below with reference to the accompanying drawings and embodiments:

[0065] like Figures 1 to 12 Shown is a schematic diagram of an embodiment of a method for manufacturing a heterojunction solar cell provided by the present invention.

[0066] A heterojunction solar cell (such as Figure 1 The manufacturing method of FIG. 1 is as follows:

[0067] S1. Double-sided texturing is performed on the N-type single crystal silicon wafer or N-type ingot silicon wafer 1. The texturing time is 8-40 minutes and the texturing temperature is 65℃-85℃. The texturing solution is an alkaline mixed solution, which is a mixture of potassium hydroxide, texturing additives and water, wherein the mass percentage of potassium hydroxide is 1% to 5%, and the mass percentage of texturing additives is 0.5% to 1%. Double-sided polishing, using an alkaline solution to remove the wire cutting damage layer on the surface of the silicon wafer. The alkaline solution can be potassium hydroxide, sodium hydroxide or a mixed solution of the two. The reaction temperature of the alkaline solution is generally between 65℃-90℃, the reaction time is 1-15min, and the single-sided removal thickness is controlled at 1-20um. Then, standard RCA cleaning is performed to remove the alkaline solution remaining on the surface of the silicon wafer (such as Figure 2 ).

[0068] S2, oxidizing the surface of the double-sided textured silicon wafer 1, forming a tunneling oxide layer 2 and growing a first intrinsic polysilicon layer 3 (such as Figure 3), the surface oxidation can be carried out by nitric acid solution oxidation, ozone oxidation or thermal oxidation. Preferably, the present invention is thermally oxidized at 500-650°C for 30 minutes in a tubular LPCVD device to form a tunneling oxide layer 2 with a thickness of 1.2-2.0nm; the tunneling oxide layer 2 is an ultra-thin silicon oxide layer. The above-mentioned ultra-thin silicon oxide layer can also be formed by vacuum plasma assisted oxidation; the formation of the first intrinsic polysilicon layer 3 and the formation of the tunneling oxide layer 2 are carried out in the same tubular LPCVD. Preferably, after thermal oxidation, the gas is evacuated and silane and other gases are introduced to grow the first intrinsic polysilicon layer 3. The growth temperature is controlled between 550-650°C and the gas pressure is controlled between 5-10000pa. The thickness of the first intrinsic polysilicon layer 3 can be 20-300nm. The above-mentioned first intrinsic polysilicon layer can also be prepared by plasma enhanced CVD (PECVD) deposition combined with subsequent high-temperature annealing. The first intrinsic polysilicon layer can also be prepared by sputtering a silicon target through physical vapor deposition to form a thin film, and then forming polysilicon through subsequent high-temperature annealing.

[0069] S3, the silicon wafer on which the polysilicon film has been oxidized and grown is subjected to high temperature diffusion, so that the first intrinsic polysilicon layer 3 is phosphorus-doped to form an N-type polysilicon layer 4 (such as Figure 4 The diffusion temperature is 780°C-950°C, and the sheet resistance of the diffused silicon wafer is 20-300Ω / □. N-type doping of the polysilicon can also be performed in situ (i.e., by introducing a phosphorus-containing gas into the atmosphere used to prepare the polysilicon). This in-situ doping avoids subsequent high-temperature diffusion of the PSG glass using furnace tubes.

[0070] S4, remove the phosphorus silicon glass layer 5 (phosphoric acid silicon oxide glass layer, PSG) formed on the surface of the silicon wafer 1 after high temperature diffusion (such as Figure 5 The cleaning solution used for removal is a chemical solution containing fluoride ions (such as diluted hydrofluoric acid or BOE solution, etc.). If a hydrofluoric acid solution is used, the mass percentage of HF acid is 0.5%-8%. The silicon wafer is treated in the HF acid solution for 1-6 minutes at a temperature of 20°C-30°C.

[0071] S5, depositing a silicon nitride protective layer 6 (i.e., a mask layer) on the front surface of the silicon wafer 1 (e.g., Figure 6 ), the silicon nitride protective layer in the present invention has a strong property of resisting alkaline solution corrosion and can resist alkaline corrosion in the texturing solution. Preferably, the thickness of the silicon nitride is The silicon nitride layer can be formed by using a thin film forming method such as sputtering or CVD. Preferably, in this embodiment, the silicon nitride layer is formed by deposition using a PECVD method.

[0072] S6. Plasma treatment is performed on the back side of the silicon wafer 1 using a tubular PECVD device. A mixed gas of hydrogen and nitrogen is introduced into the furnace tube, wherein the molar content of hydrogen is 10% to 100%. The treatment temperature is 200°C-400°C and the treatment time is 15min-60min.

[0073] S7, remove the N-type polysilicon layer and tunnel oxide layer (such as Figure 7 ), the solution used to remove the N-type polysilicon layer and the tunnel oxide layer is an alkaline solution. Since there is a silicon nitride protective layer 6 on the front side of the silicon wafer, the N-type polysilicon layer and the pyramid velvet structure on the front side of the silicon wafer are still maintained in the solution, while the N-type polysilicon layer and the tunnel oxide layer on the back side of the silicon wafer will be removed. Preferably, in this embodiment, the pyramid velvet on the back side of the silicon wafer is also removed by extending the polishing time, forming a flat surface morphology. The alkaline solution is potassium hydroxide, sodium hydroxide, or a mixture of potassium hydroxide and sodium hydroxide. Preferably, a solution of potassium hydroxide and water is used, wherein the mass percentage of potassium hydroxide is 10% to 30%. The polishing time is 1 to 10 minutes, and the polishing temperature is 65°C to 85°C.

[0074] S8, remove the silicon nitride protective layer 6 (such as Figure 8 ), the solution used to remove the protective layer is a chemical solution containing fluoride ions (such as diluted hydrofluoric acid or BOE solution), and the removal time is determined according to the corrosion resistance of silicon nitride;

[0075] S9, sequentially depositing a second intrinsic amorphous silicon layer 7 and a P-type oxygen-doped microcrystalline silicon layer 8 (such as Figure 9 ); the second intrinsic amorphous silicon layer is deposited by PECVD (plasma enhanced chemical vapor deposition) method, the deposition temperature is 150-300 ° C, a mixed gas of silane, hydrogen or carbon dioxide is introduced into the reaction chamber, wherein the molar content of silane is 5% to 100%, and the thickness of the second intrinsic amorphous silicon layer is 3-11nm; the P-type oxygen-doped microcrystalline silicon layer is deposited by PECVD deposition method, passing silane, hydrogen, carbon dioxide and diborane doping gas for deposition, and the deposition thickness is 5-25nm.

[0076] S10, depositing a transparent conductive layer 9 (i.e., a first conductive film layer and a second conductive film layer) on the front and back sides of the silicon wafer 1 (e.g., Figure 10The transparent conductive layer 9 is generally a transparent conductive oxide layer. It can be an indium oxide film layer doped with one or more different metals (such as tin, tungsten, titanium, etc.), such as ITO, IWO, or ITiO; or a zinc oxide film layer doped with one or more different metals (such as aluminum, indium, gallium, etc.), such as AZO, GZO, IZO, or IGZO. ITO (i.e., a tin-doped indium oxide film layer) is preferably used. The ITO layer is generally deposited using PVD (physical vapor deposition). The film has a transmittance of 88%-99%, a sheet resistance of 30-400Ω / □, and a film thickness of 15-150nm.

[0077] S11, forming metal gate electrodes 10 (i.e., first metal electrodes and second metal electrodes) on the front and back sides of the silicon wafer 1 (e.g., Figure 11 ), to facilitate subsequent IV testing.

[0078] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention.

[0079]

[0080] The above table shows the process parameters of each stage of P-type oxygen-doped microcrystalline silicon layer prepared by PECVD. The prepared P-type oxygen-doped microcrystalline silicon layer contains three stages: P1, P2, and P3, corresponding to the formation of Figure 13 The first non-oxygen-containing microcrystalline layer 81, the oxygen-containing microcrystalline layer 82, and the second non-oxygen-containing microcrystalline layer 83 are shown. In a preferred embodiment, each film layer of the P-type oxygen-doped microcrystalline silicon layer is deposited using a process method in which the ratio of the P-type doping gas to silane is gradually increased from 1:10 to 1:1.

[0081]

[0082] The above table compares various electrical parameters of the solar cell of the present invention without plasma treatment and with plasma treatment.

[0083] Example 2:

[0084] This embodiment differs from Embodiment 1 only in that an N-type microcrystalline silicon stack deposition step is further performed between steps S4 and S5, specifically as follows: an N-type microcrystalline silicon stack is deposited on the above-mentioned N-type polycrystalline silicon layer 4, and the N-type microcrystalline silicon stack is composed of an oxygen-containing microcrystalline layer 11a and a non-oxygen-containing microcrystalline layer 11b deposited in sequence by a PECVD deposition method, and each film layer of the N-type microcrystalline stack is deposited by a process method of gradually increasing the ratio of N-type doping gas to silane, and the ratio of N-type doping gas to silane increases from 1:10 to 1:1; the corresponding film thickness ratio of the oxygen-containing microcrystalline layer 11a and the non-oxygen-containing microcrystalline layer 11b is 1:(0.5-1.5). The oxygen-containing microcrystalline layer 11a is deposited directly on the N-type polycrystalline silicon layer 4, without the need to deposit an oxygen-containing microcrystalline silicon layer on the intrinsic amorphous silicon layer. In order to quickly crystallize the oxygen-containing microcrystalline layer, the N-type polycrystalline silicon layer 4 has a high degree of crystallinity, which enables the oxygen-containing microcrystalline layer 11a to crystallize quickly, with a high film formation rate and good conductive properties. The solar cell finally produced in this embodiment is as follows: Figure 14 shown.

[0085] Obviously, those skilled in the art may make various changes and modifications to the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the invention fall within the scope of the claims and their equivalents, the invention is intended to include such modifications and variations.

Claims

1. A method for manufacturing a heterojunction solar cell, characterized in that: It includes the following steps, A, double-sided texturing of semiconductor substrate; B, forming a tunnel oxide layer on both sides of the semiconductor substrate; C, forming an N-type polysilicon layer on the tunnel oxide layer; D. forming a mask layer on the N-type polysilicon layer on the light-facing surface of the semiconductor substrate; E, plasma treatment from the backlight side of the semiconductor substrate; F, removing the N-type polysilicon layer and the tunnel oxide layer on the backlight surface of the semiconductor substrate; G, remove the mask layer; H, forming a second intrinsic amorphous silicon layer on the backlight surface of the semiconductor substrate; I, forming a P-type oxygen-doped microcrystalline silicon layer on the second intrinsic amorphous silicon layer; The plasma treatment in step E is to ionize hydrogen or a mixed gas containing hydrogen, and perform plasma treatment on the surface of the semiconductor substrate by penetrating from the backlight side of the semiconductor substrate, so as to utilize the ionized hydrogen molecules to penetrate the semiconductor substrate to repair the defect state density between the interface of the semiconductor substrate facing the light side and the tunneling oxide layer.

2. The method for manufacturing a heterojunction solar cell according to claim 1, wherein: The specific method of step B is to form a tunneling oxide layer on the surface of the semiconductor substrate using a nitric acid oxidation process, an ozone oxidation process, a vacuum plasma assisted oxidation process or a thermal oxidation process.

3. The method for manufacturing a heterojunction solar cell according to claim 1, wherein: The specific method of step C is to form a first intrinsic polysilicon layer on the tunnel oxide layer, dope the first intrinsic polysilicon layer with phosphorus using a diffusion annealing process to form an N-type polysilicon layer and a phosphosilicate glass layer, and then remove the phosphosilicate glass layer using a fluorine-containing acidic solution; Alternatively, an LPCVD process is used to introduce a phosphorus source into the atmosphere for in-situ doping growth to form an N-type polysilicon layer.

4. The method for manufacturing a heterojunction solar cell according to claim 1, wherein: The specific method of step D is to deposit at least one film layer of silicon nitride, silicon oxynitride, and silicon oxide on the N-type polysilicon layer by plasma chemical vapor deposition or high-temperature chemical vapor deposition technology to form a mask layer.

5. The method for manufacturing a heterojunction solar cell according to claim 4, wherein: The thickness of the mask layer is 30-150 nm.

6. The method for manufacturing a heterojunction solar cell according to claim 1, wherein: The specific method of step G is to remove the mask layer by using a fluorine-containing acidic solution.

7. The method for manufacturing a heterojunction solar cell according to claim 1, wherein: The specific method of step I is to use plasma enhanced chemical vapor deposition technology or hot wire chemical vapor deposition technology to form a P-type oxygen-doped microcrystalline silicon layer composed of one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers stacked together.

8. The method for manufacturing a heterojunction solar cell according to claim 1, wherein: The thickness of the tunneling oxide layer is 1-2 nm; the thickness of the N-type polysilicon layer is 10-50 nm; and the thickness of the P-type oxygen-doped microcrystalline silicon layer is 10-30 nm.

9. The method for manufacturing a heterojunction solar cell according to claim 1, wherein: The mixed gas containing hydrogen is a mixed gas of hydrogen and nitrogen in any proportion, a mixed gas of hydrogen and ammonia in any proportion, or a mixed gas of hydrogen and argon in any proportion.

10. The method for manufacturing a heterojunction solar cell according to any one of claims 1 to 9, characterized in that: An N-type microcrystalline silicon stack deposition step is also performed between step C and step D. The specific method is to form an N-type microcrystalline silicon stack on the N-type polycrystalline silicon layer, and the N-type microcrystalline silicon stack includes one or more oxygen-containing microcrystalline layers and one or more non-oxygen-containing microcrystalline layers.

11. The method for manufacturing a heterojunction solar cell according to claim 10, wherein: The N-type microcrystalline stack includes a non-oxygen-containing microcrystalline layer and an oxygen-containing microcrystalline layer stacked in sequence from the light-facing side to the backlight side, and the corresponding film thickness ratio is (0.5-1.5):1.

Images