Ferroelectric switching device, method of preparation, method of control and three-dimensional memory

Abstract

A ferroelectric switching device can generate an in-plane electric field in a ferroelectric layer by applying a voltage on the ferroelectric layer through a first electrode and a second electrode, change the direction of the in-plane electric field by changing the direction of the voltage, control the first crack and the second crack to separate alternatively, realize the electrical connection and electrical insulation of the first conductive layer by closing and separating the first crack, realize the electrical connection and electrical insulation of the second conductive layer by closing and opening the second crack, and thus realize the function of the ferroelectric switching device. The ferroelectric switching device has higher speed, lower energy consumption and smaller chip area, and the manufacturing process is simple, compatible with Fe-NAND process, low in cost and high in economic benefit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a ferroelectric switching device, a preparation method, a control method and a three-dimensional memory. BACKGROUND

[0002] With the development of microelectronic technology, the feature size of transistors on integrated circuits is approaching the physical limit. If the device size is further reduced, there will be a serious leakage problem. Because of the mechanical "on" and "off" characteristics, the function device based on electro-mechanical coupling effectively avoids the leakage problem in the "off" state. At the same time, compared with traditional semiconductor devices, micro-electro-mechanical devices also have the advantages of large on-off ratio, low power consumption, simple structure and process, etc., which has great development potential and application value in developing high-density, low-power, high-stability memory, transistors and logic devices. SUMMARY

[0003] The technical problem to be solved by the embodiments of the present disclosure is to provide a ferroelectric switching device, a preparation method, a control method and a three-dimensional memory.

[0004] The embodiments of the present disclosure provide a ferroelectric switching device, which comprises: a ferroelectric layer; a first electrode and a second electrode, which are arranged on the ferroelectric layer along a first direction, the first electrode comprises a first bridge, and the second electrode comprises a second bridge; an interlayer insulating layer, which covers at least the first bridge and the second bridge; a first conductive layer, which is arranged on the interlayer insulating layer and corresponds to the first bridge; a second conductive layer, which is arranged on the interlayer insulating layer and corresponds to the second bridge; a first signal delivery end and a second signal delivery end, which are arranged on the first conductive layer; a third signal delivery end and a fourth signal delivery end, which are arranged on the second conductive layer; a first crack, which extends from the ferroelectric layer along a direction perpendicular to the ferroelectric layer and penetrates the first bridge, the interlayer insulating layer, and the first conductive layer between the first signal delivery end and the second signal delivery end; and a second crack, which extends from the ferroelectric layer along a direction perpendicular to the ferroelectric layer and penetrates the second bridge, the interlayer insulating layer, and the second conductive layer between the third signal delivery end and the fourth signal delivery end.

[0005] In an embodiment, the first crack does not penetrate or penetrates the ferroelectric layer, and / or the second crack penetrates or does not penetrate the ferroelectric layer.

[0006] In an embodiment, the first electrode and the second electrode are symmetrically arranged with a first gap as the center.

[0007] In an embodiment, the first electrode further comprises a first body, the first body is divided into two parts, each of which is connected to one end of the first bridge, and the width of the first body in the first direction is greater than the width of the first bridge; the second electrode further comprises a second body, the second body is divided into two parts, each of which is connected to one end of the second bridge, and the width of the second body in the first direction is greater than the width of the second bridge.

[0008] In an embodiment, the width of the first gap between the first body and the second body in the first direction is greater than the width of the first gap between the first bridge and the second bridge.

[0009] In an embodiment, the interlayer insulating layer covers part of the surface of the first body and the second body, a first conductive terminal is arranged on the surface of the first body at one end of the first bridge which is not covered by the interlayer insulating layer, and a second conductive terminal is arranged on the surface of the second body at one end of the second bridge which is not covered by the interlayer insulating layer.

[0010] In an embodiment, the interlayer insulating layer further covers the ferroelectric layer region between the first electrode and the second electrode.

[0011] In an embodiment, the interlayer insulating layer comprises: a first insulating layer arranged at least on the first bridge, the first conductive layer being arranged on the first insulating layer; a second insulating layer arranged at least on the second bridge, the second conductive layer being arranged on the second insulating layer, the first insulating layer and the second insulating layer being independent of each other.

[0012] In an embodiment, the first conductive layer and the second conductive layer are arranged along the first direction, and the first conductive layer and the second conductive layer both extend along a second direction; the first signal conveying terminal and the second signal conveying terminal are arranged along the second direction, the first crack extends along the first direction and penetrates the first conductive layer; the third signal conveying terminal and the fourth signal conveying terminal are arranged along the second direction, the second crack extends along the first direction and penetrates the second conductive layer; the first direction intersects the second direction.

[0013] In an embodiment, in the area of the orthographic projection of the first bridge on the ferroelectric layer, the orthographic projection of the first bridge covers the orthographic projection of the first conductive layer, and / or, in the area of the orthographic projection of the second bridge on the ferroelectric layer, the orthographic projection of the second bridge covers the orthographic projection of the second conductive layer.

[0014] In an embodiment, the material of the first electrode is the same as the material of the first conductive layer, and / or the material of the second electrode is the same as the material of the second conductive layer, and / or the material of the first electrode is the same as the material of the second electrode.

[0015] In an embodiment, one of the signal delivery terminals on the first conductive layer is electrically connected with one of the signal delivery terminals on the second conductive layer, to form a signal output terminal of the ferroelectric switching device.

[0016] The embodiments of the present disclosure provide a preparation method of a ferroelectric switching device, which comprises: providing a substrate; sequentially forming, on the surface of the substrate, a ferroelectric layer, a first electrode, a second electrode, an interlayer insulating layer, a first conductive layer, a second conductive layer, and a first signal delivery terminal, a second signal delivery terminal, a third signal delivery terminal, and a fourth signal delivery terminal, the first electrode comprising a first bridge, the second electrode comprising a second bridge, the first conductive layer corresponding to at least the first bridge, the second conductive layer corresponding to at least the second bridge, the first signal delivery terminal and the second signal delivery terminal being arranged on the first conductive layer, and the third signal delivery terminal and the fourth signal delivery terminal being arranged on the second conductive layer; forming a first crack and a second crack, the first crack extending from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrating the first bridge, the interlayer insulating layer, and the first conductive layer between the first signal delivery terminal and the second signal delivery terminal, and the second crack extending from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrating the second bridge, the interlayer insulating layer, and the second conductive layer between the third signal delivery terminal and the fourth signal delivery terminal.

[0017] In an embodiment, the first crack does not penetrate or penetrates the ferroelectric layer, and / or the second crack penetrates or does not penetrate the ferroelectric layer.

[0018] In an embodiment, the method for forming the first crack and the second crack comprises: applying a polarization voltage to the ferroelectric layer, so that the ferroelectric domain polarization direction of the ferroelectric layer is the same as the direction of the polarization voltage, to form a set ferroelectric domain polarization direction; applying a first flipping voltage to the ferroelectric layer through the first electrode and the second electrode, to form the first crack; and applying a second flipping voltage to the ferroelectric layer through the first electrode and the second electrode, to form the second crack, the second flipping voltage being opposite in polarity to the first flipping voltage.

[0019] The embodiment of the present disclosure further provides a control method of the ferroelectric switching device, comprising: applying a first voltage to the ferroelectric layer through the first electrode and the second electrode, controlling the separation of the first crack and the closure of the second crack, realizing the electrical insulation of the first signal transmission end and the second signal transmission end and the electrical conduction of the third signal transmission end and the fourth signal transmission end; applying a second voltage to the ferroelectric layer through the first electrode and the second electrode, controlling the closure of the first crack and the separation of the second crack, realizing the electrical conduction of the first signal transmission end and the second signal transmission end and the electrical insulation of the third signal transmission end and the fourth signal transmission end, wherein the first voltage and the second voltage are opposite in polarity.

[0020] In an embodiment, the first voltage or the second voltage is applied to the ferroelectric layer through the first electrode and the second electrode under the control of an input signal, and the logic circuit function is realized by setting the voltage levels of the first signal transmission end and the third signal transmission end.

[0021] The embodiment of the present disclosure further provides a three-dimensional memory comprising the ferroelectric switching device.

[0022] The ferroelectric switching device provided by the embodiment of the present disclosure can apply a voltage to the ferroelectric layer through the first electrode and the second electrode, so as to generate an in-plane electric field in the ferroelectric layer, change the direction of the in-plane electric field by changing the direction of the voltage, control the separation of the first crack and the second crack, realize the electrical connection and electrical insulation of the first conductive layer through the closure and separation of the first crack, realize the electrical connection and electrical insulation of the second conductive layer through the closure and separation of the second crack, and thus realize the function of the ferroelectric switching device.

[0023] Compared with the MOSFET complementary switching device, the ferroelectric switching device has higher speed, lower energy consumption and smaller chip area, and the manufacturing process is simple, compatible with the Fe-NAND process, low in cost and high in economic benefit. Moreover, the ferroelectric switching device based on the ferroelectric-crack has a sudden switching behavior and a high ON / OFF current ratio. In addition, the first conductive layer and the second conductive layer serve as a conductive channel, and at the first crack and the second crack, the contact area of the metal contact interface (fracture surface) of the two separated parts of the first conductive layer and the second conductive layer is large, so that the contact resistance is low and the signal transmission speed is fast. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 and Figure 2 is a top view schematic diagram of the ferroelectric switching device provided by the embodiment of the present disclosure, wherein, Figure 1 is a schematic diagram of the separation of the first crack and the closure of the second crack, Figure 2 is a schematic diagram of the closure of the first crack and the separation of the second crack;

[0025] Figure 3 It is along Figure 1 A schematic diagram of the cross-section of line B-B' shown;

[0026] Figure 4 It is along Figure 1 A schematic diagram of the cross-section of line C-C' shown;

[0027] Figure 5 It is along Figure 1 A schematic diagram of the cross-section of line D-D' shown;

[0028] Figure 6 It is along Figure 2 A schematic diagram of the cross-section of line B-B' shown;

[0029] Figure 7 It is along Figure 2 A schematic diagram of the cross-section of line C-C' shown;

[0030] Figure 8 It is along Figure 2 A schematic diagram of the cross-section of line D-D' shown;

[0031] Figure 9A This is a top view schematic diagram of a ferroelectric switching device provided in another embodiment of this disclosure;

[0032] Figure 9B It is along Figure 9A A schematic diagram of the cross-section of line D-D' shown;

[0033] Figure 10A This is a schematic diagram of a triangular cyclic voltage;

[0034] Figure 10B This is a schematic diagram of pulse cyclic voltage;

[0035] Figure 11 This is a schematic diagram of the steps in the fabrication method of the ferroelectric switching device provided in the embodiments of this disclosure;

[0036] Figures 12A-12D This is a schematic diagram of the device structure formed by the main steps of the fabrication method of the ferroelectric switching device provided in the embodiments of the present invention;

[0037] Figure 13 This is a schematic diagram of a logic circuit composed of a ferroelectric switching device provided in an embodiment of this disclosure;

[0038] Figure 14A It is to utilize Figure 13 The truth table for the logic circuit shown to implement the buffer function;

[0039] Figure 14B It is to utilize Figure 13 The truth table for the logic circuit shown implements the NOT gate function.

[0040] Figure 14C is a truth table of the logic circuit shown in Figure 13

[0041] Figure 14D is a truth table of the logic circuit shown in Figure 13 DETAILED DESCRIPTION

[0042] In order to make the purposes, technical means and effects of the embodiments of the present disclosure clearer, further elucidation will be made to the embodiments of the present disclosure with reference to the drawings. It should be understood that the specific embodiments described herein merely illustrate the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and are not used to limit the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0043] Figure 1 and Figure 2 is a top view of a ferroelectric switching device provided by the embodiments of the present disclosure, Figure 3 is a cross-sectional view along the line B-B’ shown in Figure 1 Figure 4 is a cross-sectional view along the line C-C’ shown in Figure 1 Figure 5 is a cross-sectional view along the line D-D’ shown in Figure 1 Figure 6 is a cross-sectional view along the line B-B’ shown in Figure 2 Figure 7 is a cross-sectional view along the line C-C’ shown in Figure 2 Figure 8 is a cross-sectional view along the line D-D’ shown in Figure 2 Figure 1 is a schematic view of the first crack A1 being separated and the second crack A2 being closed, Figure 2 is a schematic view of the first crack A1 being closed and the second crack A2 being separated.

[0044] Referring to Figures 1-8 , the ferroelectric switching device comprises a ferroelectric layer 10, a first electrode 20, a second electrode 30, an interlayer insulating layer 40, a first conductive layer 50, a second conductive layer 60, a first signal conveying end 70 and a second signal conveying end 71, a third signal conveying end 80 and a fourth signal conveying end 81. Figure 1 and Figure 2 In the ferroelectric switching device, the first electrode 20 and the second electrode 30 are shielded by the interlayer insulating layer 40, and are drawn by dashed lines.

[0045] The first electrode 20 and the second electrode 30 are arranged on the ferroelectric layer 10, and are arranged along a first direction (for example, the X direction shown in the drawings).​​​​​​​​Figure 1 The first electrode 20 and the second electrode 30 are used to apply a voltage to the ferroelectric layer 10. The first electrode 20 includes a first bridge 21, the second electrode 30 includes a second bridge 31, and the interlayer insulating layer 40 covers at least the first bridge 21 and the second bridge 31. The first conductive layer 50 is disposed on the interlayer insulating layer 40 and corresponds to the first bridge 21. The second conductive layer 60 is disposed on the interlayer insulating layer 40 and corresponds to the second bridge 31. The first signal transmission end 70 and the second signal transmission end 71 are disposed on the first conductive layer 50. The third signal transmission end 80 and the fourth signal transmission end 81 are disposed on the second conductive layer 60.

[0046] The first crack Al extends from the ferroelectric layer 10 in a direction perpendicular to the ferroelectric layer 10 (e.g., a Z direction) and penetrates the first bridge 21, the interlayer insulating layer 40, and the first conductive layer 50 between the first signal transmission end 70 and the second signal transmission end 71. The first conductive layer 50 is divided into two independent parts by the first crack Al, and the first signal transmission end 70 and the second signal transmission end 71 are respectively disposed on the two independent parts of the first conductive layer 50 divided by the first crack Al. Figure 3 The second crack A2 extends from the ferroelectric layer 10 in a direction perpendicular to the ferroelectric layer 10 (e.g., a Z direction) and penetrates the second bridge 31, the interlayer insulating layer 40, and the second conductive layer 60 between the third signal transmission end 80 and the fourth signal transmission end 81. The second conductive layer 60 is divided into two independent parts by the second crack A2, and the third signal transmission end 80 and the fourth signal transmission end 81 are respectively disposed on the two independent parts of the second conductive layer 60 divided by the second crack A2.

[0047] The second crack A2 extends from the ferroelectric layer 10 in a direction perpendicular to the ferroelectric layer 10 (e.g., a Z direction) and penetrates the second bridge 31, the interlayer insulating layer 40, and the second conductive layer 60 between the third signal transmission end 80 and the fourth signal transmission end 81. The second conductive layer 60 is divided into two independent parts by the second crack A2, and the third signal transmission end 80 and the fourth signal transmission end 81 are respectively disposed on the two independent parts of the second conductive layer 60 divided by the second crack A2. Figure 7 The second crack A2 extends from the ferroelectric layer 10 in a direction perpendicular to the ferroelectric layer 10 (e.g., a Z direction) and penetrates the second bridge 31, the interlayer insulating layer 40, and the second conductive layer 60 between the third signal transmission end 80 and the fourth signal transmission end 81. The second conductive layer 60 is divided into two independent parts by the second crack A2, and the third signal transmission end 80 and the fourth signal transmission end 81 are respectively disposed on the two independent parts of the second conductive layer 60 divided by the second crack A2.

[0048] The direction of the voltage applied to the ferroelectric layer 10 can be controlled to selectively separate the first crack Al and the second crack A2. The first crack Al and the second crack A2 are selectively separated, meaning that at the same time, the first crack Al and the second crack A2 cannot be separated at the same time, and only one of them can be separated. Similarly, at the same time, the first crack Al and the second crack A2 cannot be closed at the same time, and only one of them can be closed.

[0049] The first crack A1 may or may not penetrate the ferroelectric layer 10, and / or the second crack A2 may or may not penetrate the ferroelectric layer 10. Specifically, in one embodiment of this disclosure, at least one of the first crack A1 and the second crack A2 may penetrate the ferroelectric layer 10, wherein the direction of penetration may include the Z direction or the Y direction. In some embodiments of this disclosure, neither the first crack A1 nor the second crack A2 may penetrate the ferroelectric layer 10, and the direction of penetration may include the Z direction or the Y direction. In particular, neither the first crack A1 nor the second crack A2 penetrates the ferroelectric layer 10 in the Y direction.

[0050] In the direction perpendicular to the ferroelectric layer 10 (e.g.) Figure 3 In the Z-direction, the first electrode 20 and the second electrode 30 are independently located above the ferroelectric layer 10, that is, the first electrode 20 and the second electrode 30 are independently disposed on the upper surface of the ferroelectric layer 10. The first electrode 20 and the second electrode 30 can be metal electrodes, such as Pt, Au, Cu, or Ag. In this embodiment, the ferroelectric layer 10 is disposed on a substrate 100, the first electrode 20 and the second electrode 30 are disposed on the upper surface of the ferroelectric layer 10, and the substrate 100 is used to support the ferroelectric switching device.

[0051] The first electrode 20 and the second electrode 30 are independent of each other, meaning that the first electrode 20 and the second electrode 30 are electrically insulated from each other. In one embodiment of this disclosure, the first electrode 20 and the second electrode 30 are sequentially disposed on the surface of the ferroelectric layer 10 along the first direction, and the first electrode 20 and the second electrode 30 do not contact each other, but are spaced apart.

[0052] In some embodiments, the first electrode 20 and the second electrode 30 are symmetrically arranged with a first gap as the center. The first gap refers to the gap between the first electrode 20 and the second electrode 30. In this embodiment, the first bridge 21 is disposed on the side of the first electrode 20 facing the second electrode, and the second bridge 31 is disposed on the side of the second electrode 30 facing the first electrode 20.

[0053] Furthermore, in this embodiment, the first electrode 20 further includes a first body 22, which is divided into two parts and respectively connected to both ends of the first bridge 21 in the first direction (e.g., Figure 1 In the Y direction (as shown), the width W22 of the first body 22 is greater than the width W21 of the first bridge 21. The second electrode 30 also includes a second body 32, which is divided into two parts and connected to both ends of the second bridge 31 respectively, in the first direction (as shown). Figure 1The width W32 of the second body 32 is greater than the width W31 of the second bridge 31 in the Y direction. Figure 1 When the first bridge 21 is the region with the smallest width of the first electrode 20 and the second bridge 31 is the region with the smallest width of the second electrode 30, the electric field formed at the first bridge 21 and the second bridge 31 is the strongest when a voltage is applied to the ferroelectric layer through the first electrode 20 and the second electrode 30. Therefore, the first crack Al and the second crack A2 exist in the regions corresponding to the first bridge 21 and the second bridge 31.

[0054] Further, in the embodiment, the width of the first gap G1 between the first body 22 and the second body 32 is greater than the width of the first gap G2 between the first bridge 21 and the second bridge 32 in the Y direction, i.e., the first bridge 21 protrudes in a direction away from the first body 22 and the second bridge 31 protrudes in a direction away from the second body 32. For example, the first electrode 20 is in the shape of a positive U and the second electrode 30 is in the shape of an inverted U. The first electrode 20 and the second electrode 30 are symmetrically arranged with the first gap as the center. Figure 1

[0055] The materials of the first electrode 20 and the second electrode 30 can be intermetallic alloy materials, such as MnPt or FePt. The intermetallic alloy materials have small ductility, which enables the first crack Al and the second crack A2 to penetrate the first electrode 20 and the second electrode 30, and further extend and penetrate the first conductive layer 50 and the second conductive layer 60.

[0056] The interlayer insulating layer 40 covers at least the first bridge 21 and the second bridge 31, and functions to electrically isolate the first bridge 21 from the first conductive layer 50 and the second bridge 31 from the second conductive layer 60. In the embodiment, the interlayer insulating layer 40 also covers part of the surfaces of the first body 22 and the second body 32.

[0057] ​Further, in the present embodiment, a first conductive terminal 23 is provided on the surface of the first body 22 at one end of the first bridge 21 and not covered by the interlayer insulating layer 40, and the first conductive terminal 23 is connected to a voltage process circuit, which applies a potential to the first electrode 20 through the first conductive terminal 23. A second conductive terminal 33 is provided on the surface of the second body 32 at one end of the second bridge 31 and not covered by the interlayer insulating layer 40, and the second conductive terminal 33 is connected to a voltage process circuit, which applies a potential to the second electrode 30 through the second conductive terminal 33. In other embodiments of the present disclosure, the first conductive terminal 23 and the second conductive terminal 33 can not be provided, and the voltage process circuit can be directly connected to the surfaces of the first electrode 20 and the second electrode 30 not covered by the interlayer insulating layer 40.

[0058] The interlayer insulating layer 40 includes, but is not limited to, an oxide layer, a nitride layer, a high-K dielectric layer, etc. For example, the oxide layer can be an aluminum oxide layer. When the ferroelectric layer 10 forms the first crack Al and the second crack A2, the first crack Al and the second crack A2 also extend through the interlayer insulating layer 40 to extend and penetrate the first conductive layer 50 and the second conductive layer 60.

[0059] Further, in some embodiments, the interlayer insulating layer 40 also covers the region of the ferroelectric layer 10 between the first electrode 20 and the second electrode 30, i.e., covers the exposed surface of the ferroelectric layer 10 between the first electrode 20 and the second electrode 30, to further ensure the electrical isolation between the first electrode 20 and the second electrode 30. Further, in the present embodiment, the interlayer insulating layer 40 covers all exposed surfaces of the ferroelectric layer 10.

[0060] The first conductive layer 50 is provided on the interlayer insulating layer 40 and corresponds to the first bridge 21, i.e., the first conductive layer 50 is formed on the interlayer insulating layer 40 and corresponds to the region where the first bridge 21 is located. When the ferroelectric layer 10 forms the first crack Al in the region corresponding to the first bridge 21, the first crack Al extends and penetrates the first conductive layer 50 to divide the first conductive layer 50 into two parts, which are electrically isolated.

[0061] The second conductive layer 60 is provided on the interlayer insulating layer 40 and corresponds to the second bridge 31, i.e., the second conductive layer 60 is formed on the interlayer insulating layer 40 and corresponds to the region where the second bridge 31 is located. When the ferroelectric layer 10 forms the second crack A2 in the region corresponding to the second bridge 31, the second crack A2 extends and penetrates the second conductive layer 60 to divide the second conductive layer 60 into two parts, which are electrically isolated.

[0062] The first conductive layer 50 and the second conductive layer 60 are arranged along a first direction (e.g., Y direction) and both of them extend along a second direction (e.g., X direction). The first crack Al extends along the first direction (e.g., Y direction) and penetrates the first conductive layer 50. The second crack A2 extends along the first direction (e.g., Y direction) and penetrates the second conductive layer 60. The first direction intersects the second direction, for example, in the embodiment, the first direction (e.g., Y direction) is perpendicular to the second direction (e.g., X direction). Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1

[0063] Further, the material of the first conductive layer 50 and the second conductive layer 60 can be intermetallic alloy material, for example, MnPt or FePt. The ductility of the intermetallic alloy material is small, which can make the ferroelectric layer 10 form the first crack Al and the second crack A2, and the first crack Al and the second crack A2 can extend and penetrate the first conductive layer 50 and the second conductive layer 60.

[0064] Further, in some embodiments, the material of the first electrode 20 is the same as the material of the first conductive layer 50, and / or the material of the second electrode 30 is the same as the material of the second conductive layer 60, and / or the material of the first electrode 20 is the same as the material of the second electrode 30.

[0065] ​​​​​​Specifically, in this embodiment, the materials of the first conductive layer 50 and the second conductive layer 60 are the same as those of the first electrode 20 and the second electrode 30. Since the first conductive layer 50, the second conductive layer 60, and the first electrode 20 and the second electrode 30 have the same ductility, it is convenient to select an appropriate voltage to further ensure that the first crack A1 and the second crack A2 can penetrate the first conductive layer 50 and the second conductive layer 60. In other embodiments of this disclosure, the material of the first conductive layer 50 may be different from the material of the first electrode 20 but have similar ductility to further avoid the situation where the first crack A1 only penetrates the first electrode 20 but not the first conductive layer 50; similarly, the material of the second conductive layer 60 may be different from the material of the second electrode 30 but have similar ductility to further avoid the situation where the second crack A2 only penetrates the second electrode 30 but not the second conductive layer 60. In another embodiment of this disclosure, the materials of the first conductive layer 50, the second conductive layer 60, the first electrode 20, and the second electrode 30 are all the same to reduce differences in voltage control and avoid yield losses in ferroelectric switching devices.

[0066] Furthermore, in this embodiment, in order to ensure that the first crack A1 can divide the first conductive layer 50 into two completely broken parts, in the direction perpendicular to the ferroelectric layer 10 (e.g., Figure 3 In the Z-direction, in the orthogonal projection region of the first bridge 21 onto the ferroelectric layer 10, the orthogonal projection of the first bridge 21 covers the orthogonal projection of the first conductive layer 50. That is, in the first direction (e.g., Z-direction), Figure 1 In the Y direction (as shown), the edge of the orthographic projection of the first conductive layer 50 onto the ferroelectric layer 10 lies within the area of ​​the orthographic projection of the first bridge 21 onto the ferroelectric layer 10. If the edge of the orthographic projection of the first conductive layer 50 onto the ferroelectric layer 10 lies outside the area of ​​the orthographic projection of the first bridge 21 onto the ferroelectric layer 10, then the first crack A1 may only penetrate part of the first conductive layer 50 without dividing the first conductive layer 50 into two completely broken parts, thus failing to achieve electrical isolation between the first signal transmission terminal 70 and the second signal transmission terminal 71.

[0067] Furthermore, in this embodiment, in order to ensure that the second crack A2 can divide the second conductive layer 60 into two completely broken parts, in the direction perpendicular to the ferroelectric layer 10 (e.g., Figure 3 In the Z-direction, in the orthographic projection region of the second bridge 31 onto the ferroelectric layer 10, the orthographic projection of the second bridge 31 overlaps the orthographic projection of the second conductive layer 60, i.e., in the first direction (e.g., Z-direction), Figure 1In the second direction (e.g., the X direction) perpendicular to the ferroelectric layer 10, the second signal transmission end 71 is located on the side of the first bridge 21 opposite to the first signal transmission end 70, and does not overlap with the first bridge 21 in the direction (e.g., the Z direction) perpendicular to the ferroelectric layer 10, so as to avoid the first crack Al formed in the corresponding region of the first bridge 21 from being formed below the first signal transmission end 70 or the second signal transmission end 71, thereby affecting the electrical insulation of the first signal transmission end 70 and the second signal transmission end 71. The first crack Al extends in the first direction (e.g., the Y direction), so as to separate the first conductive layer 50 into two independent parts, and the first signal transmission end 71 and the second signal transmission end 72 are arranged on the two independent parts of the first conductive layer 50. In this embodiment, the first signal transmission end 70 is a first input end of the electrical signal of the ferroelectric switching device, and the second signal transmission end 71 is a first output end of the electrical signal of the ferroelectric switching device. In another embodiment, the first signal transmission end 70 is a first output end of the electrical signal of the ferroelectric switching device, and the second signal transmission end 71 is a first input end of the electrical signal of the ferroelectric switching device.

[0068] The third signal transmission end 80 and the fourth signal transmission end 81 are arranged in the second direction (e.g., the X direction) perpendicular to the ferroelectric layer 10. In this embodiment, the third signal transmission end 80 and the fourth signal transmission end 81 are located on the two sides of the second bridge 31, and do not overlap with the second bridge 31 in the direction (e.g., the Z direction) perpendicular to the ferroelectric layer 10, so as to avoid the second crack A2 formed in the corresponding region of the second bridge 31 from being formed below the third signal transmission end 80 or the fourth signal transmission end 81, thereby affecting the electrical insulation of the third signal transmission end 80 and the fourth signal transmission end 81. The second crack A2 extends in the first direction (e.g., the Y direction), so as to separate the second conductive layer 60 into two independent parts, and the third signal transmission end 80 and the fourth signal transmission end 81 are arranged on the two independent parts of the second conductive layer 60. In this embodiment, the third signal transmission end 80 is a first input end of the electrical signal of the ferroelectric switching device, and the fourth signal transmission end 81 is a first output end of the electrical signal of the ferroelectric switching device. In another embodiment, the third signal transmission end 80 is a first output end of the electrical signal of the ferroelectric switching device, and the fourth signal transmission end 81 is a first input end of the electrical signal of the ferroelectric switching device. Figure 1 Figure 3 The third signal transmission end 80 and the fourth signal transmission end 81 are arranged in the second direction (e.g., the X direction) perpendicular to the ferroelectric layer 10. In this embodiment, the third signal transmission end 80 and the fourth signal transmission end 81 are located on the two sides of the second bridge 31, and do not overlap with the second bridge 31 in the direction (e.g., the Z direction) perpendicular to the ferroelectric layer 10, so as to avoid the second crack A2 formed in the corresponding region of the second bridge 31 from being formed below the third signal transmission end 80 or the fourth signal transmission end 81, thereby affecting the electrical insulation of the third signal transmission end 80 and the fourth signal transmission end 81. The second crack A2 extends in the first direction (e.g., the Y direction), so as to separate the second conductive layer 60 into two independent parts, and the third signal transmission end 80 and the fourth signal transmission end 81 are arranged on the two independent parts of the second conductive layer 60. In this embodiment, the third signal transmission end 80 is a first input end of the electrical signal of the ferroelectric switching device, and the fourth signal transmission end 81 is a first output end of the electrical signal of the ferroelectric switching device. In another embodiment, the third signal transmission end 80 is a first output end of the electrical signal of the ferroelectric switching device, and the fourth signal transmission end 81 is a first input end of the electrical signal of the ferroelectric switching device. Figure 1 The third signal transmission end 80 and the fourth signal transmission end 81 are arranged in the second direction (e.g., the X direction) perpendicular to the ferroelectric layer 10. In this embodiment, the third signal transmission end 80 and the fourth signal transmission end 81 are located on the two sides of the second bridge 31, and do not overlap with the second bridge 31 in the direction (e.g., the Z direction) perpendicular to the ferroelectric layer 10, so as to avoid the second crack A2 formed in the corresponding region of the second bridge 31 from being formed below the third signal transmission end 80 or the fourth signal transmission end 81, thereby affecting the electrical insulation of the third signal transmission end 80 and the fourth signal transmission end 81. The second crack A2 extends in the first direction (e.g., the Y direction), so as to separate the second conductive layer 60 into two independent parts, and the third signal transmission end 80 and the fourth signal transmission end 81 are arranged on the two independent parts of the second conductive layer 60. In this embodiment, the third signal transmission end 80 is a first input end of the electrical signal of the ferroelectric switching device, and the fourth signal transmission end 81 is a first output end of the electrical signal of the ferroelectric switching device. In another embodiment, the third signal transmission end 80 is a first output end of the electrical signal of the ferroelectric switching device, and the fourth signal transmission end 81 is a first input end of the electrical signal of the ferroelectric switching device.

[0069] Figure 1 The third signal transmission end 80 and the fourth signal transmission end 81 are arranged in the second direction (e.g., the X direction) perpendicular to the ferroelectric layer 10. In this embodiment, the third signal transmission end 80 and the fourth signal transmission end 81 are located on the two sides of the second bridge 31, and do not overlap with the second bridge 31 in the direction (e.g., the Z direction) perpendicular to the ferroelectric layer 10, so as to avoid the second crack A2 formed in the corresponding region of the second bridge 31 from being formed below the third signal transmission end 80 or the fourth signal transmission end 81, thereby affecting the electrical insulation of the third signal transmission end 80 and the fourth signal transmission end 81. The second crack A2 extends in the first direction (e.g., the Y direction), so as to separate the second conductive layer 60 into two independent parts, and the third signal transmission end 80 and the fourth signal transmission end 81 are arranged on the two independent parts of the second conductive layer 60. In this embodiment, the third signal transmission end 80 is a first input end of the electrical signal of the ferroelectric switching device, and the fourth signal transmission end 81 is a first output end of the electrical signal of the ferroelectric switching device. In another embodiment, the third signal transmission end 80 is a first output end of the electrical signal of the ferroelectric switching device, and the fourth signal transmission end 81 is a first input end of the electrical signal of the ferroelectric switching device. Figure 4 Figure 1 ​​​The second conductive layer 60 is divided into two independent parts by the third signal transmission end 80 and the fourth signal transmission end 81, which are arranged on the two independent parts of the second conductive layer 60. In this embodiment, the third signal transmission end 80 is the second input end of the electric signal of the ferroelectric switching device, and the fourth signal transmission end 81 is the second output end of the electric signal of the ferroelectric switching device. In another embodiment, the third signal transmission end 80 is the second output end of the electric signal of the ferroelectric switching device, and the fourth signal transmission end 81 is the second input end of the electric signal of the ferroelectric switching device.

[0070] The first signal transmission end 70 and the second signal transmission end 71 are independent of each other, and there is no direct electrical connection between them. The third signal transmission end 80 and the fourth signal transmission end 81 are independent of each other, and there is no direct electrical connection between them.

[0071] Further, in another embodiment, one of the signal transmission ends on the first conductive layer 50 and one of the signal transmission ends on the second conductive layer 60 are electrically connected to form a signal output end of the ferroelectric switching device.

[0072] Further, in order to simplify the layout design, the signal transmission end on the first conductive layer 50 and the signal transmission end on the second conductive layer 60, which constitute the signal output end, are arranged on the same side of the first electrode 20 and the second electrode 30. For example, the second signal transmission end 71 on the first conductive layer 50 and the fourth signal transmission end 81 on the second conductive layer 60 are arranged on the same side of the first electrode 20 and the second electrode 30, and the second signal transmission end 71 and the fourth signal transmission end 81 are electrically connected to form a signal output end of the ferroelectric switching device.

[0073] When the first crack Al corresponding to the first electrode 20 is closed and the second crack A2 corresponding to the second electrode 30 is separated, the electric signal required by the outside to be transmitted through the ferroelectric switching device is input through the first signal transmission end 70, conducted through the first conductive layer 50, and then output through the second signal transmission end 71. When the first crack Al corresponding to the first electrode 20 is separated and the second crack A2 corresponding to the second electrode 30 is closed, the electric signal required by the outside to be transmitted through the ferroelectric switching device is input through the third signal transmission end 80, conducted through the second conductive layer 60, and then output through the fourth signal transmission end 81. Due to the electrical isolation effect of the interlayer insulating layer 40, the electric signal required by the outside to be transmitted through the ferroelectric switching device will not be transmitted to the first electrode 20 and the second electrode 30, thereby avoiding disturbing the normal operation of the ferroelectric switching device.

[0074] Furthermore, the first signal transmission terminal 70, the second signal transmission terminal 71, the third signal transmission terminal 80, and the fourth signal transmission terminal 81 can be metal terminals, and their materials include, but are not limited to, Pt, Au, Cu, or Ag. In this embodiment, the materials of the first conductive terminal 23 and the second conductive terminal 33 are the same as the materials of the first signal transmission terminal 70, the second signal transmission terminal 71, the third signal transmission terminal 80, and the fourth signal transmission terminal 81, thereby allowing them to be prepared in the same step and reducing the number of process steps.

[0075] In the above embodiments, the interlayer insulating layer 40 is a continuous layer covering the first electrode 20, the second electrode 30, and the ferroelectric layer 10. However, in other embodiments of this disclosure, the interlayer insulating layer may also be a discontinuous layer. For example, please refer to... Figure 9A and Figure 9B ,in, Figure 9A This is a top view schematic diagram of a ferroelectric switching device provided in another embodiment of this disclosure. Figure 9B It is along Figure 9A The schematic diagram of the cross-section of the D-D' line is shown. In this embodiment, the interlayer insulation layer includes a first insulation layer 40A and a second insulation layer 40B. The first insulation layer 40A and the second insulation layer 40B are independent of each other, that is, the first insulation layer 40A and the second insulation layer 40B are not connected to each other. The first insulation layer 40A is disposed on the first bridge 21, and the first conductive layer 50 is disposed on the first insulation layer 40A. The first insulation layer 40A is used to electrically isolate the first electrode 20 from the first conductive layer 50 and the first signal transmission terminal 70 and the second signal transmission terminal 71. The second insulation layer 40B is disposed on the second bridge 31, and the second conductive layer 60 is disposed on the second insulation layer 40B. The second insulation layer 40B is used to electrically isolate the second electrode 30 from the second conductive layer 60 and the third signal transmission terminal 80 and the fourth signal transmission terminal 81.

[0076] This disclosure also provides a control method for a ferroelectric switching device. The control method includes: applying a first voltage to the ferroelectric layer via the first and second electrodes to control the closure of the first crack and the separation of the second crack, thereby achieving electrical conduction between the first and second signal transmission terminals and electrical insulation between the third and fourth signal transmission terminals; applying a second voltage to the ferroelectric layer via the first and second electrodes to control the separation of the first crack and the closure of the second crack, thereby achieving electrical insulation between the first and second signal transmission terminals and electrical conduction between the third and fourth signal transmission terminals, wherein the first voltage and the second voltage have opposite polarities.

[0077] For example, please refer toFigure 1 、 Figures 3-5 When a first voltage U1 is applied to the ferroelectric layer 10 via the first electrode 20 and the second electrode 30, the first crack Al changes from the closed state to the separated state, and the second crack A2 changes from the separated state to the closed state, so that the first signal transmission terminal 70 and the second signal transmission terminal 71 are electrically insulated, the second input terminal 80 and the fourth signal transmission terminal 81 are electrically connected, and the signal received by the third signal transmission terminal 80 is output via the fourth signal transmission terminal 81.

[0078] Please refer to Figure 2 、 Figures 6-8 When a second voltage U2 is applied to the ferroelectric layer via the first electrode 20 and the second electrode 30, the first crack Al changes from the separated state to the closed state, and the second crack A2 changes from the closed state to the separated state, so that the first signal transmission terminal 70 and the second signal transmission terminal 71 are electrically connected, the second input terminal 80 and the fourth signal transmission terminal 81 are electrically insulated, and the signal received by the first signal transmission terminal 70 is output via the second signal transmission terminal 71.

[0079] The first voltage U1 and the second voltage U2 are opposite in polarity, that is, the first voltage U1 is a positive voltage, and the second voltage U2 is a negative voltage, or the first voltage U1 is a negative voltage, and the second voltage U2 is a positive voltage. For example, in the embodiment, the first voltage U1 is a positive voltage in the direction from the first electrode 20 to the second electrode 30, and the second voltage U2 is a negative voltage in the direction from the first electrode 20 to the second electrode 30, while in other embodiments, the first voltage U1 is a negative voltage in the direction from the first electrode 20 to the second electrode 30, and the second voltage U2 is a positive voltage in the direction from the first electrode 20 to the second electrode 30.

[0080] For the ferroelectric layer 10, its ferroelectric domains have polarization directions. When the direction of the electric field formed by the voltage applied to the ferroelectric layer 10 is opposite to the polarization direction of the ferroelectric domains, the ferroelectric domains in the ferroelectric layer 10 will flip. Due to the pinning effect of defects and dopants in the ferroelectric layer 10 on the domain walls, stress will be generated on the ferroelectric domain walls. Cracks will separate at the stress concentration points. When the direction of the electric field formed by the voltage applied to the ferroelectric layer 10 is the same as the polarization direction of the ferroelectric domains, the stress will dissipate and the cracks will close. Therefore, in this embodiment, the ferroelectric switching device applies a voltage to the ferroelectric layer 10 via the first electrode 20 and the second electrode 30. This voltage creates an in-plane electric field within the ferroelectric layer 10. Below the first electrode 20 and the second electrode 30, the directions of the electric field components perpendicular to the ferroelectric layer 10 are opposite, and the polarization direction of the ferroelectric domains in the ferroelectric layer 10 is the same as the direction of one of the electric field components. This causes cracks in the ferroelectric layer region where the electric field component direction is opposite to the ferroelectric domain polarization direction to separate, while cracks in the ferroelectric layer region where the electric field component direction is the same as the ferroelectric domain polarization direction close. Furthermore, the inventors have found that when a voltage is applied to the ferroelectric layer, cracks appear in the region with the strongest electric field strength. Therefore, this embodiment achieves the function of a ferroelectric switching device by changing the polarity of the voltage applied to the ferroelectric layer, allowing cracks in different regions of the ferroelectric layer to separate selectively. The shape of the first and second electrodes is used to control the electric field strength in different regions of the first and second electrodes, thereby controlling the crack location.

[0081] For example, such as Figure 5 As shown, the polarization direction D of the ferroelectric domains in the ferroelectric layer 10 points towards the upper surface of the ferroelectric layer 10 (Z direction in Figure 5). When a first voltage U1 is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30, the first bridge 21 and the second bridge 31 are the regions with the largest electric field strength. Therefore, below the first bridge 21, the electric field component E1 in the Z direction of the in-plane electric field E1 formed by the first voltage U1 within the ferroelectric layer 10 is... Z1 Pointing to the lower surface of the ferroelectric layer 10, below the second bridge 31, the electric field component E1 of the in-plane electric field E1 in the Z direction. Z2 The electric field component E1 points towards the upper surface of the ferroelectric layer 10. Z1 The direction is opposite to the polarization direction of the ferroelectric domains in ferroelectric layer 10, and the electric field component E1 Z2 If the direction is the same as the polarization direction D of the ferroelectric domains of the ferroelectric layer 10, then the first crack A1 changes from a closed state to a separated state, and the second crack A2 changes from a separated state to a closed state.

[0082] For example, such as Figure 8 As shown, the polarization direction D of the ferroelectric domains in the ferroelectric layer 10 points towards the upper surface of the ferroelectric layer 10 (e.g., ...). Figure 8In the Z-direction, when the voltage applied to the ferroelectric layer 10 via the first electrode 20 and the second electrode 30 changes from a first voltage U1 to a second voltage U2 with opposite polarity, the in-plane electric field E2 formed by the second voltage U2 within the ferroelectric layer 10 below the first bridge 21 will have an electric field component E2 in the Z-direction. Z1 Pointing to the upper surface of the ferroelectric layer 10, below the second bridge 31, the electric field component E2 of the in-plane electric field E2 in the Z direction. Z2 The electric field component E2 points towards the lower surface of ferroelectric layer 10. Z1 The direction is the same as the polarization direction D of the ferroelectric domains of ferroelectric layer 10, and the electric field component E2 Z2 If the direction of the crack A1 is opposite to the polarization direction D of the ferroelectric domains of the ferroelectric layer 10, then the first crack A1 changes from a separated state to a closed state, and the second crack A2 changes from a closed state to a separated state.

[0083] It is understood that in other embodiments of this disclosure, the polarization direction of the ferroelectric domains of the ferroelectric layer 10 may also point to the lower surface of the ferroelectric layer 10, in which case the separation state and the closure state of the first crack A1 and the second crack A2 are interchanged.

[0084] The first crack A1 can originate from the ferroelectric layer 10 along a direction perpendicular to the ferroelectric layer 10 (e.g., Figure 3 The conductive layer 50 extends and penetrates the first bridge 21, the interlayer insulation layer 40, and the first signal transmission end 70 and the second signal transmission end 71 in the Z-direction, and is divided into two independent parts by the first crack A1. When the first crack A1 is in a separated state, the two parts of the first conductive layer 50 are separated and not connected, thereby achieving electrical insulation between the first signal transmission end 70 and the second signal transmission end 71; when the first crack A1 is in a closed state, the two parts of the first conductive layer 50 are in contact and connected, thereby achieving electrical conduction between the first signal transmission end 70 and the second signal transmission end 71.

[0085] The second crack A2 originates from the ferroelectric layer 10 along a direction perpendicular to the ferroelectric layer 10 (e.g., Figure 7The second crack A2 extends in the Z direction and penetrates the second bridge 31, the interlayer insulating layer 40, and the second conductive layer 60 between the third signal transmission end 80 and the fourth signal transmission end 81, and the second conductive layer 60 is divided into two independent parts by the second crack A2. When the second crack A2 is in the open state, the two parts of the second conductive layer 60 are separated and not connected, the third signal transmission end 80 and the fourth signal transmission end 81 cannot be electrically connected through the second conductive layer 60, thereby breaking the signal transmission between the third signal transmission end 80 and the fourth signal transmission end 81; when the second crack A2 is in the closed state, the two parts of the second conductive layer 60 are in contact and connected, the third signal transmission end 80 and the fourth signal transmission end 81 can be electrically connected through the second conductive layer 60, thereby enabling the signal transmission between the third signal transmission end 80 and the fourth signal transmission end 81.

[0086] It should be noted that after the ferroelectric layer 10 generates a crack in the region corresponding to the first bridge 21 or the second bridge 31, it will not generate a second crack in the corresponding region due to stress release, and therefore, there will be no case of multiple cracks in the region corresponding to the same electrode.

[0087] In some embodiments, a cyclic voltage can be applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30 to control the opening and closing of the first crack and the second crack, for example, a triangular cyclic voltage and a pulse voltage. Figure 10A is a schematic diagram of a triangular cyclic voltage, wherein when the positive voltage of the triangular cyclic voltage reaches a value, for example, the peak value U 峰 , the ferroelectric domain is flipped, stress is generated, the first crack A1 is opened, and the second crack A2 is closed; when the negative voltage of the triangular cyclic voltage reaches a value, for example, the valley value U 谷 , the ferroelectric domain is flipped again, the first crack A1 is closed, and the second crack A2 is opened. Figure 10B is a schematic diagram of a pulse cyclic voltage, which is a periodically reversed pulse, when the positive pulse voltage U 正 reaches a value, the ferroelectric domain is flipped, stress is generated, the first crack A1 is opened, and the second crack A2 is closed; when the negative pulse voltage U 负 reaches a value, the ferroelectric domain is flipped again, the first crack A1 is closed, and the second crack A2 is opened.

[0088] The ferroelectric switching device control method provided by the embodiments of the present disclosure utilizes the alternative separation of the first crack and the second crack to realize the function of the ferroelectric switching device, has higher speed, lower energy consumption and smaller chip area than the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) complementary switch, and has simple manufacturing process, is compatible with the Fe-NAND flash process, has low cost and great economic benefits. In addition, the ferroelectric switching device based on the ferroelectric-nano crack has a sudden switching behavior and a high ON / OFF current ratio. In addition, the first conductive layer 50 and the second conductive layer 60 are full layers as conductive channels, and at the first crack and the second crack, the contact area of the metal contact interface (fracture surface) of the two separated parts of the first conductive layer 50 and the second conductive layer 60 is large, so that the contact resistance is low and the signal transmission speed is fast.

[0089] The embodiments of the present disclosure also provide a preparation method of the ferroelectric switching device. Figure 11 is a schematic diagram of the steps of the preparation method of the ferroelectric switching device provided by the embodiments of the present disclosure, please refer to Figure 11 , the preparation method comprises: step S201, providing a substrate; step S202, sequentially forming a ferroelectric layer, a first electrode, a second electrode, an interlayer insulating layer, a first conductive layer, a second conductive layer, and a first signal transmission end, a second signal transmission end, a third signal transmission end and a fourth signal transmission end on the surface of the substrate, the first electrode comprises a first bridge, the second electrode comprises a second bridge, the first conductive layer corresponds to at least the first bridge, the second conductive layer corresponds to at least the second bridge, the first signal transmission end and the second signal transmission end are arranged on the first conductive layer, and the third signal transmission end and the fourth signal transmission end are arranged on the second conductive layer; step S203, forming a first crack and a second crack, the first crack extends from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrates the first bridge, the interlayer insulating layer, and the first conductive layer between the first signal transmission end and the second signal transmission end; the second crack extends from the ferroelectric layer in a direction perpendicular to the ferroelectric layer and penetrates the second bridge, the interlayer insulating layer, and the second conductive layer between the third signal transmission end and the fourth signal transmission end.

[0090] Figures 12A-12D is a schematic diagram of the device structure formed by the main steps of the preparation method of the ferroelectric switching device provided by the embodiments of the present disclosure.

[0091] Please refer to steps S201 and Figure 12A , a substrate 100 is provided.

[0092] The substrate 100 can be a Si substrate, a Ge substrate, a SiGe substrate, a SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like. In the present embodiment, the substrate 100 is preferably a Si substrate for supporting a device structure thereon.

[0093] Referring to steps S202 and Figure 12B A ferroelectric layer 10, a first electrode 20, a second electrode 30, an interlayer insulating layer 40, a first conductive layer 50, a second conductive layer 60, and a first signal transport end 70, a second signal transport end 71, a third signal transport end 80, and a fourth signal transport end 81 are sequentially formed on the surface of the substrate 100. The first electrode 20 includes a first bridge 21, the second electrode 30 includes a second bridge 31, the first conductive layer 50 corresponds to at least the first bridge 21, the second conductive layer 60 corresponds to at least the second bridge 31, the first signal transport end 70 and the second signal transport end 71 are disposed on the first conductive layer 50, and the third signal transport end 80 and the fourth signal transport end 81 are disposed on the second conductive layer 60.

[0094] In an embodiment, a chemical vapor deposition, an atomic layer deposition, a pulsed laser deposition, a molecular beam epitaxy, or the like can be used to form a ferroelectric material layer on the surface of the substrate 100, and a photolithography and an etching, or the like can be used to pattern the ferroelectric material layer to form the ferroelectric layer 10. In the present embodiment, the material of the ferroelectric layer 10 includes HfZrOx, where Ox represents an oxide with a varying stoichiometry, which can be suitable for a hafnium-based complementary metal oxide semiconductor (CMOS) compatible ferroelectric NAND (Fe-NAND) flash memory to simplify a manufacturing process. In other embodiments of the present disclosure, the material of the ferroelectric layer 10 can also include one or more of lead magnesium niobate-lead titanate (PMN-PT), lead zirconate titanate (PZT), lead indium niobate-lead titanate (PIN-PT), or lead magnesium niobate-lead zirconate titanate-lead titanate (PMN-PZT-PT), BaTiO3 (BTO), or the like.

[0095] In an embodiment, a chemical vapor deposition, an atomic layer deposition, a pulsed laser deposition, a molecular beam epitaxy, or the like can be used to form an electrode material layer on the surface of the ferroelectric layer 10, and a photolithography and an etching, or the like can be used to pattern the electrode material layer to form the first electrode 20 and the second electrode 30. The material of the first electrode 20 and the second electrode 30 can be an intermetallic alloy material, such as MnPt or FePt.

[0096] In an embodiment, a layer of interlayer insulating material is formed on the first electrode 20 and the second electrode 30 by chemical vapor deposition, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, and the like, and the layer of interlayer insulating material is patterned by photolithography and etching to form the interlayer insulating layer 40. In this embodiment, the interlayer insulating layer 40 can cover not only the first electrode 20 and the second electrode 30, but also the exposed surface of the ferroelectric layer 10. The interlayer insulating layer 40 includes, but is not limited to, an oxide layer, a nitride layer, a high-K dielectric layer, and the like. For example, the oxide layer can be an aluminum oxide layer.

[0097] In an embodiment, a layer of conductive material is formed on the interlayer insulating layer 40 by chemical vapor deposition, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, and the like, and the layer of conductive material is patterned by photolithography and etching to form the first conductive layer 50 and the second conductive layer 60. The material of the first conductive layer 50 and the second conductive layer 60 can be an intermetallic alloy material, such as MnPt or FePt. The ductility of the first conductive layer 50 and the second conductive layer 60 is the same as or similar to that of the first electrode 20 and the second electrode 30. Further, in this embodiment, the material of the first conductive layer 50 and the second conductive layer 60 is the same as that of the first electrode 20 and the second electrode 30, and in other embodiments of the present disclosure, the material of the first conductive layer 50 and the second conductive layer 60 can be different from that of the first electrode 20 and the second electrode 30 but have similar ductility.

[0098] A layer of signal transmission material is formed on the first conductive layer 50 and the second conductive layer 60 by chemical vapor deposition, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, and the like, and the layer of signal transmission material is patterned by photolithography and etching to form the first signal delivery end 70, the second signal delivery end 71, the third signal delivery end 80, and the fourth signal delivery end 81. The first signal delivery end 70 and the second signal delivery end 71 are independent of each other and not directly connected, and the third signal delivery end 80 and the fourth signal delivery end 81 are independent of each other and not directly connected. In this step, the first conductive terminal 23 and the second conductive terminal 33 can be formed at the same time. The first conductive terminal 23 is disposed on the first electrode 20, and the second conductive terminal 33 is disposed on the second electrode 30.

[0099] Please refer to steps S203, Figure 12C and Figure 12D to form the first crack A1 and the second crack A2.

[0100] The first crack A1 extends from the ferroelectric layer 10 in a direction perpendicular to the ferroelectric layer 10 (e.g., the direction of the arrow A1 in FIG. 2A), and the second crack A2 extends from the ferroelectric layer 10 in a direction perpendicular to the ferroelectric layer 10 (e.g., the direction of the arrow A2 in FIG. 2A). Figure 3The first crack Al extends in a direction perpendicular to the ferroelectric layer 10 (e.g., the Z direction) and penetrates the first bridge 21, the interlayer insulating layer 40, and the first conductive layer 50 between the first signal transport end 70 and the second signal transport end 71, and the first conductive layer 50 is divided into two independent parts by the first crack Al, and the first signal transport end 70 and the second signal transport end 71 are respectively arranged on the two independent parts of the first conductive layer 50 divided by the first crack Al.

[0101] The second crack A2 extends in a direction perpendicular to the ferroelectric layer 10 (e.g., the Z direction) and penetrates the second bridge 31, the interlayer insulating layer 40, and the second conductive layer 60 between the third signal transport end 80 and the fourth signal transport end 81, and the second conductive layer 60 is divided into two independent parts by the second crack A2, and the third signal transport end 80 and the fourth signal transport end 81 are respectively arranged on the two independent parts of the second conductive layer 60 divided by the second crack A2. Figure 3

[0102] In an embodiment of the present disclosure, at least one of the first crack Al and the second crack A2 can penetrate the ferroelectric layer 10, wherein the penetrating direction can include the Z direction or the Y direction. In some embodiments of the present disclosure, neither the first crack Al nor the second crack A2 can penetrate the ferroelectric layer 10, and the penetrating direction can include the Z direction or the Y direction, and in particular, neither the first crack Al nor the second crack A2 can penetrate the ferroelectric layer 10 in the Y direction.

[0103] For the ferroelectric layer 10, the ferroelectric domains thereof have a polarization direction, and when the direction of the electric field formed by the voltage applied on the ferroelectric layer 10 is opposite to the polarization direction of the ferroelectric domains, the ferroelectric domains in the ferroelectric layer 10 will flip, and due to the pinning effect of defects and dopants in the ferroelectric layer 10 on the domain wall, stress will be generated at the ferroelectric domain wall, and cracks will be formed at the stress concentration. Therefore, the present disclosure further provides a method for forming the cracks. The method for forming the cracks includes the following steps:

[0104] ​A polarization voltage is applied to the ferroelectric layer 10 to make the polarization direction of the ferroelectric domains in the ferroelectric layer 10 the same as the direction of the polarization voltage, thus forming the set polarization direction D of the ferroelectric domains. The polarization voltage forms a vertical electric field in the ferroelectric layer 10 to make the polarization direction of the ferroelectric domains in the ferroelectric layer 10 the same as the direction of the electric field. For the ferroelectric layer 10, when no polarization voltage is applied, i.e. no external electric field, the ferroelectric domains are randomly distributed in the ferroelectric layer 10, and when a polarization voltage is applied, i.e. an external electric field, the ferroelectric domains along the direction of the electric field grow, the ferroelectric domains along the opposite direction of the electric field disappear, and the ferroelectric domains along other directions turn to the direction of the electric field, thus forming the ferroelectric domains with the same direction as the electric field, i.e. the set polarization direction D of the ferroelectric domains. In some embodiments, the electric field formed by the polarization voltage has a strength greater than the coercive field of the ferroelectric domains, to further ensure that the ferroelectric domains with the same direction as the electric field can be formed.

[0105] Please refer to Figure 12C , a first flipping voltage U11 is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30 to form the first crack A1. Please refer to Figure 12D , a second flipping voltage U22 is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30 to form the second crack A2, and the second flipping voltage U11 and the first flipping voltage U22 are opposite in polarity.

[0106] In the embodiments of the present disclosure, please continue to refer to Figure 12C and Figure 5 , a first flipping voltage U11 is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30, and the first flipping voltage U11 forms an in-plane electric field E1 in the ferroelectric layer 10. Under the first electrode 20 and the second electrode 20, the direction of the electric field component of the in-plane electric field along the vertical direction of the ferroelectric layer 10 is exactly opposite, for example, the direction of the electric field component E1 Z1 of the in-plane electric field along the vertical direction of the ferroelectric layer 10 under the first electrode 20 is opposite to the direction of the electric field component E1 Z2 of the in-plane electric field along the vertical direction of the ferroelectric layer 10 under the second electrode 30. The polarization direction of the ferroelectric domains in the ferroelectric layer 10 is the same as the direction of one of the electric field components and opposite to the direction of the other electric field component, for example, the polarization direction of the ferroelectric domains in the ferroelectric layer 10 (in the same direction as the Z direction in the figure) is the same as the direction of the electric field component E1 Z2 of the in-plane electric field along the vertical direction of the ferroelectric layer 10 under the second electrode 30, and opposite to the direction of the electric field component E1 Z1If the direction of the electric field component E2 Z1 is opposite to the direction of the electric field component E2 Z2 , the ferroelectric domains in the ferroelectric layer 10 will be reversed under the second electrode 30, stress will be generated at the ferroelectric domain wall, and the electric field intensity is the strongest at the region corresponding to the second bridge 31, so the second crack A2 will be formed at this region.

[0107] In the embodiments of the present disclosure, please continue to refer to Figure 12D and Figure 8 , a second flipping voltage U22 is applied to the ferroelectric layer 10 through the first electrode 20 and the second electrode 30, and the second flipping voltage U22 forms an in-plane electric field in the ferroelectric layer 10. The direction of the electric field component E2 Z1 along the vertical direction of the ferroelectric layer 10 under the first electrode 20 is opposite to the direction of the electric field component E2 Z2 along the vertical direction of the ferroelectric layer 10 under the second electrode 30. The polarization direction of the ferroelectric domains in the ferroelectric layer 10 is the same as the direction of one of the electric field components and opposite to the direction of the other electric field component, for example, the polarization direction of the ferroelectric domains in the ferroelectric layer 10 (in the same direction as the Z direction in the figure) is the same as the direction of the electric field component E2 Z1 along the vertical direction of the ferroelectric layer 10 under the first electrode 20 and opposite to the direction of the electric field component E2 Z2 along the vertical direction of the ferroelectric layer 10 under the second electrode 30. The ferroelectric domains in the ferroelectric layer 10 will be reversed under the second electrode 30, stress will be generated at the ferroelectric domain wall, and the electric field intensity is the strongest at the region corresponding to the second bridge 31, so the second crack A2 will be formed at this region. The first electrode 20 is affected by the change of the electric field direction, and the stress in the ferroelectric layer is dissipated, so the first crack A1 is closed.

[0108] In the above example, the polarization direction D of the ferroelectric domains of the ferroelectric layer 10 points to the lower surface of the ferroelectric layer 10. It can be understood that in other embodiments of the present disclosure, the polarization direction D of the ferroelectric domains of the ferroelectric layer 10 can also point to the lower surface of the ferroelectric layer 10, and the formation order of the first crack A1 and the second crack A2 is interchanged.

[0109] The preparation method provided by the embodiments of the present disclosure can prepare a ferroelectric switching device with complementary switching function, and the manufacturing process is simple, compatible with Fe-NAND process, low in cost, and high in economic benefit.

[0110] The embodiments of the present disclosure also provide a three-dimensional memory. The three-dimensional memory comprises the ferroelectric switching device as described above. The ferroelectric switching device can replace the CMOS complementary switching device in the three-dimensional memory. The application of the ferroelectric switching device in the three-dimensional memory is exemplified below.

[0111] In some embodiments of the present disclosure, the three-dimensional memory utilizes the ferroelectric switching device to realize the logic circuit function.

[0112] For example, Figure 13 is a schematic diagram of the logic circuit composed of the ferroelectric switching device provided by an embodiment of the present disclosure, please refer to Figures 1-2 , the level corresponding to the voltage applied on the first electrode 20 and the second electrode 30 is input as an input signal from the input end IN, the second signal delivery end 71 and the fourth signal delivery end 81 are collectively used as the output end OUT, the first signal delivery end 70 is used as the first control signal input end D1, and the third signal delivery end 80 is used as the second control signal input end D2, so that the logic circuit function can be realized by setting the levels of the first control signal input end D1 and the second control signal input end D2.

[0113] The voltage supply circuit is controlled by the input signal required to be input to the logic circuit to apply the first voltage and the second voltage on the first electrode 20 and the second electrode 30, realizing the alternative separation of the first crack A1 and the second crack A2, so as to realize the function of the logic circuit. For example, when the input signal required to be input to the logic circuit is at a low level, the voltage supply circuit is controlled by the input signal required to be input to the logic circuit to apply the first voltage on the first electrode 20 and the second electrode 30, when the input signal required to be input to the logic circuit is at a high level, the voltage supply circuit is controlled by the input signal required to be input to the logic circuit to apply the second voltage on the first electrode 20 and the second electrode 30, realizing the alternative separation of the first crack A1 and the second crack A2; or, when the input signal required to be input to the logic circuit is at a high level, the voltage supply circuit is controlled by the input signal required to be input to the logic circuit to apply the first voltage on the first electrode 20 and the second electrode 30, when the input signal required to be input to the logic circuit is at a low level, the voltage supply circuit is controlled by the input signal required to be input to the logic circuit to apply the second voltage on the first electrode 20 and the second electrode 30, realizing the alternative separation of the first crack A1 and the second crack A2.

[0114] Figure 14A is a truth table for realizing the buffer function of the logic circuit using Figure 13 , please refer to Figure 13 and Figure 14AThe first signal delivery end is connected with low level and the third signal delivery end is connected with high level, that is, the truth value of the input signal of the first control signal input end D1 is "0" and the truth value of the input signal of the second control signal input end D2 is "1". When the input signal needed to be input to the logic circuit is low level and the truth value is "0", the voltage supply circuit applies the first voltage on the first electrode 20 and the second electrode 30, the first crack is closed and the second crack is separated, the truth value of the input signal of the input end IN is "0", the first signal delivery end and the second signal delivery end are conducted, and the truth value of the output signal of the output end OUT is "0". When the input signal needed to be input to the logic circuit is high level and the truth value is "1", the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, the first crack is separated and the second crack is closed, the truth value of the input signal of the input end IN is "1", the third signal delivery end and the fourth signal delivery end are conducted, and the truth value of the output signal of the output end OUT is "1", thereby realizing the function of the buffer circuit.

[0115] It can be understood that in another embodiment, when the input signal needed to be input to the logic circuit is low level and the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, the input signal needed to be input to the logic circuit is high level and the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, in order to realize the function of the buffer circuit, the first signal delivery end is connected with high level and the third signal delivery end is connected with low level.

[0116] Figure 14B is realized by using Figure 13 the truth table of the logic circuit for realizing the function of the NOT gate circuit is shown in Table 1, please refer to Figure 13 and Figure 14BThe first signal delivery end is connected with high level and the third signal delivery end is connected with low level, that is, the truth value of the input signal of the first control signal input end D1 is "1" and the truth value of the input signal of the second control signal input end D2 is "0". When the input signal needed to be input to the logic circuit is low level and the truth value is "0", the voltage supply circuit applies the first voltage on the first electrode 20 and the second electrode 30, the first crack is closed and the second crack is separated, the truth value of the input signal of the input end IN is "0", the first signal delivery end and the second signal delivery end are conducted, and the truth value of the output signal of the output end OUT is "1". When the input signal needed to be input to the logic circuit is high level and the truth value is "1", the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, the first crack is separated and the second crack is closed, the truth value of the input signal of the input end IN is "1", the third signal delivery end and the fourth signal delivery end are conducted, and the truth value of the output signal of the output end OUT is "0". The input signal input to the logic circuit is output after being logically negated, and the function of the NOT gate circuit is realized.

[0117] It can be understood that, in another embodiment, when the input signal needed to be input to the logic circuit is low level and the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, the first signal delivery end is connected with low level and the third signal delivery end is connected with high level when the input signal needed to be input to the logic circuit is high level and the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, in order to realize the function of the NOT gate circuit.

[0118] Figure 14C is realized by using Figure 13 the truth table of the logic circuit realizing the AND gate circuit function, please refer to Figure 13 and Figure 14CThe first signal delivery end is connected with low level, the third signal delivery end is connected with high level or low level, that is, the truth value of the input signal of the first control signal input end D1 is "0", and the truth value of the input signal of the second control signal input end D2 is "0" or "1". When the input signal required to be input into the logic circuit is low level, and the truth value thereof is "0", the voltage supply circuit applies the first voltage on the first electrode 20 and the second electrode 30, the first crack is closed, the second crack is separated, the truth value of the input signal of the input end IN is "0", then the first signal delivery end and the second signal delivery end are conducted, regardless of the truth value of the input signal of the second control signal input end D2, the truth value of the output signal of the output end OUT is "0"; when the input signal required to be input into the logic circuit is high level, and the truth value thereof is "1", the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, the first crack is separated, the second crack is closed, the truth value of the input signal of the input end IN is "1", then the third signal delivery end and the fourth signal delivery end are conducted, if the truth value of the input signal of the second control signal input end D2 is "0", the truth value of the output signal of the output end OUT is "0", if the truth value of the input signal of the second control signal input end D2 is "1", the truth value of the output signal of the output end OUT is "1", the input signal input into the logic circuit and the input signal of the second control signal input end D2 are output after logical "and", realizing the function of the AND gate circuit.

[0119] It can be understood that in another embodiment, when the input signal required to be input into the logic circuit is low level, the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, when the input signal required to be input into the logic circuit is high level, the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, the first signal delivery end is connected with high level or low level, the third signal delivery end is connected with low level, the input signal input into the logic circuit and the input signal of the first control signal input end D1 are output after logical "and", realizing the function of the AND gate circuit.

[0120] Figure 14D is realized by using Figure 13 the truth table of the logic circuit realizing the OR gate circuit function shown in Figure 13 and Figure 14DThe third signal transmission end is connected with high level, the first signal transmission end is connected with high level or low level, that is, the truth value of the input signal of the second control signal input end D2 is "1", and the truth value of the input signal of the first control signal input end D1 is "0" or "1". When the input signal to be input into the logic circuit is low level and the truth value is "0", the voltage supply circuit applies the first voltage on the first electrode 20 and the second electrode 30, the first crack is closed, the second crack is separated, the truth value of the input signal of the input end IN is "0", the third signal transmission end and the fourth signal transmission end are turned on, and the truth value of the output signal of the output end OUT is "1" regardless of the truth value of the input signal of the first control signal input end D1, the input signal to be input into the logic circuit is logically "or" with the input signal of the first control signal input end D1, and the or gate circuit function is realized.

[0121] It can be understood that in another embodiment, when the input signal to be input into the logic circuit is low level, the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, and when the input signal to be input into the logic circuit is high level, the voltage supply circuit applies the second voltage on the first electrode 20 and the second electrode 30, the first signal transmission end is connected with high level, the third signal transmission end is connected with low level or high level, the input signal to be input into the logic circuit is logically "or" with the input signal of the second control signal input end D2, and the or gate circuit function is realized.

[0122] The three-dimensional memory includes a storage array (Array) region and a peripheral circuit (Periphery) region. The storage array region is used for storing information, and the peripheral circuit region can be located above or below the storage array region, or can be located around the storage array region, and the peripheral circuit region is used for controlling the corresponding storage array region. The ferroelectric switching device can be arranged in the peripheral circuit region.

[0123] The ferroelectric switching device can also be applied to other microelectronic devices, such as non-volatile flash (NorFlash) and the like, and the specific limitation is not made.

[0124] The above merely describes the preferred embodiments of the present disclosure, and it should be pointed out that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present disclosure, and these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A ferroelectric switching device, characterized by, The application relates to a ferroelectric memory cell, comprising: a ferroelectric layer; a first electrode and a second electrode arranged on the ferroelectric layer and arranged along a first direction, the first electrode comprising a first bridge and the second electrode comprising a second bridge; an interlayer insulating layer covering at least the first bridge and the second bridge; a first conductive layer arranged on the interlayer insulating layer and corresponding to the first bridge; a second conductive layer arranged on the interlayer insulating layer and corresponding to the second bridge; a first signal transmission end and a second signal transmission end arranged on the first conductive layer; a third signal transmission end and a fourth signal transmission end arranged on the second conductive layer; a first crack extending from the ferroelectric layer along a direction perpendicular to the ferroelectric layer and penetrating through the first bridge, the interlayer insulating layer and the first conductive layer between the first signal transmission end and the second signal transmission end; a second crack extending from the ferroelectric layer along a direction perpendicular to the ferroelectric layer and penetrating through the second bridge, the interlayer insulating layer and the second conductive layer between the third signal transmission end and the fourth signal transmission end.

2. The ferroelectric switching device of claim 1, wherein, The first crack does not penetrate or penetrates through the ferroelectric layer, and / or the second crack penetrates or does not penetrate through the ferroelectric layer.

3. The ferroelectric switching device of claim 1, wherein, The first electrode and the second electrode are symmetrically arranged with a first gap as a center.

4. The ferroelectric switching device of claim 1, wherein, The first electrode further comprises a first body, the first body is divided into two parts and connected to two ends of the first bridge, and the width of the first body is greater than the width of the first bridge in the first direction; the second electrode further comprises a second body, the second body is divided into two parts and connected to two ends of the second bridge, and the width of the second body is greater than the width of the second bridge in the first direction.

5. The ferroelectric switching device of claim 4, wherein, The width of the first gap between the first body and the second body in the first direction is greater than the width of the first gap between the first bridge and the second bridge.

6. The ferroelectric switching device of claim 4, wherein, The interlayer insulating layer covers part of the surface of the first body and the second body, a first conductive terminal is arranged on the surface of the first body at one end of the first bridge which is not covered by the interlayer insulating layer, and a second conductive terminal is arranged on the surface of the second body at one end of the second bridge which is not covered by the interlayer insulating layer.

7. The ferroelectric switching device of claim 1, wherein, The interlayer insulating layer further covers a ferroelectric layer region between the first electrode and the second electrode.

8. The ferroelectric switching device of claim 1, wherein, The interlayer insulating layer comprises: a first insulating layer arranged at least on the first bridge, the first conductive layer being arranged on the first insulating layer; a second insulating layer arranged at least on the second bridge, the second conductive layer being arranged on the second insulating layer, and the first insulating layer and the second insulating layer being independent of each other.

9. The ferroelectric switching device of claim 1, wherein, The first conductive layer and the second conductive layer are arranged along the first direction, and the first conductive layer and the second conductive layer both extend along a second direction; the first signal transmission end and the second signal transmission end are arranged along the second direction, the first crack extends along the first direction and penetrates the first conductive layer; the third signal transmission end and the fourth signal transmission end are arranged along the second direction, the second crack extends along the first direction and penetrates the second conductive layer; the first direction intersects the second direction.

10. The ferroelectric switching device of claim 1, wherein, In the area of the first bridge on the orthographic projection of the ferroelectric layer, the orthographic projection of the first bridge covers the orthographic projection of the first conductive layer, and / or, in the area of the second bridge on the orthographic projection of the ferroelectric layer, the orthographic projection of the second bridge covers the orthographic projection of the second conductive layer.

11. The ferroelectric switching device of claim 1, wherein, The material of the first electrode is the same as the material of the first conductive layer, and / or, the material of the second electrode is the same as the material of the second conductive layer, and / or, the material of the first electrode is the same as the material of the second electrode.

12. The ferroelectric switching device of claim 1, wherein, One of the signal transmission ends on the first conductive layer is electrically connected with one of the signal transmission ends on the second conductive layer, constituting a signal output end of the ferroelectric switching device.

13. A method of fabricating a ferroelectric switching device, characterized by, Comprising: Providing a substrate; Forming, on the surface of the substrate, a ferroelectric layer, a first electrode, a second electrode, an interlayer insulating layer, a first conductive layer, a second conductive layer, and a first signal transmission end, a second signal transmission end, a third signal transmission end and a fourth signal transmission end in sequence, the first electrode comprising a first bridge, the second electrode comprising a second bridge, the first conductive layer corresponding to at least the first bridge, the second conductive layer corresponding to at least the second bridge, the first signal transmission end and the second signal transmission end being arranged on the first conductive layer, and the third signal transmission end and the fourth signal transmission end being arranged on the second conductive layer; Forming a first crack and a second crack, the first crack extending from the ferroelectric layer along a direction perpendicular to the ferroelectric layer and penetrating the first bridge, the interlayer insulating layer, and the first conductive layer between the first signal transmission end and the second signal transmission end, and the second crack extending from the ferroelectric layer along a direction perpendicular to the ferroelectric layer and penetrating the second bridge, the interlayer insulating layer, and the second conductive layer between the third signal transmission end and the fourth signal transmission end; The method for forming the first crack and the second crack comprises: Applying a polarization voltage to the ferroelectric layer to make the polarization direction of the ferroelectric domain of the ferroelectric layer the same as the direction of the polarization voltage, forming a set polarization direction of the ferroelectric domain; Applying a first flipping voltage to the ferroelectric layer through the first electrode and the second electrode to form the first crack, and applying a second flipping voltage to the ferroelectric layer through the first electrode and the second electrode to form the second crack, the second flipping voltage being opposite in polarity to the first flipping voltage.

14. The method for preparing the ferroelectric switching device according to claim 13, characterized in that, The first crack does not penetrate or penetrates the ferroelectric layer, or / and, the second crack penetrates or does not penetrate the ferroelectric layer.

15. A method of controlling a ferroelectric switching device as claimed in any one of claims 1 to 12, characterized in that Comprising: A first voltage is applied to the ferroelectric layer through the first electrode and the second electrode to control the separation of the first crack and the closure of the second crack, so as to realize electrical insulation between the first signal transmission end and the second signal transmission end and electrical conduction between the third signal transmission end and the fourth signal transmission end; a second voltage is applied to the ferroelectric layer through the first electrode and the second electrode to control the closure of the first crack and the separation of the second crack, so as to realize electrical conduction between the first signal transmission end and the second signal transmission end and electrical insulation between the third signal transmission end and the fourth signal transmission end, wherein the first voltage and the second voltage are opposite in polarity.

16. The method of controlling a ferroelectric switching device according to claim 15, wherein, The first voltage or the second voltage is applied to the ferroelectric layer through the first electrode and the second electrode under the control of an input signal, and the logic circuit function is realized by setting the voltage levels of the first signal transmission end and the third signal transmission end.

17. A three-dimensional memory, comprising: The ferroelectric switching device according to any one of claims 1-12.

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