A sigma-delta modulator and method based on switched-capacitor control
By using a sigma-delta modulator based on switched capacitor control, and employing a switched capacitor array and common-mode feedback circuit, the accuracy and power consumption issues of existing Sigma-Delta modulators in temperature sensors are solved, achieving a performance improvement of high accuracy and low power consumption, making it suitable for digital temperature sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 西安翔腾微电子科技有限公司
- Filing Date
- 2022-08-20
- Publication Date
- 2026-05-15
AI Technical Summary
Existing Sigma-Delta modulators suffer from low output accuracy, large capacitance area, and complex control timing in temperature sensors, making them particularly unsuitable for high-resolution and low-power temperature sensors.
A sigma-delta modulator based on switched capacitor control is designed. It adopts a switched capacitor array and a common-mode feedback circuit. By introducing a new reference voltage and simple timing control, it uses a unit capacitor of the same size, simplifies the control timing, reduces the capacitor area, and improves accuracy.
It improves the overall accuracy of the modulator and reduces power consumption, achieving low-power performance indicators, and is suitable for 13-bit and 16-bit digital temperature sensors.
Smart Images
Figure CN115425984B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of temperature sensors, and particularly relates to a sigma-delta modulator and method based on switched capacitor control. Background Technology
[0002] Among numerous environmental measurement parameters, temperature is closely related to people's lives. Whether in industrial and agricultural production or scientific research, temperature has always been a key focus for measurement and control. Integrated temperature sensors based on CMOS technology are smaller in size and more functional, and can be embedded in a system-on-chip (SoC) for rapid and efficient design of various functions, making the system easier and more reliable. To adapt to the continuous development of temperature sensors towards smaller size, lower power consumption, and lower cost, the core component inside the temperature sensor, the analog-to-digital converter (ADC), is also developing towards higher speed and higher precision. Therefore, the Sigma-Delta ADC, as a high-precision, low-bandwidth ADC structure, is widely used in temperature sensors. The Sigma-Delta modulator is the core and key structure of the Sigma-Delta ADC; its performance directly determines the performance of the entire converter and also affects various performance parameters of the temperature sensor. See also Figure 1 Existing Sigma-Delta modulators, such as Figure 1 As shown, it mainly consists of two operational amplifiers (ATO). This modulator has problems such as low output accuracy, large capacitor area, and complex control timing.
[0003] Therefore, it is necessary to design a Sigma-Delta modulator suitable for temperature sensors. Currently, the implementation of Sigma-Delta modulator circuits is mainly based on switched-capacitor technology, using α times ΔVBE as the feedback voltage signal. The internal analog circuit structure often employs capacitors of different sizes as sampling capacitors, integrating capacitors, and feedback capacitors in the modulator. This structure reduces the timing complexity of the digital circuit, but increases the area, power consumption, and accuracy of the internal analog circuitry of the modulator, making it unsuitable for high-resolution, low-power temperature sensors. Summary of the Invention
[0004] To address the technical problems existing in the background art, the present invention provides a sigma-delta modulator and method based on switched capacitor control, which can be used in digital SPI temperature sensors, and the sigma-delta modulator is suitable for both 13-bit and 16-bit digital temperature sensors.
[0005] The technical solution of the present invention is as follows: The present invention is a sigma-delta modulator based on switched capacitor control, including an input voltage, two operational amplifiers ATO1 and ATO2, and a quantizer. The input voltage is connected to the quantizer in sequence through operational amplifiers ATO1 and ATO2. The special feature is that the modulator also includes a switched capacitor array, which is connected to the input voltage and operational amplifier ATO1 respectively.
[0006] Furthermore, the switched capacitor array includes 16 switches: S1_P—S8_P and S1_N—S8_N, 4 unit capacitors C1_P, C2_P, C1_N, and C2_N, and two input voltages VBE2 and VBE3 are introduced through transistors, which are respectively connected to the positive and negative input terminals of the first-stage operational amplifier ATO1, as follows: one end of switch S1_P is connected to the common-mode voltage VCM, and the other end is connected to capacitor C1_P; one end of switch S2_P is connected to the positive input terminal of operational amplifier ATO1, and the other end is connected to capacitor C1_P together with switch S1_P; one end of capacitor C1_P is connected to switch S1_P... P and S2_P, the other end is connected to switches S3_P and S5_P; one end of switch S3_P is connected to capacitor C1_P, and the other end is connected to input voltage VBE2 and switch S4_P; one end of switch S4_P is connected to input voltage VBE2 and switch S4_P, and the other end is connected to capacitor C2_P; one end of switch S5_P is connected to capacitor C1_P, and the other end is connected to input voltage VBE3 and switch S6_P; one end of switch S6_P is connected to input voltage VBE3 and switch S6_P, and the other end is connected to capacitor C2_P; one end of capacitor C2_P is connected to switches S4_P and switch S6_P, and the other end is connected to switches S7_P and S8_P; the switch S7_P... One end of switch P is connected to the common-mode voltage VCM, and the other end is connected to switch S8_P; one end of switch S8_P is connected to capacitor C2_P and switch S7_P, and the other end is connected to the positive input terminal of operational amplifier ATO1; one end of switch S1_N is connected to the common-mode voltage VCM, and the other end is connected to capacitor C1_N; one end of switch S2_N is connected to the inverting input terminal of operational amplifier ATO1, and the other end is connected to capacitor C1_N together with switch S1_N; one end of capacitor C1_N is connected to switches S1_N and S2_N, and the other end is connected to switches S3_N and S5_N; one end of switch S3_N is connected to capacitor C1_N, and the other end is connected to input voltage VBE2 and switch S4_N; switch S... One end of switch S4_N is connected to the input voltage VBE2 and switch S4_N, and the other end is connected to capacitor C2_N; one end of switch S5_N is connected to capacitor C1_N, and the other end is connected to the input voltage VBE3 and switch S6_N; one end of switch S6_N is connected to the input voltage VBE3 and switch S6_N, and the other end is connected to capacitor C2_N; one end of capacitor C2_N is connected to switches S4_N and S6_N, and the other end is connected to switches S7_N and S8_N; one end of switch S7_N is connected to the common-mode voltage VCM, and the other end is connected to switch S8_N; one end of switch S8_N is connected to capacitor C2_N and switch S7_N, and the other end is connected to the inverting input terminal of operational amplifier ATO1.
[0007] Furthermore, operational amplifier ATO1 includes a bias voltage V. A Circuit, bias voltage V A The circuit consists of NMOS transistors M11, M12, and M13, and PMOS transistors M14 and M15; the gate of NMOS transistor M11 is connected to the control voltage V.b1 The drain is connected to the gate of NMOS transistor M12 and the drain of NMOS transistor M13, and serves as the output voltage V. A The gate of NMOS transistor M12 is connected to the drain of NMOS transistor M13 and the drain of NMOS transistor M11, with the drain connected to the source of NMOS transistor M13; the gate of NMOS transistor M13 is connected to voltage V. B The drain of the PMOS transistor M14 is connected to the gate of NMOS transistor M12 and the drain of NMOS transistor M11, while the source is connected to the drain of NMOS transistor M12. The gate of PMOS transistor M14 is connected to voltage V. C The drain of the transistor is connected to the drain of the NMOS transistor M13, and the source is connected to the source of the PMOS transistor M15; the drain of the PMOS transistor M15 is connected to the source of the PMOS transistor M14, and the gate is connected to the voltage VD.
[0008] Furthermore, the operational amplifier ATO1 also includes a common-mode feedback circuit, which comprises four capacitors C0, C1, C2, and C3; eight switches: S1P-S4P and S1N-S4N; one end of capacitor C0 is connected to a voltage V. OP One end of capacitor C1 is connected to switch S2P, and the other end is connected to voltage VBIAS and switch S4P; one end of capacitor C1 is connected to switch S2P and switch S1P, and the other end is connected to switch S4P and S3P; one end of capacitor C2 is connected to voltage VBIAS and switch S4N, and the other end is connected to voltage VON and switch S2N; one end of capacitor C3 is connected to switch S4N and switch S3N, and the other end is connected to switch S2N and switch S1N; one end of switch S1P is connected to voltage VCM, and the other end is connected to capacitor C1 and switch S2P; one end of switch S2P is connected to capacitor C1 and switch S1P, and the other end is connected to voltage VOP and capacitor C0. One end of switch S3P is connected to voltage VA, and the other end is connected to capacitor C1 and switch S4P; one end of switch S4P is connected to capacitor C1 and switch S3P, and the other end is connected to capacitor C0 and voltage VBIAS; one end of switch S1N is connected to voltage VCM, and the other end is connected to capacitor C3 and switch S2N; one end of switch S2N is connected to capacitor C3 and switch S1N, and the other end is connected to voltage VON and capacitor C2; one end of switch S3N is connected to voltage VA, and the other end is connected to capacitor C3 and switch S4N; one end of switch S4N is connected to capacitor C3 and switch S3N, and the other end is connected to capacitor C2 and voltage VBIAS.
[0009] Furthermore, the modulator also includes digital circuitry, and the quantizer is connected to the switched capacitor array via digital circuitry.
[0010] A method for implementing the above-described sigma-delta modulator based on switched capacitor control, characterized in that the method includes the following steps:
[0011] 1) When switches S11_P and S12_N are closed, the output voltages VBE2 and AVBE3 of the transistor are input to the positive and negative input terminals of operational amplifier ATO1, thus making the positive and negative input terminals of the operational amplifier...
[0012] 2) The output DOUT of the quantizer controls the timing of all switches in the feedback loop. If the output of the quantizer is 0, then switches S1_P, S8_P, S3_P, and switch S6_P are closed. The charge stored in capacitor C1_P is Q = C1_P(VBE2-VCM). The charge stored in capacitor C2_N at the inverting input terminal of operational amplifier ATO1 is Q = C2_N(VBE3-VCM). And switches S9_P and S10_N are closed, resulting in a voltage difference of VFE = αΔVBE + VBE at the positive and negative input terminals of operational amplifier ATO1.
[0013] 3) Achieve quantitative output control over feedback.
[0014] This invention proposes a sigma-delta modulator circuit and method based on switched capacitor control, applicable to the internal circuitry of a temperature sensor. It primarily aims to provide a novel feedback loop circuit and method to address the accuracy problem of modulators in temperature sensors. Firstly, a new reference voltage is introduced into the modulator structure of the temperature sensor to improve the accuracy of the modulator output. Secondly, common-mode feedback is achieved in the operational amplifier using a small unit capacitor of the same area with simple timing control, reducing the capacitor area and simplifying the control timing. This invention has the following advantages:
[0015] 1. In the common-mode feedback circuit of the present invention, a unit capacitor of the same size is used to reduce the error caused by capacitor mismatch in the operational amplifier circuit.
[0016] 2. Compared with the common-mode feedback mechanism using two capacitors of different sizes, one large and one small, the present invention uses a small unit capacitor of the same area to increase the accuracy of common-mode feedback, improve the overall accuracy of the modulator, reduce the modulator circuit area, and achieve low power consumption performance.
[0017] 3. This invention controls the number of capacitors of similar size connected in series or in parallel using digital circuits to design the modulator's proportional coefficient. Compared to the conventional structure, this invention increases the number of switches and digital control timing, reducing the area, power consumption, and slew rate of the modulator's analog circuit section, which helps improve the overall performance of the temperature sensor.
[0018] 4. The common structure uses α times ΔVBE as the feedback voltage signal, while the present invention uses single ΔBE as the feedback voltage based on switched capacitor control, which reduces the quantization scale of the feedback voltage, improves the accuracy of the modulator output signal, and optimizes the overall accuracy of the modulator. Attached Figure Description
[0019] Figure 1 A schematic diagram of an existing Sigma-Delta modulator structure;
[0020] Figure 2 This is a circuit block diagram of the present invention;
[0021] Figure 3 This is a circuit diagram of the present invention;
[0022] Figure 4 This is the circuit diagram of the operational amplifier ATO1 of the present invention;
[0023] Figure 5 This is a common-mode feedback circuit diagram in the operational amplifier ATO1 of the present invention. Detailed Implementation
[0024] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0025] See Figure 2 The circuit structure of a specific embodiment of the present invention includes an input voltage, two operational amplifiers ATO1 and ATO2, a switched capacitor array, a digital circuit, and a quantizer. The input voltage is sequentially connected to the quantizer through operational amplifiers ATO1 and ATO2. The switched capacitor array is connected to both the input voltage and operational amplifier ATO1. The quantizer is connected to the switched capacitor array through the digital circuit.
[0026] Two-stage operational amplifiers ATO1 and ATO2: They adopt a cascaded single-pole amplifier circuit structure and a switched capacitor controlled common-mode feedback circuit. The cascaded structure uses two identical single-pole amplifier circuits. The single-pole operational amplifier structure uses two differential input transistors to achieve a single-stage amplification of the input signal.
[0027] The switched capacitor array uses four small-sized unit capacitors of the same area, C0, C1, C2, and C3, and four differential switches with different timing controls.
[0028] The modulator coefficient design is based on the number of parallel unit capacitors controlled by switches to determine the internal proportional coefficient of the modulator.
[0029] The common-mode feedback circuit accumulates the corresponding feedback voltage ΔVBE or VBE with the input voltage signal based on the comparator's output result of "0" or "1", adjusts the voltage difference at the comparator's input terminal, and achieves feedback compensation.
[0030] Digital circuits can be used to implement switch control using existing digital circuits.
[0031] See Figure 3The switched capacitor array of this invention includes 16 switches: S1_P—S8_P and S1_N—S8_N, 4 unit capacitors C1_P, C2_P, C1_N, C2_N, and two input voltages VBE2 and VBE3 are introduced through transistors, which are respectively connected to the positive and negative input terminals of the first-stage operational amplifier ATO1, as follows: one end of switch S1_P is connected to the common-mode voltage VCM, and the other end is connected to capacitor C1_P; one end of switch S2_P is connected to the positive input terminal of operational amplifier ATO1, and the other end is connected to capacitor C1_P together with switch S1_P; one end of capacitor C1_P is connected to switch S1_P... P and S2_P, the other end is connected to switches S3_P and S5_P; one end of switch S3_P is connected to capacitor C1_P, and the other end is connected to input voltage VBE2 and switch S4_P; one end of switch S4_P is connected to input voltage VBE2 and switch S4_P, and the other end is connected to capacitor C2_P; one end of switch S5_P is connected to capacitor C1_P, and the other end is connected to input voltage VBE3 and switch S6_P; one end of switch S6_P is connected to input voltage VBE3 and switch S6_P, and the other end is connected to capacitor C2_P; one end of capacitor C2_P is connected to switches S4_P and switch S6_P, and the other end is connected to switches S7_P and S8_P; the switch S7_P... One end of switch P is connected to the common-mode voltage VCM, and the other end is connected to switch S8_P; one end of switch S8_P is connected to capacitor C2_P and switch S7_P, and the other end is connected to the positive input terminal of operational amplifier ATO1; one end of switch S1_N is connected to the common-mode voltage VCM, and the other end is connected to capacitor C1_N; one end of switch S2_N is connected to the inverting input terminal of operational amplifier ATO1, and the other end is connected to capacitor C1_N together with switch S1_N; one end of capacitor C1_N is connected to switches S1_N and S2_N, and the other end is connected to switches S3_N and S5_N; one end of switch S3_N is connected to capacitor C1_N, and the other end is connected to input voltage VBE2 and switch S4_N; switch S... One end of switch S4_N is connected to the input voltage VBE2 and switch S4_N, and the other end is connected to capacitor C2_N; one end of switch S5_N is connected to capacitor C1_N, and the other end is connected to the input voltage VBE3 and switch S6_N; one end of switch S6_N is connected to the input voltage VBE3 and switch S6_N, and the other end is connected to capacitor C2_N; one end of capacitor C2_N is connected to switches S4_N and S6_N, and the other end is connected to switches S7_N and S8_N; one end of switch S7_N is connected to the common-mode voltage VCM, and the other end is connected to switch S8_N; one end of switch S8_N is connected to capacitor C2_N and switch S7_N, and the other end is connected to the inverting input terminal of operational amplifier ATO1.
[0032] Secondly, the present invention adds a bias voltage and common-mode voltage feedback circuit structure inside the operational amplifier ATO1.
[0033] See Figure 4 As shown in the dashed box in the figure, this invention adds a bias voltage V to the existing operational amplifier circuit.A Circuit, bias voltage V A The circuit includes NMOS transistors M11, M12, and M13; and PMOS transistors M14 and M15. The gate of NMOS transistor M11 is connected to the control voltage V. b1 The drain is connected to the gate of NMOS transistor M12 and the drain of NMOS transistor M13, and serves as the output voltage V. A The gate of NMOS transistor M12 is connected to the drain of NMOS transistor M13 and the drain of NMOS transistor M11, with the drain connected to the source of NMOS transistor M13; the gate of NMOS transistor M13 is connected to voltage V. B The drain of the PMOS transistor M14 is connected to the gate of NMOS transistor M12 and the drain of NMOS transistor M11, while the source is connected to the drain of NMOS transistor M12. The gate of PMOS transistor M14 is connected to voltage V. C The drain of the transistor is connected to the drain of the NMOS transistor M13, and the source is connected to the source of the PMOS transistor M15; the drain of the PMOS transistor M15 is connected to the source of the PMOS transistor M14, and the gate is connected to the voltage VD.
[0034] See Figure 5 This invention adds a common-mode feedback circuit to the existing operational amplifier circuit. The common-mode feedback circuit includes four capacitors C0, C1, C2, and C3; eight switches: S1P-S4P and S1N-S4N; one end of capacitor C0 is connected to a voltage V. OP One end of capacitor C1 is connected to switch S2P, and the other end is connected to voltage VBIAS and switch S4P; one end of capacitor C1 is connected to switch S2P and switch S1P, and the other end is connected to switch S4P and S3P; one end of capacitor C2 is connected to voltage VBIAS and switch S4N, and the other end is connected to voltage VON and switch S2N; one end of capacitor C3 is connected to switch S4N and switch S3N, and the other end is connected to switch S2N and switch S1N; one end of switch S1P is connected to voltage VCM, and the other end is connected to capacitor C1 and switch S2P; one end of switch S2P is connected to capacitor C1 and switch S1P, and the other end is connected to voltage VOP and capacitor C0. One end of switch S3P is connected to voltage VA, and the other end is connected to capacitor C1 and switch S4P; one end of switch S4P is connected to capacitor C1 and switch S3P, and the other end is connected to capacitor C0 and voltage VBIAS; one end of switch S1N is connected to voltage VCM, and the other end is connected to capacitor C3 and switch S2N; one end of switch S2N is connected to capacitor C3 and switch S1N, and the other end is connected to voltage VON and capacitor C2; one end of switch S3N is connected to voltage VA, and the other end is connected to capacitor C3 and switch S4N; one end of switch S4N is connected to capacitor C3 and switch S3N, and the other end is connected to capacitor C2 and voltage VBIAS.
[0035] This invention also proposes a method for improving the accuracy of a sigma-delta modulator based on switched capacitor control in a temperature sensor, specifically including the following steps:
[0036] 1) When switches S11_P and S12_N are closed, the output voltages VBE2 and AVBE3 of the transistor are input to the positive and negative input terminals of operational amplifier ATO1, thus making the positive and negative input terminals of the operational amplifier...
[0037] 2) The output DOUT of the quantizer controls the timing of all switches in the feedback loop. If the output of the quantizer is 0, then switches S1_P, S8_P, S3_P, and switch S6_P are closed. The charge stored in capacitor C1_P is Q = C1_P(VBE2-VCM). The charge stored in capacitor C2_N at the inverting input terminal of operational amplifier ATO1 is Q = C2_N(VBE3-VCM). And switches S9_P and S10_N are closed, resulting in a voltage difference of VFE = αΔVBE + VBE at the positive and negative input terminals of operational amplifier ATO1.
[0038] 3) Achieve quantitative output control over feedback.
[0039] The present invention adds a common-mode feedback structure to the operational amplifier in order to realize that when VOP and VON increase, VBIAS will increase, which will increase the leakage current of M3 and M4. The gate-source voltage of M7-M10 will not change. Therefore, in order to balance the branch current, the drain-source voltage of M7-M10 can only be increased to reduce the VOP and VON voltage, thereby achieving the regulation of VBIAS.
[0040] Specifically, it includes the following steps:
[0041] 1) Switches S1P, S3P, S3N, and S1N are closed, while switches S2P, S4P, S4N, and S2N are open; the charge stored in capacitor C1 is C1(VCM-VA), the charge stored in capacitor C3 is C3(VCM-VA), the charge stored in capacitor C0 is C0(VOP-VBAIS), and the charge stored in capacitor C2 is C2(VON-VBAIS); the total charge in the feedback circuit at this time is:
[0042] Q1=(C1+C3)(VCM-VA)+(VON-VB)C2+(VOP-VB)C0
[0043] 2) When switches S2P, S4P, S4N, and S2N are closed, and switches S1P, S3P, S3N, and S1N are open, the charge stored in capacitor C0 is C0(VOP - VBAIS), the charge stored in capacitor C2 is C2(VON - VBAIS), the charge stored in capacitor C1 is C1(VOP - VBAIS), and the charge stored in capacitor C3 is C3(VON - VBAIS). The total charge in the feedback circuit at this time is:
[0044] Q2=(VON-VB)(C2+C3)+(VOP-VB)(C0+C1)
[0045] Steps 1) and 2) are achieved using the principle of charge conservation:
[0046] VBIAS = 1 / 2(VON + VOP) - VCM + VA
[0047] 3) Therefore, VBAIS can be adjusted according to the output VOP and VON of the operational amplifier. When VBAIS = VA through the bias circuit, 1 / 2(VON + VOP) = VCM, thus realizing the common-mode feedback of the operational amplifier.
[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A sigma-delta modulator based on switched capacitor control, comprising an input voltage, two operational amplifiers ATO1 and ATO2, and a quantizer, wherein the input voltage is sequentially connected to the quantizer through operational amplifiers ATO1 and ATO2, characterized in that: The modulator also includes a switched capacitor array, which is connected to the input voltage and operational amplifier ATO1. The switched capacitor array includes 16 switches: S1_P—S8_P and S1_N—S8_N, and four unit capacitors C1_P, C2_P, C1_N, and C2_N. Two input voltages, VBE2 and VBE3, are introduced through transistors and connected to the positive and negative input terminals of the first-stage operational amplifier ATO1, respectively. Specifically, one end of switch S1_P is connected to the common-mode voltage VCM, and the other end is connected to capacitor C1_P; one end of switch S2_P is connected to the positive input terminal of operational amplifier ATO1, and the other end is connected to... Connect switch S1_P together with capacitor C1_P; one end of capacitor C1_P is connected to switches S1_P and S2_P, and the other end is connected to switches S3_P and S5_P; one end of switch S3_P is connected to capacitor C1_P, and the other end is connected to input voltage VBE2 and switch S4_P; one end of switch S4_P is connected to input voltage VBE2, and the other end is connected to capacitor C2_P; one end of switch S5_P is connected to capacitor C1_P, and the other end is connected to input voltage VBE3 and switch S6_P; one end of switch S6_P is connected to input voltage VBE3, and the other end is connected to capacitor C2_P; one end of capacitor C2_P is connected to switches S4_P and S6_P, and the other end is connected to switch S7_P. Switches S7 and S8 are connected; one end of switch S7 is connected to the common-mode voltage VCM, and the other end is connected to switch S8; one end of switch S8 is connected to capacitor C2 and switch S7, and the other end is connected to the positive input terminal of operational amplifier ATO1; one end of switch S1 is connected to the common-mode voltage VCM, and the other end is connected to capacitor C1; one end of switch S2 is connected to the inverting input terminal of operational amplifier ATO1, and the other end is connected to capacitor C1 together with switch S1; one end of capacitor C1 is connected to switches S1 and S2, and the other end is connected to switches S3 and S5; one end of switch S3 is connected to capacitor C1, and the other end is connected to the input voltage VCM. BE2 and switch S4_N; one end of switch S4_N is connected to input voltage VBE2, and the other end is connected to capacitor C2_N; one end of switch S5_N is connected to capacitor C1_N, and the other end is connected to input voltage VBE3 and switch S6_N; one end of switch S6_N is connected to input voltage VBE3, and the other end is connected to capacitor C2_N; one end of capacitor C2_N is connected to switches S4_N and S6_N, and the other end is connected to switches S7_N and S8_N; one end of switch S7_N is connected to common-mode voltage VCM, and the other end is connected to switch S8_N; one end of switch S8_N is connected to capacitor C2_N and switch S7_N, and the other end is connected to the inverting input terminal of operational amplifier ATO1.
2. The sigma-delta modulator based on switched capacitor control according to claim 1, characterized in that: The operational amplifier ATO1 includes a bias voltage V. A The circuit, the bias voltage V A The circuit consists of NMOS transistors M11, M12, and M13, and PMOS transistors M14 and M15; the gate of NMOS transistor M11 is connected to the control voltage V. b1 The drain is connected to the gate of NMOS transistor M12 and the drain of NMOS transistor M13, and serves as the output voltage V. A The source of the NMOS transistor M12 is grounded; the gate of the NMOS transistor M12 is connected to the drain of the NMOS transistor M13 and the drain of the NMOS transistor M11, and the drain is connected to the source of the NMOS transistor M13, which is grounded; the gate of the NMOS transistor M13 is connected to voltage V. B The drain of the PMOS transistor M14 is connected to the gate of NMOS transistor M12 and the drain of NMOS transistor M11, and the source is connected to the drain of NMOS transistor M12; the gate of the PMOS transistor M14 is connected to voltage V. C The drain is connected to the drain of NMOS transistor M13, and the source is connected to the drain of PMOS transistor M15; the source of PMOS transistor M15 is connected to voltage VDD, and the gate is connected to voltage VD.
3. The sigma-delta modulator based on switched capacitor control according to claim 2, characterized in that: The operational amplifier ATO1 also includes a common-mode feedback circuit, which comprises four capacitors C0, C1, C2, and C3; and eight switches: S1P-S4P and S1N-S4N; one end of capacitor C0 is connected to a voltage V. OP One end of capacitor C1 is connected to switch S2P, and the other end is connected to voltage VBIAS and switch S4P; one end of capacitor C1 is connected to switch S2P and switch S1P, and the other end is connected to switch S4P and S3P; one end of capacitor C2 is connected to voltage VBIAS and switch S4N, and the other end is connected to voltage VON and switch S2N; one end of capacitor C3 is connected to switch S4N and switch S3N, and the other end is connected to switch S2N and switch S1N; one end of switch S1P is connected to voltage VCM, and the other end is connected to capacitor C1 and switch S2P; one end of switch S2P is connected to capacitor C1 and switch S1P, and the other end is connected to voltage VOP and capacitor C0. One end of switch S3P is connected to voltage VA, and the other end is connected to capacitor C1 and switch S4P; one end of switch S4P is connected to capacitor C1 and switch S3P, and the other end is connected to capacitor C0 and voltage VBIAS; one end of switch S1N is connected to voltage VCM, and the other end is connected to capacitor C3 and switch S2N; one end of switch S2N is connected to capacitor C3 and switch S1N, and the other end is connected to voltage VON and capacitor C2; one end of switch S3N is connected to voltage VA, and the other end is connected to capacitor C3 and switch S4N; one end of switch S4N is connected to capacitor C3 and switch S3N, and the other end is connected to capacitor C2 and voltage VBIAS.
4. The sigma-delta modulator based on switched capacitor control according to any one of claims 1 to 3, characterized in that: The modulator also includes digital circuitry, and the quantizer is connected to the switched capacitor array via digital circuitry.