Storage addressing method for LDPC decoder

Abstract

The application provides a storage addressing method suitable for an LDPC decoder, comprising: allocating a RAM array; storing initial channel information in the RAM array by means of bit splicing; calculating a starting reading address and a starting offset address of the RAM in the RAM array and saving; generating a reading address and an offset address of the RAM according to the starting reading address and the starting offset address; reading information in the RAM according to the reading address of the RAM, and sending the information to a check node updating unit or a variable node updating unit for processing after data bit sequence adjustment according to the offset address; and writing information processed by the check node updating unit or the variable node updating unit into corresponding RAMs in sequence. Through bit splicing storage, complicated reading and simple writing, the decoder can avoid address access conflict problems when completing LDPC decoding, and can achieve parallel high-speed decoding efficiency while realizing low operation complexity.

Description

Technical Field

[0001] This invention belongs to the field of communications, and in particular relates to a storage addressing method suitable for LDPC decoders. Background Technology

[0002] LDPC codes, or Low Density Parity Check codes, were first proposed by Dr. Gallager in 1962 and rediscovered by Mackey and Neal in 1996. LDPC codes possess superior error correction performance and low hardware implementation complexity, thus they are widely used in deep space communication.

[0003] With technological advancements, the academic community has proposed various decoding algorithms for LDPC codes. Among them, the probabilistic-domain backpropagation (BP) decoding algorithm is one of the mainstream LDPC decoding algorithms, but it requires a large number of multiplication operations, making it difficult to implement in hardware. The logarithmic-domain LLR (Log Likely Rate) BP decoding algorithm transforms the multiplication operations in the probabilistic-domain BP decoding algorithm into addition operations, reducing computational complexity. However, due to the presence of logarithmic operations, the hardware implementation complexity remains high. The minimum sum decoding algorithm (MSA) is a further simplification of the logarithmic-domain LLR BP decoding algorithm; the simplified MSA only requires addition and comparison operations. The multiplicative modified minimum sum decoding algorithm (NMSA) is a modification of MSA, making its error correction performance closer to that of the logarithmic-domain LLR BP decoding algorithm. Although NMSA has low computational complexity and is extremely suitable for hardware implementation, its decoding mechanism based on two-phase message passing (TPMP) results in a significant amount of invalid waiting time.

[0004] With the development of communication technology, there are further requirements for decoding speed and efficiency. How to design a corresponding FPGA-based decoder for LDPC decoding and obtain parallel high-speed decoding efficiency is a problem faced by those skilled in the art. Summary of the Invention

[0005] The main technical problem solved by this invention is to provide a storage addressing method suitable for LDPC decoders, which achieves parallel high-speed decoding efficiency while achieving low computational complexity.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A memory addressing method suitable for LDPC decoders is provided, including:

[0008] S201: Allocate RAM array;

[0009] S202: Store the initial channel information in the RAM array by bit splicing;

[0010] S203: Calculate and save the starting read address and starting offset address of the RAM in the RAM array;

[0011] S204: Generate the RAM read address and offset address based on the starting read address and starting offset address;

[0012] S205: Read the information in RAM according to the RAM read address, adjust the data bit order of the information according to the offset address, and send it to the check node update unit or variable node update unit for processing;

[0013] S206: Write the information processed by the check node update unit or the variable node update unit into the corresponding RAM in sequence.

[0014] Furthermore, step S201 also includes:

[0015] The RAM array used to store channel initial information is the first storage RAM, and the RAM arrays used to store intermediate transmission information are the second storage RAM and the third storage RAM. The intermediate transmission information includes vertical update information and horizontal update information. The second storage RAM is used to store vertical update information, and the third storage RAM is used to store horizontal update information.

[0016] Furthermore, step S201 also includes:

[0017] Allocate 16 RAM blocks to the first storage RAM, 64 RAM blocks to the second storage RAM, and 64 RAM blocks to the third storage RAM. Each RAM block can store 511 data blocks of 7 bits each.

[0018] Furthermore, step S202 also includes:

[0019] The parity check matrix H used by the LDPC decoder is divided into 14 blocks by rows and 112 blocks by columns. The smallest submatrix of each block is 73×73. Each smallest submatrix is ​​iteratively updated simultaneously.

[0020] Furthermore, step S202 also includes:

[0021] When storing, the initial channel information is quantized using 6 bits, and the intermediate information is quantized using 7 bits. That is, the initial channel information includes 1 sign bit and 5 absolute bits, and the intermediate information has one more decimal place than the initial channel information.

[0022] Furthermore, the method of median splicing in step S202 also includes:

[0023] The initial channel information is grouped, with each group containing 511 data points. The bit width of each RAM block is set to 49, and the depth is set to 73.

[0024] Furthermore, step S202 also includes:

[0025] Each RAM block contains 0-72 memory addresses, each memory address stores 7 data items, and each data item contains 7 bits;

[0026] The seven data items are assigned offset addresses 1-7 in order from left to right, and adjacent data items are spaced 73 bits apart during storage.

[0027] Further, step S203 calculates the starting read address and starting offset address of the 64 RAM blocks in the second storage RAM using the following method:

[0028] The first step is to retrieve the positions of the 64th element (1) in the first row and the 512th row of the parity check matrix H to obtain the first position index;

[0029] The second step is to normalize all the first position indices to the interval (1, 511) to obtain the second position index; where the second position index is the remainder obtained by dividing the first position index by 511.

[0030] The third step is to divide the interval (1, 511) into 7 sub-intervals with an interval of 73. Based on the different sub-intervals in which the second position index is located, the corresponding RAM is assigned a starting offset address of 1 to 7. The starting offset address is obtained by dividing the second position index by 73 and then rounding it up.

[0031] The fourth step is to normalize the second position index to the interval (1, 73) to obtain the third position index. Then, subtract 1 from the third position index to obtain the starting read address. The third position index is the remainder obtained by dividing the second position index by 73.

[0032] Further, step S203 calculates the starting read address and starting offset address of the 64 RAM blocks in the third storage RAM using the following method:

[0033] The first step is to retrieve the position of the 64th element 1 in the 511*n+1th column of the parity matrix H to obtain the first position index, where n is an integer, and the values ​​are n = 0, 1, ..., 15.

[0034] The second step is to normalize all the first position indices to the interval (1, 511) to obtain the second position index; where the second position index is the remainder obtained by dividing the first position index by 511.

[0035] The third step is to divide the interval (1, 511) into 7 sub-intervals with an interval of 73. Based on the different sub-intervals in which the second position index is located, the corresponding RAM is assigned a starting offset address of 1 to 7. The starting offset address is obtained by dividing the second position index by 73 and then rounding it up.

[0036] The fourth step is to normalize the second position index to the interval (1, 73) to obtain the third position index. Then, subtract 1 from the third position index to obtain the starting read address. The third position index is the remainder obtained by dividing the second position index by 73.

[0037] Furthermore, step S204 also includes:

[0038] During each iteration, the address is read and assigned values ​​cyclically from 0 to 72, with each cycle containing 73 clock cycles;

[0039] Each time the address is read once, the offset address is incremented by 1.

[0040] The beneficial effects of this invention are: by designing a storage addressing method suitable for LDPC decoders, storing data by bit concatenation, and reading and writing data using both complex and simplified methods, the decoder avoids address access conflicts when performing LDPC decoding, and achieves parallel high-speed decoding efficiency while achieving low computational complexity. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the trajectory of element 1 of the sub-circular matrix A of the verification matrix H according to an embodiment of the present invention;

[0042] Figure 2 This is a transmission frame structure of an embodiment of the LDPC code of the present invention (8176, 7154);

[0043] Figure 3 This is a schematic diagram of the horizontal and vertical updates of an embodiment of the overlapping partially parallel decoding algorithm of the present invention;

[0044] Figure 4 This is a flowchart illustrating the computation of an embodiment of the overlapping partial parallel decoding algorithm of the present invention.

[0045] Figure 5 This is a schematic diagram of the architecture of an embodiment of the decoder of the present invention;

[0046] Figure 6 This is a schematic diagram of the architecture of an embodiment of the iterative update unit of the present invention;

[0047] Figure 7 This is a flowchart of an embodiment of the storage addressing method of the present invention;

[0048] Figure 8This is a schematic diagram of the array distribution of RAM in the first storage RAM for storing channel initial information according to an embodiment of the present invention;

[0049] Figure 9 This is a schematic diagram of the array distribution of the storage RAM for storing intermediate information transmission according to an embodiment of the present invention;

[0050] Figure 10 This is a schematic diagram illustrating the storage of a set of channel initial information according to an embodiment of the present invention;

[0051] Figure 11 This is a schematic diagram of a "traditional reading and simplified writing" storage addressing mode according to an embodiment of the present invention;

[0052] Figures 12a-12c This is a schematic diagram of a horizontal update process according to an embodiment of the present invention;

[0053] Figures 13a-13c This is a schematic diagram of the vertical update process according to an embodiment of the present invention;

[0054] Figure 14 This is a schematic diagram of the initialization of channel initial information by the initialization storage unit according to an embodiment of the present invention;

[0055] Figure 15 This is a diagram showing the correspondence between the initial channel information written to the first storage RAM and the second storage RAM according to an embodiment of the present invention.

[0056] Figure 16 This is a schematic diagram of the structure of a verification node update unit according to an embodiment of the present invention;

[0057] Figure 17 This is a schematic diagram of the structure of a variable node update unit according to an embodiment of the present invention;

[0058] Figure 18 This is a timing diagram of the decoder iteration process according to an embodiment of the present invention;

[0059] Figure 19 This is a flowchart of a verification method according to an embodiment of the present invention;

[0060] Figure 20 This is a schematic diagram of the verification storage of an embodiment of the verification unit of the present invention;

[0061] Figure 21 This is a flowchart of the verification sub-process of an embodiment of the verification method of the present invention;

[0062] Figure 22 This is a structural block diagram of an embodiment of the verification device of the present invention;

[0063] Figure 23 This is a comparison chart of the quantification effect according to an embodiment of the present invention;

[0064] Figure 24 This is a comparison chart of the effects of the maximum number of iterations in one embodiment of the present invention. Detailed Implementation

[0065] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0066] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0067] The abbreviations used in this invention are defined as follows:

[0068] QC-LDPC: Quasi-Cyslic-Low-Density Parity-Check Codes

[0069] CCSDS: Consultative Committee for Space Data Systems

[0070] C2V: Check to Variable, Horizontal Update

[0071] V2C: Variable to Check, Vertical Update

[0072] CNU: Check Node Unit

[0073] VNU: Variable Node Unit, Variable Node Update Unit

[0074] RAM: Random Access Memory, Register

[0075] The LDPC code selected in this invention is the QC-LDPC code, specifically the (8176, 7154) LDPC code recommended by the International Space Data Systems Consultative Committee (CCSDS) channel coding standard. This code inherently possesses quasi-cyclic properties and has low hardware implementation complexity. The parity check matrix H of the (8176, 7154) LDPC code is a regular quasi-cyclic matrix with a size of 1022 × 8176. The row weight is 32, and the column weight is 4. The row weight is the number of "1"s in each row, and the column weight is the number of "1"s in each column. Therefore, the parity check matrix H contains only a very small number of "1"s, with the vast majority of matrix elements being zero. The specific construction of the parity check matrix H is shown below:

[0076]

[0077] Where A represents a sub-circular matrix of the parity check matrix H, and the index of A represents its position in the parity check matrix H. Each A is 511×511 in size, and the row weight and column weight of each row are both 2. The element 1 in the l-th row (l=2,3,…,511) of A is the cyclic right shift of the element 1 in the (l-1)-th row. In this invention, the set of points formed by cyclically shifting a certain element 1 in A 510 times is defined as the trajectory of this element 1, such as... Figure 1 As shown, we can see that there are two trajectories of element 1 in A: L1 and L2.

[0078] Figure 2 The transmission frame structure of the (8176, 7154) LDPC code specified by CCSDS is given. For example... Figure 2 As shown, since the first 18 bits are frozen bits 0 and are not sent, a complete transmission frame contains only 8160 bits, of which the first 7136 bits are information bits, the middle 1022 bits are check bits, and the last two bits are padding bits 0.

[0079] The BP decoding algorithm for LDPC codes mainly includes two processes: horizontal update and vertical update. The horizontal update is a parallel update where the check node transmits information to the variable node. The module responsible for this update process is called the check node update unit, abbreviated as CNU in this invention. The vertical update is a parallel update where the variable node transmits information to the check node. The module responsible for this update process is called the variable node update unit, abbreviated as VNU in this invention. The BP decoding algorithm is based on a two-phase message passing (TPMP) decoding mechanism, meaning the horizontal and vertical update processes alternate. The advantage of this decoding mechanism is that the check node update unit and the variable node update unit can utilize entirely new transmitted information. The disadvantage is that the hardware utilization rate is low, only 50%. The NMSA algorithm, optimized from the BP decoding algorithm, still uses the two-phase message passing (TPMP) mechanism, thus still suffers from a significant amount of invalid waiting time.

[0080] To achieve a higher parallel decoding rate, this invention uses an overlapping partially parallel decoding algorithm for LDPC decoding. The overlapping partially parallel decoding algorithm (overlapped NMSA) is proposed based on NMSA to address the problem of excessive invalid waiting time in the NMSA algorithm.

[0081] Furthermore, such as Figure 3 As shown, when applying the overlapping partially parallel decoding algorithm, the parity check matrix H is first divided into blocks. For the horizontal update process, H is divided into blocks uniformly according to rows; for the vertical update process, H is divided into blocks uniformly according to columns. The sub-circular matrices after block division contain the same number of rows and columns, denoted as K. Figure 3 In the diagram, A1 is a sub-circular matrix containing K rows and K columns. During iteration, each sub-circular matrix is ​​updated simultaneously both horizontally and vertically. As shown in the diagram, in the first cycle, the first row of sub-circular matrix A1 is updated horizontally, and the first column is updated vertically. In the second cycle, the second row of sub-circular matrix A1 is updated horizontally, and the second column is updated vertically. This process continues until the Kth cycle, when the Kth row of sub-circular matrix A1 is updated horizontally, and the Kth column is updated vertically. This completes one iteration of sub-circular matrix A1. Similarly, for other sub-circular matrices, iteration is performed within the same K cycles, completing one iteration of all sub-circular matrices in the Kth cycle.

[0082] This allows horizontal and vertical updates to complete iterations simultaneously within the same timeframe, enabling the algorithm to achieve twice as many iterations as NMSA within the same time period.

[0083] Specifically, refer to Figure 4 The computation process for implementing the overlapping partially parallel decoding algorithm is as follows:

[0084] S101: Initialization, store the initial channel information and obtain intermediate transmission information;

[0085] S102: Iterative update, performing both horizontal and vertical updates simultaneously;

[0086] S103: Decision, make a decision based on the updated sub-circular matrix to obtain the corresponding decoded codeword;

[0087] S104: Verification. Verification is performed after each iteration. If the verification result is true, or the number of iterations reaches the maximum value, decoding stops; otherwise, jump to S102 and continue to the next iteration update.

[0088] S105: Stop decoding and output the decoding result.

[0089] Further, step S101 includes the following calculations:

[0090]

[0091]

[0092] l = 1.

[0093] in, express The log-likelihood ratio, express The log-likelihood ratio, y j Here, K represents the initial channel information, K is the number of rows or columns of the sub-circular matrix after block division, and q... ji This represents the information (vertical update information) passed from the j-th variable node to the i-th check node, r. ij This represents the information (horizontal update information) passed from the i-th check node to the j-th variable node. This indicates the initial vertical update information. This represents the initial horizontal update information. l represents the current iteration number, l = 1, 2, ..., max, where max is the maximum iteration number.

[0094] Further, step S102 includes the following calculations:

[0095] for(j=i=1;j≤K;j++,i++)

[0096] {

[0097] Horizontal update, verification node update unit calculation and processing

[0098]

[0099] Where, j'∈R i\j This indicates that the j-th variable node is deleted from the set of variable nodes connected to the i-th verification node. η represents the correction value, which is 0.75 in this invention.

[0100] For vertical updates, the variable node update unit calculation is processed as follows:

[0101]

[0102]

[0103] Where i'∈C j\i This means deleting the i-th check node from the set of check nodes connected to the j-th variable node.

[0104] };

[0105] Further, step S103 includes the following calculations:

[0106] If L(q) j If ) < 0, then c j =1, otherwise c j =0. Where, c j This represents the decoded codeword.

[0107] Further, step S104 includes the following calculations:

[0108] If H·c T If l = 0 or l = max, then stop decoding; otherwise, l = l + 1 and return to step S102 to continue iteration.

[0109] The main idea of ​​this algorithm is to perform the horizontal and vertical update processes simultaneously. Although this update method prevents the check node update unit and the variable node update unit from utilizing the new transmitted information, resulting in a slower convergence speed than NMSA in terms of the number of iterations, the algorithm can achieve twice as many iterations as NMSA in the same amount of time, which is enough to make up for its slow convergence speed.

[0110] Example 1

[0111] Furthermore, such as Figure 5 , 6 As shown, this invention provides an FPGA-based LDPC decoder for implementing the overlapping partially parallel decoding algorithm of the above QC-LDPC codes, achieving parallel high-speed decoding efficiency while achieving low computational complexity.

[0112] Figure 5 The following is an architecture diagram of the decoder, including: receiving unit 101, control unit 102, iterative update unit 103, and verification unit 104.

[0113] The receiving unit 101 is responsible for receiving the initial channel information and sending it to the iterative update unit 103 for storage, while notifying the control unit 102 to start decoding.

[0114] According to the notification from the receiving unit 101, the control unit 102 controls the iterative update unit 103 to start the iterative update, and decides whether to perform the next iteration based on the verification result of the verification unit 104.

[0115] After receiving the initial channel information received by the receiving unit 101, the iterative update unit 103 stores the information and starts the iterative update according to the control command of the control unit 102, and outputs the decision information generated by each iteration update to the verification unit 104.

[0116] The verification unit 104 performs verification based on the decision information and outputs the result to the control unit 102.

[0117] Further, refer to Figure 6 , Figure 6 The detailed architecture diagram of the iterative update unit 103 includes: an initialization storage unit 1031, an addressing unit 1032, a variable node update unit library 1033, a check node update unit library 1034, a data bit order adjustment unit 1035, and corresponding storage RAM.

[0118] Furthermore, the storage RAM includes a first storage RAM 1036 for storing channel initial information, and a second storage RAM 1037 and a third storage RAM 1038 for storing intermediate transmission information.

[0119] Furthermore, the intermediate transmission information includes vertical update information (generated during vertical update) and horizontal update information (generated during horizontal update). The second storage RAM 1037 is used to store the vertical update information, and the third storage RAM 1038 is used to store the horizontal update information.

[0120] Furthermore, each variable node update unit library 1033 contains 112 variable node update units, and each check node update unit library 1034 contains 14 check node update units, used to handle intermediate information transmission. This is because, to further improve parallelism, the sub-circular matrix is ​​divided into minimum submatrices, where the minimum submatrix size is 73*73, and each minimum submatrix is ​​iteratively updated simultaneously. Accordingly, if each minimum submatrix needs to be updated horizontally and vertically simultaneously, 14 check node update units and 112 variable node update units are required.

[0121] For each frame's initial channel information, N iterations of decoding are performed until the decoding of this frame's initial channel information is successfully completed, at which point the iteration task ends, and the decoding of the next frame's initial channel information begins. The structure of each frame's initial channel information is as follows: Figure 2 As shown, the first 18 frozen bits are not sent, and the last two padding bits do not need to be processed during iteration. Therefore, when storing locally, the storage information of the 18 frozen bits needs to be regenerated, while the last two padding bits are discarded. That is to say, each frame corresponds to 8176 data when storing, of which the first 18 data are fixed values, and the actual changes are in the last 8158 data.

[0122] At the beginning of each frame iteration decoding, the initialization storage unit 1031 stores the initial channel information into the first storage RAM 1036, and at the same time stores the initial channel information into the second storage RAM 1037.

[0123] During each iteration initialization of the same frame, the initialization storage unit 1031 reads the channel initial information from the first storage RAM 1036 and stores it in the second storage RAM 1037. When the current iteration ends, the initialization storage unit 1031 clears the second storage RAM 1037 and the third storage RAM 1038.

[0124] When all iterations of decoding of the channel initial information belonging to the same frame are completed, the initialization storage unit 1031 not only clears the third storage RAM 1038 and the second storage RAM 1037, but also clears the first storage RAM 1036, so as to receive the channel initial information of the next frame and start the decoding work of the new frame.

[0125] During an iterative update process, after the initialization storage unit 1031 completes its initialization, the control unit 102 immediately sends a read enable signal to the addressing unit 1032. During the period when the read enable signal is present, the addressing unit 1032 continuously generates read addresses for the RAM. The intermediate transmission information read from the second storage RAM 1037 and the third storage RAM 1038 is processed by the data bit order adjustment unit 1035 and then sent to the verification node update unit library 1034 and the variable node update unit library 1033, respectively. The intermediate transmission information processed by the verification node update unit library 1034 and the variable node update unit library 1033 is then sent back to the third storage RAM 1038 and the second storage RAM 1037 for storage.

[0126] After an iteration update is completed, the variable node update unit library 1033 will generate decision information. The verification unit 104 will perform verification based on the decision information and output the verification result. The control unit 102 will choose to continue the iteration or control the verification unit 104 to output the decoding result based on the verification result of the verification unit 104.

[0127] Furthermore, in order to implement the addressing method in Embodiment 2, the present invention optimizes the initialization storage unit 1031, the addressing unit 1032, and the data bit order adjustment unit 1035 as follows.

[0128] After the initial channel information arrives, refer to Figure 14 The initialization storage unit 1031 starts from address 0 of the first storage RAM 1036 and reads the data at each address sequentially. It returns to address 0 after reading address 72. The read data is the raw data, abbreviated as DB. The lower 42 bits of DB are assigned to the higher 42 bits of the write register. Correspondingly, a bit 0 is added to the end of the channel initial information and assigned to the lower 7 bits of the write register. Then, the value in the write register is sent to the first storage RAM 1036 and the second storage RAM 1037 for storage. After this cycle is repeated 7 times, one set (511) of channel initial information can be stored in RAM according to... Figure 10 The storage is performed as shown. After storing one frame of initial channel information (8158 data points), the initialization storage unit 1031 notifies the control unit 102 that the initialization storage is complete.

[0129] Furthermore, when the value written to the register is sent to the first storage RAM 1036 and the second storage RAM 1037, their correspondence is as follows: Figure 15 As shown. Here, WE represents write enable. Thus, the synchronous initialization storage of the first storage RAM 1036 and the second storage RAM 1037 is completed. Note that the initial information is not stored in the third storage RAM 1038 at this time. Instead, the result of the horizontal update is stored in the third storage RAM 1038 during the subsequent iterative update process.

[0130] Furthermore, the addressing unit 1032 is responsible for generating the read address of the RAM in the second storage RAM 1037 (third storage RAM 1038) and the offset address used by the data bit order adjustment unit 1035. The generation method adopts the method in Embodiment 2. The data bit order adjustment unit 1035 is implemented using a barrel shift register.

[0131] During an iteration, the offset address changes at most once. If the starting read address of a RAM block is 0, its offset address will not change throughout the entire iteration, i.e., it will always remain at the starting offset address. In this case, if the barrel shift register were to provide a complete functional description of the offset address (3 bits), it would be a huge waste of hardware resources. Therefore, this invention further modifies the offset address (3 bits) generated in the addressing unit 1032 into an offset enable variable (1 bit). When the offset enable is 0, the barrel shift register performs a cyclic left shift of the input data according to the corresponding starting offset address. When the offset enable is 1, it represents adding one to the original starting offset address, and the barrel shift register performs a cyclic left shift of the input data according to the updated offset address.

[0132] To accommodate the above optimizations and adjustments, this invention divides the barrel shift register into 7 modules: SL_1, SL_2, ..., SL_7.

[0133] Among them, SL_1 stores the input data once and outputs it when the offset enable is 0, without performing a circular left shift. When the offset enable is 1, the input data is circularly shifted left by 7 bits and then output.

[0134] When the offset enable is 0, SL_2 will output the input data after a 7-bit circular left shift. When the offset enable is 1, it will output the input data after a 14-bit circular left shift.

[0135] When the offset enable is 0, SL_3 will output the input data after a 14-bit circular left shift; when the offset enable is 1, it will output the input data after a 21-bit circular left shift.

[0136] When the offset enable is 0, SL_4 will output the input data after a 21-bit circular left shift; when the offset enable is 1, it will output the input data after a 28-bit circular left shift.

[0137] When the offset enable is 0, SL_5 will output the input data after a 28-bit circular left shift. When the offset enable is 1, it will output the input data after a 35-bit circular left shift.

[0138] When the offset enable is 0, SL_6 will output the input data after a 35-bit circular left shift; when the offset enable is 1, it will output the input data after a 42-bit circular left shift.

[0139] SL_7 outputs the input data after a 42-bit circular left shift when the offset enable is 0, and outputs the input data after a 49-bit circular left shift when the offset enable is 1.

[0140] Depending on the starting offset address of the RAM in the second storage RAM 1037 (or the third storage RAM 1038), the output data of the RAM is connected to the corresponding SL_i, i = 1, 2, ..., 7. For example, if the starting offset address of a RAM is 2, then its output data is connected to SL_2. This allows the barrel shift register to achieve the function of the original circuit while greatly reducing its hardware resource consumption.

[0141] Furthermore, Figure 16 This is a schematic diagram of the structure of the verification node update unit. The sign operation unit is based on a tree-like operation structure and is divided into 6 levels. It is responsible for performing the calculation and processing of the sign bit of the input data in the horizontal update.

[0142] Furthermore, this invention inserts a 6-stage pipeline into the verification node update unit. The first stage performs the absolute value operation on the input data. Stages 2 to 5, the "accompanying second smallest value comparator," find the second smallest value, the minimum value, and the position index of the minimum value in the input data. The sixth stage assigns the corrected minimum or second smallest value to the lower 6 bits of the 32 output data based on the minimum value position index obtained by the comparator, and assigns the output bit of the sign operation unit to the highest bit of the 32 output data. The 32 data are processed in parallel because the row weight of the H matrix is ​​32.

[0143] Furthermore, Figure 17This is a schematic diagram of the variable node update unit. In this invention, a 6-stage pipeline is inserted into the variable node update unit. Stage 1 converts the input data into signed numbers. Stages 2 through 5 complete the vertical update. Stage 6 limits the output data from stage 5 and outputs it. Four data points are processed in parallel because the H matrix has four column weights.

[0144] In the initial addition operations, the number of bits is increased to prevent overflow. For example, the number of signed bits is increased from 7 to 9. However, the final processed data is still converted back to a 7-bit signed number for storage in RAM. Therefore, the banding operation converts the 9-bit signed number to a 7-bit signed number. In other words, the data range is converted from [-128, 127] to [-32, 31].

[0145] The calculation process of the above-described pipeline from level 2 to level 5 is similar to the calculation process of the variable node update unit in step S102 of the overlapping partial parallel decoding algorithm described above.

[0146] like Figure 18 This is a complete timing diagram of the decoder's iterative process after the addition of the pipeline, where CNU is the check node update unit and VNU is the variable node update unit. At time t0, VNU has reached the 4th stage of the pipeline, meaning it has completed the vertical update. The calculation has been completed, thus satisfying the prerequisites for the decision, and the decision calculation in step S103 can be performed, that is: if L(q) j If ) < 0, then c j =1, otherwise c j =0. Therefore, at time t0, the verification enable is started, and the decision bit is generated immediately.

[0147] In the pipeline of the variable node update unit, the first stage, which converts the input data into signed numbers, should ideally be completed by the check node update unit in the last stage. This invention assigns this part of the combinational logic circuit to the variable node update unit, thereby balancing the delay path lengths of the check node update unit and the variable node update unit. In other words, the pipeline stages of the variable node update unit and the check node update unit are equal, allowing them to complete their respective iterative update processes synchronously within the same clock cycle. Conversely, if the two pipeline stages are different, for example, one is 4 stages and the other is 8 stages, then one iteration requires waiting for the 8-stage update unit to complete its iteration before it can be completed. This invention's design of setting the pipeline stages of both equal not only reduces the number of clock cycles required for the decoder to complete one iteration but also synchronizes the operating speeds of the check node update unit and the variable node update unit, reducing the design complexity of the control unit 102 state machine.

[0148] Example 2

[0149] Furthermore, such as Figure 7 As shown, the present invention provides a memory addressing method that is more suitable for high-parallelism decoders. This memory addressing method not only avoids the address access conflict problem, but is also simple and efficient.

[0150] like Figure 7 As shown, the method includes:

[0151] S201: Allocate RAM array;

[0152] S202: Store the initial channel information in the RAM array by bit splicing;

[0153] S203: Calculate and save the starting read address and starting offset address of the RAM in the RAM array;

[0154] S204: Generate the read address and offset address of the RAM;

[0155] S205: Read the information in RAM according to the read address of RAM, adjust the data bit order of the information according to the offset address, and send it to the verification node update unit or the variable node update unit for processing;

[0156] S206: Write the information processed by the check node update unit or the variable node update unit into the corresponding RAM in sequence.

[0157] Steps S204 to S206 above are executed in sequence during each iteration.

[0158] Furthermore, step S201 includes allocating a RAM array for initial channel information and allocating a RAM array for intermediate transmission information.

[0159] Furthermore, Figure 8 The diagram shows the array distribution of RAM in the first storage RAM 1036 for storing initial channel information. There are 16 RAM blocks in total. Referring to the definition of sub-circular matrix A in the parity check matrix H, the two sub-circular matrices A in each column of the following formula share the same RAM block. For example, A1,1 and A2,1 share the same RAM block.

[0160]

[0161] The initial channel information is divided into groups of 511, and one RAM block is responsible for storing each group of initial channel information. The first group contains only 493 initial channel information, because there are 18 frozen bits (0) before the information bits, and the last two initial channel information are padding information and can be ignored.

[0162] Furthermore, Figure 9 The diagram shows the array distribution of the RAM for storing intermediate transmission information. Since element 1 in the check matrix represents the definite connection between the check node and the variable node for information transmission, the intermediate transmission information in this invention is set to include vertical update information (generated during vertical update) and horizontal update information (generated during horizontal update). The RAM for storing intermediate transmission information is divided into a second RAM 1037 and a third RAM 1038. The second RAM 1037 is used to store vertical update information, and the third RAM 1038 is used to store horizontal update information.

[0163] Specifically, according to the definition of the parity-check matrix H, a sub-circular matrix A has two trajectories with elements 1. Therefore, four RAM blocks are allocated to each sub-circular matrix A: two blocks belong to the second storage RAM 1037, used to store the vertical update information of the sub-circular matrix A during iterative updates; and two blocks belong to the third storage RAM 1038, used to store the horizontal update information of the sub-circular matrix A during iterative updates. Therefore, Figure 9 The display shows the array distribution of RAM storing vertical or horizontal update information. Specifically, the RAM array storing vertical update information includes 64 RAM blocks, and the RAM array storing horizontal update information also includes 64 RAM blocks.

[0164] Furthermore, step S202 also includes:

[0165] The parity-check matrix H is evenly divided into 14 rows and 112 columns, with each block having a minimum submatrix size of 73×73. Each minimum submatrix is ​​iteratively updated simultaneously. This refines the 511×511 subcircular matrix A into seven 73×73 minimum submatrices B, further improving the parallel computing speed. When the minimum submatrix is ​​73×73, the decoder completes one iteration in only 73+α clock cycles, where α depends on the number of pipeline stages inserted in the decoder. As shown in Example 1, if 6 pipeline stages are added to both the parity node update unit and the variable node update unit, then one iteration requires 73+5=78 clock cycles.

[0166] Furthermore, each channel initial information input to the LDPC decoder after demodulation is subjected to amplitude-limited quantization before storage, i.e., (6, 7) quantization. This means the channel initial information is quantized with 6 bits, and the intermediate transmission information is quantized with 7 bits. In other words, the channel initial information uses 1 sign bit and 5 absolute bits, while the intermediate transmission information has one more decimal place than the initial information. For example, for a received frame of channel initial information containing 8176 bits, each bit of the channel initial information to be processed is quantized into 6 bits before storage.

[0167] Specifically, refer to Figure 23 When designing an LDPC decoder, fixed-point quantization of the information variables during the decoding process is required, which inevitably leads to a partial loss in decoding performance. Clearly, the more quantization bits, the smaller the performance loss, but the greater the hardware resource consumption. To determine the final quantization bit depth of the decoder, simulation experiments were conducted on three quantization methods, expressed in the form of (x, y), where x represents the number of quantization bits for the initial channel information, and y represents the number of quantization bits for the intermediate transmitted information. This is because a correction factor less than 1 is required during horizontal updates; therefore, an additional bit is added to the quantization bits for the initial channel information to represent the decimal places, thus maximizing the quantization accuracy of the decoder.

[0168] from Figure 23 As can be seen, the three values ​​of quantization method (x, y) (6, 7), (7, 8) and (8, 9) correspond to three different curves. The horizontal axis is the bit signal-to-noise ratio Eb / N0, and the vertical axis is the bit error rate (also known as the bit error rate).

[0169] When the bit signal-to-noise ratio Eb / N0 is less than 3.0, the three curves basically overlap. That is to say, when the bit signal-to-noise ratio Eb / N0 < 3.0, the bit error rate of these three curves decreases by the same amount as the bit signal-to-noise ratio Eb / N0 increases.

[0170] When the bit signal-to-noise ratio (SNR) Eb / N0 > 3.0, the decrease in bit error rate (BER) as the SNR increases for these three curves differs. It can be seen that at any SNR value (e.g., when Eb / N0 = 3.5), the BER gradually decreases as the number of quantization bits in the quantization method increases, i.e.:

[0171] The bit error rate of (8, 9) is less than that of (7, 8) and the bit error rate of (6, 7).

[0172] Furthermore, when the bit signal-to-noise ratio (Eb / N0) > 3.0, as the Eb / N0 increases, the bit error rate (BER) of (7, 8) decreases less compared to (6, 7), while (8, 9) shows a greater BER decrease compared to (6, 7), but higher quantization bits also require more hardware resources. Therefore, this invention selects (6, 7) quantization as the optimal method.

[0173] Furthermore, multiple initial channel information or intermediate transmission information are stored in a single address in RAM by bit concatenation, specifically by linking the first and last bits together. For example... Figure 10 The diagram shown illustrates the storage of a set of initial channel information. Figure 10 Seven squares of the same gray level represent a memory address in RAM. The seven data points in an address are assigned offsets of 1-7 in order from left to right, and adjacent data points are spaced 73 bits apart. Each data point contains seven bits.

[0174] Furthermore, by setting the bit width of a RAM block to 49 and the depth to 73, a set of initial channel information of length 511 can be stored in a single RAM block through bit concatenation, where 511 represents the number of data items, and each data item contains 6 bits. This concatenation method improves the parallelism of decoded data processing and simplifies the implementation of simultaneous horizontal and vertical updates.

[0175] Furthermore, in steps S203 to S206, in order to more efficiently realize the reading and writing of intermediate transmitted information by the verification node update unit and the variable node update unit, the following steps were used: Figure 11 The "simplified reading and simplified writing" memory addressing mode is shown. During reading, the data is read from the real-time generated read address, and the data bit order is adjusted according to the real-time generated offset address before being output to the variable node update unit or the check node update unit. During writing, the information processed by the variable node update unit or the check node update unit is directly concatenated bit by bit and written sequentially to the corresponding RAM, starting at address 0, without requiring the calculation and addressing operations of the read address and offset address during reading.

[0176] Specifically, each RAM block in the second storage RAM 1037 and the third storage RAM 1038 has a corresponding start read address, start offset address, and offset address. The offset address is marked as OA (3 bits).

[0177] Further, step S203 calculates the starting read address and the starting offset address using the following method:

[0178] For the 64 RAM blocks in the second storage RAM1037:

[0179] The first step is to retrieve the positions of the 64th element (1) in the first row and the 512th row of the parity check matrix H to obtain the first position index;

[0180] The second step is to normalize all the first position indices to the interval (1, 511) to obtain the second position index. The second position index is the remainder obtained by dividing the first position index by 511. If the first position index is less than 511, the second position index is still assigned the value of the first position index.

[0181] The third step is to divide the interval (1, 511) into 7 sub-intervals with an interval of 73. Based on the different sub-intervals where the second position index is located, the corresponding RAM is assigned a starting offset address of 1 to 7. The starting offset address is obtained by dividing the second position index by 73 and then rounding it up.

[0182] The fourth step is to normalize the second position index to the interval (1, 73) to obtain the third position index. Then, subtract 1 from the third position index to obtain the starting read address. The third position index is the remainder obtained by dividing the second position index by 73.

[0183] For the 64 RAM blocks in the third storage RAM1038, first retrieve the position index of the 64th element 1 in the 511*n+1th column (n=0,1,…,15) of H. The other operations are the same as above, as follows:

[0184] The first step is to retrieve the position of the 64th element 1 in the 511*n+1th column of the parity matrix H to obtain the first position index, where n is an integer, and the values ​​are n = 0, 1, ..., 15.

[0185] The second step is to normalize all the first position indices to the interval (1, 511) to obtain the second position index; where the second position index is the remainder obtained by dividing the first position index by 511.

[0186] The third step is to divide the interval (1, 511) into 7 sub-intervals with an interval of 73. Based on the different sub-intervals in which the second position index is located, the corresponding RAM is assigned a starting offset address of 1 to 7. The starting offset address is obtained by dividing the second position index by 73 and then rounding it up.

[0187] The fourth step is to normalize the second position index to the interval (1, 73) to obtain the third position index. Then, subtract 1 from the third position index to obtain the starting read address. The third position index is the remainder obtained by dividing the second position index by 73.

[0188] Furthermore, the calculation process for the starting read address and starting offset address of the 64 RAM blocks in the second storage RAM 1037 is given below:

[0189] Here, the first index positions of element 1 in the first row and the 512th row of the parity-check matrix H are respectively denoted as RA1st. 1,j and RA1st 512,j j = 1, 2, ..., 32, the starting offset address is denoted as OA1st 1,j and OA1st 512,j ,j=1,2,…,32.

[0190] The first step is to retrieve the index of the first position of element 1 in the first row of the parity matrix H:

[0191] P 1,j =find(H(1,:)==1);j=1,2,…,32;

[0192] The second step is to put P 1,j and P 512,j Normalized to the interval [1-511]:

[0193] for j=1:32

[0194] while P 1,j >511

[0195] P 1,j =P 1,j -511;

[0196] end

[0197] End

[0198] Third step, based on P 1,j Different starting offset addresses are assigned to different intervals:

[0199] Switch P 1,j

[0200] Case[1,73]

[0201] OA1st 1,j =1;

[0202] Case[74,146]

[0203] OA1st 1,j =2;

[0204] Case[147,219]

[0205] OA1st 1,j =3;

[0206] Case[220,292]

[0207] OA1st1,j =4;

[0208] Case[293,365]

[0209] OA1st 1,j =5;

[0210] Case[366,438]

[0211] OA1st 1,j =6;

[0212] Case[439,511]

[0213] OA1st 1,j =7;

[0214] end

[0215] Step 4, P 1,j and P 512,j Normalized to the interval [0-72]:

[0216] for j=1:32

[0217] while P 1,j >73

[0218] P 1,j =P 1,j -73;

[0219] end

[0220] while P 512,j >73

[0221] P 512,j =P 512,j -73;

[0222] end

[0223] P 1,j =P 1,j -1;

[0224] P 512,j =P 512,j -1;

[0225] End

[0226] Furthermore, after calculating the starting read address and starting offset address using the above method in step S203, the starting read address and starting offset address are saved for use in subsequent iterations. Once calculated, the starting read address and starting offset address do not need to be modified; that is, for the decoder in this invention, they are unique and unchanging constant data. Therefore, the starting read address and starting offset address can be saved in a local file that the decoder can read, or they can be initialized and written into the decoder's addressing unit when the decoder is started, for use in calculating new read addresses and offset addresses in subsequent iterations.

[0227] Further, step S204 includes: during each iteration, the read address is incremented by 1 with each rising edge of the system clock, and when address 72 is reached, the next clock cycle returns to address 0. The offset address is incremented by 1 when the read address returns from address 72 to address 0, and remains unchanged at other times.

[0228] Further, step S205 includes: data bit order adjustment is implemented using a barrel shift register, where the input data is cyclically shifted left according to the value of offset address OA before output. For example: OA = 1, the input data remains unchanged; OA = 2, the input data is cyclically shifted left by 7 bits; OA = 3, the input data is cyclically shifted left by 14 bits; and so on, with OA taking the value of an integer from 1 to 7. After this cyclic processing, the output data is sent to the variable node update unit and the check node update unit for subsequent calculation processing.

[0229] Further, step S206 includes: concatenating the output data of the variable node update unit or the check node update unit in a specific order, and then writing it sequentially into the corresponding RAM starting from address 0.

[0230] Specifically, the present invention will now be described using... Figure 1 Taking the L1 trajectory as an example, this section explains the specific data reading and writing process for the horizontal and vertical updates corresponding to this trajectory.

[0231] like Figure 1 As shown, the position index of element 1 in the first row is 177. After calculation, the starting read address of the second storage RAM 1037 is 30, and the starting offset address is 3. Specifically, since 177 is less than 511, the second position index is 177. Dividing by 73 and rounding up, we get the starting offset address as 3. The third position index is the remainder 31 after dividing 177 by 73. Since 31-1=30, 30 is the starting read address.

[0232] For details, please refer to the following: Figure 12aThe horizontal update process shown in -c is as follows: After the iteration process begins, the read address slides sequentially from address 30, while the offset address remains unchanged until the read address returns from address 72 to address 0, at which point the offset address is incremented by 1 to become 4. When the check node update unit (variable node update unit) starts outputting data, the output data of the check node update unit is concatenated bit by bit in top-to-bottom order and written sequentially to the third storage RAM 1038, starting at address 0.

[0233] Figure 12a If the read pointer points to the starting read address 30 of the second memory RAM, and the starting offset address OA is 3, then the data is read from the starting read address 30 of the second memory RAM. The bit order of this read data is then adjusted. Since the starting offset address OA = 3, it needs to be shifted left by two data bits. For example, it can be seen that... Figure 12a The "3" in the input data is obtained by left-shifting the "3" in the read data by 2 data bits. Then, this input data is processed into the output data D1D2D3D4D5D6D7 of the check node update unit, which is then concatenated bit by bit to form the write data D1D2D3D4D5D6D7, and finally written to address 0 of the write pointer in the third storage RAM. It's important to note that adjusting the bit order here refers to adjusting the data bits; when each data point is represented by 7 bits, the corresponding left-shift adjustment involves 2 * 7 = 14 bits.

[0234] Figure 12b The read pointer points to read address 72 of the second memory RAM, and the offset address OA is 3. The data is then read from read address 72 of the second memory RAM. The bit order of this read data is then adjusted. Since the offset address OA = 3, the data needs to be shifted left by two bits. Figure 12a The same applies in the middle. Then, the input data is processed into the output data D1D2D3D4D5D6D7 of the check node update unit, which is then concatenated bit by bit into the write data D1D2D3D4D5D6D7, and then written to the address 42 corresponding to the write pointer in the third storage RAM for storage.

[0235] Figure 12c The read pointer points to read address 0 of the second storage RAM. The offset address OA is incremented by 1, becoming 4. The data is then read from read address 0 of the second storage RAM. The bit order of this read data is adjusted; since offset address OA = 4, it needs to be shifted left by three data bits, which is 3 * 7 = 21 bits. This input data is then processed into the check node update unit output data D1D2D3D4D5D6D7, which is concatenated bit by bit to form the write data D1D2D3D4D5D6D7, and then written to address 43 of the third storage RAM corresponding to the write pointer for storage. Figure 12a As shown in -c, the write pointers correspond to 0, 42, and 43 respectively, indicating sequential writing to the third-level RAM without offset addresses. This achieves the process of simplified writing after complex reading.

[0236] Further, refer to Figure 1 During vertical updates, the position index of element 1 in the first column is 336. After calculation, the starting read address of the third storage RAM1038 is 43, and the starting offset address is 5. Specifically, since 336 is less than 511, the second position index is 336. Dividing this by 73 and rounding up, we get the starting offset address as 5. The third position index is the remainder of 44 after dividing 336 by 73. Since 44-1=43, 43 is the starting read address.

[0237] For details, please refer to the following: Figure 13a The vertical update process shown in -c is similar to the horizontal update process, and is also simplified in traditional Chinese.

[0238] Figure 13a The read pointer points to the starting read address 43 of the third memory RAM, and the offset address OA is 5. The data is then read from the starting read address 43 of the third memory RAM. The bit order of this read data is then adjusted. Since the offset address OA = 5, it needs to be shifted left by 4 data bits. For example, it can be seen that… Figure 13a The "5" in the input data is obtained by left-shifting the "5" in the read data by 4 data bits. Then, this input data is processed into the variable node update unit output data D1D2D3D4D5D6D7, which is then concatenated bit by bit to form the write data D1D2D3D4D5D6D7, and finally written to address 0 of the write pointer in the second storage RAM. It's important to note that adjusting the bit order here refers to adjusting the data bits; when each data point is represented by 7 bits, the corresponding left-shift adjustment involves 2 * 7 = 14 bits.

[0239] Figure 13b The read pointer points to read address 72 of the third memory RAM, and the offset address OA is 5. The data is then read from read address 72 of the third memory RAM. The bit order of this read data is then adjusted. Since the offset address OA = 5, it needs to be shifted left by 4 data bits. Figure 13a Similar to the above. Then, the input data is processed into the variable node update unit output data D1D2D3D4D5D6D7, which is then concatenated bit by bit to form the write data D1D2D3D4D5D6D7, and then written to the address 29 corresponding to the write pointer in the second storage RAM for storage.

[0240] Figure 13cThe read pointer points to read address 0 of the third storage RAM. The offset address OA is incremented by 1, becoming 6. The data is then read from read address 0 of the third storage RAM. The bit order of the read data is then adjusted. Since the offset address OA = 6, it needs to be shifted left by 5 data bits, which is 5 * 7 = 35 bits. This input data is then processed into the variable node update unit output data D1D2D3D4D5D6D7, which is then concatenated bit by bit to form the write data D1D2D3D4D5D6D7, and finally written to address 30 of the second storage RAM corresponding to the write pointer for storage.

[0241] Example 3

[0242] Further, refer to Figure 18-22 The present invention optimizes the design of the verification unit.

[0243] The verification unit is mainly responsible for verifying the decoding result generated after each iteration and counting the number of iterations. The conventional verification method is H·c. T =0, meaning the decoding result is substituted into the parity matrix H to calculate the parity value. If the parity value is 0, the decoding is correct, and the decision bit is output; otherwise, the decoding is incorrect, and the process is to continue iterating or exit decoding. However, this verification method is complex to implement with hardware circuitry, and the verification process requires a long clock cycle, which does not meet the design requirements of high-speed decoding.

[0244] This invention proposes a more practical verification method for LDPC decoders, such as... Figure 19 As shown, the steps include:

[0245] S301: During the Nth iteration update, store the decision result generated by the iteration update as the Nth decision result, where N is a positive integer greater than or equal to 1;

[0246] S302: Compare and verify the Nth judgment result with the (N-1)th judgment result to obtain the Nth verification result. The Nth verification result may be the same or different.

[0247] S303: Judge the result of the Nth verification. If the result of the Nth verification is the same or N reaches the maximum number of iterations, then jump to step S304; otherwise, end the current verification.

[0248] S304: Output the decoding result.

[0249] Specifically, the decision result consists of bits with values ​​of 1 or 0. By concatenating all the decision results obtained when one iteration is completed, the complete decoding result is obtained.

[0250] The above method essentially compares the decoding result of the current iteration with the decoding result of the previous iteration. If the two decoding results are the same, the decoding is considered complete; otherwise, the iteration continues until the maximum number of iterations is reached. This method is based on the convergence of the decoding algorithm, meaning that if the decoding is correct, subsequent iterations should also yield correct results, thus reducing the complexity of the hardware circuit implementation.

[0251] Furthermore, step S302 also includes:

[0252] S3021: The Nth decision result includes multiple Nth decision bits generated in real time at different times;

[0253] S3022: Compare and verify the newly generated Nth decision bit at each time step with the corresponding N-1th decision bit at the same time step;

[0254] S3023: If the comparison and verification results are different, stop the comparison and verification, and confirm that the Nth verification result is different.

[0255] The N-1th decision bit at the corresponding time refers to the N-1th decision bit generated at the same time in the previous iteration update.

[0256] Specifically, let the result of the Nth decision be a set of bits b = [b1, b2, ..., bM], where bM is the Nth decision bit newly generated at time M;

[0257] Accordingly, let the result of the (N-1)th decision be a set of bits a = [a1, a2, ..., aM], where aM is the newly generated (N-1)th decision bit at time M;

[0258] Step S3022 refers to: at time M, comparing and verifying bM with aM.

[0259] Specifically, as described in Example 2, the update time for each iteration is equal to the update time for the smallest submatrix. For example, if the smallest submatrix is ​​73*73, then 73 clock cycles are required to complete one iteration update. Correspondingly, each smallest submatrix will generate decision bits sequentially at 73 time points. Assuming that the comparison results are the same from time point 1 to time point 49, the comparison and verification continues at time point 50. If the comparison and verification results are different at time point 50, the comparison and verification stops, and it is confirmed that the verification results of this iteration update are different, thus avoiding the need to wait for all 73 decision bits to be compared before obtaining the result.

[0260] Therefore, it can be seen that since the LDPC code used in this invention has a code length of 8176 bits, direct verification would require two 8176-bit registers: one to store the decoding result of the previous iteration and the other to store the decoding result of the current iteration, followed by a complete comparison between the two. However, by using the method of real-time comparison at each moment, continuously input decision bits can be compared in real time. Once a decision bit is detected to be inconsistent with the previous iteration, the current decoding result is determined to be erroneous regardless of whether subsequent decision bits are the same. This eliminates the need to compare the complete LDPC codes generated by two iterations. Instead, once a different bit is detected in the middle, the current verification result is confirmed to be different, thus determining the current decoding result to be erroneous. This allows the verification result to be obtained before obtaining the complete decoding, further improving efficiency and saving storage resources.

[0261] Furthermore, in order to save storage space and further improve computing efficiency, the storage scheme of the verification unit adopted in this invention is specifically described below.

[0262] Furthermore, step S301 also includes:

[0263] The parity check matrix H of the LDPC code is divided into 14 blocks according to rows and 112 blocks according to columns, thereby dividing the 511×511 subcircular matrix A into 7 73×73 minimum submatrices B. Each minimum submatrice B is iteratively updated simultaneously during each iteration.

[0264] The number of bits in a set of decision bits generated in real time at the same moment is determined to be 98;

[0265] A total of 98 decision bit registers, each with a length of 73 bits, are set up to store the decision bits.

[0266] Specifically, Figure 2 The transmission frame structure of the (8176, 7154) LDPC code specified by CCSDS is given. For example... Figure 2 As shown, since the first 18 bits are frozen bits (0) and not transmitted, a complete transmission frame contains only 8160 bits, of which the first 7136 bits are information bits, the middle 1022 bits are parity bits, and the last two bits are padding bits (0). As seen in the previous embodiment, the LDPC code's parity-check matrix H is evenly divided into 14 rows and 112 columns, thus dividing the 511×511 sub-circular matrix A into seven 73×73 minimum sub-matrices B. During each iteration update, each of these minimum sub-matrices B is simultaneously iterated and updated.

[0267] 7136 + 18 = 7154 = 73 * 98;

[0268] Based on the above calculations, it can be deduced that the 7136 information bits of the LDPC code contain at most 98 73×73 minimum submatrices B. Therefore, the number of decision bits generated at the same time during each iteration update is determined to be 98.

[0269] Furthermore, step S301 also includes:

[0270] The decision bits generated at different times are stored in the decision bit register in ascending order;

[0271] When storing a set of decision bits, first shift the bit data in each decision bit register one bit to the left, and then store each decision bit into the 0th bit of a decision bit register. Each decision bit register stores one decision bit, with the 0th bit being the least significant bit.

[0272] Once the Nth decision result is stored, it will overwrite the (N-1)th decision result stored in the decision bit register, thus reusing the decision bit register.

[0273] Furthermore, step S302 also includes:

[0274] When a set of decision bits is stored, the highest decision bit in the decision bit register is shifted out and another set of decision bits is formed. The two sets of decision bits are compared and verified, and the comparison result is recorded. The comparison result is either the same or different.

[0275] Furthermore, step S302 also includes:

[0276] During the comparison and verification, the 98 decision bits generated in this iteration are concatenated to obtain the current decision comparison signal. The highest decision bit before the decision bit register is shifted left is concatenated to obtain the previous decision comparison signal. Then, the current decision comparison signal is compared with the previous decision comparison signal to obtain the comparison result.

[0277] The specific implementation method is as follows:

[0278] refer to Figure 18 Where CNU is the check node update unit and VNU is the variable node update unit. When the decoder reaches the fourth level of the variable node update unit (or check node update unit), that is... Figure 18 At time t0, the first set (98) of decision bits is generated. The check enable CE is pulled high at this time, and the check unit begins to check and store the decision bits.

[0279] Specifically, the reason why each set of decision bits consists of 98 bits is as follows:

[0280] refer to Figure 2The initial information frame of a channel contains 18 + 7136 = 7154 frozen bits and information bits. Therefore, only the first 7154 data bits need to be judged to obtain the true information; the subsequent check bits do not need to be considered. In this invention, the smallest submatrix is ​​73*73, and 7154 = 73*98; therefore, 98 decision bits are generated each time.

[0281] Figure 20 The diagram illustrates the verification storage process. Msg_i, i = 1, 2, ..., 98 are registers responsible for storing decision bits, each 73 bits long. Err is the error flag signal, initially 0 (0 indicates no error, 1 indicates an error). Bin[97:0] is a signal formed by concatenating the 98 decision bits generated in this iteration, and Ref_Bin[97:0] is a signal formed by concatenating the most significant bit of register Msg_i, i = 1, 2, ..., 98. When the verification unit detects that the verification enable CE is high, register Msg_i shifts left by one bit and stores the corresponding decision bit in bit 0. Simultaneously, Bin[97:0] and Ref_Bin[97:0] are compared. If they are the same, the Err signal (error value) remains unchanged; otherwise, the Err signal (error value) is set to 1. After 73 clock cycles, the verification unit completes the storage and preliminary verification of 7154 decision bits.

[0282] Subsequent verification sub-processes are as follows Figure 21 As shown, the error value corresponds to the Err signal mentioned above, the current error value corresponds to the signal Bin[97:0], and the previous error value corresponds to the signal Ref_Bin[97:0]. First, the iteration count is initialized to 0, and then the first iteration verification begins. At the beginning of each iteration verification, the error values ​​are initialized to 0, and then it is determined whether the decision bits have been input. Since decision bits are continuously generated, it is necessary to re-determine whether the decision bits have been input whenever a new set of decision bits is input. If it is determined that there are still new input decision bits, the current decision bit signal is compared with the previous decision bit signal. If the comparison result is different, the error value is set to 1; if the comparison result is the same, the error value remains unchanged at 0. When all decision bits have been input and the comparison is completed, the error value and iteration count are judged. If the error value is 0 or the maximum iteration count has been reached, the decoding result is output; otherwise, the iteration count is incremented by 1, and the next round of verification is awaited. The preferred maximum iteration count of this invention is 15.

[0283] The maximum number of iterations is a key parameter affecting the performance of an LDPC decoder. Generally, a higher number of iterations results in better decoding performance, but also increases decoding latency. Therefore, a suitable maximum number of iterations needs to be selected to balance decoding performance and latency.

[0284] Figure 24 The decoding performance curves for different maximum iteration counts are presented, including maximum iteration counts of 10, 15, and 20. The horizontal axis represents the bit signal-to-noise ratio (Eb / N0), and the vertical axis represents the bit error rate (BER).

[0285] When the bit signal-to-noise ratio Eb / N0 is less than 3.5, the three curves basically overlap. That is to say, when the bit signal-to-noise ratio Eb / N0 < 3.5, the bit error rate of these three curves decreases by the same amount as the bit signal-to-noise ratio Eb / N0 increases.

[0286] When the bit signal-to-noise ratio (SNR) Eb / N0 > 3.5, the decrease in bit error rate (BER) for these three curves with increasing Eb / N0 varies. It can be seen that at any given ENR value (e.g., Eb / N0 = 3.8), the BER gradually decreases with increasing maximum iteration count, i.e.:

[0287] The bit error rate of 20 is less than the bit error rate of 15, which is less than the bit error rate of 10.

[0288] Furthermore, when the bit signal-to-noise ratio (SNR) Eb / N0 > 3.5, as the SNR Eb / N0 increases, the bit error rate decreases significantly with a maximum iteration count of 15 compared to a maximum iteration count of 10, while the decrease is smaller with a maximum iteration count of 20 compared to a maximum iteration count of 15. This indicates that increasing the maximum iteration count from 10 to 15 significantly improves decoding performance, while increasing it from 15 to 20 provides a relatively smaller improvement. Therefore, to achieve a higher decoding rate (lower decoding delay) while maintaining decoding performance, this paper selects a maximum iteration count of 15.

[0289] The above verification storage method requires only 98 registers, each 73 bits long. The length of the bit vector involved in the comparison is reduced from 8176 bits to 98 bits, significantly reducing the consumption of hardware resources. More importantly, it improves the verification speed. Figure 18 It can be seen that it can provide the verification result at time t1, that is, before the end of this iteration process, which meets the design requirements of the high-speed decoder.

[0290] Furthermore, step S302 also includes:

[0291] While storing a set of decision bits, read the comparison result of the previous set of decision bits and make a judgment. If the comparison result is the same, continue the comparison; if the comparison result is different, stop the comparison.

[0292] Specifically, while storing a set of decision bits, the comparison result of the previous set of decision bits is read and judged. If the comparison result is the same, the comparison continues; if the comparison result is different, the comparison is stopped. This can further save CPU resources. For example, if the comparison result is different when the 50th clock arrives, the comparison will stop from the 51st clock, saving 23 comparison calculations for the two 98-bit sequences in the following 23 clock cycles.

[0293] Furthermore, step S304 also includes:

[0294] The decoding result is obtained by concatenating the decision results generated by the iterative update. In fact, the codewords in the decoding correspond to the decision bits in the decision result.

[0295] On the other hand, such as Figure 22 As shown, the present invention provides a verification device 201 suitable for LDPC decoders, comprising: a receiving unit 2011, a storage unit 2012, a comparison unit 2013, and a control unit 2014;

[0296] The receiving unit 2011 receives the decision result generated by the iterative update in the LDPC decoder and stores it in the storage unit 2012;

[0297] The storage unit 2012 stores the decision bits from the decision results generated at different times into the register in ascending order. Each time a new bit is stored, the register is shifted left by one bit, thus reusing the register.

[0298] The control unit 2014 makes a judgment to determine when to start and stop the comparison, and whether to output the decoding result generated by the iterative update in the LDPC decoder;

[0299] The comparison unit 2013 receives instructions from the control unit 2014 and reads the decision bits from the storage unit 2012 for comparison and verification.

[0300] In another aspect, the present invention provides an LDPC decoder, including the verification device 201 as described above for an LDPC decoder.

[0301] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A memory addressing method suitable for an LDPC decoder, characterized in that, include: S201: Allocate RAM array; The RAM array includes a first storage RAM for storing channel initial information, and a second storage RAM and a third storage RAM for storing intermediate transmission information. The intermediate transmission information includes vertical update information and horizontal update information. The second storage RAM is used to store vertical update information, and the third storage RAM is used to store horizontal update information. 16 RAM blocks are allocated to the first storage RAM, 64 RAM blocks are allocated to the second storage RAM, and 64 RAM blocks are allocated to the third storage RAM, wherein each RAM block can store 511 data blocks of 7 bits in length; S202: Store the initial channel information in the RAM array by bit splicing; The parity check matrix H used by the LDPC decoder is evenly divided into 14 blocks according to rows and 112 blocks according to columns. The size of each smallest submatrix after the division is 73×73. Each smallest submatrix is ​​iteratively updated simultaneously. S203: Calculate and save the starting read address and starting offset address of the RAM in the RAM array; S204: Generate the read address and offset address of the RAM based on the starting read address and the starting offset address; S205: Read the information in RAM according to the read address of RAM, adjust the data bit order of the information according to the offset address, and send it to the verification node update unit or the variable node update unit for processing; S206: Write the information processed by the check node update unit or the variable node update unit into the corresponding RAM in sequence.

2. The memory addressing method suitable for LDPC decoder according to claim 1, characterized in that, Step S202 further includes: When storing, the initial channel information is quantized using 6 bits, and the intermediate transmission information is quantized using 7 bits. That is, the data of the initial channel information includes 1 sign bit and 5 absolute bits, and the data of the intermediate transmission information has one more decimal place than the data of the initial channel information.

3. The memory addressing method suitable for LDPC decoder according to claim 2, characterized in that, The method of mid-position splicing in step S202 also includes: The initial channel information is grouped, with each group containing 511 data points. The bit width of each RAM block is set to 49, and the depth is set to 73.

4. The memory addressing method suitable for LDPC decoder according to claim 3, characterized in that, Step S202 further includes: Each of the RAM blocks contains 0-72 memory addresses, each memory address stores 7 data items, and each data item contains 7 bits; The seven data points are assigned offset addresses from 1 to 7 in order from left to right, and adjacent data are spaced 73 bits apart during storage.

5. The memory addressing method suitable for LDPC decoder according to claim 4, characterized in that, Step S203 uses the following method to calculate the starting read address and starting offset address of the 64 RAM blocks in the second storage RAM: The first step is to retrieve the positions of the 64th element (1) in the first row and the 512th row of the parity check matrix H to obtain the first position index; The second step is to normalize all the first position indices to the interval (1, 511) to obtain the second position index; where the second position index is the remainder obtained by dividing the first position index by 511. The third step is to divide the interval (1, 511) into 7 sub-intervals with an interval of 73. Based on the different sub-intervals in which the second position index is located, the corresponding RAM is assigned a starting offset address of 1 to 7. The starting offset address is obtained by dividing the second position index by 73 and then rounding it up. The fourth step is to normalize the second position index to the interval (1, 73) to obtain the third position index. Then, subtract 1 from the third position index to obtain the starting read address. The third position index is the remainder obtained by dividing the second position index by 73.

6. The storage addressing method for LDPC decoders according to claim 5, characterized in that, Step S203 uses the following method to calculate the starting read address and starting offset address of the 64 RAM blocks in the third storage RAM: The first step is to retrieve the first parity check matrix H. Find the index of the first position of the 64 elements 1 in the column, where n is an integer, and takes the values ​​sequentially. ; The second step is to normalize all the first position indices to the interval (1, 511) to obtain the second position index; where the second position index is the remainder obtained by dividing the first position index by 511. The third step is to divide the interval (1, 511) into 7 sub-intervals with an interval of 73. Based on the different sub-intervals in which the second position index is located, the corresponding RAM is assigned a starting offset address of 1 to 7. The starting offset address is obtained by dividing the second position index by 73 and then rounding it up. The fourth step is to normalize the second position index to the interval (1, 73) to obtain the third position index. Then, subtract 1 from the third position index to obtain the starting read address. The third position index is the remainder obtained by dividing the second position index by 73.

7. The storage addressing method for LDPC decoders according to claim 6, characterized in that, Step S204 also includes: During each iteration, the read address is cyclically assigned values ​​from 0 to 72, with each cycle containing 73 clock cycles; Each time the read address loops once, the offset address is incremented by 1.

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