Pixel unit, pixel array and image sensor
By introducing potential well control unit and parasitic capacitors into the pixel unit of the CMOS image sensor, the problem of difficult to shorten the conduction time of the transmission transistor is solved, and higher frame rate and signal reading efficiency are achieved, avoiding additional power consumption and area Overhead.
Patent Information
- Application Number
- CN202210891660.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-27
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2042-07-27
AI Technical Summary
When the existing CMOS image sensors shorten the signal reading cycle, the on-time of the transmission transistor is difficult to shorten, resulting in the ADC conversion time being unable to be further compressed, which in turn affects the frame rate and signal reading efficiency.
By introducing a potential well control unit into the pixel unit, a parasitic capacitance is formed using the potential well control line and the voltage driving circuit, the potential well difference between the photodiode and the transmission transistor is increased, the conduction speed of the transmission transistor is increased, and the conduction time is shortened.
It effectively shortens the on-time of the transmission transistor, reduces the time required for ADC conversion, improves the frame rate and signal reading efficiency of the image sensor, and avoids the defects of increasing power consumption and area overhead.
Smart Images
Figure CN115426461B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a pixel unit, a pixel array and an image sensor. Background Art
[0002] CMOS image sensors (CIS) have been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. With the increasing requirements of various applications, CIS not only needs to have high resolution, but also needs to have a higher frame rate, which requires the signal reading cycle of CIS to be further shortened. The mainstream CIS is read based on a column-parallel analog-to-digital converter (ADC) architecture. The ADC conversion time can be shortened by increasing the number of parallel ADCs and increasing the ADC clock frequency, but this is at the expense of increased power consumption and area overhead. When the ADC conversion time is compressed to a certain extent, it can no longer be shortened. At this time, it is necessary to reduce the time occupied by pixel operation. The most time-consuming operation in the pixel operation is the operation of the transfer transistor Mtg to transfer the photoelectrons in the photodiode FD. It needs to completely transfer the electrons in the photodiode PD, which requires a certain conduction time to ensure. If the conduction time is shortened, it will cause problems such as smearing and the inability to read small signals.
[0003] Therefore, the present invention proposes a pixel unit, a pixel array and an image sensor to shorten the conduction time of the transmission transistor Mtg, so as to shorten the time required for ADC conversion. Summary of the invention
[0004] The present invention provides a pixel unit, a pixel array and an image sensor to shorten the conduction time of the transmission transistor Mtg, so as to shorten the time required for ADC conversion.
[0005] In the first aspect, the present invention provides a pixel unit, comprising: a photodiode, a transfer transistor, a reset transistor, a source follower, a row selection transistor and a potential well control unit; the anode of the photodiode is grounded, and the cathode of the photodiode is connected to the source of the transfer transistor; the gate of the transfer transistor is used to receive a TX signal, the drain of the transfer transistor is connected to the source of the reset transistor, the gate of the source follower and one end of the potential well control unit, the potential well control unit is used to increase the potential well difference between a floating node and the photodiode, and the drain of the transfer transistor is the floating node; the drain of the reset transistor is connected to a power supply, and the gate of the reset transistor receives an RX signal; the drain of the source follower is connected to a power supply, the source of the source follower is connected to the drain of the row selection transistor, the gate of the row selection transistor receives a SEL signal, and the source of the row selection transistor serves as the output of the pixel unit.
[0006] Its beneficial effect is that by connecting the drain of the transfer transistor to the source of the reset transistor, the gate of the source follower and one end of the potential well control unit, the potential well difference between the floating node and the photodiode can be increased, so as to improve the transmission speed when the transfer transistor is turned on, shorten its conduction time, and thus shorten the time required for ADC conversion.
[0007] Optionally, the potential well control unit includes: a potential well control circuit. The beneficial effect is that compared with the background technology that achieves the purpose of shortening the conversion time of the ADC at the cost of increasing power consumption and area overhead, the present application can only form a parasitic capacitor between the potential well control circuit 601 and the peripheral devices, without the need to connect additional capacitors, which can save design space.
[0008] Optionally, the other end of the potential well control unit is connected to a voltage driving circuit, and the voltage driving circuit is used to provide voltage to the potential well control unit.
[0009] In a second aspect, the present invention provides a pixel array, comprising: pixel units as described in the first aspect arranged in an array; the other ends of all the potential well control units in the pixel array are connected together. Its beneficial effect is that by connecting the other ends of all the potential well control units together, the present application only needs one voltage control action or one voltage control device to achieve the purpose of voltage control of all the potential well control units in the pixel array.
[0010] In a third aspect, the present invention provides a CMOS image sensor, comprising: a pixel unit as described in any one of the first aspects or a pixel array as described in the second aspect, an analog-to-digital converter module, a ramp generator, a timing control module, a row selection decoding driving module, and an output signal processing module; the pixel unit or the pixel array is used to collect light signals and convert the light signals into electrical signals; the timing control module is used to control the working timing of the row selection decoding driving module, the ramp generator, the analog-to-digital converter module and the output signal processing module; the row selection decoding driving module is connected to the pixel array or the pixel unit, and is used to input a SEL signal to the pixel unit or the pixel unit in the pixel array; the analog-to-digital converter module is respectively connected to the pixel array or the pixel unit, and the ramp generator, and is used to obtain the output of the pixel unit or the pixel unit in the pixel array, and obtain the output of the ramp generator, and is used to output a corresponding digital signal; the output signal processing module is connected to the analog-to-digital converter module, and is used to process the digital signal output by the analog-to-digital converter module to generate image information.
[0011] Optionally, the analog-to-digital converter module includes: a comparator and a counter.
[0012] Optionally, the CMOS image sensor further includes: an inverter, wherein the inverter is connected between the comparator and the counter, and the inverter serves as a buffer for a comparison result of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 This is a schematic diagram of a CIS standard four-pixel unit circuit structure;
[0014] Figure 2 A schematic diagram of the working timing of a CIS standard four-tube pixel unit;
[0015] Figure 3 is a schematic diagram of the structure of a CIS;
[0016] Figure 4 A schematic diagram of the working sequence of a CIS;
[0017] Figure 5 A schematic structural diagram of a pixel unit embodiment provided in the present application;
[0018] Figure 6 A schematic structural diagram of another pixel unit embodiment provided by the present application;
[0019] Figure 7 A comparative schematic diagram of an image smear effect provided in this application. DETAILED DESCRIPTION
[0020] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "a", "the", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear indication to the contrary in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in a "or" relationship.
[0021] References to "one embodiment" or "some embodiments" etc. described in this specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connection" includes direct connection and indirect connection, unless otherwise specified. "First" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
[0022] In the embodiments of the present application, the words "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.
[0023] Figure 1It is a CIS standard four-tube pixel unit circuit structure, which is widely used in CIS with row exposure mode. It consists of a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, a source follower Msf, and a row selection transistor Msel. The anode of the photodiode PD is grounded, and the cathode is connected to the source of the transfer transistor Mtg; the gate of the transfer transistor Mtg is used to receive the TX signal, the drain of the transfer transistor Mtg is connected to the source of the reset transistor Mrst, and the gate of the source follower Msf; the drain of the reset transistor Mrst is connected to the power supply, and the gate of the reset transistor Mrst receives the RX signal; the drain of the source follower Msf is connected to the power supply, the source of the source follower Msf is connected to the drain of the row selection transistor Msel, the gate of the row selection transistor Msel receives the SEL signal, and the source of the row selection transistor Msel is connected to the row output line of the pixel array. When the photodiode PD is exposed to light, it generates photoelectrons proportional to the light intensity. The function of the transfer transistor Mtg is to transfer the photoelectrons in the photodiode PD. When the TX signal is at a high potential, the transfer transistor Mtg is turned on, and the photoelectrons in the photodiode PD are transferred to the floating node FD. The function of the reset transistor Mrst is to reset the potential of the floating node FD when the RX signal is at a high potential. The source follower Msf is an amplifier. When SEL is at a high potential, the row selection transistor Msel is turned on, and the source follower Msf, the row selection transistor Msel and the current source to the ground form a path. At this time, the source follower Msf follows the change in the potential of the floating node FD and is finally output by the output bus PIX_OUT.
[0024] Figure 2 for Figure 1The working sequence of the four-tube pixel unit shown is divided into reset (Rst), exposure (Exp), and signal reading (Read). In the Rst stage, the TX signal and the RX signal are at a "high" potential, the transmission transistor Mtg and the reset transistor Mrst are both turned on, the floating node FD is reset and its potential is pulled up to the power supply voltage VDD. After that, the RX signal and the TX signal become "low" potentials, and the Exp stage is entered, and the floating point PD is sensitive to light and accumulates electrons. Then, the Read stage is entered, SEL is at a "high" potential, the RX signal is first at a "high" potential, and after resetting the potential of the floating node FD, the RX signal is pulled to a "low" potential again, and the TX signal remains at a "low" potential. At this time, the source follower Msf is controlled by the potential of the floating node FD and outputs the reset potential VRST through the output bus PIX_OUT. After that, the TX signal is pulled to a "high" potential, and the electrons on the photodiode PD are transferred to the floating node FD. At this time, the source follower Msf is controlled by the potential of the floating node FD and outputs the integration potential VSIG through the output bus PIX_OUT. The difference between VRST and VSIG is the analog voltage corresponding to the photoelectrons on the photodiode PD. The VRST and VSIG potentials are converted into digital quantities by the analog-to-digital converter (ADC) circuit and subtracted to obtain the actual digital quantity corresponding to the photoelectrons on the photodiode PD. If the ADC is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT = (VRST-VSIG) × 2 12 / VREF.
[0025] Figure 3 The schematic diagram of the structure of CIS is shown in Figure 1. The CIS includes: pixel array, ADC module, ramp generator, timing control module, row selection decoding drive module, and output signal processing module. The pixel array consists of several modules such as Figure 1 The pixel unit P shown is composed of the pixel unit P shown. The pixel array is read out row by row, and the specific order is ROW(0), ROW(1), ... ROW(k-1), ROW(k). The k is a positive integer. Each column in the pixel array is connected to an output bus, and these output buses are PIX_OUT(0), PIX_OUT(1), ... PIX_OUT(n-1), PIX_OUT(n). The output ends of these output buses are connected to the ADC module. The ADC module is composed of a comparator and a counter. The comparator compares the output pixel signal with the ramp signal RAMP, and the comparison result determines the size of the counter count value. The ADC module will also judge the above-mentioned VRST and VSIG potentials respectively, and convert the VRST-VSIG difference into a digital output.
[0026] Figure 4 for Figure 3 The working timing of the CIS shown is Figure 2The Read phase of the timing. Entering the Read phase, SEL is pulled to a "high" potential, RX is a "high" potential, and the pixel unit is reset. RST_CM is the comparator reset control signal, and RST_CM is also pulled to a "high" potential to reset the comparators in all ADC modules. Then RX and RST_CM change from a "high" potential to a "low" potential, and the ADC module enters a normal working state. The working process of the ADC module consists of two processes: comparison and counting. First, when the ramp RAMP potential begins to decrease, the counter CNT starts counting until the comparator signal flips from a "low" potential to a "high" potential. The counter CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC module needs to perform the above operation twice, that is, as the benchmark of the ADC module, two ramps will be generated. The first ramp stage (that is, Figure 4 The ADC module will determine and store the reset potential VRST, and the counter CNT will count and store the count value CN1 corresponding to the t1 period during the t1 period; the second ramp stage (i.e. Figure 4 In the "VS phase" of the TX high pulse signal, the ADC module will determine and store the reset potential VSIG, and the counter CNT will count and store the count value CN2 corresponding to the t2 time period within the t2 time period. Finally, the counter CNT will output the count difference ΔCN=CN2-CN1, which corresponds to the difference between VSIG-VRST. From the above working process, it can be seen that the TX high pulse needs to take up a certain time between the two ramp signals. In order to ensure the integrity of the signal transmission, there are some intervals between the ramp signals before and after the TX high pulse, which are generally 0.1~0.2μs, and the TX high pulse maintenance time is generally determined according to the size of the pixel array, which is about 1μs. If the TX pulse width is compressed to a very short time, such as 0.1μs, it will cause problems such as image smearing and failure of small signal reading.
[0027] In order to solve the above problems, the present application provides a pixel unit, such as Figure 5As shown, it includes: a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, a source follower Msf, a row selection transistor Msel and a potential well control unit 501; the anode of the photodiode PD is grounded, and the cathode is connected to the source of the transfer transistor Mtg; the gate of the transfer transistor Mtg is used to receive a TX signal, the drain of the transfer transistor Mtg is connected to the source of the reset transistor Mrst, the gate of the source follower Msf and one end of the potential well control unit 501, and the potential well control unit 501 It can be used to form a parasitic capacitor to increase the potential well difference between the drain of the floating node FD (the transfer transistor Mtg) and the photodiode PD; the drain of the reset transistor Mrst is connected to the power supply VCC, and the gate of the reset transistor Mrst receives the RX signal; the drain of the source follower Msf is connected to the power supply, the source of the source follower Msf is connected to the drain of the row selection transistor Msel, the gate of the row selection transistor Msel receives the SEL signal, and the source of the row selection transistor Msel serves as the output of the pixel unit.
[0028] The present application connects the source of the reset transistor, the gate of the source follower and one end of the potential well control unit through the drain of the transfer transistor, thereby increasing the potential well difference between the floating node and the photodiode, thereby improving the transmission speed when the transfer transistor is turned on, shortening its conduction time, and thereby shortening the time required for ADC conversion.
[0029] In some embodiments, the potential well control unit includes: a potential well control circuit 601. Figure 6 As shown, the drain of the transfer transistor Mtg is connected to the source of the reset transistor Mrst, the gate of the source follower Msf and one end of the potential well control circuit 601, and the other end BST of the potential well control circuit is used to connect the voltage drive circuit 602, and the voltage drive circuit 602 is used to provide voltage to the potential well control circuit 601, so that a parasitic capacitance is formed between the potential well control circuit 601 and the peripheral devices. Compared with the background technology, which achieves the purpose of shortening the conversion time of the ADC at the cost of "increasing power consumption and area overhead", the present application can only form the parasitic capacitance between the potential well control circuit 601 and the peripheral devices, without the need to connect additional capacitors, which can save design space. The voltage drive circuit provided in the present application includes: a switch tube and a power supply.
[0030] Exemplarily, by default, the other end BST of the potential well control circuit is at a low potential (similar to being directly connected to GND); when the potential well control circuit is in the "Read" stage, when the TX signal is at a "high" potential, the other end BST of the potential well control circuit is also at a "high" potential. At this time, the potential of the floating node FD will be pulled up, and the increase is: Where, C is the parasitic capacitance on the potential well control circuit 601, C ALL It is all parasitic capacitances on the floating node FD, including: parasitic capacitance from the floating node FD to the drain of the source follower Msf, parasitic capacitance from the floating node FD to the source of the source follower Msf, parasitic capacitance from the floating node FD to the gate of the transfer transistor Mtg, parasitic capacitance from the floating node FD to the drain of the transfer transistor Mtg, and parasitic capacitance from the floating node FD to the potential well control circuit 601. By setting the voltage provided by the voltage driving circuit to the potential well control circuit 601, ΔV FD The value of can control the potential well difference between the floating node FD and the photodiode PD. The larger the difference, the faster the transmission speed when the transfer transistor Mtg is turned on, and the shorter its conduction time. The present application only needs to form a parasitic capacitor C between the potential well control circuit 601 and the floating node FD, and there is no need to design the occupied area of a capacitor separately. In addition, the voltage cannot be set too large, otherwise the floating node FD will be pulled too high, and then after all the electrons on the photodiode PD are transferred to the floating node FD, the FD potential will fall back from a higher potential, and the establishment time will be longer. Therefore, the voltage provided by the voltage drive circuit to the potential well control circuit 601 and the size of the parasitic capacitor C should be set according to the actual process and design requirements.
[0031] Regarding the comparison of the image smear effect between the pixel unit proposed by the present invention and the traditional pixel unit, as shown in FIG. Figure 7 As shown, the dotted line part is the relationship between the smear effect of the image obtained by the traditional pixel unit and the change of the conduction time of the transfer transistor, and the solid line part is the relationship between the smear effect of the image obtained by the pixel unit proposed in this application and the change of the conduction time of the transfer transistor. When the image is obtained by using the traditional pixel unit, the conduction time of the transfer transistor Mtg needs to be more than 0.5μs, and the smear can be less than 0.5% (from a visual point of view, only the smear less than 0.5% can appear inconspicuous on the image), while the image obtained by the pixel unit proposed in this application, when the conduction time of the transfer transistor Mtg is 0.2μs, the smear is only 0.2%. Therefore, in terms of effect, the pixel unit proposed in this application can shorten the conduction time of the transfer transistor Mtg when transmitting the signal by half or more, which can effectively shorten the time of reading the pixel signal.
[0032] Based on the pixel units described in any of the above embodiments, the present invention provides a pixel array, comprising: the pixel units described in any of the above embodiments arranged in an array; the other ends of all the potential well control units in the pixel array are connected together.
[0033] Based on the pixel array or pixel unit provided in the above embodiment, the present invention provides a CMOS image sensor, comprising: a pixel unit or a pixel array as described in the above embodiment, an analog-to-digital converter module, a ramp generator, a timing control module, a row selection decoding driving module, and an output signal processing module; the pixel unit or the pixel array is used to collect light signals and convert the light signals into electrical signals; the timing control module is used to control the working timing of the row selection decoding driving module, the ramp generator, the analog-to-digital converter module and the output signal processing module; the row selection decoding driving module is connected to the pixel array or the pixel unit, and is used to input a SEL signal to the pixel unit or the pixel unit in the pixel array; the analog-to-digital converter module is respectively connected to the pixel array or the pixel unit, and the ramp generator, and is used to obtain the output of the pixel unit or the pixel unit in the pixel array, and obtain the output of the ramp generator, and is used to output a corresponding digital signal; the output signal processing module is connected to the analog-to-digital converter module, and is used to process the digital signal output by the analog-to-digital converter module to generate image information. Because the conduction time of the transfer transistor in the pixel unit provided by the present application is shortened, the working time of the analog-to-digital converter module is also shortened, which can improve the processing efficiency of the image sensor.
[0034] In some embodiments, the analog-to-digital converter module includes: a comparator and a counter.
[0035] In some embodiments, the CMOS image sensor further includes: an inverter connected between the comparator and the counter, and the inverter serves as a buffer for a comparison result of the comparator.
[0036] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed in the embodiment of the present application should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application should be based on the protection scope of the claims.
Claims
1. A pixel unit, characterized in that: include: A photodiode, a transfer transistor, a reset transistor, a source follower, a row selection transistor, and a potential well control unit; The anode of the photodiode is grounded, and the cathode of the photodiode is connected to the source of the transfer transistor; The gate of the transmission transistor is used to receive the TX signal, the drain of the transmission transistor is connected to the source of the reset transistor, the gate of the source follower and one end of the potential well control unit, the potential well control unit is used to increase the potential well difference between the floating node and the photodiode, and the drain of the transmission transistor is the floating node; The drain of the reset transistor is connected to a power supply, and the gate of the reset transistor receives an RX signal; The drain of the source follower is connected to a power supply, the source of the source follower is connected to the drain of the row selection transistor, the gate of the row selection transistor receives a SEL signal, and the source of the row selection transistor serves as the output of the pixel unit.
2. The pixel unit according to claim 1, characterized in that: The potential well control unit comprises: a potential well control circuit.
3. The pixel unit according to claim 2, characterized in that: The other end of the potential well control unit is connected to a voltage driving circuit, and the voltage driving circuit is used to provide voltage to the potential well control unit.
4. A pixel array, characterized in that: include: The pixel units as claimed in any one of claims 1 to 3 are arranged in an array; The other ends of all the potential well control units in the pixel array are connected together.
5. A CMOS image sensor, characterized in that: include: The pixel unit according to any one of claims 1 to 3 or the pixel array according to claim 4, the analog-to-digital converter module, the ramp generator, the timing control module, the row selection decoding drive module, and the output signal processing module; The pixel unit or the pixel array is used to collect light signals and convert the light signals into electrical signals; The timing control module is used to control the working timing of the row selection decoding driving module, the ramp generator, the analog-to-digital converter module and the output signal processing module; The row selection decoding driving module is connected to the pixel array or the pixel unit, and is used to input a SEL signal to the pixel unit or the pixel unit in the pixel array; The analog-to-digital converter module is respectively connected to the pixel array or the pixel unit, and the ramp generator, and is used to obtain the output of the pixel unit or the pixel unit in the pixel array, and obtain the output of the ramp generator, and is used to output a corresponding digital signal; The output signal processing module is connected to the analog-to-digital converter module and is used to process the digital signal output by the analog-to-digital converter module to generate image information.
6. The CMOS image sensor according to claim 5, characterized in that: The analog-to-digital converter module includes a comparator and a counter.
7. The CMOS image sensor according to claim 6, characterized in that: Also includes: An inverter is connected between the comparator and the counter, and the inverter serves as a buffer for the comparison result of the comparator.