Semiconductor device and semiconductor module

Abstract

A semiconductor device includes a semiconductor element (11), a conductor (10) joined to a back surface (11b) side of the semiconductor element, and a sealant (12) covering a side surface (11c) of the semiconductor element and a part of the conductor. The semiconductor device includes a rewiring layer (15) having an insulating layer (151) covering a surface (11a) of the semiconductor element and a part of the sealant, a first electrode (13) and a second electrode (14) connected to the semiconductor element, a conductive first external exposure layer (152) covering a part of the first electrode exposed from the insulating layer, and a conductive second external exposure layer (153) covering a part of the second electrode exposed from the insulating layer. An end portion of the second electrode on a side opposite to the semiconductor element is extended to a position outside an outer contour of the semiconductor element in the rewiring layer. The second external exposure layer covers a part of the second electrode located outside the outer contour of the semiconductor element. A lower surface (10b) of the conductor on a side opposite to an upper surface (10a) joined to the back surface of the semiconductor element is exposed from the sealant.

Description

[0001] Cross Reference to Related Applications

[0002] This application is based on Japanese Patent Application No. 2020-74422 filed on April 17, 2020, and Japanese Patent Application No. 2021-28963 filed on February 25, 2021, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to a semiconductor device of a fan-out package configuration, and a semiconductor module using the same. BACKGROUND

[0004] In the past, as a semiconductor device having a semiconductor element and a semiconductor module of a two-side heat dissipation configuration using the same, for example, a structure described in Patent Literature 1 can be cited. The semiconductor module described in Patent Literature 1 is provided with a semiconductor device having a semiconductor element, two heat sinks arranged on both sides sandwiching the semiconductor device, a lead terminal, and a wire connecting the semiconductor device and the lead terminal. Further, in order to prevent short circuiting due to contact of the wire with the heat sink, the semiconductor module is provided with a heat dissipation block composed of a material having high thermal conductivity between the face on the side of the wire in the semiconductor device and the heat sink on the side of the face.

[0005] PRIOR ART DOCUMENTS

[0006] PATENT LITERATURE

[0007] Patent Literature 1: Japanese Patent Application Publication No. 2001-156225 SUMMARY

[0008] However, the semiconductor module described above is a configuration in which the gap between the semiconductor device and the heat sink is made to be equal to or greater than a predetermined value by the heat dissipation block to prevent contact of the wire with the heat sink, and therefore the heat dissipation block becomes a hindrance to thinning. Further, since the heat dissipation block is arranged between the semiconductor device and the heat sink, the thermal resistance increases in correspondence with the heat dissipation block, and the heat dissipation of the semiconductor module decreases.

[0009] Therefore, the inventors of the present application have made intensive studies on the configuration of the semiconductor device and the semiconductor module for thinning and high heat dissipation of such a semiconductor module. As a result, a semiconductor module of the following configuration has been conceived: the semiconductor device is made into a fan-out package configuration formed with a rewiring layer, the heat sink is joined to both faces of the semiconductor device without passing through the heat dissipation block, and the lead terminal is connected to the rewiring layer without passing through the wire. Thus, a semiconductor module of a two-side heat dissipation configuration not having the heat dissipation block and the wire, which achieves thinning and high heat dissipation, is obtained.

[0010] Here, a semiconductor device having a fan-out package structure of a semiconductor element requires that a back surface of the semiconductor element on the side opposite to the surface covered by the re-wiring layer be exposed. Such a semiconductor device is manufactured, for example, by the following steps: fixing the surface of the power semiconductor element to a temporary fixing member with close contact and covering the back surface side with a sealing member, peeling the power semiconductor element from the temporary fixing member and forming a re-wiring layer on the surface, after that, grinding the sealing member to expose the back surface, and forming an electrode on the back surface.

[0011] However, the above manufacturing method has many steps, and the manufacturing cost becomes large. Furthermore, as a result of the inventors' dedicated studies, it has been found that in the grinding step of exposing the back surface from the sealing member, peeling of the side surface of the semiconductor element from the sealing member can occur. If such peeling occurs, damage to the re-wiring layer is caused by the progress of the peeling, and moisture intrudes from the gap between the side surface of the semiconductor element and the sealing member, and the reliability of the semiconductor device decreases.

[0012] The present application is a semiconductor device having a fan-out package structure in which peeling of the side surface of the semiconductor element is suppressed, and the manufacturing cost is reduced compared to the past, and a semiconductor module having high reliability using the same.

[0013] According to one aspect of the present application, a semiconductor device has: a semiconductor element; a conductor joined to the back surface of the semiconductor element; a sealing member covering a part of the conductor and a side surface of the semiconductor element; and a re-wiring layer having an insulating layer covering a part of the sealing member and a surface of the semiconductor element, a first electrode and a second electrode connected to the semiconductor element, a first external exposure layer having conductivity covering a part of the first electrode exposed from the insulating layer, and a second external exposure layer having conductivity covering a part of the second electrode exposed from the insulating layer; an end portion of the second electrode on the side opposite to the semiconductor element is provided to extend to a position in the re-wiring layer outside the outer contour of the semiconductor element; the second external exposure layer covers a part of the second electrode outside the outer contour of the semiconductor element; and a lower surface of the conductor on the side opposite to the upper surface joined to the back surface of the semiconductor element is exposed from the sealing member.

[0014] Thus, the boundary portions of the side surface of the semiconductor element and the sealing member are covered by the conductor, so that the force acting on these boundary portions at the time of grinding of the sealing member is reduced, and a semiconductor device having a fan-out package structure in which peeling at the boundary portions is suppressed is obtained. Furthermore, the back surface of the semiconductor element is covered by the conductor, so that the grinding tool does not reach the back surface of the semiconductor element at the time of grinding of the sealing member, and even if an electrode exists on the back surface of the semiconductor element, the electrode is not shaved off by the grinding of the sealing member. Thus, a step of forming an electrode on the back surface of the semiconductor element after the grinding of the sealing member is not required, and the semiconductor device also has a structure in which the manufacturing cost is reduced compared to the past.

[0015] According to another aspect of the present application, a semiconductor device includes a semiconductor element, a sealing member covering a side surface of the semiconductor element, and a rewiring layer having an insulating layer covering a surface of the semiconductor element and a portion of the sealing member, a first electrode and a second electrode connected to the semiconductor element, a first external exposure layer having conductivity covering a portion of the first electrode exposed from the insulating layer, and a second external exposure layer having conductivity covering a portion of the second electrode exposed from the insulating layer. An end portion of the second electrode on a side opposite to the semiconductor element is extended to a position in the rewiring layer outside an outer contour of the semiconductor element. The second external exposure layer covers a portion of the second electrode outside the outer contour of the semiconductor element. Another face of the sealing member on a side opposite to a face covered by the rewiring member is protruded from a back surface of the semiconductor element and has a recessed portion recessed toward the face. A portion or all of the back surface of the semiconductor element is exposed from the sealing member in the recessed portion of the sealing member.

[0016] The other face of the sealing member on a side opposite to the face covered by the rewiring layer is made to be protruded from the back surface of the semiconductor element, so that a force acting on a boundary portion between the side surface of the semiconductor element and the sealing member at the time of polishing of the sealing member is moderated. Further, since the other face of the sealing member is made to be in a state of being protruded from the back surface of the semiconductor element, even if there is an electrode on the back surface of the semiconductor element, the electrode is not shaved off by the polishing of the sealing member, and a post-polishing electrode formation of the sealing member is not needed, so that manufacturing cost is reduced compared to the past. Thus, a semiconductor device is obtained which is a configuration in which peeling due to the polishing of the sealing member at an interface between the side surface of the semiconductor element and the sealing member is suppressed, and manufacturing cost is reduced compared to the past.

[0017] Further, according to one aspect of the present application, a semiconductor module includes: a semiconductor device including a semiconductor element, a first sealing member covering a side surface of the semiconductor element, and a redistribution layer having an insulating layer covering a surface of the semiconductor element and a portion of the first sealing member, an electrode connected to the semiconductor element, and an external exposure layer having conductivity covering a portion of the electrode exposed from the insulating layer; a heat dissipation member engaged with a portion of a back surface of the semiconductor element exposed from the sealing member via a bonding member; a lead frame electrically engaged with the electrode via the external exposure layer or the bonding member; and a second sealing member covering the semiconductor device, a portion of the heat dissipation member, and a portion of the lead frame; the semiconductor device is a fan-out package structure in which an end portion of the electrode exposed from the insulating layer is disposed to a position outside an outer contour of the semiconductor element; another surface of the sealing member opposite to a surface covered by the redistribution layer is protruded from the back surface of the semiconductor element and has a recessed portion recessed toward the surface; a portion or all of the back surface of the semiconductor element is exposed from the sealing member in the recessed portion of the sealing member and is engaged with the heat dissipation member via the bonding member.

[0018] Thus, a semiconductor module of a semiconductor device in which another surface of a sealing member opposite to a surface covered by a redistribution layer is made to protrude from a back surface of a semiconductor element to thereby suppress peeling at an interface between a side surface of the semiconductor element and the sealing member is obtained. The semiconductor module has high reliability because a semiconductor device in which peeling at an interface between a side surface of a semiconductor element and a sealing member is suppressed is used, and reliability is improved. In the semiconductor device, the back surface of the semiconductor element exposed from the sealing member in a recessed portion of the sealing member is engaged with the heat dissipation member via the bonding member. Further, because the heat dissipation member is engaged by providing the recessed portion in the sealing member and disposing the bonding member in the recessed portion, the bonding member has a thickness corresponding to a depth of the recessed portion, and an effect of easily controlling the thickness of the bonding member is obtained.

[0019] In addition, the reference numerals in parentheses assigned to each constituent element or the like indicate one example of a correspondence relationship with a specific constituent element or the like described in the following embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a cross-sectional view showing a structure of the semiconductor device of the first embodiment.

[0021] Figure 2 is a perspective view of the semiconductor device of Figure 1 when viewed from the redistribution layer side.

[0022] Figure 3A is a cross-sectional view showing a bonding process of a conductive body and a semiconductor element in a manufacturing process of the semiconductor device of the first embodiment.

[0023] Figure 3B is a cross-sectional view showing a manufacturing process next to Figure 3A .

[0024] Figure 3C is a cross-sectional view showing a manufacturing process next to Figure 3B .

[0025] Figure 3D is a cross-sectional view showing a manufacturing process next to Figure 3C .

[0026] Figure 3E is a cross-sectional view showing a manufacturing process next to Figure 3D .

[0027] Figure 3F is a cross-sectional view showing a manufacturing process next to Figure 3E .

[0028] Figure 3G is a cross-sectional view showing a manufacturing process next to Figure 3F .

[0029] Figure 3H is a cross-sectional view showing a manufacturing process next to Figure 3G .

[0030] Figure 3I is a cross-sectional view showing a manufacturing process next to Figure 3H .

[0031] Figure 3J is a cross-sectional view showing a manufacturing process next to Figure 3I .

[0032] Figure 3J is a cross-sectional view showing another manufacturing process of the semiconductor device of Embodiment 1, that is, a formation process of an insulating layer.

[0033] Figure 4A is a cross-sectional view showing a manufacturing process next to Figure 4B .

[0034] Figure 4A is a cross-sectional view showing an example in which the first electrode and the second electrode in the rewiring layer are formed, respectively.

[0035] Figure 4C is a cross-sectional view showing a semiconductor device of a conventional fan-out package structure.

[0036] Figure 5 is a cross-sectional view showing a grinding process of a sealing member in a manufacturing process of the conventional semiconductor device shown in Figure 6 .

[0037] Figure 5 is a cross-sectional view showing a grinding process of a sealing member in a manufacturing process of the conventional semiconductor device shown in Figure 7The enlarged view of region VII is an enlarged cross-sectional view showing delamination at the interface between the side surface of the semiconductor element and the sealing material in a conventional semiconductor device.

[0038] Figure 6 It is a cross-sectional view showing a structural example of a semiconductor module using the semiconductor device according to the first embodiment.

[0039] Figure 8 It is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment.

[0040] Figure 9 This is a diagram for explaining how interfacial delamination between the conductor and the sealing material is suppressed by the through-hole provided in the conductor.

[0041] Figure 10 It is a cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment.

[0042] Figure 11 It is a cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment.

[0043] Figure 12 It is a cross-sectional view showing a fourth modified example of the semiconductor device according to the first embodiment.

[0044] Figure 13 It is a cross-sectional view showing a fifth modification of the semiconductor device according to the first embodiment.

[0045] Figure 14 It is a cross-sectional view showing a sixth modification of the semiconductor device according to the first embodiment.

[0046] Figure 15 It is a cross-sectional view showing a seventh modification of the semiconductor device according to the first embodiment.

[0047] Figure 16 It is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0048] Figure 17 It is a cross-sectional view showing a step of forming a temporary protective member on a conductor in the manufacturing process of the semiconductor device according to the second embodiment.

[0049] Figure 18A It means next Figure 18B A cross-sectional view of the manufacturing process.

[0050] Figure 18A It means next Figure 18C A cross-sectional view of the manufacturing process.

[0051] Figure 18B It means next Figure 18D A cross-sectional view of the manufacturing process.

[0052] Figure 18C is a cross-sectional view showing a manufacturing step next to Figure 18E .

[0053] Figure 18D is an enlarged cross-sectional view showing an example in which the filler enters between the insulating layer and the semiconductor element in a case where the sealing member containing the filler is formed after the bonding of the conductive body and the semiconductor element.

[0054] Figure 19 is a cross-sectional view showing a structure of the semiconductor device of the third embodiment.

[0055] Figure 20 is a cross-sectional view showing a step of forming a back surface protective member to the semiconductor element in a manufacturing step of the semiconductor device of the third embodiment.

[0056] Figure 21A is a cross-sectional view showing a manufacturing step next to Figure 21B .

[0057] Figure 21A is a cross-sectional view showing a manufacturing step next to Figure 21C .

[0058] Figure 21B is a cross-sectional view showing a manufacturing step next to Figure 21D .

[0059] Figure 21C is a cross-sectional view showing a manufacturing step next to Figure 21E .

[0060] Figure 21D is a cross-sectional view showing a step of ultraviolet irradiation in a case where the back surface protective member is peeled using a UV tape.

[0061] Figure 22 is a cross-sectional view showing a first modification example of the semiconductor device of the third embodiment.

[0062] Figure 23 is a cross-sectional view showing a second modification example of the semiconductor device of the third embodiment.

[0063] Figure 24 is a cross-sectional view showing a structure of the semiconductor device of the fourth embodiment.

[0064] Figure 25 is a cross-sectional view showing a step of temporarily fixing the semiconductor element to the support substrate using a temporary fixing member in a manufacturing step of the semiconductor device of the fourth embodiment.

[0065] Figure 26A is a cross-sectional view showing a manufacturing step next to Figure 26B .

[0066] Figure 26A is a cross-sectional view showing a manufacturing step next to Figure 26C .

[0067] Figure 26B is a cross-sectional view showing a manufacturing step next to Figure 26D .

[0068] Figure 26C is a cross-sectional view showing a structure of a semiconductor device of the fifth embodiment.

[0069] Figure 27 is a scanning electron microscope (SEM) photograph showing an enlarged XXVIII region of Figure 28 .

[0070] Figure 27 is a cross-sectional view showing a step of preparing a material and a substrate for constituting a conductive body in a manufacturing step of the semiconductor device of the fifth embodiment.

[0071] Figure 29A is a cross-sectional view showing a manufacturing step next to Figure 29B .

[0072] Figure 29A is a cross-sectional view showing a manufacturing step next to Figure 29C .

[0073] Figure 29B is a cross-sectional view showing a manufacturing step next to Figure 29D .

[0074] Figure 29C is a cross-sectional view showing a manufacturing step next to Figure 29E .

[0075] Figure 29D is a cross-sectional view showing a manufacturing step next to Figure 29F .

[0076] Figure 29E is a cross-sectional view showing another structure example of the semiconductor device of the fifth embodiment.

[0077] Figure 30 is a cross-sectional view showing an example of a semiconductor module using the semiconductor device of the third embodiment. DETAILED DESCRIPTION

[0078] Hereinafter, embodiments of the present application will be described based on the drawings. Also, in each of the following embodiments, portions that are the same or equivalent to each other are assigned the same reference numerals and will be described.

[0079] (First Embodiment)

[0080] Referring toFigure 31 、 Figure 1 A semiconductor device 1 according to the first embodiment will be described.

[0081] Figure 2 yes Figure 1 The cross-sectional view between II is shown. Figure 2 In order to facilitate understanding of the first externally exposed layer 152 and the second externally exposed layer 153 described later, hatching is applied to the externally exposed layers 152 and 153, although cross sections are not shown.

[0082] 〔structure〕

[0083] The semiconductor device 1 of this embodiment is, for example, Figure 2 As shown, the semiconductor device 1 includes a conductor 10, a semiconductor element 11 having a first electrode 13 and a second electrode 14 formed thereon, a sealing member 12, and a redistribution layer 15. The semiconductor device 1 is structured such that the semiconductor element 11 is mounted on the conductor 10 having a larger planar size than the semiconductor element 11, and the sides thereof are covered with a sealing member 12, and the redistribution layer 15 is formed on the semiconductor element 11 and the sealing member 12. The semiconductor device 1 is a fan-out type package structure in which one end of the first electrode 13 is connected to an electrode pad (not shown) of the semiconductor element 11, one end of the second electrode 14 is connected to another electrode pad (not shown), and the other end is extended to the outside of the outer contour of the semiconductor element 11. Hereinafter, for simplicity of explanation, the fan-out type package structure may sometimes be referred to as an "FOP structure."

[0084] For example, Figure 1 As shown, the surface of the semiconductor element 11 covered by the redistribution layer 15 is the surface 11a, and the conductor 10 is a component that covers the back surface 11b, which is the opposite surface. The conductor 10 is electrically connected to the back surface 11b of the semiconductor element 11, and is made of, for example, any conductive material such as Cu (copper), sintered Ag (silver), solder, etc. When the conductor 10 is made of solder, it is directly bonded to the back surface 11b of the semiconductor element 11. When it is made of a Cu plate, it is bonded via any conductive bonding material such as solder (not shown). Regarding the conductor 10, for example, the upper surface 10a facing the semiconductor element 11 is connected to an electrode (not shown) formed on the back surface 11b of the semiconductor element 11, and the opposite surface of the upper surface 10a, that is, the lower surface 10b, is exposed from the sealing member 12 and functions as a back electrode. In addition, when the conductor 10 is made of a material with high thermal conductivity such as Cu, it also serves to dissipate heat from the semiconductor element 11 to the outside.

[0085] Furthermore, from the viewpoint of suppressing warping of the semiconductor element 11 , the conductor 10 is preferably made of a material having higher rigidity than the semiconductor element 11 and a bonding material (not shown) used for bonding with the semiconductor element 11 .

[0086] In the present embodiment, the planar size of the electrically conductive body 10 is larger than the semiconductor element 11, and the electrically conductive body 10 is connected in a manner that the entire area of the back surface lib of the semiconductor element 11 is positioned inside the outer contour of the electrically conductive body 10. This is to improve the adhesion of the interface and the reliability of the semiconductor device 1 when the surface 11a and the back surface lib of the semiconductor element 11 are connected by a surface that is made into a side surface 11c, and the boundary of the side surface 11c of the semiconductor element 11 and the sealing member 12 is covered by the electrically conductive body 10. Details will be described later together with the manufacturing method of the semiconductor device 1.

[0087] The semiconductor element 11 is mainly composed of a semiconductor material such as silicon, silicon carbide, and the like, and is, for example, a power semiconductor element such as a MOS transistor, an IGBT (Insulated Gate Bipolar Transistor), and the like, which is manufactured by a general semiconductor process.

[0088] The semiconductor element 11 has, for example, a plurality of electrode pads not shown composed of Al (aluminum) or the like on the surface 11a, and has the first electrode 13 and a plurality of second electrodes 14 composed of a metal material such as Cu (copper) or the like on the electrode pads. The semiconductor element 11 is, for example, configured such that an electrode pad not shown and a third electrode not shown covering the same are formed on the back surface lib, and the third electrode is connected to the outside via the electrically conductive body 10. The first electrode 13 and the third electrode not shown are, for example, a pair, and are used as a main current path of the semiconductor element 11. At least one of the plurality of second electrodes 14 is used as a gate electrode for controlling the on-off of the current between the first electrode 13 and the third electrode. The first electrode 13 is laminated on the electrode pad not shown, and is an inner electrode disposed inside the re-wiring layer 15, as shown in FIG. 1, and is connected to the first external exposure layer 152. The plurality of second electrodes 14 are inner electrodes laminated on the electrode pad not shown as with the first electrode 13, and are respectively connected to the second external exposure layer 153. In addition, the plurality of second electrodes 14 function as internal wiring for connecting the second external exposure layer 153 and the electrode pad not shown of the semiconductor element 11 inside the re-wiring layer 15. The same applies to the first electrode 13, and in the case where the first electrode 13 is referred to as a "first wiring" inside the re-wiring layer 15, the second electrode 14 can be referred to as a "second wiring". Figure 1 The sealing member 12 is, for example, a resin material such as an epoxy resin or the like, and is formed by, for example, a transfer molding method or the like.

[0089] Figure 1 ​The sealing member 12 covers the portion of the conductive body 10 other than the lower surface 10b and the side surface 11c of the semiconductor element 11, and is formed of an arbitrary resin material such as an epoxy resin, for example. Specifically, the sealing member 12 covers the upper surface 10a and the end surface 10c of the conductive body 10 facing the semiconductor element 11, and the side surface 11c of the semiconductor element 11, respectively. A part of the sealing member 12 and the lower surface 10b of the conductive body 10 constitute the back surface 1b of the semiconductor device 1.

[0090] The re-wiring layer 15 covers one surface including the surface 11a of the semiconductor element 11 and a part of the sealing member 12, and has an insulating layer 151, a first external exposure layer 152, and a second external exposure layer 153, in addition to the first electrode 13 and the second electrode 14, as shown in Figure 1 The re-wiring layer 15 is formed by a known re-wiring formation technique, for example.

[0091] The insulating layer 151 is formed of an insulating material such as a polyimide, for example, by an arbitrary coating process or the like.

[0092] The first external exposure layer 152 and the second external exposure layer 153 are formed of a metal material such as Ni, for example, by non-electroplating or the like. The first external exposure layer 152 is formed inside the outer contour of the semiconductor element 11 in plan view, and a part thereof is exposed from the insulating layer 151 on the surface 1a side of the semiconductor device 1, as shown in Figure 1 , and enables electrical connection from the outside to the first electrode 13. The second external exposure layer 153 covers a part of the region of the second electrode 14 on the outside of the outer contour of the semiconductor element 11. The second external exposure layer 153 is formed in the same number as the second electrode 14, for example, and is exposed from the insulating layer 151 on the surface 1a side of the semiconductor device 1, as shown in Figure 2 , and enables electrical connection from the outside to the semiconductor element 11 via the second electrode 14. Note that the external exposure layers 152 and 153 are merely a medium for electrically connecting other components to the semiconductor element 11, and are not limited to a plating layer of Ni or the like, but can be a bump formed of solder or the like, or a structure in which a plating layer and a bump are stacked.

[0093] Note that, in Figure 2 , an example in which five second external exposure layers 153 are formed to cover different parts of the second electrode 14 is shown, but the number of the second electrode 14 and the second external exposure layers 153 covering the same is arbitrary.

[0094] The above is the basic structure of the semiconductor device 1 of the present embodiment. The semiconductor device 1 is an FOP structure in which the conductor 10 is connected to the back surface lib of the semiconductor element 11, and the conductor 10 is exposed instead of the semiconductor element 11. Therefore, in the semiconductor device 1, the interfaces of the side surface lie of the semiconductor element 11 and the sealing member 12 are not exposed, and the effect of improved adhesion at these interfaces can be obtained.

[0095] [Manufacturing method]

[0096] Next, a manufacturing method of the semiconductor device 1 will be described with reference to Figure 2 A manufacturing method of the semiconductor device 1 will be described.

[0097] First, the conductor 10 and the semiconductor element 11, which is manufactured by a usual semiconductor process and has an electrode pad not shown, are prepared. Next, the back surface lib of the semiconductor element 11 is joined to the conductor 10 by a solder or the like not shown, for example, as shown in FIG. 2. Figures 3A-3J

[0098] Next, as shown in FIG. 3, the surface lie of the semiconductor element 11 is attached to the support substrate 200, and the semiconductor element 11 with the conductor 10 joined thereto is held. The support substrate 200 uses, for example, an arbitrary substrate having an adhesive sheet not shown with high adhesion to silicon on the surface. Figure 3A

[0099] Next, a mold not shown is prepared, and the semiconductor element 11 held on the support substrate 200 is covered with a resin material such as an epoxy resin by compression molding or the like, and hardened by heating or the like, so that the sealing member 12 is formed as shown in FIG. 4. Thus, the side surface lie of the semiconductor element 11 and the conductor 10 are covered with the sealing member 12. Then, the conductor 10 and the semiconductor element 11 covered with the sealing member 12 are peeled from the support substrate 200. Figure 3B

[0100] Next, on the surface lie of the semiconductor element 11 exposed from the sealing member 12, a solution containing a photosensitive resin material such as polyimide is applied by a spin coating method or the like and dried, so that a first layer 1511 constituting an insulating layer 151 is formed as shown in FIG. 5. The first layer 1511 is formed into a prescribed pattern shape covering the surface lie of the semiconductor element 11 except for a portion (an electrode pad not shown) where the first electrode 13 and the second electrode 14 are formed, and the sealing member 12, for example, by a photolithography method. After the layout of the first layer 1511, a seed layer 16 covering the first layer 1511 and the exposed portion of the semiconductor element 11 is formed by vacuum deposition, for example, by a sputtering method or the like. The seed layer 16 is composed of a conductive material such as Cu, for example. Figure 3C

[0101] ​​​​Next, a resist layer 17 is formed to cover the first layer 1511 and the seed layer 16. The resist layer 17 is made of, for example, a resin material having photosensitive and insulating properties, and is formed by a wet film forming method such as spin coating, similarly to the first layer 1511, and is formed into a predetermined pattern shape by photolithography. Figure 3D As shown, in the semiconductor element 11 , electrode pads (not shown) forming the first electrode 13 and the second electrode 14 and a portion of the first layer 1511 are exposed from the resist layer 17 .

[0102] Then, for example, by electroplating, Figure 3E As shown in FIG. 1 , a first electrode 13 and a second electrode 14 made of Cu or the like are formed.

[0103] Then, if Figure 3F As shown, for example, after the resist layer 17 is removed by a stripping solution or the like, a portion of the seed layer 16 exposed by the removal of the resist layer 17 is removed by an etching solution.

[0104] Then, for example, similarly to the first layer 1511, a resin material having photosensitivity and insulating properties is used to form the second layer 1512 constituting the insulating layer 151 by spin coating, and then patterned by photolithography. Figure 3G As shown, the insulating layer 151 constituting the rewiring layer 15 is formed, and a portion of the first electrode 13 and the second electrode 14 is exposed to the outside from the insulating layer 151 .

[0105] Then, if Figure 3H As shown, a first externally exposed layer 152 made of Ni or the like is formed by, for example, electroless plating to cover the first electrode 13, and a second externally exposed layer 153 is formed to cover a portion of the plurality of second electrodes 14. Thus, a redistribution layer 15 including the first electrode 13, the second electrode 14, the insulating layer 151, and the externally exposed layers 152 and 153 is formed on the semiconductor element 11 and the sealing member 12.

[0106] Finally, if Figure 3I As shown, the sealing member 12 is thinned from the back surface 11b side of the semiconductor element 11 by grinding or the like, thereby exposing the conductor 10. By bonding the conductor 10 to the back surface 11b of the semiconductor element 11 and thinning the sealing member 12 by grinding or the like to expose the conductor 10, it is no longer necessary to form new electrodes on the back surface 11b of the semiconductor element 11 after thinning, thereby reducing manufacturing costs.

[0107] For example, through the above-described steps, the semiconductor device 1 of this embodiment can be manufactured.

[0108] In addition, the manufacturing method described above is only an example, and is not limited thereto. For example, the first electrode 13, the second electrode 14, and other wiring can be formed by repeatedly performing the above-described rewiring formation process to form a rewiring layer 15 of more layers. Furthermore, the first electrode 13 and the second electrode 14 can be formed by a screen printing method instead of plating.

[0109] Specifically, the semiconductor element 11 formed with the electrode pads 11d, 11e is prepared, and the semiconductor element 11 is bonded to the conductor 10 and the sealing member 12 is formed in the order described above. Figure 3J Figures 3A-3C The first layer 1511, which is a part of the insulating layer 151, is formed and patterned so that the electrode pads 11d, 11e are exposed from the insulating layer 151. Then, as shown in FIG. 6, for example, the sintered Cu paste material is formed by screen printing using a screen mask not shown, and then sintered to form the first electrode 13 connected to the electrode pad 11d and the second electrode 14 connected to the electrode pad 11e. Figure 4A

[0110] In this case, the formation process of the electrodes 13, 14 can be simplified, and the thickness of the electrodes 13, 14 can be made thicker than in plating. In addition, in the case where the electrodes 13, 14 are formed by a screen printing method, it is easy to make the thickness 20 μm or more, and low inductance along with low resistance and low thermal resistance of the wiring due to thickening can be achieved.

[0111] In addition, as shown in FIG. 7, the first electrode 13 and the second electrode 14 can be formed of different paste materials. For example, in the case where the first electrode 13 is connected to the emitter and the second electrode 14 is connected to the gate or the like and is used for signal transmission, the second electrode 14 can be formed of a low-stress paste material after the first electrode 13 is formed of a sintered Cu paste material. As a low-stress paste material, for example, a conductive paste material containing silver fillers in a resin material or the like can be given. Thus, it is easier to form the first electrode 13 and the second electrode 14 of materials that meet the desired characteristics than in the case of plating. Figure 4B

[0112] 〔Effect of the Conductor〕

[0113] The conductor 10 prevents the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12 from being exposed during grinding in the thinning process, and functions to suppress peeling at these interfaces and the intrusion of moisture into the peeling interface.

[0114] Here, a semiconductor device of a conventional FOP configuration that does not have the conductor 10 is described. For example, as shown in FIG. 8, a semiconductor element 11 is prepared, and the semiconductor element 11 is bonded to a conductor 10 and a sealing member 12 is formed in the order described above. Figure 4C ​​​As shown, the semiconductor device 300 of the conventional FOP configuration is a configuration in which the back surface 301b on the opposite side of the surface 301a of the semiconductor element 301 covered with the re-wiring layer 303 is exposed from the sealing member 302.

[0115] The semiconductor device 300 is manufactured, for example, as shown in FIG. 2, by grinding the sealing member 302 from the surface of the semiconductor element 301 on the back surface 301b side using a grinder 210, for a workpiece in which the semiconductor element 301 is covered with the sealing member 302 and the re-wiring layer 303 is formed. Figure 5 At this time, the force at the time of grinding acts on the interface of the side surface 301c of the semiconductor element 301 and the sealing member 302, and as shown in FIG. 3, for example, there are cases in which peeling occurs at these interfaces.

[0116] Figure 6 If such peeling occurs, the interface peeling can reach the re-wiring layer 303, and wire disconnection in the re-wiring layer 303 can occur.

[0117] Further, if moisture intrudes into the peeling interface, corrosion of the metal material in the re-wiring layer 303 and evaporation of the intruded moisture at the time of joining the semiconductor device 300 with other components by reflowing can cause peeling of the re-wiring layer 303 and wire disconnection. Furthermore, if the moisture intruding into the peeling interface reaches the interface of the surface of the semiconductor element 301 and the re-wiring layer 303 and stays at these interfaces, the close contact of the semiconductor element 301 and the re-wiring layer 303 can decrease. If the close contact of the semiconductor element 301 and the re-wiring layer 303 decreases, in the case of manufacturing a plurality of semiconductor devices 300 at a time, it can also become a cause of chip pop and wafer breakage of the semiconductor element 301 from the re-wiring layer 303 at the time of heating or cutting, and the like.

[0118] ​In contrast, the semiconductor device 1 of the present embodiment is configured such that the conductive body 10, which has a larger planar size than the semiconductor element 11 on the back surface of the semiconductor element 11, is arranged inward of the outer contour of the conductive body 10. In other words, the semiconductor device 1 is configured such that the boundary portion between the side surface 11c of the semiconductor element 11 and the sealing member 12 is covered and shielded by the conductive body 10. Therefore, in a process of grinding and removing the sealing member 12 from the surface on the back surface side of the semiconductor element 11 (hereinafter referred to as "back surface grinding"), the boundary portion between the side surface 11c of the semiconductor element 11 and the sealing member 12 is not exposed to a grinding tool such as a grinding machine. Thus, in the back surface grinding, stress acting on the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12 is reduced, peeling occurring at the interface is suppressed, and the intrusion of moisture into the interfaces and the resulting adverse conditions described above can be prevented.

[0119] In addition, in Figure 7 , a structure in which the electrodes on the surface side of the semiconductor element 301 are omitted and the rewiring layer 303 including the wiring connected to the electrodes not shown of the semiconductor element 301 is simplified is shown.

[0120] 〔Application Example to Semiconductor Module〕

[0121] Next, with reference to Figures 5-7 , an example of a semiconductor module using the semiconductor device 1 of the present embodiment will be described. In Figure 8 , the portions of the wiring connected to the outside in other cross sections in the second heat sink 3 described later are shown by broken lines.

[0122] The semiconductor device 1 is preferably used, for example, in the case where it is applied to a semiconductor module S1 of a two-surface heat dissipation structure as shown in Figure 8 . In addition, in the present specification, the case where the semiconductor device 1 is applied to a semiconductor module of a two-surface heat dissipation structure is described as a representative example, but the application is not limited to this example.

[0123] The semiconductor module S1 has the semiconductor device 1, the first heat sink 2, the second heat sink 3, the lead frame 4, the bonding member 5, and the sealing member 6 as shown in Figure 8 . The two heat sinks 2, 3 of the semiconductor module S1 are arranged in opposition to each other with the semiconductor device 1 interposed therebetween, and the semiconductor module S1 is a two-surface heat dissipation structure in which heat generated by the semiconductor device 1 is released to the outside from both surfaces via the heat sinks 2, 3.

[0124] The first heat sink 2 is made of a material having a high thermal conductivity, such as copper or aluminum, as shown in Figure 8As shown, the first heat sink 2 is a plate having an upper surface 2a and a lower surface 2b in a front-to-back relationship, and is made of a metal material such as Cu or Fe (iron). The semiconductor device 1 is mounted on the upper surface 2a via a bonding material 5 made of solder, and the lower surface 2b is exposed from the sealing member 6. The first heat sink 2 serves as a current path for the semiconductor device 1, and a portion of the upper surface 2a side extends to the outside of the sealing member 6. In other words, in this embodiment, the first heat sink 2 serves as both a heat dissipation component and a wiring. In addition, the first heat sink 2 can be referred to as a "first heat dissipation component."

[0125] The back surface 1b of the semiconductor device 1 is connected to the first heat sink 2 via a bonding material 5, and the front surface 1a of the semiconductor device 1 is connected to the second heat sink 3 via a bonding material 5. The semiconductor device 1 is arranged so that the entire back surface 1b is contained within the outer contour of the upper surface 2a of the first heat sink 2. The second heat sink 3 has one surface 3a as the surface exposed to the outside and another surface 3b as the surface facing the semiconductor device 1. The semiconductor device 1 is arranged so that, for example, a portion of the area including the second externally exposed layer 153 is located outside the outer contour of the other surface 3b of the second heat sink 3. The second externally exposed layer 153 of the semiconductor device 1 is connected to the lead frame 4, for example, via a bonding material 5.

[0126] The second heat sink 3 Figure 8 As shown, it is a plate having one surface 3a and the other surface 3b in a front-back relationship, and is made of the same material as the first heat sink 2. In the second heat sink 3, the other surface 3b is arranged opposite to a portion of the upper surface 2a of the semiconductor device 1, and the one surface 3a is exposed from the sealing member 6. The second heat sink 3 is electrically connected to the first external exposure layer 152 and the first electrode 13 via the bonding member 5, and becomes a current path for the semiconductor element 11 in the same manner as the first heat sink 2. In addition, in the connection with Figure 8 In the different cross sections, a portion of the other surface 3b of the second heat sink 3 extends outside the seal 6, serving as both a heat dissipation member and an electrical wiring.

[0127] The lead frame 4 is made of metal materials such as Cu or Fe. Figure 1 As shown, the lead frame 4 is electrically connected to the second externally exposed layer 153 in the semiconductor device 1 via the bonding material 5. The lead frame 4 includes a plurality of leads having the same number as the second electrode 14, for example.

[0128] In addition, the lead wires are connected to the adjacent lead wires by a tie bar not shown, for example, until the sealing member 6 is formed, and the tie bar is removed by punching or the like after the sealing member 6 is formed so as to be in a separated state. Further, the lead frame 4 can be configured as the same member as the second heat sink 3, and is linked by a tie bar not shown until the sealing member 6 is formed. In this case, the tie bar is also removed by punching or the like after the sealing member 6 is formed so that the lead frame 4 is in a separated state from the second heat sink 3.

[0129] The bonding member 5 is a bonding member that bonds the constituent elements of the semiconductor module S1 to each other, and a material having electrical conductivity, such as solder or the like, is used for electrical connection. In addition, the bonding member 5 is not limited to solder.

[0130] The sealing member 6 is configured of a thermosetting resin such as epoxy resin or the like, for example, and covers the semiconductor device 1, a part of the heat sinks 2, 3, a part of the lead frame 4, and the bonding member 5, as shown in FIG. 1. Figure 8 In a case where the sealing member 12 that is a part of the semiconductor device 1 is referred to as a "first sealing member", the sealing member 6 can be said to be a "second sealing member" that covers the semiconductor device 1.

[0131] The semiconductor module S1 is a configuration in which the second external exposure layer 153 of the semiconductor device 1 and the lead frame 4 are bonded by the bonding member 5. Therefore, unlike the conventional semiconductor module described in Japanese Patent Application Publication No. 2001-156225, a wire connection between the semiconductor device 1 and the lead frame 4 is not required. Further, since a wire is not used, a heat sink for preventing the wire from contacting the second heat sink 3 is also not required to be disposed between the semiconductor device 1 and the second heat sink 3. Thus, the thickness of the semiconductor module can be reduced by an amount corresponding to the heat sink, and since the thermal resistance of the heat sink does not exist, the thermal resistance from the semiconductor device 1 to the second heat sink 3 is reduced.

[0132] Thus, the semiconductor module S1 is configured to achieve thinness and low thermal resistance by using the semiconductor device 1, compared to the conventional configuration.

[0133] According to the present embodiment, the boundary portions between the side surface 11c of the semiconductor element 11 and the sealing member 12 are covered with the conductive body 10, so that the force acting on these boundary portions at the time of the grinding process of the sealing member 12 is reduced, and a semiconductor device 1 of a FOP configuration in which peeling at the boundaries is suppressed is obtained. Further, the semiconductor device 1 has the conductive body 10 bonded to the back surface 11b of the semiconductor element 11, and the conductive body 10 is exposed from the sealing member 12 earlier than the semiconductor element 11 at the time of the grinding process of the sealing member 12, so that the back surface electrode of the semiconductor element 11 is not cut at the time of grinding. That is, the manufacturing process of the semiconductor device 1 is simplified compared with the past, and the process of forming an electrode on the back surface 11b after thinning is not required, so that a configuration in which the manufacturing cost is reduced is obtained. Furthermore, the semiconductor device 1 is capable of electrically connecting the lead frame 4 and the second electrode 14 which is a fan-out wiring by bonding to the second external exposure layer 153 via the bonding member 5, so that the semiconductor device 1 is particularly suitable for thinning and low thermal resistance of a semiconductor module of a two-side heat dissipation configuration.

[0134] (First Modification of the First Embodiment)

[0135] The semiconductor device 1 may, for example, have a through-hole 101 which is provided so as to extend in the thickness direction in a portion of the conductive body 10 which is outside the outer contour of the semiconductor element 11, as shown in Figure 8

[0136] Specifically, when the sealing member 12 is ground from the back surface 11b side of the semiconductor element 11 in the state shown in Figure 9 the manufacturing process of the semiconductor device 1 of the above-described first embodiment, the through-hole 101 disperses the force acting on the boundary between the end surface 10c of the conductive body 10 and the sealing member 12. In the case where the conductive body 10 does not have the through-hole 101, the force at the time of grinding acts on the boundary between the end surface 10c of the conductive body 10 and the sealing member 12 in the grinding process, and it is possible that they peel.

[0137] In contrast, in the case where the conductive body 10 has the through-hole 101, the force at the time of grinding acts on the boundary between the end surface 10c of the conductive body 10 and the sealing member 12, and the boundary between the through-hole 101 and the sealing member 12. That is, by providing the through-hole 101 to the conductive body 10, the force acting on the boundary between the end surface 10c of the conductive body 10 and the sealing member 12 is reduced in the grinding process of the sealing member 12, and peeling at these boundaries is suppressed. Further, the number, size, and arrangement of the through-holes 101 are arbitrary, and can be appropriately changed.

[0138] Even if it is assumed that the conductive body 10 has a plurality of through-holes 101, as shown in Figure 3I ​the interface peeling P1 between the end surface 10c of the electric conductor 10 and the sealing member 12 occurs, and since the through-hole 101 exists on the inner side of the end surface 10c, even if the interface peeling P1 wants to further progress to the inside, it stops at the through-hole 101 of the upper surface 10a. Further, since the sealing member 12 filled in the inside of the through-hole 101 is restricted in movement at the time of cold and heat cycles by the inner wall of the through-hole 101, even if the interface peeling P2 between the through-hole 101 and the sealing member 12 occurs, the interface peeling P2 hardly progresses to the inside. As a result, whichever of the interface peelings P1, P2 occurs, the case that the peeling progresses to the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12 is also suppressed.

[0139] By this modification example, the same effect as the above-described first embodiment can also be obtained. Further, the interface peeling between the end surface 10c of the electric conductor 10 and the sealing member 12 is suppressed, and even if the interface peeling between the electric conductor 10 and the sealing member 12 occurs, it hardly reaches the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12, becoming the semiconductor device 1 that can obtain a more highly reliable effect.

[0140] (Second Modification Example of First Embodiment)

[0141] The semiconductor device 1 may, for example, have a groove portion 102 in the electric conductor 10 on the outside of the semiconductor element 11 as shown in Figure 10 The groove portion 102 is provided in order to stop the interface peeling between the end surface 10c of the electric conductor 10 and the sealing member 12 and hinder the progress to the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12 in the case that the interface peeling occurs.

[0142] The groove portion 102 is, for example, annular to surround the semiconductor element 11, but as long as it can suppress the interface peeling between the electric conductor 10 and the sealing member 12 toward the side surface 11c of the semiconductor element 11, the shape is arbitrary. The groove portion 102 is formed by, for example, an arbitrary machining method such as press machining, laser machining, and the like.

[0143] By this modification example, the same effect as the above-described first embodiment can also be obtained. Further, even if the interface peeling between the electric conductor 10 and the sealing member 12 occurs, the peeling is stopped by the groove portion 102, becoming the semiconductor device 1 that can obtain the effect that the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12 is highly reliable.

[0144] (Third Modification Example of First Embodiment)

[0145] The semiconductor device 1 may, for example, have a groove portion 102 in the electric conductor 10 on the outside of the semiconductor element 11 as shown in Figure 11As shown, the protruding portion 103 is provided on the end surface 10c of the electrically conductive body 10. The protruding portion 103 is provided to suppress the progress of interface peeling between the end surface 10c of the electrically conductive body 10 and the sealing member 12 in the event that interface peeling occurs.

[0146] The protruding portion 103 is formed, for example, in a ring shape over the entire area of the end surface 10c of the electrically conductive body 10, but the shape and the like thereof are arbitrary as long as the interface peeling between the end surface 10c of the electrically conductive body 10 and the sealing member 12 can be suppressed. The protruding portion 103 is formed, for example, by an arbitrary machining method such as cutting machining.

[0147] With this modification example as well, the semiconductor device 1 that can obtain the same effects as the above-described second modification example is obtained.

[0148] (4th Modification Example of 1st Embodiment)

[0149] The semiconductor device 1 may, for example, have, as shown, Figure 12 a high adhesion portion 104 having higher adhesion between the electrically conductive body 10 and the sealing member 12 than the electrically conductive body 10 in a portion of the upper surface 10a of the electrically conductive body 10 that is outside the outer contour of the semiconductor element 11. The high adhesion portion 104 is provided to improve the adhesion between the electrically conductive body 10 and the sealing member 12 and to suppress the progress of interface peeling between the end surface 10c of the electrically conductive body 10 and the sealing member 12 to the semiconductor element 11 in the event that interface peeling occurs.

[0150] The high adhesion portion 104 is formed, for example, of a resin material such as polyimide by an arbitrary wet film formation method such as dispenser coating. The high adhesion portion 104 is formed, for example, in a ring shape that surrounds the semiconductor element 11 in a frame shape in the upper surface 10a, but is not limited thereto and the arrangement and the shape and the like thereof can be appropriately changed.

[0151] With this modification example as well, the semiconductor device 1 that can obtain the same effects as the above-described second modification example is obtained.

[0152] (5th Modification Example of 1st Embodiment)

[0153] The semiconductor device 1 may, for example, have, as shown, Figure 13 a roughened portion 105 having a concavo-convex shape of microns or less in a portion of the upper surface 10a of the electrically conductive body 10 that is outside the outer contour of the semiconductor element 11. The roughened portion 105 is provided to improve the adhesion between the electrically conductive body 10 and the sealing member 12 by an anchor effect and to suppress the progress of interface peeling between the end surface 10c of the electrically conductive body 10 and the sealing member 12 to the semiconductor element 11 in the event that interface peeling occurs.

[0154] The roughened portion 105 is formed, for example, in the upper surface 10a in a ring shape that surrounds the semiconductor element 11 in a frame shape, but is not limited thereto, and the arrangement, shape, and the like can be appropriately changed. The roughened portion 105 is formed, for example, by an arbitrary processing method such as laser processing.

[0155] By the present modification example, the semiconductor device 1 that can obtain the same effect as the above-described second modification example is also obtained.

[0156] (Sixth Modification Example of First Embodiment)

[0157] The semiconductor device 1 can also have, for example, as shown in Figure 14 the roughened portion 111 having a concavo-convex shape of microns or less on the side surface 11c of the semiconductor element 11. The roughened portion 111 is provided to improve the adhesion between the semiconductor element 11 and the sealing member 12 by the anchoring effect, and to suppress the progress of the interface peeling between the semiconductor element 11 and the sealing member 12 even if the interface peeling occurs between the conductive body 10 and the sealing member 12.

[0158] The roughened portion 111 can be formed, for example, by roughening processing by laser processing when the semiconductor element 11 is cut from a silicon wafer. Hereinafter, for the sake of simplicity of explanation, the roughening processing by laser processing of the side surface 11c of the semiconductor element 11 described above is sometimes referred to as "laser cutting".

[0159] According to the present modification example, the same effect as the above-described first embodiment is obtained. Further, even if the interface peeling occurs between the conductive body 10 and the sealing member 12, the progress of the peeling to the rewiring layer 15 is suppressed by improving the adhesion of the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12, and a semiconductor device 1 with higher reliability is obtained.

[0160] (Seventh Modification Example of First Embodiment)

[0161] The semiconductor device 1 can also have, for example, as shown in Figure 15 the structure in which the recessed portion 112 is provided on the back surface 11b of the semiconductor element 11, and the conductive body 10 is housed in the recessed portion 112 and is joined to the bottom portion 112a of the recessed portion 112. In addition, the "bottom portion 112a of the recessed portion 112" refers to a portion that is located on the bottom surface of the recessed portion 112 when viewed from the normal direction with respect to the back surface 11b side, for example.

[0162] In this case, the thickness of the semiconductor element 11 is larger than that of the above-described first embodiment, and thus the contact area between the side surface 11c of the semiconductor element 11 and the sealing member 12 is increased, and the interface peeling between the side surface 11c of the semiconductor element 11 and the sealing member 12 at the back surface polishing of the sealing member 12 is suppressed. Further, in the present modification example, the planar size of the conductive body 10 is smaller than that of the semiconductor element 11, and the thickness of the conductive body 10 is the same as the depth of the recessed portion 112.

[0163] The recess 112 is formed, for example, by forming a protective film in a predetermined pattern on the back surface 11b of the semiconductor element 11 and then anisotropically etching the exposed portion of the protective film using an alkaline solution such as that used in silicon etching. Alternatively, the recess 112 can be formed by separately preparing a ring-shaped silicon substrate having an inner diameter larger than the outer diameter of the conductor 10 and performing anodic bonding on the back surface 11b of the semiconductor element 11. In the latter case, the back surface 11b of the semiconductor element 11 serves as the bottom 112a of the recess 112.

[0164] In this modified example, during back grinding of seal 12, the boundary between side surface 11c of semiconductor element 11 and seal 12 contacts the surface of the grinding machine. However, the increased contact area between side surface 11c of semiconductor element 11 and seal 12 suppresses delamination at this boundary. Furthermore, during back grinding of seal 12, the boundary contacting the grinding tool, such as the grinding machine, includes not only the boundary between side surface 11c of semiconductor element 11 and seal 12, but also the boundary between conductor 10 and seal 12, and recess 112 and seal 12. Consequently, the force during back grinding is dispersed, reducing the force acting on the boundary between side surface 11c of semiconductor element 11 and seal 12, thereby suppressing delamination at this boundary.

[0165] Therefore, according to this modification, similarly to the first embodiment, delamination at the interface between the side surface 11 c of the semiconductor element 11 and the sealing member 12 is suppressed, thereby achieving a highly reliable semiconductor device 1 .

[0166] (Second embodiment)

[0167] Reference Figure 16 A semiconductor device 1 according to a second embodiment will be described.

[0168] The semiconductor device 1 of this embodiment is, for example, Figures 17-19 As shown, the present embodiment differs from the first embodiment in that the side surfaces 11c of the semiconductor element 11 are covered with sidewall insulating portions 18 made of an insulating material. This embodiment will mainly describe this difference.

[0169] The semiconductor device 1 of this embodiment is, for example, Figure 17 Manufactured using the manufacturing process shown.

[0170] Specifically, first, Figures 18A-18DAs shown, a prescribed region including a region where the semiconductor element 11 is to be bonded later in the upper surface 10a of the electrically conductive body 10 is coated with the temporary protective member 110. The temporary protective member 110 is made of an arbitrary material that can be peeled off after the seal 12 is formed, such as an adhesive material or a photosensitive resin material, or the like. The temporary protective member 110 can use, for example, a material whose adhesive force with the electrically conductive body 10 is reduced by ultraviolet irradiation or heating, or the like in the case of being made of an adhesive material, and a positive resist material or the like in the case of being made of a photosensitive resin material.

[0171] In addition, the temporary protective member 110 is used in order to provide the recess 121 described later, and in the case where it is desired to make the depth of the recess 121 prescribed or more (not limited, for example, 20 μm or more), it is preferable to be made of an adhesive material and a temporary member. In this case, the temporary member can use an arbitrary material as long as it is a material that has heat resistance and that does not have compatibility with the material that constitutes the seal 12 and that can withstand the heating in the molding process of the seal 12. The temporary protective member 110 is larger in planar size than the semiconductor element 11 in order to allow the semiconductor element 11 to be contained in the recess 121 that is formed later.

[0172] Next, as shown in FIG. 6, the workpiece in which the temporary protective member 110 and the electrically conductive body 10 are covered with the seal 12 is peeled off from the support substrate 200, and the seal 12 is ground from the side of the lower surface 10b of the electrically conductive body 10 to expose the lower surface 10b of the electrically conductive body 10. Next, by peeling off the temporary protective member 110 from the electrically conductive body 10, for example, as shown in FIG. 7, the seal 12 is formed with the recess 121 that exposes the electrically conductive body 10. Figure 18A

[0173] Next, as shown in FIG. 6, the workpiece in which the temporary protective member 110 and the electrically conductive body 10 are covered with the seal 12 is peeled off from the support substrate 200, and the seal 12 is ground from the side of the lower surface 10b of the electrically conductive body 10 to expose the lower surface 10b of the electrically conductive body 10. Next, by peeling off the temporary protective member 110 from the electrically conductive body 10, for example, as shown in FIG. 7, the seal 12 is formed with the recess 121 that exposes the electrically conductive body 10. Figure 18B Figure 18C

[0174] Then, as shown in FIG. 8, the semiconductor element 11 is housed in the recess 121, and the electrically conductive body 10 is bonded to the back surface lib of the semiconductor element 11 by a bonding member that is not shown. In addition, the semiconductor element 11 can be made to have the roughened portion 111 shown in FIG. 9 on the side surface lie by laser cutting or the like in order to further improve the adhesion between the side wall insulating portion 18 that is formed later and the side surface lie. Figure 18D Figure 18D

[0175] Next, as shown in FIG. 6, the workpiece in which the temporary protective member 110 and the electrically conductive body 10 are covered with the seal 12 is peeled off from the support substrate 200, and the seal 12 is ground from the side of the lower surface 10b of the electrically conductive body 10 to expose the lower surface 10b of the electrically conductive body 10. Next, by peeling off the temporary protective member 110 from the electrically conductive body 10, for example, as shown in FIG. 7, the seal 12 is formed with the recess 121 that exposes the electrically conductive body 10. Figure 15 ​​​​​As shown, a first layer 1511 of the insulating layer 151 is formed by a wet film formation method such as spin coating. At this time, the insulating layer material flows into the gap between the recess 121 and the side surface 11c of the semiconductor element 11 and hardens, thereby forming the first layer 1511 and the side wall insulating portion 18. That is, the side wall insulating portion 18 is formed of the same insulating material as the insulating layer 151, such as polyimide.

[0176] Hereinafter, the rewiring layer 15 is formed by the same process as the manufacturing method explained in the above first embodiment, whereby the semiconductor device 1 of the present embodiment can be manufactured.

[0177] In the manufacturing method of the above first embodiment, it is possible that the resin material constituting the sealing member 12 enters between the support substrate 200 and the surface 11a of the semiconductor element 11 at the time of molding of the sealing member 12 for some reason. In this case, when the sealing member 12 is constituted of an insulating material containing a filler such as a heat dissipation filler, as shown in Figure 18E The filler 122 can enter between the insulating layer 151, which is a part of the rewiring layer 15, and the surface 11a of the semiconductor element 11. If such a filler 122 exists between the insulating layer 151 and the semiconductor element 11, the thickness of the insulating layer 151 on the filler 122 becomes thin, which can become a cause of insulation failure.

[0178] In contrast, the semiconductor device 1 of the present embodiment is manufactured by joining the conductor 10 and the semiconductor element 11 after molding of the sealing member 12 and forming the insulating layer 151, and therefore the constituting material of the sealing member 12 does not exist on the surface 11a of the semiconductor element 11. Therefore, the semiconductor device 1 becomes a structure in which insulation failure due to the filler 122 does not occur even when the sealing member 12 is constituted of an insulating material containing the filler 122.

[0179] Further, since the conductor 10 is joined to the semiconductor element 11 after back surface grinding of the sealing member 12, stress at the time of grinding does not act between the side surface 11c of the semiconductor element 11 and the side wall insulating portion 18, and interface peeling due to back surface grinding does not occur.

[0180] By the present embodiment, the semiconductor device 1 capable of obtaining the same effects as the above first embodiment is also obtained.

[0181] (Third Embodiment)

[0182] Reference will be made to Figure 19 The semiconductor device 1 of the third embodiment will be explained.

[0183] The semiconductor device 1 of the present embodiment is, for example, as Figures 20-22As shown, the conductive member 10 is not provided, and a recess 123 is formed on the surface of the sealing member 12 opposite the redistribution layer 15. Part or all of the back surface 11b of the semiconductor element 11 is exposed from the sealing member 12 within the recess 123. The semiconductor device 1 of this embodiment differs from the first embodiment described above in this respect. In this embodiment, this difference will be mainly described.

[0184] The semiconductor device 1 of this embodiment has a structure in which the other surface 12b of the sealing member 12 protrudes beyond the back surface 11b of the semiconductor element 11 and includes a recess 123 in which the back surface 11b of the semiconductor element 11 is exposed from the sealing member 12. Because the other surface 12b of the sealing member 12 protrudes beyond the back surface 11b of the semiconductor element 11, the boundary between the side surface 11c of the semiconductor element 11 and the sealing member 12 is not exposed to the grinding tool during grinding of the sealing member 12. Consequently, the semiconductor device 1 has a structure that suppresses delamination at the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12.

[0185] [Manufacturing method]

[0186] The semiconductor device 1 of this embodiment is, for example, Figure 20 Manufactured using the manufacturing process shown.

[0187] Specifically, for example Figures 21A-21D As shown, the semiconductor element 11 is prepared, and the entire area of ​​the back surface 11b is covered with a back surface protective member 120. The back surface protective member 120 is made of any material that can be peeled off after the sealing member 12 is formed, such as an adhesive material whose adhesion to the back surface 11b of the semiconductor element 11 decreases by ultraviolet irradiation or heating. Here, the case of using an adhesive material whose adhesion decreases by ultraviolet irradiation as the back surface protective member 120 is described as a representative example. In this case, as the back surface protective member 120, for example, any tape having an acrylic or silicone adhesive material that is cured by ultraviolet light on any base material such as PVC or polyolefin can be used.

[0188] Then, if Figure 21A As shown, the surface 11 a of the semiconductor element 11 is attached to the support substrate 200 , and the sealing member 12 covering the conductor 10 and the back surface protection member 120 is molded by compression molding or the like using a mold (not shown).

[0189] Then, if Figure 21B As shown in FIG. 1 , for example, a redistribution layer 15 is formed on the surface 11 a side of the semiconductor element 11 by the same steps as those in the first embodiment described above.

[0190] Then, the surface of the sealing member 12 on the side on which the back surface protective member 120 is covered is ground, as shown in Figure 21C , so as to expose the back surface protective member 120. In addition, in the grinding process of the sealing member 12, in order to prevent the back surface 1 lb of the semiconductor element 11 from being ground by mistake, the thickness of the back surface protective member 120 is not limited, but is preferably set to, for example, 60 μm or more.

[0191] Next, as shown by an arrow in Figure 21D , ultraviolet rays (UV) are irradiated from the other surface 12b side of the sealing member 12, so as to lower the adhesion of the back surface protective member 120, and lower the tightness between the back surface protective member 120 and the back surface 1 lb of the semiconductor element 11.

[0192] Finally, the back surface protective member 120 after the UV irradiation is peeled off by a cutting tape not shown, and as shown in Figure 21E , the sealing member 12 is formed with the recess 123 that exposes the back surface 1 lb of the semiconductor element 11.

[0193] For example, the semiconductor device 1 can be manufactured by the manufacturing method described above. Since the recess 123 is formed by peeling off the back surface protective member 120, and the back surface 1 lb of the semiconductor element 11 is exposed, the electrode forming process at the back surface 1 lb of the semiconductor element 11 after the grinding of the sealing member 12 is not necessary. In addition, the semiconductor device 1 can also be used to construct a semiconductor module having the same configuration as the first embodiment described above, in which case, the other member such as a heat dissipation member is joined to the back surface 1 lb of the semiconductor element 11 by applying the joining member 5 in the recess 123.

[0194] 〔Manufacturing Method Modification Example 1〕

[0195] In peeling off the back surface protective member 120, the back surface protective member 120 can also be peeled off via an adhesive tape whose adhesion is lowered by ultraviolet rays (hereinafter referred to as "UV tape").

[0196] Specifically, after the ultraviolet rays are irradiated, as shown in Figure 20 , the UV tape T is attached to the other surface 12b of the sealing member 12 and the back surface protective member 120, and the ultraviolet rays are irradiated to the portion of the UV tape T that is attached to the back surface protective member 120 using a mask M. Then, a cutting tape not shown is attached to the UV tape T, and the back surface protective member 120 is peeled off together with the UV tape T, and becomes Figure 22The semiconductor device 1 shown. Thereby, the back surface protector 120 is peeled off via the UV tape T which becomes a state of strong adhesion with the back surface protector 120 and low adhesion with the sealing member 12, the peeling force of the dicing tape is reduced, the load other than the back surface protector 120 is suppressed, and the deformation of the semiconductor device 1 is suppressed. That is, by using the UV tape T, the effect of improving the yield of the semiconductor device 1 of the present embodiment can be obtained.

[0197] 〔Manufacturing method modification example 2〕

[0198] In the above, an example in which an adhesive material is used as the back surface protector 120 and peeled off by the dicing tape is described, but is not limited thereto.

[0199] For example, the back surface protector 120 can be formed of a thermoplastic resin, and the recess 123 can be formed by dissolving and removing the back surface protector 120 with a chemical solution after polishing of the sealing member 12. For example, in this case, when polybutadiene is used as the back surface protector 120, as a chemical solution used to dissolve and remove the back surface protector 120, a solvent that does not dissolve the sealing member 12 but dissolves polybutadiene is used. As such a chemical solution, for example, toluene (8.9), dimethyl ether (8.8), and epoxy resin (10.9) having a solubility parameter value (SP value) close to that of polybutadiene (8.1 to 8.6) can be mentioned.

[0200] In this case, regarding the Figure 20 The attachment of the back surface protector 120 to the back surface 11b of the semiconductor element 11 shown can be performed by heat press bonding.

[0201] By this method, since no physical force is applied to the sealing member 12 when the back surface protector 120 is removed, the deformation of the semiconductor device 1 is suppressed, and the effect of improving the yield at the time of manufacturing can be obtained.

[0202] 〔Manufacturing method modification example 3〕

[0203] As the back surface protector 120, any material that decreases the adhesion between the back surface 11b of the semiconductor element 11 by heating can be used.

[0204] In this case, the back surface protector 120 uses a material that has a property of decreasing the adhesion force at a temperature higher than the heating temperature at the time of peeling the support substrate 200 after the sealing member 12 is molded. For example, in a case where the temperature at which the support substrate 200 and the workpiece after the sealing member 12 is molded are peeled is 190°C, as the back surface protector 120, a material that decreases the adhesion force at a temperature exceeding 190°C can be used. In this case, for example, as the adhesive material of the support substrate 200, Riva Alpha (registered trademark) 3195V manufactured by Nitto Denko Corporation that can be peeled at 190°C can be used. Further, as the back surface protector 120, Riva Alpha (registered trademark) 3195E manufactured by the same company that can be peeled at 230°C can be used. However, the above-described used material is only an example, and other publicly known materials can be used. Further, the peeling temperature can be appropriately changed.

[0205] Further, the back surface protector 120 is preferably composed of a material having low elasticity from the viewpoint of suppressing warping of the semiconductor element 11. This is to suppress generation of internal stress of the semiconductor element 11 as a cause of warping after peeling by hindering warping of the semiconductor element 11 due to heating at the time of peeling.

[0206] By this method, since no physical force acts on the sealing member 12 at the time of peeling the back surface protector 120, deformation of the semiconductor device 1 is suppressed, and an effect of improving the yield at the time of manufacturing can be obtained.

[0207] According to the present embodiment, the semiconductor device 1 that can obtain the same effect as the above-described first embodiment is obtained. Further, by having the recessed portion 123, in a case where the back surface 11b of the semiconductor element 11 in the semiconductor device 1 is joined to another member using the joining member 5, since the thickness of the joining member 5 is equal to or greater than the depth of the recessed portion 123, an effect that the thickness of the joining member 5 can be ensured to be equal to or greater than a predetermined value can be obtained. Further, in a case where, for example, a solder foil is used as the joining member 5, the solder foil can be previously disposed in the recessed portion 123 and then assembled to another member, and an effect that positioning of the joining member 5 at the time of assembly is not required can be obtained.

[0208] (First Modification of the Third Embodiment)

[0209] The recessed portion 123 is not limited to the example in which the shape is the same as that of the semiconductor element 11 as shown in FIG. 10, but for example, as shown in FIG. 11, the planar size of the back surface 11b of the semiconductor element 11 can be smaller than that of the recessed portion 123, and the recessed portion 123 can be formed so as to be included inside the outer contour of the back surface 11b of the semiconductor element 11. Figure 21A Figure 20

[0210] ​​The semiconductor device 1 is configured so that the boundary between the side surface 11c of the semiconductor element 11 and the sealing member 12 is covered by the sealing member 12, and thus the force acting on the boundary portion at the time of grinding of the sealing member 12 is further reduced compared with the third embodiment described above.

[0211] In this case, the portion of the sealing member 12 covering the back surface 11b becomes an "overhanging portion" that overhangs toward the back surface 11b of the semiconductor element 11. The overhanging portion presses the semiconductor element 11, and stabilizes the interface between the side surface 11c of the semiconductor element 11 and the sealing member 12. Further, in the case where a plurality of semiconductor devices 1 are manufactured at one time using a silicon wafer, the overhanging portion also functions to suppress chip pop and wafer breakage at the time of grinding and cutting of the sealing member 12 by pressing the semiconductor element 11.

[0212] According to the present modification, in addition to the effects of the third embodiment described above, the effects of suppressing chip pop and wafer breakage at the time of manufacturing a plurality of semiconductor devices 1 at one time are obtained.

[0213] (Second Modification of the Third Embodiment)

[0214] The recessed portion 123 may, for example, be larger than the planar size of the back surface 11b of the semiconductor element 11, and formed so that the back surface 11b of the semiconductor element 11 is contained inside the recessed portion 123, as shown in FIG. 12. Figure 23

[0215] The semiconductor device 1 is configured so that, at the time of joining a heat dissipation member or the like to the back surface 11b of the semiconductor element 11 via the joining member 5, the heat of the semiconductor element 11 is diffused to a larger area through the joining member 5 filled in the recessed portion 123, and thus becomes a configuration in which the heat dissipation property is improved. That is, the semiconductor device 1 of the present modification becomes a configuration suitable for constituting a semiconductor module in which the heat dissipation is improved.

[0216] According to the present modification, in addition to the effects of the third embodiment described above, the effects of further improving the heat dissipation property of the semiconductor element 11 of the mounted semiconductor device 1 are obtained.

[0217] (Fourth Embodiment)

[0218] Referring to Figures 25-26D The semiconductor device 1 of the fourth embodiment will be described.

[0219] The semiconductor device 1 of the present embodiment is, for example, as shown in FIG. 13. Figure 25 ​As shown, the present invention is different from the third embodiment described above in that it includes a substantially frame-shaped frame covering portion 19 that covers the side surface 11c of the semiconductor element 11. In this embodiment, this difference will be mainly described.

[0220] In the present embodiment, the side surfaces 11 c of the semiconductor element 11 are covered by the frame cover 19 , while the back surface 11 b of the semiconductor element 11 is not covered by the frame cover 19 and is exposed to the outside.

[0221] The frame cover 19 is made of any insulating material having a higher adhesion to the semiconductor element 11 than the sealing material 12, such as polyimide, polyamide, or butyl acetate. Figure 25 As shown, its thickness dimension is larger than that of the semiconductor element 11, and it has a generally cylindrical shape with a flange portion protruding along the film plane on the redistribution layer 15 side. The frame cover 19 has the same thickness as the sealing material 12 and has an opening 191 that exposes the back surface 11b of the semiconductor element 11 to the outside. This opening 191 corresponds to the recess 123 in the third embodiment described above.

[0222] The frame cover 19 covers the back surface 11b and side surfaces 11c of the semiconductor element 11 during the period from molding to grinding of the seal 12 in the manufacturing process of the semiconductor device 1, which will be described later. It is a member that protects the back surface 11b of the semiconductor element 11 during grinding of the seal 12. The frame cover 19 has the above-described shape by removing the portion covering the back surface 11b of the semiconductor element 11 after grinding of the seal 12.

[0223] The semiconductor device 1 of this embodiment is, for example, Figures 26A-26D The manufacturing process shown is used to manufacture.

[0224] First, for example Figure 26A As shown, after the surface 11a of the semiconductor element 11 is attached to the support substrate 200, a resin sheet 190 made of polyimide or the like is attached to the semiconductor element 11. As a result, the back surface 11b and side surfaces 11c of the semiconductor element 11 are covered and protected by the resin sheet 190, and chip floating from the support substrate 200 and positional deviation on the support substrate 200 are suppressed.

[0225] Then, for example Figure 26B As shown, a mold (not shown) is prepared, and the sealing member 12 covering the semiconductor element 11 is molded together with the resin sheet 190 by compression molding or the like. Then, the workpiece is peeled from the supporting substrate 200 by any method such as heating, so that the surface 11a of the semiconductor element 11 is exposed to the outside.

[0226] Then, for example Figure 26C As shown, the redistribution layer 15 covering the surface 11 a of the semiconductor element 11 , a portion of the frame cover 19 , and the one surface 12 a of the sealing material 12 is formed by the same steps as those in the first embodiment.

[0227] Then, for example Figure 26D As shown, the sealing member 12 is ground from its surface covering the resin sheet 190 using a grinding tool such as a grinder, so that the portion of the resin sheet 190 covering the back surface 11 b of the semiconductor element 11 is exposed from the sealing member 12 .

[0228] Finally, the portion of the resin sheet 190 covering the back surface 11 b of the semiconductor element 11 is removed by any method such as photolithography or laser processing to form an opening 191 , exposing the back surface 11 b of the semiconductor element 11 to the outside.

[0229] This manufacturing method enables the manufacture of the semiconductor device 1, wherein the back surface 11b of the semiconductor element 11 is protected by the resin sheet 190 during the grinding of the seal 12, thereby eliminating the need for an electrode forming step on the back surface 11b side of the seal 12 after grinding. Furthermore, since the portion of the resin sheet 190 covering the back surface 11b of the semiconductor element 11 is selectively removed by an arbitrary etching method, physical forces are less likely to act on the boundary between the side surface 11c of the semiconductor element 11 and the frame cover 19. Furthermore, by forming the frame cover 19 from a resin material having a higher adhesion to the semiconductor element 11 than the seal 12, the interface between the side surface 11c of the semiconductor element 11 and the frame cover 19 becomes more closely adhered, thereby suppressing peeling at this interface.

[0230] This embodiment also achieves the same effects as those of the third embodiment. Furthermore, since the semiconductor element 11 is covered with the resin sheet 190 after being mounted on the support substrate 200, chip floating and positional deviation are suppressed, thereby improving the manufacturing yield.

[0231] Furthermore, when manufacturing a plurality of semiconductor devices 1 of this embodiment at once, the resin sheet 190 is attached so as to cover all of the plurality of semiconductor elements 11 mounted on the support substrate 200. In this case, the flange portion of the frame cover 19 is extended along the film plane of the redistribution layer 15 to the end face of the semiconductor device 1.

[0232] (Fifth embodiment)

[0233] Reference Figures 27-29F A semiconductor device 1 according to a fifth embodiment will be described.

[0234] The semiconductor device 1 of this embodiment is, for example, Figure 27 As shown, the protrusion 106 of the conductor 10 covering the back surface 11b of the semiconductor element 11, located outside the outer contour of the semiconductor element 11, has a porous structure with a lower density than other parts of the conductor 10. This point differs from the first embodiment described above. In this embodiment, this difference will be mainly described.

[0235] In this embodiment, the conductor 10 is composed of, for example, a sintered metal. The "sintered metal" herein refers to a structure primarily composed of a metal material having at least electrical conductivity, with a low-density porous structure (described later) formed in a portion where no predetermined pressure is applied. Examples of sintered metals include, but are not limited to, sintered silver primarily composed of silver and sintered copper primarily composed of copper. In this embodiment, the conductor 10 is described as being composed of sintered silver as a representative example.

[0236] In this embodiment, the conductor 10 is larger in planar size than the semiconductor element 11 and is configured to cover the entire area of ​​the back surface 11b of the semiconductor element 11. Figure 27 As shown, the area of ​​lower surface 10b located inside the outer contour of semiconductor element 11, that is, directly below, is exposed to the outside. Meanwhile, the portion of conductor 10 located outside the outer contour of semiconductor element 11 serves as protrusion 106, and a portion of the area of ​​lower surface 10b located at protrusion 106 is tilted toward semiconductor element 11 and covered by sealing material 12.

[0237] The protrusion 106 has a porous structure with a lower density than other parts of the conductor 10. Specifically, the protrusion 106 is, for example, Figure 28 As shown, the porous body has numerous micropores or voids on the order of microns or less, and has a lower density than the rest of the conductor 10. This is because the protrusion 106 is a flash generated during the process of forming the conductor 10, where a portion of the material constituting the conductor 10 extends outward from the outer contour of the semiconductor element 11, thereby forcibly protecting the area from pressure. The process of forming the conductor 10 will be described later.

[0238] The protrusion 106 is formed with many micropores connected to at least the outermost surface of the protrusion 106, and the seal 12 is in a state of entering the micropores. In addition, with respect to the micropores of the protrusion 106, the minimum width of the opening located at the outermost surface of the protrusion 106 is greater than 10 nm, so that the resin material constituting the seal 12 can enter when the seal 12 is formed. As a result, an anchoring effect is generated, and the adhesion between the protrusion 106 and the seal 12 is improved, thereby suppressing the interface peeling between the protrusion 106 and the seal 12 starting from the lower surface 10b side of the conductor 10. In addition, the protrusion 106 has a concave-convex shape formed on the outermost surface, that is, a tiny concave-convex shape. In addition to the anchoring effect brought by the micropores, an anchoring effect is also generated due to the seal 12 following the tiny concave-convex shape. As a result, the semiconductor device 1 of this embodiment suppresses the interface peeling between the side 11c of the semiconductor element 11 and the seal 12, and becomes a highly reliable structure.

[0239] On the other hand, the directly lower portion of the conductor 10 located directly below the semiconductor element 11 in a plan view is a region where the constituent material of the conductor 10 is pressed via the semiconductor element 11 during the formation process of the conductor 10. Therefore, the directly lower portion of the conductor 10 is, for example, Figure 28 As shown, it is denser than the protrusion 106, with fewer voids and a higher density.

[0240] [Manufacturing method]

[0241] Next, a method for manufacturing the semiconductor device 1 of this embodiment will be described. Figures 29A-29F The following mainly describes the steps that are different from those in the first embodiment.

[0242] First, for example Figure 29A As shown, a conductive sheet 100, which will later constitute the conductor 10, and a base sheet 201 serving as its foundation are prepared. For example, a sinterable film containing metal particles such as silver nanoparticles or silver microparticles can be used as the conductive sheet 100. For example, a sheet made of a resin material such as rubber that can withstand the temperatures of the stamping process described later (e.g., a silicone rubber sheet) can be used as the base sheet 201.

[0243] The conductive sheet 100 has a thickness of, for example, 10 μm to 100 μm and an elastic modulus of approximately 20 GPa to 80 GPa. The base sheet 201 has a thickness of, for example, 0.1 mm to 1 mm and an elastic modulus of approximately 5 MPa.

[0244] Then, for example Figure 29BAs shown, the conductive sheet 100 is overlapped with the base sheet 201, and a semiconductor element 11 prepared separately is placed on the conductive sheet 100. Note that, here, the case where one semiconductor element 11 is placed on the conductive sheet 100 is described as a representative example for the sake of easy understanding of the process, but the present application is not limited thereto, and a plurality of semiconductor elements 11 can be placed to manufacture a plurality of semiconductor devices 1 at a time.

[0245] Next, as shown in FIG. 6, for example, the semiconductor element 11 is pressed from the surface 11a side using a pressing mechanism not shown, and a portion of the conductive sheet 100 is pushed. At this time, a portion of the base sheet 201 including the region directly below the semiconductor element 11 is elastically deformed, and a shearing force is generated between the directly below region of the semiconductor element 11 and the region adjacent thereto in the conductive sheet 100. As a result, the directly below portion of the semiconductor element 11 and the peripheral region thereof in the conductive sheet 100 are punched and transferred to the semiconductor element 11 as shown in FIG. 7. Figure 29C Figure 29D

[0246] Note that, the above punching process can be performed, for example, in the atmosphere at 100°C to 200°C and 1 MPa to 5 MPa, but the temperature, pressure, and the like can be appropriately changed depending on the materials of the conductive sheet 100 and the base sheet 201. Further, by the punching process, a portion of the lower surface 10b of the conductive body 10 at the protruding portion 106 becomes a state of being inclined toward the semiconductor element 11 side, that is, the upper side.

[0247] Then, for example, on a heating stage not shown, the semiconductor element 11 and the conductive material after the transfer are heated at a firing temperature of 200°C to 300°C to sinter the conductive material. By this, the protruding portion 106 can become a porous structure having many micropores, and the conductive body 10 in which the directly below portion of the semiconductor element 11 is densified more than the protruding portion 106 is formed. Further, by the sintering process, the conductive body 10 becomes a state of being joined to the back surface 11b of the semiconductor element 11.

[0248] Next, as shown in FIG. 8, for example, the surface 11a of the semiconductor element 11 is attached to the support base plate 200, and the semiconductor element 11 to which the conductive body 10 is joined is held. Figure 29E

[0249] Next, a mold not shown is prepared, and the semiconductor element 11 held by the support base plate 200 is covered with a resin material such as an epoxy resin by compression molding or the like, and hardened by heating or the like, whereby the semiconductor element 11 is embedded in the resin material as shown in FIG. 9. Figure 29F ​​​The seal 12 is formed as shown. Thereby, the side surface 11c of the semiconductor element 11 and the conductive body 10 become a state of being covered with the seal 12. In particular, the protruding portion 106 having many micropores in the conductive body 10 becomes a state of being highly adhered to the seal 12 compared to other portions of the conductive body 10 by an anchoring effect.

[0250] Next, the semiconductor device 1 of the present embodiment can be manufactured by performing the same procedures as the semiconductor device 1 of the above-described first embodiment, for example. Figures 3D-3J The semiconductor device 1 of the present embodiment becomes a configuration in which the force acting on the boundary portions between the side surface 11c of the semiconductor element 11 and the seal 12 is reduced at the time of the grinding process of the seal 12, since the boundary portions are covered with the conductive body 10, as with the above-described first embodiment. Therefore, the same effects as the above-described first embodiment can be obtained. Further, since the protruding portion 106 in the conductive body 10 is a porous body, the seal 12 enters and an anchoring effect is generated, so the adhesion between the seal 12 and the protruding portion 106 is further improved, and the effect of further suppressing the interface peeling between the side surface 11c of the semiconductor element 11 and the seal 12 is obtained.

[0251] The semiconductor device 1 of the present embodiment becomes a configuration in which the force acting on the boundary portions between the side surface 11c of the semiconductor element 11 and the seal 12 is reduced at the time of the grinding process of the seal 12, since the boundary portions are covered with the conductive body 10, as with the above-described first embodiment. Therefore, the same effects as the above-described first embodiment can be obtained. Further, since the protruding portion 106 in the conductive body 10 is a porous body, the seal 12 enters and an anchoring effect is generated, so the adhesion between the seal 12 and the protruding portion 106 is further improved, and the effect of further suppressing the interface peeling between the side surface 11c of the semiconductor element 11 and the seal 12 is obtained.

[0252] In the above-described embodiment, an example in which the conductive body 10 is formed by the punching and transfer process using the conductive sheet 100 and the base sheet 201 is described, but is not limited to this process. For example, a sinterable paste material or the like composed of metal fine particles such as silver nanoparticles can be dispenser-coated, the semiconductor element 11 can be placed on the coated silver paste, and the conductive body 10 can be formed by performing sintering after pressure is applied via the semiconductor element 11. In this case, the conductive body 10 is formed, for example, as shown in FIG. 9. Figure 30 As shown in FIG. 9, the entire region of the lower surface 10b is a flat surface, and the entire region of the lower surface 10b is exposed from the seal 12, but since the high adhesion of the protruding portion 106 to the seal 12 is secured, there is no particular problem. That is, in the present embodiment, with respect to the conductive body 10, as long as the protruding portion 106 is a porous body having a lower density than the directly underlying portion, the outer shape can be changed according to the manufacturing process.

[0253] (Other Embodiments)

[0254] The present application is described in terms of embodiments, but it is understood that the application is not limited to the embodiments or constructions. The application includes various modifications and equivalent arrangements within the scope of the application. In addition, various combinations and configurations including more than one element, either of the elements, or none of the elements, of the combinations and configurations are also within the scope of the application.

[0255] For example, in the above-described second to fifth embodiments, the roughened portion 111 can be formed on the side surface 11c of the semiconductor element 11. In addition, the semiconductor device 1 of the above-described first embodiment is not limited, and the semiconductor device 1 of other embodiments can be used to configure the semiconductor module. For example, as shown in FIG. 10, in the case where the semiconductor device 1 of the third embodiment is used, the semiconductor module in which the interface peeling of the side surface 11c of the semiconductor element 11 is suppressed and thinning and high heat dissipation are achieved is obtained. Figure 31 For example, in the above-described second to fifth embodiments, the roughened portion 111 can be formed on the side surface 11c of the semiconductor element 11. In addition, the semiconductor device 1 of the above-described first embodiment is not limited, and the semiconductor device 1 of other embodiments can be used to configure the semiconductor module. For example, as shown in FIG. 10, in the case where the semiconductor device 1 of the third embodiment is used, the semiconductor module in which the interface peeling of the side surface 11c of the semiconductor element 11 is suppressed and thinning and high heat dissipation are achieved is obtained.

Claims

1. A semiconductor device characterized by comprising: a semiconductor element; a conductor joined to one side of a back surface of the semiconductor element; a sealing member covering a side surface of the semiconductor element and a part of the conductor; and a rewiring layer having an insulating layer covering a surface of the semiconductor element and a part of the sealing member, a first electrode and a second electrode connected to the semiconductor element, a first external exposing layer having electric conductivity covering a part of the first electrode exposed from the insulating layer, and a second external exposing layer having electric conductivity covering a part of the second electrode exposed from the insulating layer; an end portion of the second electrode on a side opposite to the semiconductor element is extended to a position in the rewiring layer which is outside an outer contour of the semiconductor element; the second external exposing layer covers a part of the second electrode which is outside the outer contour of the semiconductor element; an entire area of the back surface of the semiconductor element is inside an outer contour of the conductor; a planar dimension of the conductor in plan view is larger than that of the semiconductor element, the conductor is composed of a metal sintered body, and a lower surface of the conductor on a side opposite to an upper surface of the conductor joined to the back surface of the semiconductor element is exposed from the sealing member; a part of the conductor which is outside the outer contour of the semiconductor element is made into a protruding portion, the protruding portion has at least a plurality of voids of submicron order or less connected to a surface layer, and a density of the protruding portion is lower than that of the remaining part of the conductor.

2. The semiconductor device according to claim 1, characterized in that the semiconductor element has a roughened portion having a concavo-convex shape of submicron order or less on a side surface connecting the surface and the back surface.

3. A semiconductor device characterized by comprising: a semiconductor element; a sealing member covering a side surface of the semiconductor element; and a rewiring layer having an insulating layer covering a surface of the semiconductor element and a part of the sealing member, a first electrode and a second electrode connected to the semiconductor element, a first external exposing layer having electric conductivity covering a part of the first electrode exposed from the insulating layer, and a second external exposing layer having electric conductivity covering a part of the second electrode exposed from the insulating layer; an end portion of the second electrode on a side opposite to the semiconductor element is extended to a position in the rewiring layer which is outside an outer contour of the semiconductor element; the second external exposing layer covers a part of the second electrode which is outside the outer contour of the semiconductor element; a side surface of the sealing member opposite to a side covered by the rewiring layer is protruded from a back surface of the semiconductor element, and has a recessed portion recessed toward the side; a part or all of the back surface of the semiconductor element is exposed from the sealing member in the recessed portion of the sealing member; a side surface of the semiconductor element connecting the surface and the back surface has a high adhesion portion having a higher adhesion between the sealing member than the back surface; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The high adhesion portion is a frame-shaped frame covering portion that covers the side surface of the semiconductor element; The frame covering portion is made of a resin material different from the seal, the resin material having higher adhesion to the semiconductor element than the seal and higher adhesion between the seal and the semiconductor element than the seal, the frame covering portion having the same thickness as the seal, and the frame covering portion covering the wall surface of the recess of the seal.

4. A semiconductor module, comprising: a semiconductor device including a semiconductor element, a first seal covering a side surface of the semiconductor element, a rewiring layer, and a conductive body, the rewiring layer having an insulating layer covering a surface of the semiconductor element and a portion of the first seal, an electrode connected to the semiconductor element, and an external exposure layer having conductivity covering a portion of the electrode exposed from the insulating layer, the conductive body being joined to a back surface of the semiconductor element opposite the surface; a heat dissipation member joined to a portion of the conductive body exposed from the first seal via a joining member; a lead frame electrically joined to the electrode via the external exposure layer or the joining member; and a second seal covering the semiconductor device, a portion of the heat dissipation member, and a portion of the lead frame; an entire area of the back surface of the semiconductor element is inside an outer contour of the conductive body; a planar dimension of the conductive body in plan view is larger than the semiconductor element, the conductive body is made of a metal sintered body, and a lower surface of the conductive body opposite an upper surface joined to the back surface of the semiconductor element is exposed from the seal; a portion of the conductive body outside the outer contour of the semiconductor element is formed as a protruding portion, the protruding portion has at least a plurality of voids of submicron order connected to a surface layer, and a density of the protruding portion is lower than a remaining portion of the conductive body; the semiconductor device is a fan-out package structure in which an end portion of the electrode exposed from the insulating layer is extended to a position outside the outer contour of the semiconductor element. ​ ​

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