Timing editing method and test system for infrared focal plane array device testing

Abstract

The present invention discloses a timing editing method and test system for testing infrared focal plane array devices. The method includes: decomposing the timing based on the timing minimum unit as a reference, decomposing to obtain a set of timing minimum units, selecting and defining the output interface corresponding to each timing minimum unit; determining the required timing minimum unit according to the test requirements, sorting and reorganizing the determined timing minimum units according to the analysis results based on the input operation formula through semantic analysis, and obtaining the driving timing; determining the driving timing based on the test requirements, completing the timing editing if it meets the requirements, otherwise re-editing the driving timing. The present invention can simplify the timing editing operation used in infrared focal plane array device testing, making the timing editing universal. When different devices require different driving timings, editing the timing is simpler, and adjustment during the test process can be more easily achieved, making it easy to operate.

Description

Technical Field

[0001] The present invention relates to the field of infrared detection technology, and in particular to a timing editing method and a testing system for testing an infrared focal plane array device. Background Art

[0002] Infrared imaging is the product of the comprehensive development of multidisciplinary and multi-field technologies. Its key technologies include infrared-sensitive materials, semiconductor device processing, integrated circuit design, packaging, testing, and vacuum technology. In recent years, with the rapid development of various technologies, infrared imaging technology has also developed rapidly, gaining widespread application in both civilian and military fields. Infrared focal plane arrays (IRFPAs) are widely used in infrared imaging, precision weapon guidance, reconnaissance and surveillance, and driver vision enhancement, with the pursuit of longer range and higher image clarity. Because the performance of IRFPAs not only affects imaging but is also directly related to the performance evaluation of infrared thermal imagers and the optimization of image processing algorithms, performance testing is necessary to develop IRFPAs with better imaging results. Test results will demonstrate the performance of IRFPAs from an application perspective, and therefore, the methods for testing IRFPAs are particularly important.

[0003] In existing testing methods for infrared focal plane array devices, the infrared focal plane array serves as the device under test. A computer transmits corresponding control commands of the infrared focal plane matrix to a control module. The control module then transmits corresponding drive timing and bias voltage to the infrared focal plane matrix, thereby driving the infrared focal plane array to detect infrared radiation released by a blackbody radiation source. At this time, the infrared focal plane array performs signal processing through photoelectric conversion, and performs data acquisition and processing on the converted electrical signal, thereby completing the test of the infrared focal plane array device.

[0004] In the above process, the drive timing is one of the core parts of the IR FPA testing method and is related to the characteristics of the IR FPA. Different models of IR FPAs have different timing diagrams and corresponding drive timings. The timing diagram mainly consists of the main clock signal, frame reset signal, integration signal, etc. For some IR FPA devices with more comprehensive functions, in addition to the normal basic timing, there is also a timing for on-chip correction. The on-chip correction function is used to improve the uniformity of the analog output voltage. In addition, it also includes serial control timing. Many functions of the IR FPA, such as on-chip correction enable, single-ended and double-ended output selection, image flipping, gain control, etc., are controlled by serial control timing.

[0005] In the prior art, Xu Long et al. proposed a design method for the timing output circuit of an infrared focal plane array in "128×128 Infrared Focal Plane Array Timing Analysis and Temperature Control Circuit Design" (Journal of Infrared and Millimeter Waves, Vol. 22, No. 4, August 2003). They used Altera's Flex10K chip for FPGA programming of the timing portion and employed the simulation software ModelSim SE PLUS for timing design and simulation. This method is a relatively common method, primarily used for programming basic timing signals such as the master clock signal, integration signal, and frame reset signal. It can be applied to specific device drivers, improving operability to a certain extent.

[0006] However, the aforementioned timing editing operation is relatively complex and only applies to specific devices. Different infrared focal plane array devices require different drive timings, making drive timing editing difficult, difficult to edit, and not universally applicable. Furthermore, existing techniques ignore the adjustments required during testing, resulting in limitations during testing and hindering the ease of use of timing editing. Summary of the Invention

[0007] To address the deficiencies of the above-mentioned prior art, the present invention provides a timing editing method and test system for testing infrared focal plane array devices. The timing editing method segments the driving timing based on the minimum timing unit and utilizes a semantic analysis method to convert an in-order formula into a post-order formula. The output timing has high fault tolerance, thereby improving the universality of testing infrared focal plane array devices. The timing editing operation is simple, the anti-interference capability is strong, and the editing cycle is short.

[0008] In a first aspect, the present disclosure provides a timing editing method for testing an infrared focal plane array device:

[0009] A timing editing method for testing an infrared focal plane array device comprises the following steps:

[0010] Decompose the time sequence based on the minimum time sequence unit to obtain a set of minimum time sequence units, and select and define the output interface corresponding to each minimum time sequence unit;

[0011] Determine the required minimum timing unit according to the test requirements, parse the input operation formula through semantic analysis, and sort and reorganize the determined minimum timing units according to the analysis results to obtain the driving timing;

[0012] Determine the drive timing based on the test requirements. If it meets the requirements, complete the timing editing. Otherwise, re-edit the drive timing.

[0013] According to a further technical solution, the minimum timing unit set includes functional test timings corresponding to all test requirements.

[0014] According to a further technical solution, the functional test timing includes main clock timing, frame reset timing, integration timing, on-chip correction enable timing, single-ended output timing, dual-ended output timing, gain control timing, and image flip timing.

[0015] A further technical solution is that the input operation formula is an in-order operation, the in-order operation is parsed into a post-order operation through a semantic analysis method, and the determined minimum timing units are sorted and reorganized according to the post-order operation to obtain the driving timing.

[0016] As a further technical solution, the semantic analysis method is to separate the operation symbols and the minimum time sequence units in the in-order operation and re-sort them in order from left to right.

[0017] A further technical solution is to store different operation formulas and the driving timings corresponding to the operation formulas obtained by encoding.

[0018] A further technical solution is to save corresponding calculation formulas according to different test requirements, and directly obtain the required driving timing through the input calculation formula during the test process.

[0019] In a second aspect, the present disclosure provides a test system for testing infrared focal plane array devices, including a signal generation module, wherein the signal generation module executes the above-mentioned timing editing method, edits the driving timing, and generates a driving timing signal.

[0020] According to a further technical solution, the signal generating module is electrically connected to a main control computer and is connected to an infrared focal plane array device via a cable. After the main control computer is turned on, the corresponding control command of the infrared focal plane matrix is ​​transmitted to the signal generating module. The signal generating module edits the driving timing and transmits the edited timing signal to the infrared focal plane array device to test the infrared focal plane array device.

[0021] According to a further technical solution, the system further includes a display module, which is electrically connected to the signal generating module and is used to display the driving timing signal after editing is completed.

[0022] One or more of the above technical solutions have the following beneficial effects:

[0023] 1. The present invention provides a timing editing method and a test system for testing infrared focal plane array devices. The method divides the driving timing into sections based on the minimum timing unit, which is conducive to the convenience of changing the timing during testing.

[0024] 2. The semantic analysis method proposed in the present disclosure, which converts in-order equations into post-order equations, has high output timing fault tolerance, is easy for users to understand, and is simple to operate, thereby improving the universality of testing infrared focal plane array devices.

[0025] 3. The solution disclosed in the present invention can simplify the timing editing operation used in the testing of infrared focal plane array devices, making the timing editing universal. When different devices require different driving timings, the timing editing is simple and can be more easily adjusted during the testing process, making it easy to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0027] Figure 1 This is an overall flow chart of the timing editing method for testing an infrared focal plane array device according to the first embodiment of the present invention;

[0028] Figure 2 It is a working timing diagram of an existing test device;

[0029] Figure 3 The circuit logic diagram of the existing infrared focal plane array device test system;

[0030] Figure 4 This is a circuit logic diagram of the test system for generating timing signals according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs.

[0032] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0033] Example 1

[0034] This embodiment provides a timing editing method for testing an infrared focal plane array device, such as Figure 1 As shown, the method includes the following steps:

[0035] Decompose the time sequence based on the minimum time sequence unit to obtain a set of minimum time sequence units, and select and define the output interface corresponding to each minimum time sequence unit;

[0036] Determine the required minimum timing unit according to the test requirements, parse the input operation formula through semantic analysis, and sort and reorganize the determined minimum timing units according to the analysis results to obtain the driving timing;

[0037] Determine the drive timing based on the test requirements. If it meets the requirements, complete the timing editing. Otherwise, re-edit the drive timing.

[0038] In this embodiment, first, different output channels are selected as transmission channels for different timing signals, such as Figure 2 As shown, MCLK, RST, and INT represent the transmission channels of three different timing signals (i.e. Figure 2 The middle frame 2 represents a transmission channel of a certain time sequence); then, the time sequence is decomposed into the time sequence minimum unit according to the time sequence diagram, and the time sequence minimum unit set {S1, S2, S3…S N}, select and determine the output interface corresponding to each timing minimum unit (i.e. Figure 2 The middle box 1 represents the output interface corresponding to the minimum unit in each defined timing sequence. This minimum timing unit set contains all functional test timing sequences corresponding to the test requirements, including the main clock timing, frame reset timing, integration timing, on-chip correction enable timing, single-ended output timing, dual-ended output timing, gain control timing, and image flip timing.

[0039] With the minimum unit set {S1, S2, S3…S N}Based on the test requirements, determine the required minimum timing unit {S ’ 1,S ’ 2…S ’ n}, and then sort the minimum time sequence unit according to the input operation formula. Specifically, the input operation formula is an in-order operation. The in-order operation is parsed into a post-order operation through the semantic analysis method. The determined minimum time sequence units are sorted and reorganized according to the post-order operation to obtain the driving timing. The above-mentioned semantic analysis method refers to separating the operator symbols and the minimum time sequence units in the in-order operation and re-sorting them in order from left to right. For example, the in-order operation is the four arithmetic operations in the manual writing habit, such as: 58*(21+3^10 / 78-211) / 13, and the post-order operation is the stack reading method in the computer, such as: 58,21,3,10,^,78, / +211,-*13, / . The rule for converting the in-order expression into a post-order expression is to read the expression numbers from left to right and fill them in order, where the operators are inserted in accordance with the priority.

[0040] Preferably, the driving timing is determined by the test requirements. If it meets the requirements, the timing editing is completed, otherwise the driving timing is re-edited. The test requirements here refer to the test operations that need to be performed. Therefore, the specific operations are different, and the corresponding waveforms are also different. The corresponding waveforms are drawn based on the acquired driving timing, and the waveform diagram to be output (i.e., the timing diagram) is displayed in a preview manner. At this time, it is manually judged whether the waveform or timing meets the test requirements. If it meets the test requirements, the timing editing is completed, otherwise the driving timing is re-edited according to the test requirements. Through the above-mentioned judgment scheme, the accuracy of the driving timing is further improved.

[0041] Finally, the drive timing is transmitted to the IRFPAA device through multiple channels, completing the entire IRFPAA timing editing and testing process. Compared to the method that uses Altera's Flex10K chip for FPGA programming of the timing portion and uses the simulation software ModelSim SE PLUS for timing design and simulation, the timing editing method described in this embodiment offers ease of operation, strong anti-interference capabilities, high universality, and a short editing cycle.

[0042] In fact, considering that different infrared focal plane array devices usually only differ in special functions, during the test process, only a small part of the driving timing needs to be changed to achieve the test of different devices. Therefore, for the convenience of coding, different calculation formulas and their corresponding driving timings are saved, and only the minimum timing unit that needs to be modified needs to be changed to meet the test requirements.

[0043] Therefore, as another implementation method, the corresponding calculation formula is saved according to different test requirements, and the required driving timing is obtained directly through the input calculation formula during the test process, avoiding the steps of determining the required minimum timing unit according to the test requirements and the semantic analysis calculation formula and sorting and reorganizing the determined timing minimum units according to the analysis results, further improving efficiency and simplifying the timing encoding process.

[0044] Example 2

[0045] Existing infrared focal plane array device testing systems such as Figure 3 As shown in the figure, the infrared focal plane array is used as the device under test. The computer transmits the corresponding control commands of the infrared focal plane matrix to the control module. The control module then transmits the corresponding driving timing and bias voltage to the infrared focal plane matrix. The bias voltage provides the low-noise DC bias required for the infrared focal plane array device under test. The driving timing control modules can work synchronously and coordinately. At this time, the infrared focal plane array detects the infrared radiation released by the blackbody radiation source. At this time, the infrared focal plane array performs signal processing through photoelectric conversion, and collects and processes data on the converted electrical signal to complete the test of the infrared focal plane array device.

[0046] Based on the existing test system, this embodiment provides a test system for testing infrared focal plane array devices, which includes a signal generating module, such as Figure 4 As shown, the signal generating module is controlled by a main control computer. Specifically, in the test system proposed in this embodiment, the signal generating module is electrically connected to the main control computer and is connected to the infrared focal plane array device through a cable. After the main control computer is turned on, the corresponding control command of the infrared focal plane matrix is ​​transmitted to the signal generating module. The signal generating module executes the timing editing method described in Example 1 to edit the driving timing, and transmits the edited timing signal to the infrared focal plane array device to perform the test of the infrared focal plane array device.

[0047] As another embodiment, the system may further include a display module, which is electrically connected to the signal generating module and is used to display the driving timing signal after editing, so as to facilitate the tester to preview the edited timing.

[0048] Through the above scheme, the timing editing operation applied in the test of infrared focal plane array devices can be simplified, making the timing editing universal. When different devices require different driving timings, editing the timing is simple, and the above timing editing scheme can more easily realize adjustments during the test process and is easy to operate.

[0049] The steps involved in the above embodiment 2 correspond to those in the method embodiment 1. For specific implementation methods, please refer to the relevant description section of embodiment 1. Those skilled in the art should understand that the modules or steps of the present invention described above can be implemented using a general-purpose computer device. Alternatively, they can be implemented using program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module for implementation. The present invention is not limited to any specific combination of hardware and software.

[0050] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0051] Although the above describes the specific embodiments of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without any creative work are still within the scope of protection of the present invention.

Claims

1. A timing editing method for testing infrared focal plane array devices, characterized in that: The following steps are involved: Decompose the time sequence based on the minimum time sequence unit to obtain a set of minimum time sequence units, and select and define the output interface corresponding to each minimum time sequence unit; Determine the required minimum timing unit according to the test requirements, parse the input operation formula through the semantic analysis method, and sort and reorganize the determined minimum timing units according to the analysis results to obtain the driving timing; the input operation formula is an in-order operation, and the in-order operation is parsed into a post-order operation through the semantic analysis method, and the determined minimum timing units are sorted and reorganized according to the post-order operation to obtain the driving timing; the semantic analysis method is to separate the operation symbols and the minimum timing units in the in-order operation and re-sort them in order from left to right; Determine the drive timing based on the test requirements. If it meets the requirements, complete the timing editing. Otherwise, re-edit the drive timing. According to different test requirements, the corresponding calculation formula is saved, and the required driving timing is directly obtained through the input calculation formula during the test process.

2. A timing editing method for testing an infrared focal plane array device as claimed in claim 1, characterized in that: The minimum timing unit set includes all functional test timings corresponding to the test requirements.

3. A timing editing method for testing an infrared focal plane array device as claimed in claim 2, characterized in that: The functional test timing includes main clock timing, frame reset timing, integration timing, on-chip correction enable timing, single-ended output timing, double-ended output timing, gain control timing, and image flip timing.

4. A timing editing method for testing an infrared focal plane array device as claimed in claim 1, characterized in that: Also includes: Different operation formulas and the driving timing corresponding to the operation formulas obtained by encoding are stored.

5. A timing editing method for testing an infrared focal plane array device as claimed in claim 4, characterized in that: According to different test requirements, the corresponding calculation formula is saved, and the required driving timing is directly obtained through the input calculation formula during the test process.

6. A test system for testing infrared focal plane array devices, characterized in that: The device comprises a signal generating module, which executes the timing editing method for testing an infrared focal plane array device according to any one of claims 1 to 5, edits the driving timing, and generates a driving timing signal.

7. A test system for testing infrared focal plane array devices as claimed in claim 6, characterized in that: The signal generating module is electrically connected to the main control computer and is connected to the infrared focal plane array device via a cable; After the main control computer is turned on, the corresponding control commands of the infrared focal plane matrix are transmitted to the signal generation module. The signal generation module edits the driving timing and transmits the edited timing signal to the infrared focal plane array device to test the infrared focal plane array device.

8. A test system for testing infrared focal plane array devices as claimed in claim 6, characterized in that: The system further comprises a display module, which is electrically connected to the signal generating module and is used for displaying the driving timing signal after editing.

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