Multi-channel data transmission defect detection and repair method and system

Abstract

The present invention discloses a multi-channel data transmission defect detection and repair method and system. The method comprises: a radio frequency receiving and acquisition device and a signal processing device of a distributed digital phased array radar system operate under the same clock source, the radio frequency receiving and acquisition device acquires multi-channel high-speed AD sampling data of array antenna signals, and transmits the multi-channel high-speed AD sampling data to the signal processing device using multiple optical fibers; the signal processing device implements timing alignment and repair of the multi-channel high-speed AD sampling data through a data detection and repair method. The present invention introduces data frame index numbers into the high-speed sampling data between multiple high-speed sampling boards through a synchronous trigger mechanism, and then completes single-channel data detection and repair, multi-channel data timing alignment and recovery at the signal processing end based on the data frame index numbers, effectively ensuring the efficiency of back-end digital beamforming, truly restoring spatial signals, and improving system reception performance.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission of a distributed digital phased array radar system, and in particular to a method and system for detecting and repairing multi-channel data transmission defects. Background Art

[0002] Radar systems widely utilize technologies such as phased array antennas and high-speed AD sampling. The RF receiving front end houses multiple high-speed AD sampling boards and signal processing boards in separate chassis. After completing AD sampling, these boards transmit the high-speed sampled data via multiple optical fibers to the processing boards. The processing boards receive the multi-channel, high-speed sampled data via multiple GTX high-speed serial interfaces for subsequent processing, such as digital down-conversion and digital beamforming.

[0003] Currently, high-speed ADC chips typically have a JESD204B interface, and multi-chip ADC sampling synchronization is generally achieved by adopting the synchronization principles and mechanisms of JESD204B. However, in distributed systems, multi-channel AD sampling data is transmitted between the RF receiving and acquisition equipment and the signal processing equipment through multiple optical fibers. During this period, wiring differences, logic processing, optical fiber transmission links, and other links will cause uncertain delays between channels. At the same time, bit errors on the transmission link may cause frame errors or missing frames in the data. Even if the AD sampling of the RF front end is synchronized, the timing correspondence of the multi-channel received data at the signal processing end cannot be guaranteed after transmission.

[0004] High-speed AD sampling data is streaming data, and each sampling point reflects the phase information of the received signal. If the receiving end cannot align the multi-channel sampling data, that is, the phase information synchronization between multiple channels cannot be guaranteed, then in subsequent digital beamforming and other processing, it will lead to problems such as reduced beamforming efficiency, distortion of the synthesized signal, and phase instability, which will greatly affect the receiving performance of the radar receiving equipment. Summary of the Invention

[0005] The present invention aims to provide a method and system for detecting and repairing multi-channel data transmission defects. Based on the transmission and use characteristics of high-speed AD sampling data in a digital phased array radar system, the present invention provides a method for realizing data detection, repair, and multi-channel data timing alignment at the signal processing end after the multi-channel high-speed AD sampling data is transmitted via optical fiber, thereby eliminating data errors caused by the transmission link and improving the system beamforming efficiency and receiving performance.

[0006] The present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a method for detecting and repairing multi-channel data transmission defects, the method comprising:

[0008] The RF receiving and acquisition equipment and signal processing equipment of the distributed digital phased array radar system operate under the same clock. The RF receiving and acquisition equipment collects multi-channel high-speed AD sampling data of the array antenna signal and transmits the multi-channel high-speed AD sampling data to the signal processing equipment using multiple optical fibers; the signal processing equipment uses data detection and repair methods to achieve timing alignment and repair of the multi-channel high-speed AD sampling data.

[0009] The solution of the present invention introduces data frame index numbers into the high-speed sampling data between multiple high-speed AD sampling boards through a synchronous trigger mechanism, and then completes single-channel data detection and repair, and multi-channel data timing alignment and recovery at the signal processing end according to the data frame index numbers, effectively ensuring the efficiency of the back-end digital beamforming, truly restoring the spatial signal, and improving the system reception performance.

[0010] Furthermore, the radio frequency receiving and collecting device collects multiple high-speed AD sampling data of the array antenna signal and transmits the multiple high-speed AD sampling data to the signal processing device using multiple optical fibers, including:

[0011] The RF receiving and collecting equipment completes multi-channel analog signal collection through multiple high-speed AD sampling boards set up inside it, forming multiple high-speed AD sampling data streams;

[0012] Under the control of the alignment trigger signal, a data frame index number is generated and inserted into the corresponding high-speed AD sampling data stream;

[0013] Transmit multiple high-speed AD sampling data streams to signal processing equipment through multiple optical fibers.

[0014] Furthermore, the alignment trigger signal is a high-speed differential signal, which can be generated independently by the RF receiving and acquisition device or generated externally, and the alignment trigger signal is input into the FPGA chip of multiple high-speed AD sampling boards after equal length processing.

[0015] Furthermore, the data frame index number cnt is a counter, which is generated synchronously in multiple high-speed AD sampling boards;

[0016] The counting clock of the counter is determined according to the sending data clock, transmission speed, and data framing length.

[0017] Furthermore, the sampling data frame format of the high-speed AD sampling data stream is a frame header + a data frame index number + sampling point data in the same channel.

[0018] Furthermore, the signal processing device implements timing alignment and repair of multiple channels of high-speed AD sampling data through a data detection and repair method, including:

[0019] The signal processing device receives high-speed AD sampling data streams through multiple optical fibers and performs multi-channel data extraction in the processing board FPGA set in the signal processing device;

[0020] Based on the extracted multi-channel data, the channel data anomaly or error detection method is used to detect channel data anomalies or errors, and complete the single channel data repair;

[0021] After completing the repair of single channel data, the timing alignment method is used to achieve timing alignment and repair of multi-channel channel data.

[0022] Furthermore, the detection steps of the channel data anomaly or error detection method are as follows:

[0023] Each channel simultaneously detects whether the signal processing device IP core outputs the RXCHARISK signal, and detects the degree of consistency between the RXCHARISK signal and the K character;

[0024] Count the number of times the RXCHARISK signal does not match the K character within a certain period of time;

[0025] If the channel does not output the RXCHARISK signal or the number of non-compliance exceeds the set threshold, the channel is abnormal or the bit error rate is too high. The signal processing device generates a reset mark to reset the transmitting IP core and the transmitting optical module. Otherwise, the channel is normal and the signal processing device does not generate a reset mark.

[0026] Furthermore, the alignment steps of the timing alignment method are:

[0027] The signal processing device parses the sampled data frame data according to the frame header K character of the sampled data frame of each channel;

[0028] Construct multiple fifo buffers in the FPGA of the signal processing device to extract the data frame index number cnt value and the corresponding sampling point data of each channel;

[0029] According to the continuity of the single-channel data frame index number cnt value, single-channel data detection and repair are realized;

[0030] According to the synchronization of the index number cnt value of multiple data frames, the timing alignment and recovery of multiple AD sampling data streams are achieved;

[0031] The detection and repair of single-channel data are realized based on the continuity of the single-channel data frame index number cnt value, including:

[0032] If the data frame index number cnt value of a frame of a single channel has no continuous relationship with the data frame index number cnt values ​​of the frames before and after it, the data frame index number cnt value of the frame will be modified, and the sampling point data will remain unchanged;

[0033] If the data frame index number cnt value of a frame of a single channel is lost, the data frame is added, and the sampling point data of the data frame is added by smooth fitting based on the sampling point data of the previous and next frames of the frame.

[0034] In a second aspect, the present invention further provides a multi-channel data transmission defect detection and repair system, which supports the multi-channel data transmission defect detection and repair method described above; the system includes a radio frequency receiving and acquisition device and a signal processing device, the radio frequency receiving and acquisition device and the signal processing device operating under the same source clock;

[0035] RF receiving and collecting equipment, used to receive array antenna signals and complete multi-channel high-speed AD synchronous sampling; and use multiple optical fibers to transmit the multi-channel high-speed AD sampling data to the signal processing equipment;

[0036] The signal processing device is used to receive multiple channels of high-speed AD sampling data from the radio frequency receiving and collecting device, and realize the timing alignment and repair of the multiple channels of high-speed AD sampling data through data detection and repair methods.

[0037] Furthermore, the radio frequency receiving and collecting equipment includes a plurality of identical high-speed AD sampling boards;

[0038] A high-speed AD sampling board is used to complete multi-channel analog signal acquisition and form a high-speed AD sampling data stream; under the control of an alignment trigger signal, it generates a data frame index number cnt and inserts the data frame index number into the high-speed AD sampling data stream; and transmits the high-speed AD sampling data stream to a signal processing device via multiple optical fibers;

[0039] The signal processing device includes a plurality of processing boards;

[0040] The processing board is used to receive high-speed AD sampling data streams through multiple optical fibers and extract multiple channels of data within the processing board FPGA. Based on the extracted multiple channels of data, a channel data anomaly or error detection method is used to detect channel data anomalies or errors and complete single channel data repair. After completing the single channel data repair, a timing alignment method is used to achieve timing alignment and repair of multiple channel data.

[0041] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0042] The present invention provides a multi-channel data transmission defect detection and repair method and system. The method introduces data frame index numbers into high-speed sampling data between multiple high-speed sampling boards through a synchronous trigger mechanism. Then, at the signal processing end, single-channel data detection and repair, multi-channel data timing alignment and recovery are completed according to the data frame index numbers, effectively ensuring the efficiency of back-end digital beamforming, truly restoring spatial signals, and improving system reception performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0044] Figure 1 This is a principle block diagram of a multi-channel data transmission defect detection and repair method and system of the present invention. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0046] Example 1

[0047] like Figure 1 As shown, the present invention provides a multi-channel data transmission defect detection and repair method, the method comprising:

[0048] The RF receiving and acquisition equipment and signal processing equipment of the distributed digital phased array radar system operate under the same clock. The RF receiving and acquisition equipment collects multiple channels of high-speed AD sampling data and transmits the multiple channels of high-speed AD sampling data to the signal processing equipment using multiple optical fibers. The signal processing equipment uses data detection and repair methods to achieve timing alignment and repair of the multiple channels of high-speed AD sampling data.

[0049] As a further implementation, the radio frequency receiving and collecting device collects multiple channels of high-speed AD sampling data of the array antenna signal and transmits the multiple channels of high-speed AD sampling data to the signal processing device using multiple optical fibers, including:

[0050] The RF receiving and collecting equipment completes multi-channel analog signal collection through multiple high-speed AD sampling boards set up inside it, forming multiple high-speed AD sampling data streams;

[0051] Under the control of the alignment trigger signal, a data frame index number is generated and inserted into the corresponding high-speed AD sampling data stream;

[0052] Transmit multiple high-speed AD sampling data streams to signal processing equipment through multiple optical fibers.

[0053] As a further implementation, the alignment trigger signal is a high-speed differential signal. The alignment trigger signal can be generated independently by the RF receiving and acquisition equipment or generated externally, and the alignment trigger signal is input into the FPGA chip of multiple high-speed AD sampling boards after equal length processing.

[0054] As a further implementation, the data frame index number cnt is a counter, which is generated synchronously in multiple high-speed AD sampling boards;

[0055] The counting clock of the counter is determined according to the sending data clock, transmission speed, and data framing length.

[0056] As a further implementation, the sampling data frame format of the high-speed AD sampling data stream is a frame header+data frame index number+sampling point data in the same channel.

[0057] As a further implementation, the signal processing device implements timing alignment and repair of multiple channels of high-speed AD sampling data through data detection and repair methods, including:

[0058] The signal processing device receives high-speed AD sampling data streams through multiple optical fibers and performs multi-channel data extraction in the processing board FPGA set in the signal processing device;

[0059] Based on the extracted multi-channel data, the channel data anomaly or error detection method is used to detect channel data anomalies or errors, and complete the single channel data repair;

[0060] After completing the repair of single channel data, the timing alignment method is used to achieve timing alignment and repair of multi-channel channel data.

[0061] As a further implementation, the detection steps of the channel data anomaly or error detection method are as follows:

[0062] Each channel simultaneously detects whether the signal processing device IP core outputs the RXCHARISK signal, and detects the degree of consistency between the RXCHARISK signal and the K character;

[0063] Count the number of times the RXCHARISK signal does not match the K character within a certain period of time;

[0064] If the channel does not output the RXCHARISK signal or the number of non-compliance exceeds the set threshold, the channel is abnormal or the bit error rate is too high. The signal processing device generates a reset mark to reset the transmitting IP core and the transmitting optical module. Otherwise, the channel is normal and the signal processing device does not generate a reset mark.

[0065] As a further implementation, the alignment steps of the timing alignment method are:

[0066] The signal processing device parses the sampled data frame data according to the frame header K character of the sampled data frame of each channel;

[0067] Construct multiple fifo buffers in the FPGA of the signal processing device to extract the data frame index number cnt value and the corresponding sampling point data of each channel;

[0068] According to the continuity of the single-channel data frame index number cnt value, single-channel data detection and repair are realized;

[0069] According to the synchronization of the index number cnt value of multiple data frames, the timing alignment and recovery of multiple AD sampling data streams are achieved;

[0070] The detection and repair of single-channel data are realized based on the continuity of the single-channel data frame index number cnt value, including:

[0071] If the data frame index number cnt value of a frame of a single channel has no continuous relationship with the data frame index number cnt values ​​of the previous and next frames, the data frame index number cnt value of the frame is modified, and the sampling point data remains unchanged;

[0072] If the data frame index number cnt value of a frame of a single channel is lost, the data frame is added, and the sampling point data of the data frame is added by smooth fitting based on the sampling point data of the previous and next frames of the frame.

[0073] The specific implementation process of the present invention is as follows:

[0074] 1. The RF receiving and collecting equipment and signal processing equipment start working under the same clock;

[0075] 2. The FPGA of each high-speed sampling board of the RF receiving and acquisition equipment generates a counter cnt on the rising edge of the alignment trigger signal. cnt will be used as the data frame index number. The counting clock of the counter is determined by the sending data clock, transmission rate and data frame length.

[0076] 3. Design a high-speed data transmission rate based on the actual ADC chip sampling rate and effective number of bits. Assume there are 16 ADC sampling channels, each with a sampling rate of 400 Mbps and an effective number of bits of 14 bits. Design a fiber transmission line rate of 8 Gbps. Each sampling channel's sampled data is transmitted via one optical fiber, for a total of 16 optical fibers.

[0077] The transmission design for each channel is as follows: the sampled data is framed for transmission, and the CNT value is inserted into the transmission frame in real time. The transmission sampled data frame format is shown in Table 1. One frame is 160 bits in total, containing 10 sampling point data. After 8B / 10B encoding, it meets the line rate of 8Gps. The transmitted AD sample stream data appears in the form of repeated transmission frames.

[0078] Table 1 Transmission frame format

[0079] Frame composition number of bits Remark 0xBC 8 Frame header, K character cnt 12 Data frame index number data1~data10 14×10 10 sampling points data of the same channel

[0080] 4. After framing, the 16-channel AD sampling data is converted into high-speed electrical signals through the GTX high-speed interface, and then transmitted to the signal processing equipment through optical fiber after electro-optical conversion;

[0081] 5. The processing board of the signal processing equipment receives the optical fiber data, and after optical-electrical conversion, completes 8B / 10B decoding, serial conversion and processing in the FPGA through multiple GTX high-speed interfaces;

[0082] 6. Each channel performs the following processing simultaneously:

[0083] Check whether the IP core of each processing board outputs the RXCHARISK signal and the degree of consistency between the RXCHARISK signal and the K character, and count the number of non-compliance within a certain period of time;

[0084] If there is no RXCHARISK signal or the number of non-matching is too high, the channel is abnormal or the bit error rate is too high. The signal processing device generates a reset mark to reset the transmitting IP core and the transmitting optical module. If the channel is normal, proceed to the next step.

[0085] 7. According to the frame header K character of the sampled data frame, parse the frame data, establish a fifo to extract the index number cnt value of each channel data frame and the corresponding sampling point data;

[0086] 8. Single channel data detection and repair: The cnt value of a single channel should be a continuous count value. If an error frame occurs, that is, the cnt value of the frame changes suddenly and has no continuous relationship with the cnt values ​​of the previous and next frames, the cnt value of the frame should be repaired. For example, the continuous cnt value of channel 1 is (cnt1_1=10, cnt1_2=11, cnt1_3=12, cnt1_4=45, cnt1_5=14), cnt1_4 is repaired to 13, and the sampling point data remains unchanged; if a missing frame occurs, that is, the continuous cnt value of the frame changes suddenly and has no continuous relationship with the cnt values ​​of the previous and next frames, the cnt value of the frame should be repaired. For example, the continuous cnt value of channel 1 is (cnt1_1=10, cnt1_2=11, cnt1_3=12, cnt1_4=45, cnt1_5=14), and the cnt1_4 is repaired to 13, and the sampling point data remains unchanged; If the nt value is lost, a data frame should be added, and the sampling point data of the added data frame should be smoothly fitted according to the sampling point data of the previous and next frames. For example, if the continuous cnt value of channel 1 is (cnt1_1=10, cnt1_2=11, cnt1_3=12, cnt1_4=14, cnt1_5=15), then data frame 13 should be added to frames 12 and 14, and the sampling point data of frame 13 should be smoothly fitted according to the sampling point data of frames 12 and 14 to ensure the timing relationship of the sampled data stream;

[0087] 9. Multi-channel data timing alignment: After completing the detection and repair of a single channel data frame, the data of 16 channels are time-aligned. That is, 16 FIFO buffers are established inside the FPGA, and the data frame index number cnt in the 16-channel data stream is extracted. The timing alignment and recovery of the 16-channel high-speed sampling data are completed according to the cnt value.

[0088] 10. Single-channel data detection and repair, and multi-channel data timing alignment are all sliding window stream data processing, which will not cause blockage or loss of sampled data stream;

[0089] 11. Perform subsequent digital signal processing based on the 16-channel sampled data stream restored after timing alignment.

[0090] The present invention discloses a multi-channel data transmission defect detection and repair method. The method introduces data frame index numbers into high-speed sampling data between multiple high-speed sampling boards through a synchronous trigger mechanism. Then, at the signal processing end, single-channel data detection and repair, multi-channel data timing alignment and recovery are completed according to the data frame index numbers, effectively ensuring the efficiency of back-end digital beamforming, truly restoring spatial signals, and improving system reception performance.

[0091] Example 2

[0092] like Figure 1 As shown, the difference between this embodiment and embodiment 1 is that this embodiment provides a multi-channel data transmission defect detection and repair system, which supports the multi-channel data transmission defect detection and repair method described in embodiment 1;

[0093] The system includes a radio frequency receiving and collecting device and a signal processing device, and the radio frequency receiving and collecting device and the signal processing device operate under the same clock source;

[0094] RF receiving and collecting equipment, used to receive array antenna signals and complete multi-channel high-speed AD synchronous sampling; and use multiple optical fibers to transmit the multi-channel high-speed AD sampling data to the signal processing equipment;

[0095] The radio frequency receiving and collecting equipment includes a plurality of identical high-speed AD sampling boards; the high-speed AD sampling boards are used to complete multi-channel analog signal acquisition and form a high-speed AD sampling data stream; under the control of an alignment trigger signal, a data frame index number cnt is generated and the data frame index number is inserted into the high-speed AD sampling data stream; and the high-speed AD sampling data stream is transmitted to the signal processing equipment via multiple optical fibers;

[0096] The signal processing device is used to receive multiple channels of high-speed AD sampling data from the radio frequency receiving and collecting device, and realize the timing alignment and repair of the multiple channels of high-speed AD sampling data through data detection and repair methods.

[0097] The signal processing device includes multiple processing boards; each processing board receives a high-speed AD sampling data stream from a high-speed AD sampling board; the processing board is used to receive the high-speed AD sampling data stream through multiple optical fibers and extract multiple data within the processing board FPGA; based on the extracted multiple data, a channel data anomaly or error detection method is used to detect channel data anomalies or errors and complete single channel data repair; after completing the single channel data repair, a timing alignment method is used to achieve timing alignment and repair of multiple channel data.

[0098] Among them, the homologous clock is used to provide a homologous clock for RF receiving and acquisition equipment and signal processing equipment. The internal boards of each device use this clock as a reference to generate the required working clock, ensuring AD sampling synchronization and the homologous source of high-speed data transmission and reception, preventing data errors caused by cross-clock domains;

[0099] Among them, the alignment trigger signal: provides a periodic alignment trigger signal for multiple high-speed sampling boards of the RF receiving and acquisition equipment; the alignment trigger signal is a high-speed differential signal that can be independently generated by the RF receiving and acquisition equipment, and the input to each high-speed sampling board should be processed with equal length;

[0100] Among them, the reset flag: the processing board detects abnormal data in a certain channel and initiates a reset of the high-speed sampling board optical module and the high-speed serial transmission IP core in the FPGA.

[0101] In a radar system based on a digital phased array, the radio frequency receiving and collecting equipment is often close to the array antenna, and it is necessary to transmit multi-channel high-speed AD sampling data to the signal processing equipment through multiple optical fibers, and complete digital signal processing and beam synthesis processing in the signal processing equipment. If the transmission link brings uncertain time delays between channels, transmission errors will cause data frame errors and frame omissions, resulting in the signal processing equipment receiving multi-channel AD sampling data unable to align the timing, that is, the phase information synchronization between multiple channels cannot be guaranteed, which will lead to problems such as reduced beam synthesis efficiency, transmission waveform distortion, and phase instability. Based on the characteristics of high-speed AD sampling data transmission, the system of the present invention provides a method for realizing data detection, repair, and multi-channel data timing alignment and recovery at the signal processing end after multi-channel high-speed AD sampling data is transmitted through optical fibers, thereby eliminating the data error problem caused by the transmission link. The use of the present invention can significantly improve the efficiency of beam synthesis, restore spatial signals, and enhance the system receiving performance.

[0102] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0103] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0104] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0105] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0106] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A multi-channel data transmission defect detection and repair method, characterized in that: The method includes: The radio frequency receiving and acquisition equipment and signal processing equipment of the distributed digital phased array radar system operate under the same clock. The radio frequency receiving and acquisition equipment collects multiple high-speed AD sampling data of the array antenna signal and transmits the multiple high-speed AD sampling data to the signal processing equipment using multiple optical fibers. The signal processing equipment realizes the timing alignment and repair of the multiple high-speed AD sampling data through data detection and repair methods. The radio frequency receiving and collecting device collects multi-channel high-speed AD sampling data of the array antenna signal and transmits the multi-channel high-speed AD sampling data to the signal processing device using multiple optical fibers, including: The RF receiving and collecting equipment completes multi-channel analog signal collection through multiple high-speed AD sampling boards set up inside it, forming multiple high-speed AD sampling data streams; Under the control of the alignment trigger signal, a data frame index number is generated, and the data frame index number is inserted into the corresponding high-speed AD sampling data stream; Transmit multiple high-speed AD sampling data streams to signal processing equipment through multiple optical fibers; The sampling data frame format of the high-speed AD sampling data stream is frame header + data frame index number + sampling point data in the same channel; The signal processing device realizes timing alignment and repair of the multi-channel high-speed AD sampling data through a data detection and repair method, including: The signal processing device receives high-speed AD sampling data streams through multiple optical fibers and performs multi-channel data extraction in the processing board FPGA set in the signal processing device; Based on the extracted multi-channel data, the channel data anomaly or error detection method is used to detect channel data anomalies or errors, and complete the single channel data repair; After completing the repair of single channel data, the timing alignment method is used to achieve timing alignment and repair of multi-channel channel data.

2. The multi-channel data transmission defect detection and repair method according to claim 1, characterized in that: The alignment trigger signal is a high-speed differential signal, which is generated independently by the radio frequency receiving and acquisition device or generated externally, and the alignment trigger signal is input into the FPGA chip of multiple high-speed AD sampling boards after equal length processing.

3. The multi-channel data transmission defect detection and repair method according to claim 1, characterized in that: The data frame index number is a counter, which is generated synchronously in multiple high-speed AD sampling boards; The counting clock of the counter is determined according to the data sending clock, the transmission speed, and the data framing length.

4. The multi-channel data transmission defect detection and repair method according to claim 1, characterized in that: The detection steps of the channel data anomaly or error detection method are as follows: Each channel simultaneously detects whether the IP core in the signal processing device outputs the RXCHARISK signal, and detects the degree of conformity between the RXCHARISK signal and the K character; Count the number of times the RXCHARISK signal does not match the K character within a preset time; If the channel does not output the RXCHARISK signal or the number of non-compliance exceeds the set threshold, the channel is abnormal or the bit error rate is high, and the signal processing device generates a reset mark to reset the transmitting IP core and the transmitting optical module; otherwise, the channel is normal and the signal processing device does not generate a reset mark.

5. The multi-channel data transmission defect detection and repair method according to claim 1, characterized in that: The alignment steps of the timing alignment method are: The signal processing device parses the sampled data frame data according to the frame header K character of the sampled data frame of each channel; Construct multiple fifo buffers in the FPGA of the signal processing device to extract the data frame index number value and the corresponding sampling point data of each channel; According to the continuity of the index number value of the single-channel data frame, the detection and repair of the single-channel data are realized; According to the synchronization of the index number values ​​of multiple data frames, the timing alignment and recovery of multiple AD sampling data streams are achieved; The detection and repair of single-channel data are realized based on the continuity of the index number value of the single-channel data frame, including: If the data frame index number value of a frame of a single channel has no continuous relationship with the data frame index number values ​​of the frames before and after it, the data frame index number value of the frame will be modified, and the sampling point data will remain unchanged; If the data frame index number value of a frame of a single channel is lost, the data frame is added, and the sampling point data of the data frame is added by smooth fitting based on the sampling point data of the previous and next frames of the frame.

6. A multi-channel data transmission defect detection and repair system, characterized in that: The system supports a multi-channel data transmission defect detection and repair method as described in any one of claims 1 to 5; the system includes a radio frequency receiving and collecting device and a signal processing device, wherein the radio frequency receiving and collecting device and the signal processing device operate under the same source clock; The radio frequency receiving and collecting equipment is used to receive array antenna signals and complete multi-channel high-speed AD synchronous sampling; And use multiple optical fibers to transmit multiple channels of high-speed AD sampling data to signal processing equipment; The signal processing device is used to receive multiple channels of high-speed AD sampling data from a radio frequency receiving and collecting device, and to achieve timing alignment and repair of the multiple channels of high-speed AD sampling data through a data detection and repair method.

7. The multi-channel data transmission defect detection and repair system according to claim 6, characterized in that: The radio frequency receiving and collecting equipment includes a plurality of identical high-speed AD sampling boards; A high-speed AD sampling board is used to complete multi-channel analog signal acquisition and form a high-speed AD sampling data stream; under the control of an alignment trigger signal, a data frame index number is generated and the data frame index number is inserted into the high-speed AD sampling data stream; and transmitting the high-speed AD sampling data stream to a signal processing device via multiple optical fibers; The signal processing device includes a plurality of processing boards; The processing board is used to receive high-speed AD sampling data streams through multiple optical fibers and perform multi-channel data extraction within the processing board FPGA; based on the extracted multi-channel data, a channel data anomaly or error detection method is used to perform channel data anomaly or error detection and complete single channel data repair; After completing the repair of single channel data, the timing alignment method is used to achieve timing alignment and repair of multi-channel channel data.

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