An online upgrading method for a heterogeneous dual-core dual-cache embedded system

Abstract

The application discloses an online upgrading method of a heterogeneous dual-core dual-cache embedded system, and uses the heterogeneous dual-core dual-cache embedded system, and the online upgrading method comprises the following steps: powering on the heterogeneous dual-core dual-cache embedded system, and the first processor is in a starting state; resetting the second processor by the first processor, and waking up the second processor; acquiring an upgrading file from a server; and upgrading the first processor or the second processor online according to requirements. The application can realize real-time online upgrading program in the whole running cycle of the heterogeneous dual-core dual-cache embedded system. The online upgrading can be realized whether the system is just powered on and started or in the running period of user code.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically to an online upgrade method for a heterogeneous dual-core dual-cache embedded system. Background Technology

[0002] With the continuous development of electronic technology and the information industry, various products based on heterogeneous dual-core processors are now being applied in various scenarios. When user needs change or when a product needs functional iterations during its lifecycle, the product's application needs to be upgraded.

[0003] Currently, the common method for upgrading heterogeneous dual-core embedded systems is as follows: after the embedded system is reset, within a certain time (using a countdown timer), the first processor receives and verifies the application file to be upgraded from the second processor, and then writes it to Flash to replace the original application. This method is simple to operate and easy to implement. However, because the application of the second processor can only be upgraded when the first processor is reset during the operation of the embedded system, and there are strict limitations on the time for receiving online upgrade commands, if the user misses this time, they can only restart the system to operate, resulting in a waste of time and resources. Moreover, it cannot meet the special requirements of users who need to upgrade programs anytime and anywhere throughout the entire system operation cycle. Summary of the Invention

[0004] In view of this, the present invention provides an online upgrade method for a heterogeneous dual-core dual-buffered embedded system, which can solve the existing technical problem that it is impossible to upgrade the heterogeneous dual-core embedded system online throughout its entire operating cycle.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows.

[0006] A heterogeneous dual-core dual-cache embedded system, wherein the heterogeneous dual-core dual-cache embedded system is an embedded device, comprising:

[0007] The system comprises a first processor, a second processor, Flash memory, RAM, and an RS232 serial port. The first processor and the second processor share other hardware of the heterogeneous dual-core dual-cache embedded system. After power-on, the first processor is in a boot state and loads the application program of the second processor stored in Flash memory into RAM for execution. The first processor can reset the second processor. The Flash memory is divided into the following blocks: a first processor BOOT area, a POSFLAG storage area, an intermediate area, an application A area, and an application B area. The first processor BOOT area stores the boot program of the first processor; the POSFLAG storage area stores the POSFLAG value, which is a location identifier indicating the location of the Flash block containing the application program of the second processor; application A and application B are both Flash blocks that can store the application program of the second processor; the intermediate area is a reserved Flash block; and the RS232 serial port is used to connect to a server.

[0008] An online upgrade method for a heterogeneous dual-core dual-cache embedded system, using the heterogeneous dual-core dual-cache embedded system as described above, includes the following steps:

[0009] Step S1: Power on the heterogeneous dual-core dual-cache embedded system, and the first processor is in the startup state;

[0010] Step S2: Obtain the upgrade file from the server; perform an online upgrade of the first processor or the second processor as needed.

[0011] Preferably, step S2: performing an online upgrade of the first processor includes:

[0012] Step S211: Reset the heterogeneous dual-core dual-cache embedded system. If the first processor receives an online upgrade instruction within a first preset time period, proceed to step S212; otherwise, proceed to step S214.

[0013] Step S212: Based on the upgrade program, determine the application program corresponding to the upgrade file in the heterogeneous dual-core dual-cache embedded system; the first processor determines the program header, program tail, and first checksum of the application program in the heterogeneous dual-core dual-cache embedded system; obtain the program header and program tail of the upgrade program and calculate the second checksum; if the program header and program tail are correct, and the first checksum is consistent with the second checksum, proceed to step S213; otherwise, exit this upgrade and the method ends; the first checksum is generated based on the application program in the heterogeneous dual-core dual-cache embedded system, and the second checksum is generated based on the upgrade program;

[0014] Step S213: Determine the storage location, i.e., the startup location, of the application in the heterogeneous dual-core dual-cache embedded system on the second processor: If the current location is application area A, burn the upgrade file to application area B. After successful burning, change the startup location of the application on the second processor to application area B; if the current location is application area B, burn the upgrade file to application area A. After successful burning, change the startup location of the application on the second processor to application area A.

[0015] Step S214: Update the POSFLAG value to the startup location of the application in the second processor, and the first processor obtains the location identifier POSFLAG from Flash;

[0016] Step S215: Based on the location identifier POSFLAG, move the content of the Flash block corresponding to the location identifier POSFLAG to RAM, and run the moved content. At this point, the first processor upgrade is complete.

[0017] Preferably, the second processor is upgraded online, including:

[0018] Step S221: Based on the upgrade program, determine the application program corresponding to the upgrade program in the heterogeneous dual-core dual-cache embedded system; the second processor determines the program header, program tail, and third checksum of the application program in the heterogeneous dual-core dual-cache embedded system; obtain the program header and program tail of the upgrade program and calculate the fourth checksum; if the program header and program tail are correct, and the third checksum is consistent with the fourth checksum, proceed to step S222; otherwise, exit this upgrade and the method ends.

[0019] Step S222: The second processor obtains the location identifier POSFLAG from the Flash memory and determines the storage location, i.e., the startup location, of the second processor's application in the heterogeneous dual-core dual-cache embedded system. If the current location is application area A, the upgrade file is burned to application area B. After successful burning, the startup location of the second processor's application is changed to application area B. If the current location is application area B, the upgrade file is burned to application area A. After successful burning, the startup location of the second processor's application is changed to application area A. At this point, the upgrade of the second processor is complete.

[0020] Preferably, the application to be upgraded is compiled into a .out file using a code debugger, and then the .out file is converted into a .bin file using a corresponding mode conversion module. The .bin file is the upgrade file.

[0021] Preferably, the upgraded application can be run by powering on the heterogeneous dual-core dual-cache embedded system.

[0022] Beneficial effects:

[0023] (1) This invention enables real-time online program upgrades throughout the entire operating cycle of the system. Online upgrades can be performed whether the system is just powered on or during the execution of user code.

[0024] (2) The present invention can ensure the correct loading of the upgrade program file in the event of upgrade program abnormality, communication interruption or unexpected power failure during the upgrade process. If the program file is not successfully burned, the previous version of the program will be automatically loaded when the system is started again. That is, if the upgrade is not successful, the version of the program before the upgrade will be automatically loaded.

[0025] (3) The upgrade method of the present invention is simple and easy to implement.

[0026] (4) The present invention sets up a verification method to verify the upgrade program, making the upgrade safer and more reliable. Attached Figure Description

[0027] Figure 1 A schematic flowchart illustrating the online upgrade method for the first processor and the second processor provided by the present invention;

[0028] Figure 2 This is a schematic diagram of Flash block allocation provided by the present invention. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] like Figures 1-2As shown, this invention proposes a heterogeneous dual-core dual-cache embedded system. This system is an embedded device including a first processor, a second processor, Flash memory, RAM, and an RS232 serial port. The first processor and the second processor share other hardware within the heterogeneous dual-core dual-cache embedded system. After power-on, the first processor is in a boot state and loads the application program of the second processor stored in Flash memory into RAM for execution. The first processor can reset the second processor. The Flash memory is divided into the following blocks: a first processor BOOT area, a POSFLAG storage area, an intermediate area, an application program A area, and an application program B area. The first processor BOOT area stores the boot program of the first processor; the POSFLAG storage area stores the POSFLAG value, which is a location identifier indicating the location of the Flash memory block containing the application program of the second processor; application program A and application program B are both Flash memory blocks that can store the application program of the second processor; the intermediate area is a reserved Flash memory block; and the RS232 serial port is used to connect to a server.

[0031] This invention further provides an online upgrade method for a heterogeneous dual-core dual-cache embedded system, using the heterogeneous dual-core dual-cache embedded system as described above. The online upgrade method includes the following steps:

[0032] Step S1: Power on the heterogeneous dual-core dual-cache embedded system, and the first processor is in the startup state;

[0033] Step S2: Obtain the upgrade file from the server; perform an online upgrade of the first processor or the second processor as needed.

[0034] In this invention, the first processor and the second processor share other hardware of the heterogeneous dual-core dual-cache embedded system. In this embodiment, the server is a remote PC, which is connected to the embedded device via an RS232 serial cable; the BOOT area of ​​the first processor is used to store the boot program of the first processor, which is a BOOT program; the remote PC runs host computer software and stores .bin files corresponding to the upgrade files.

[0035] In step S2, the application to be upgraded is compiled into a .out file using a code debugger, and then the .out file is converted into a .bin file using a corresponding mode conversion module. The .bin file is the upgrade file.

[0036] Step S2: Performing an online upgrade on the first processor, including:

[0037] Step S211: Reset the heterogeneous dual-core dual-cache embedded system. If the first processor receives an online upgrade instruction within a first preset time period, proceed to step S212; otherwise, proceed to step S214.

[0038] Step S212: Based on the upgrade program, determine the application program corresponding to the upgrade file in the heterogeneous dual-core dual-cache embedded system; the first processor determines the program header, program tail, and first checksum of the application program in the heterogeneous dual-core dual-cache embedded system; and calculates the program header, program tail, and second checksum of the upgrade program; if the first checksum matches the second checksum, proceed to step S213; otherwise, exit the upgrade and the method ends; the first checksum is generated based on the application program in the heterogeneous dual-core dual-cache embedded system, and the second checksum is generated based on the upgrade program;

[0039] Step S213: Determine the storage location, i.e., the startup location, of the application in the heterogeneous dual-core dual-cache embedded system on the second processor: If the current location is application area A, burn the upgrade file to application area B. After successful burning, change the startup location of the application on the second processor to application area B; if the current location is application area B, burn the upgrade file to application area A. After successful burning, change the startup location of the application on the second processor to application area A.

[0040] Step S214: Update the POSFLAG value to the startup location of the application in the second processor, and the first processor obtains the location identifier POSFLAG from Flash;

[0041] Step S215: Based on the location identifier POSFLAG, move the content of the Flash block corresponding to the location identifier POSFLAG to RAM, and run the moved content. At this point, the first processor upgrade is complete.

[0042] Step S2: Performing an online upgrade of the second processor, including:

[0043] Step S221: Based on the upgrade program, determine the application program corresponding to the upgrade program in the heterogeneous dual-core dual-cache embedded system; the second processor determines the program header, program tail, and third checksum of the application program in the heterogeneous dual-core dual-cache embedded system; and calculates the program header, program tail, and fourth checksum of the upgrade program; if the third checksum is consistent with the fourth checksum, proceed to step S222; otherwise, exit this upgrade and the method ends.

[0044] Step S222: The second processor obtains the location identifier POSFLAG from the Flash memory and determines the storage location, i.e., the startup location, of the second processor's application in the heterogeneous dual-core dual-cache embedded system. If the current location is application area A, the upgrade file is burned to application area B. After successful burning, the startup location of the second processor's application is changed to application area B. If the current location is application area B, the upgrade file is burned to application area A. After successful burning, the startup location of the second processor's application is changed to application area A. At this point, the upgrade of the second processor is complete.

[0045] Furthermore, by powering back on the heterogeneous dual-core dual-cache embedded system, the upgraded application can be run.

[0046] Furthermore, the programming method includes:

[0047] Step S31: Obtain the location of the Flash block to be burned, and perform Flash erasure according to the size of the application to be upgraded. After each Flash block is successfully erased, the erasure progress information is sent to the host computer software via RS232 serial port for real-time display of the work progress.

[0048] Step S32: Locate a usable page in the Flash block, page by page, and write the current data packet of the application to be upgraded to the usable page; determine whether the last data packet of the application to be upgraded has been written. If not, obtain the next data packet to be written and proceed to step S32; if yes, end the burning process.

[0049] Furthermore, during the burning process, progress information is sent to the host computer software via RS232 serial port each time a page is determined to be corrupted or each page is successfully written.

[0050] The specific embodiments described above only illustrate the design principles of the present invention. The shapes and names of the components in this description may differ and are not limited. Therefore, those skilled in the art can modify or make equivalent substitutions to the technical solutions described in the foregoing embodiments; and these modifications and substitutions do not depart from the inventive spirit and technical solutions of the present invention, and should all fall within the protection scope of the present invention.

Claims

1. A heterogeneous dual-core dual-cache embedded system, characterized in that, include: The system comprises a first processor, a second processor, Flash memory, RAM, and an RS232 serial port. The first and second processors share the Flash memory, RAM, and RS232 serial port of the heterogeneous dual-core dual-cache embedded system. After power-on, the first processor is in the startup state and loads the application program of the second processor stored in Flash memory into RAM for execution. The first processor can reset the second processor. The Flash memory is divided into the following blocks: the first processor BOOT area, the POSFLAG storage area, the intermediate area, the application program A area, and the application program B area. The first processor BOOT area is used to store the startup program of the first processor. The POSFLAG storage area is used to store POSFLAG values. POSFLAG is a location identifier that indicates the location of the FLASH block where the application of the second processor is located. Application A area and Application B area are both FLASH blocks, which can store the application of the second processor. The middle area is a reserved Flash block. The RS232 serial port is used to connect to the server.

2. An online upgrade method for a heterogeneous dual-core dual-cache embedded system, using the heterogeneous dual-core dual-cache embedded system as described in claim 1, characterized in that, The online upgrade method includes the following steps: Step S1: Power on the heterogeneous dual-core dual-cache embedded system; the first processor is in the startup state. Step S2: Obtain the upgrade file from the server; The first processor or the second processor can be upgraded online as needed; in: Perform online upgrades on the first processor, including: Step S211: Reset the heterogeneous dual-core dual-cache embedded system. If the first processor receives an online upgrade instruction within the first preset time period, proceed to step S212; otherwise, proceed to step S214. Step S212: Based on the upgrade program, determine the application program corresponding to the upgrade file in the heterogeneous dual-core dual-cache embedded system; the first processor determines the program header, program tail, and first checksum of the application program in the heterogeneous dual-core dual-cache embedded system; obtain the program header and program tail of the upgrade program and calculate the second checksum; if the program header and program tail are correct, and the first checksum is consistent with the second checksum, proceed to step S213; otherwise, exit this upgrade and the method ends; the first checksum is generated based on the application program in the heterogeneous dual-core dual-cache embedded system, and the second checksum is generated based on the upgrade program; Step S213: Determine the storage location of the application in the heterogeneous dual-core dual-cache embedded system on the second processor, i.e., the startup location: If the current location is application area A, burn the upgrade file to application area B. After successful burning, change the startup location of the application on the second processor to application area B; if the current location is application area B, burn the upgrade file to application area A. After successful burning, change the startup location of the application on the second processor to application area A. Step S214: Update the POSFLAG value to the startup location of the application in the second processor, and the first processor obtains the location identifier POSFLAG from Flash; Step S215: Based on the location identifier POSFLAG, move the contents of the Flash block corresponding to the location identifier POSFLAG to RAM and run the moved contents; at this point, the first processor upgrade is complete; Perform online upgrades to the second processor, including: Step S221: Based on the upgrade program, determine the application program corresponding to the upgrade program in the heterogeneous dual-core dual-cache embedded system; the second processor determines the program header, program tail, and third checksum of the application program in the heterogeneous dual-core dual-cache embedded system; obtain the program header and program tail of the upgrade program and calculate the fourth checksum; if the program header and program tail are correct, and the third checksum is consistent with the fourth checksum, proceed to step S222; otherwise, exit this upgrade and the method ends. Step S222: The second processor obtains the location identifier POSFLAG from the Flash memory and determines the storage location of the application in the heterogeneous dual-core dual-cache embedded system, i.e., the startup location: If the current location is application area A, the upgrade file is burned to application area B. After successful burning, the startup location of the application in the second processor is changed to application area B; if the current location is application area B, the upgrade file is burned to application area A. After successful burning, the startup location of the application in the second processor is changed to application area A. At this point, the upgrade of the second processor is complete.

3. The method as described in claim 2, characterized in that, The application to be upgraded is compiled using a code debugger to generate a .out file, and then the .out file is converted into a .bin file using the corresponding mode conversion module. The .bin file is the upgrade file.

4. The method according to any one of claims 2-3, characterized in that, By powering back on the heterogeneous dual-core dual-buffered embedded system, the upgraded application can be run.

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