Balancing current consumption between different voltage sources

Abstract

This application relates to balancing current consumption between different voltage sources. A device includes a voltage regulator coupled to a first voltage source that supplies power to a core memory circuitry system. A first transistor is coupled between the output of the voltage regulator and an input / output (I / O) circuitry system. A second transistor is coupled between a second voltage source and the I / O circuitry system, the second voltage source supplying power to an I / O buffer set. Control logic coupled to the gates of the first and second transistors performs operations including: activating the second transistor to allow current to flow from the second voltage source to the I / O circuitry system; activating the first transistor in response to detecting that current draw from the I / O circuitry system meets a first threshold criterion; and deactivating the second transistor during time intervals during which the I / O circuitry system is powered by the first and second voltage sources.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to balancing current consumption between different voltage sources. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this disclosure provides an apparatus comprising: a voltage regulator coupled to a first voltage source supplying power to a core memory circuitry of a memory device; a first transistor coupled between an output of the voltage regulator and an input / output (I / O) circuitry of the memory device; a second transistor coupled between a second voltage source and the I / O circuitry, the second voltage source supplying power to an I / O buffer set; and control logic coupled to the gates of the first transistor and the second transistor, the control logic performing operations including: causing the second transistor to activate to allow current to flow from the second voltage source to the I / O circuitry; activating the first transistor in response to detecting that current draw from the I / O circuitry satisfies a first threshold criterion; and deactivating the second transistor during a time interval during which the I / O circuitry is powered by the first voltage source and the second voltage source.

[0004] In another aspect, this disclosure provides a system comprising: a first voltage source supplying power to a core memory circuitry of a memory device; a voltage regulator coupled to the first voltage source; a first transistor coupled between the output and input / output (I / O) circuitry of the voltage regulator; a second voltage source supplying power to an I / O buffer set of the memory device, the first voltage source providing a voltage higher than that of the second voltage source; a second transistor coupled between the second voltage source and the I / O circuitry; and control logic coupled to the gates of the first transistor and the second transistor, the control logic performing operations including: causing the second transistor to be activated to allow current to flow from the second voltage source to the I / O circuitry; causing the first transistor to be activated in response to detecting that current draw from the I / O circuitry satisfies a first threshold criterion; and causing the second transistor to be deactivated during a time interval during which the I / O circuitry is powered by the first voltage source and the second voltage source.

[0005] In another aspect, this disclosure provides a method comprising: causing a first voltage source to power a core memory circuitry of a memory device; causing a second voltage source to power an input / output (I / O) buffer set of the memory device; causing control logic of the memory device to immediately activate a first transistor after startup of the memory device, the first transistor being coupled between the second voltage source and the I / O circuitry of the memory device; causing the control logic to activate a second transistor coupled between a voltage regulator of the first voltage source and the I / O circuitry in response to detecting that current draw from the I / O circuitry satisfies a first threshold criterion; and causing the control logic to deactivate the first transistor during a time interval during which the I / O circuitry is powered by the first voltage source and the second voltage source. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 It is an instance computing system including a memory subsystem according to some embodiments.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 3A This is a block diagram of a memory device according to an embodiment, wherein the input / output (I / O) circuitry is powered by the smaller of two voltage sources.

[0010] Figure 3B This is a block diagram of a memory device according to another embodiment, wherein the I / O circuit system is powered by the larger of two voltage sources.

[0011] Figure 4 This is a schematic block diagram of a memory device according to an embodiment, wherein the I / O circuit system is selectively powered by two voltage sources.

[0012] Figure 5 This describes the provision provided according to the embodiments. Figure 4 A graph showing the control logic signals of the transistors coupled to each of the two voltage sources.

[0013] Figure 6 According to the embodiments Figure 4 A schematic block diagram of a voltage regulator for a memory device.

[0014] Figure 7A This is a schematic block diagram of a memory device according to another embodiment, wherein the I / O circuitry is selectively powered by two voltage sources.

[0015] Figure 7B This is a graph illustrating a curve associated with a comparator according to an embodiment, the comparator providing feedback to control logic to control the amount of current drawn by the I / O circuit system.

[0016] Figure 8A This is a flowchart of an example method according to various embodiments of selectively switching one or both of two voltage sources to power an I / O circuit system.

[0017] Figure 8B This describes the memory device and its embodiments as discussed herein. Figure 8A The method is associated with the control signal, supply voltage, and graphs of supply current and load current.

[0018] Figure 9 This is a flowchart of an example method for selectively switching power supply from one to both of two voltage sources to an I / O circuit system, according to an embodiment.

[0019] Figure 10 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0020] This disclosure addresses the balancing of current consumption between different voltage sources. The memory subsystem may be a memory device, a memory module, or a hybrid of both. The following is combined with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0021] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. See below for reference. Figure 1Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more memory dies. Each die may contain one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0022] In some memory devices, a first voltage source powers the memory cells and other core memory circuitry (e.g., page buffers), while an auxiliary (or second) voltage source powers the input / output (I / O) buffers. The first voltage source (e.g., a common-collector voltage source or Vcc) typically has a voltage greater than that of the second voltage source (also referred to herein as Vccq). The second voltage source (Vccq) is adapted to power the I / O buffers and, in some cases, also the I / O circuitry coupled between the core memory circuitry and the I / O buffers. Therefore, the I / O circuitry can be viewed as a large data serializer moving data back and forth between the NAND core circuitry and the I / O buffers.

[0023] In some memory devices, if the current budget limit (e.g., Iccq) from the second voltage source is sufficient to drive the I / O circuitry plus an external I / O buffer, then all power can be provided by the second voltage source. However, if the current budget limit from the second voltage source is insufficient to drive the I / O circuitry (as this occurs in larger memory devices with increasing I / O circuitry size), then all power can be provided by the first voltage source (Vcc). Driving the I / O circuitry system solely through the first voltage source (rather than the second voltage source) can introduce some power losses, requiring the use of a dedicated voltage regulator, which in turn employs a large decapacitive filter. Furthermore, using a voltage regulator can introduce design problems related to turn-on time and output voltage stability, which will be discussed in more detail.

[0024] This disclosure addresses the above and other deficiencies by providing a memory device that allows selective use of both a first voltage source and a second voltage source, including a transition period (e.g., a hybrid mode) when switching from the second voltage source to the first voltage source, allowing the first voltage source to gradually ramp down during the time interval. Once the first voltage source provides sufficient current to power the I / O circuitry, the control logic eliminates the need to draw power from the second voltage source. In response to detecting a decrease in current to the I / O circuitry large enough to make the second voltage source available again as the sole power source, the control logic switches back to the second voltage source and shuts down the path originating from the first voltage source.

[0025] More specifically, in various embodiments, a voltage regulator is coupled to a first voltage source (Vcc), and a first transistor (e.g., a first switch) is coupled between the output of the voltage regulator and the I / O circuitry of the memory device. A second transistor (e.g., a second switch) may be coupled between a second voltage source (Vccq) and the I / O circuitry. Additionally, control logic may be coupled to the gates of the first and second transistors. The control logic may perform the following operations: causing the second transistor to be activated to allow current to flow from the second voltage source to the I / O circuitry, for example, immediately after the memory device is powered on. In response to detecting that current draw from the I / O circuitry meets a first threshold criterion, the control logic may cause the first transistor to be activated. The control logic may further cause the second transistor to be deactivated (e.g., using a linear ramp signal) during time intervals when the I / O circuitry is powered by the first and second voltage sources, for example, in a mixed mode.

[0026] In these embodiments, once the voltage supplied to the I / O circuitry system via the first voltage source exceeds the voltage supplied by the second voltage source, the control logic immediately causes the second transistor to be completely deactivated, for example, entering amplifier mode. The voltage regulator may be an operational amplifier to allow a feedback mechanism to control offset cancellation. After detecting that the decrease in current draw from the I / O circuitry system meets a second threshold criterion, the control logic may immediately cause the first transistor to be completely deactivated and the second transistor to be fully activated to return to a short-circuit mode in which the first voltage source does not assist in providing power to the I / O circuitry system.

[0027] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, avoiding the disadvantages listed above of always remaining in the mode of powering the I / O circuit system via a first voltage source (Vcc), and instead being able to smoothly transition to such a mode when current draw from the I / O circuit system needs to be met. Thus, the selective use of both voltage sources allows for a switchback to powering via a second voltage source (Vcc) when the first power supply is not required, which is more energy efficient. Other advantages will be discussed, and several other advantages will be apparent to those skilled in the art who benefit from this disclosure.

[0028] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0031] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0032] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0033] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0037] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0038] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0040] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0041] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical block addresses (e.g., logical block addresses (LBAs), namespaces) and physical block addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system 120 into command instructions to access the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device that includes a raw memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory device 130 may represent a single die having some control logic embodied thereon (e.g., local media controller 135). In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0044] In one embodiment, the memory device 130 includes control logic 113, which can be used to receive feedback from the current supplied to the I / O circuitry system and control the gates of the first and second transistors to selectively enable the use of two different voltage sources. This selective control by the control logic 113 can, for example, depend on the current budget limit of each voltage source and the amount of current drawn from the I / O circuitry system, and the I / O circuitry system can be powered by either or both of the first and second voltage sources.

[0045] Figure 2 The first device, in the form of a memory device 130, and the memory subsystem controller 115, in the form of a memory subsystem, are, according to the embodiment, (e.g., Figure 1 A simplified block diagram of communication between a second device and a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0046] Memory device 130 includes an array 204 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the array 204 (not individually described) can be programmed to one of at least two target data states.

[0047] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 204. Memory device 130 also includes input / output (I / O) control circuitry 212, which manages inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 214 communicates with I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch address signals before decoding. Command register 224 communicates with I / O control circuitry 212 and control logic 216 to latch incoming commands.

[0048] A controller (e.g., a local media controller 135 within memory device 130) responds to commands to control access to memory cell array 204 and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 204. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 in response to address control of row decoding circuitry 208 and column decoding circuitry 210. The local media controller 135 may also be coupled to I / O control circuitry 212, other I / O circuitry, and I / O buffers that buffer data being stored in or read from memory cell array 204.

[0049] The local media controller 135 also communicates with cache register 218. Cache register 218 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 204 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 218 to data register 22 for transmission to the memory cell array 204; then, new data can be latched from I / O control circuitry 212 into cache register 218. During read operations, data can be transferred from cache register 218 to I / O control circuitry 212 for output to the memory subsystem controller 115; then, new data can be transferred from data register 220 to cache register 218. Cache register 218 and / or data register 220 may form a page buffer (e.g., a portion thereof) of the memory device 130. The page buffer may additionally include sensing devices ( Figure 2 (Not shown in the diagram), it is used to sense the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cell array 204. The status register 222 can communicate with the I / O control circuitry system 212 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0050] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 232. For example, control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 232. Memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 234, and outputs data to memory subsystem controller 115 via I / O bus 234.

[0051] For example, commands can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to command register 224. Addresses can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then written to address register 214. Data can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 218. The data can then be written to data register 220 for programming memory cell array 204.

[0052] In this embodiment, the cache register 218 may be omitted, and data may be written directly to the data register 220. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0053] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 2 The memory device 130. It should be understood that, reference Figure 2 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component.

[0054] In addition, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0055] Figure 3A This is a block diagram of a memory device 330A according to an embodiment, wherein the input / output (I / O) circuit system 312 is powered by the smaller of two voltage sources. Figure 3BThis is a block diagram of a memory device 330B according to another embodiment, wherein an I / O circuitry system 312 is powered by the larger of two voltage sources. Each of the memory devices 330A and 330B may include a core memory circuitry system 304, an I / O buffer set 316, and an I / O circuitry system 312 coupled between the core memory circuitry system 304 and the I / O buffers 316. The core memory circuitry system 304 may include a memory cell array 204, a page buffer, and a cache, as well as a reference... Figure 2 Other circuit systems discussed. I / O circuit system 312 may include I / O control circuit system 212 and other I / O circuit systems, which can be understood as large data serializers used to move data back and forth between core memory circuit system 304 and I / O buffer 316. For example, I / O buffer 316 buffers data while it is waiting to be written to or read from core memory circuit system 304 and sent to host system 120.

[0056] In various embodiments, the first voltage source is a common-collector (Vcc) source that provides primary power to the core memory circuitry 304, which is the largest power consumer. In some embodiments, a second voltage source (or Vccq) is also provided to power the I / O buffer 316 and optionally also the I / O circuitry. Thus, the first voltage source can typically have a higher voltage than the second voltage source, and therefore can supply more current or power in the case of more power-consuming I / O circuitry.

[0057] exist Figure 3A In the embodiments described, for ease of explanation, the current required by the core memory circuit system 304 is a first current (I1), the current required by the I / O circuit system 312 may be a second current (I2), and the current required by the I / O buffer 316 may be a third current (I3). As described by... Figure 3A As indicated by the rightmost diagram, the current budget limit for Vccq is the Iccq limit, which can handle currents I2 and I3. There is a sufficient current budget limit when currents I2 and I3 approach the Iccq limit in combination, and therefore, this embodiment may not require the assistance of a larger voltage from Vcc.

[0058] In another embodiment, Figure 3BThis explains how the combined currents I2 and I3 will exceed the current budget limit Iccq. Therefore, powering the I / O circuit system 312 can be switched to being powered by a first voltage source (Vcc). In this embodiment, the memory device 330B further includes a voltage regulator 317 coupled between Vcc and the I / O circuit system 312. The voltage regulator 317 can regulate the voltage from Vcc to supply the second current I2, while Vcc also supplies the first current, the Icc current limit of which can satisfy the first current, as described above. Figure 3B As illustrated in the rightmost diagram. However, using voltage regulator 317 may introduce certain power losses and voltage handling requirements. Additionally, using voltage regulator 317 can introduce design issues related to turn-on time and output voltage stability. For example, voltage regulator 317 may not be able to supply power during standby and idle modes. Furthermore, voltage regulator 317 will need to respond quickly to additional voltage supply, but it is itself a type of electrical component that does not turn on quickly. Finally, voltage regulator 317 will need to avoid voltage loops and transients when the regulator is turned on; for example, this would require managing a large decapacitated filter. Therefore, employing voltage regulator 317 at startup and as a permanent solution for managing the power supply for the I / O circuit system 312 has disadvantages.

[0059] Figure 4 This is a schematic block diagram of a memory device 430 according to an embodiment, which selectively powers an I / O circuit system 312 via two voltage sources. These two voltage sources (or power supplies) may include a first voltage source (Vcc) and a second voltage source (Vccq) previously discussed herein. The memory device 320 may include a voltage regulator 417, which may be an operational amplifier, for supplying the first voltage source (Vcc) to the I / O circuit system 312. In one embodiment, the voltage regulator 417 is... Figure 3B Voltage regulator 317. Voltage regulator 417 can receive a second voltage source (Vccq) to perform offset cancellation, such as referencing... Figure 6 More detailed description.

[0060] In various embodiments, memory device 430 includes a first transistor 421 (or a first switch) coupled between the output of voltage regulator 417 and I / O circuitry 312 of memory device 430. Memory device 430 may additionally include a second transistor 425 (or a second switch) coupled between a second voltage source (Vccq) and I / O circuitry 312, the second voltage source supplying power to I / O buffer set 316. Because the first transistor 421 and the second transistor 425 are each coupled to I / O circuitry 312, the source terminals of each of the first transistor 421 and the second transistor 425 are also coupled together at node Vcclo leading to I / O circuitry 312. The drain of the first transistor 421 may be coupled to voltage regulator 417, and the drain of the second transistor 425 may be coupled to the second voltage source (Vccq). In some embodiments, the first transistor 421 and the second transistor 425 are each n-type complementary metal-oxide-semiconductor (NMOS) transistors. In other embodiments, the first transistor 421 and the second transistor 425 are each p-type complementary metal-oxide-semiconductor (PMOS) transistors.

[0061] Figure 5 This describes the provision provided according to the embodiments. Figure 4 A graph of the control logic signals of the first transistor 421 and the second transistor 425 coupled to each of the two voltage sources. In various embodiments, the memory device 430 further includes control logic 113 coupled to the gate (“EN”) of the first transistor 421 and the gate (“JOIN”) of the second transistor 425 to facilitate selective transfer of power supplied by a power supply between the first and second voltage sources. The control logic 113 may be adapted to perform operations including causing the second transistor 425 to be activated to allow current to flow from the second voltage source (Vccq) to the I / O circuit system 412. Only the second transistor 425 is activated in Figure 5 The description indicates the first "short circuit" period, which indicates the low-resistance path set between Vccq and Vcclo.

[0062] For further reference Figure 4-5 The operation performed by control logic 113 may additionally include activating a first transistor in response to detecting that current draw from I / O circuitry 312 meets a first threshold criterion. The first threshold criterion may include meeting a predetermined current value that exceeds a current budget limit for a second current drawn from the second voltage source (Vccq). Figure 5The “mixed” time period described herein enables the memory device 430 to supply current from both Vcc and Vccq to the I / O circuitry 312. This operation may further include causing the second transistor 425 to be deactivated during the time interval (e.g., the mixed period) in which the I / O circuitry 312 is powered by the first voltage source (Vcc) and the second voltage source (Vccq). In one embodiment, control logic 113 may slowly deactivate the second transistor 425. For example, control logic 113 may cause the second transistor 425 to slope linearly from fully activated to fully deactivated. By slowly deactivating (or turning off) the second transistor 425, the voltage regulator 417 can effectively ramp up to provide a higher voltage, and thus allows the voltage regulator 417 to remain stable when initializing its output. In this way, the voltage regulator 417 avoids the need for rapid turn-on, avoids loop effects and transients, and avoids the need for a large decapacitoring circuitry. For example, a small capacitor on the output of the voltage regulator 417 may be sufficient to absorb any voltage surges.

[0063] Continue to refer to Figure 4-5 The operation may further include detecting when the voltage at Vcclo becomes higher than the output of voltage regulator 417 (e.g., a negative voltage), after which the operation may include causing the second transistor 425 to be completely deactivated. The deactivation of the second transistor 425 may mark the end of a mixing period or operation in a mixing mode. The memory device 430 may thus enter an “amplifier” period or amplifier mode of operation, where only the first voltage source (Vcc) supplies power to the I / O circuitry 312. The operation may further include detecting a decrease in current draw of the I / O circuitry 312 that satisfies a second threshold criterion. This second criterion may include a drop below a predetermined current, where the voltage demand on both voltage sources can revert to a short-circuit period or operating mode. Therefore, the operation further includes causing the first transistor 421 to be completely deactivated and causing the second transistor 425 to be completely activated. In this way, control logic 113 can selectively and smoothly direct power supply to the I / O circuitry 312 between the first and second voltage sources (e.g., which are two different power domains).

[0064] Figure 6 According to the embodiments Figure 4A schematic block diagram of a voltage regulator 417 for a memory device 430. In some embodiments, the voltage regulator 417 may include an operational amplifier 617, a first voltage divider 630 coupled between a second voltage source (Vccq) and the positive input terminal of the operational amplifier 617, and a second voltage divider 640 coupled between the output of the operational amplifier 617 and the negative input terminal of the operational amplifier 617. In one embodiment, the top resistor (R1) of the first voltage divider 630 may be adjusted (and variable) by a trim value to eliminate offset of the operational amplifier within at least one percent of the voltage of the second voltage source. In one embodiment, the trim value is set such that the input voltage at the positive input terminal of the operational amplifier 617 is within a few millivolts of the voltage supplied by the second voltage source (Vccq). The voltage regulator 417 may additionally include an output stage 650 comprising a library of NMOS (or PMOS) transistors.

[0065] Figure 7A This is a schematic block diagram of a memory device 730 according to another embodiment, in which an I / O circuitry system is selectively powered by two voltage sources. The memory device 730 may include control logic 713, which may be a portion of or a supplement to the previously mentioned control logic 113. As previously stated, control logic 713 may be coupled to the gates of a first transistor 421 and a second transistor 425. The label Ron_1 refers to the low internal resistance of the first transistor 421, and the label Ron_2 refers to the low internal resistance of the second transistor 425. Additionally, the "ampout" signal can be understood as the output of the voltage regulator 417.

[0066] In various embodiments, the memory device 730 further includes a first comparator 721 having inputs from the drain and source of the first transistor 421 and providing an output signal (Hi_curr) indicating whether a second threshold criterion is met to control logic 713 by means of digital feedback. This second criterion may include I(Vcclo) dropping below a predetermined current, where the voltage demand on the two voltage sources can revert to a short-circuit period or operating mode. This allows the first comparator 721 across the first transistor 421 to function as a current-sensing operation across Ron_1 at the voltage threshold of the first comparator 721. In one embodiment, the source input of the first comparator 721 is also connected to a feedback line leading to the negative input line of the voltage regulator 417.

[0067] In various embodiments, the memory device 730 further includes a second comparator 725 having inputs from the drain and source of the second transistor 425 and providing an output signal (Det_drop) indicating whether a first threshold criterion is met to control logic 713 by means of digital feedback. The first threshold criterion may include meeting a predetermined current value that exceeds a current budget limit (Iccq) of a second current drawn from the second voltage source (Vccq). This allows the second comparator 725 across the second transistor 425 to be used for current sensing operation across Ron_2 at a voltage threshold of the second comparator 725.

[0068] Figure 7B This is a graph illustrating a curve associated with a comparator according to an embodiment, the comparator providing feedback to control logic to control the amount of current drawn by the I / O circuit system 312. From top to bottom, the graph includes the current I drawn by the I / O circuit system 312, the output signal (Hi_Curr) from the first comparator 721, the voltage level at Vcclo leading to the I / O circuit system 312 that overlaps with the threshold voltage (Vth) of the second comparator 725, and the output signal (Det_drop) from the second comparator 725. Figure 7B The voltage (V1) on the Vcclo curve can be assigned to allow selection of the desired or preferred value of the I(Vcclo) current, where the current will begin, for example, according to the current budget limit specification, also supplied by Vcc.

[0069] In these embodiments, further reference is made to Figure 7A In short-circuit mode, when the EN signal is zero, the voltage regulator 417 is off, the OEN signal is zero, and the JOIN signal is one. Conversely, when the EN signal is one, the voltage regulator 417 is on, and the voltage is adjusted according to the value of the I(Vcclo) current drawn by the I / O circuit system 312 and... Figure 8A The switching sequence described herein is used to enable the first transistor 421 and the second transistor 425.

[0070] Figure 8A This is a flowchart of an example method 800, according to various embodiments, of selectively switching power to an I / O circuit system from one or both of two voltage sources. Method 800 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 800 is performed by… Figure 1 The control logic 113 and / or 713 and / or logic execution of the local media controller 135. Figure 8BThis describes the memory device and its embodiments as discussed herein. Figure 8A The method is associated with the control signal, supply voltage, and graphs of supply current and load current.

[0071] Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. Furthermore, in some embodiments, one or more operations may be omitted. Therefore, not all operations described are required in every embodiment, and other processing flows are possible.

[0072] At operation 810, the memory device operates in short-circuit mode. More specifically, the processing logic activates the second transistor 425 (where JOIN=1), keeps the first transistor 427 deactivated (where OEN=0), and sets the voltage threshold (Vt) of the second comparator 725 to zero (“0”). At zero, V1 exists at Vt of the second comparator (see...). Figure 7B It is a programmed positive voltage used to switch to power the I / O circuit system 312 via a first voltage source (Vcc).

[0073] At operation 820, the voltage drop is determined. More specifically, the processing logic determines whether the output signal (Det_drop) of the second comparator 725 has been triggered, for example, indicating that the first threshold criterion has been met. If the output signal of the second comparator 725 has not been triggered (value "0"), then method 800 returns to operation 810. If the output signal of the second comparator 725 has been triggered (value "1"), then method 800 proceeds to the next operating mode.

[0074] At operation 830, the memory device transitions to a mixed mode. More specifically, the processing logic activates the first transistor 421 (where OEN=1) while keeping the second transistor 425 active (JOIN=1), for example, operating in mixed mode. The processing logic also sets the voltage threshold (Vt) of the second comparator 725 to a value of one (“1”). At value one, the voltage threshold of the second comparator 725 can be a relatively small voltage value less than zero to be triggered when a negative voltage is detected. A negative voltage indicates that the voltage output has exceeded the voltage output provided only by the second voltage source (Vccq), and therefore, Vccq is no longer needed.

[0075] At operation 840, the second voltage source is de-scaled off. More specifically, the processing logic slowly deactivates the second transistor 425 during the time interval in which the I / O circuit system 312 is powered, for example, by the first voltage source (Vcc) and the second voltage source (Vccq) in mixed mode. For example, the processing logic may cause the JOIN signal to scalp linearly or gradually toward zero to provide a smooth transition from the supply power to the voltage regulator 417 being in amplifier mode.

[0076] At operation 850, the voltage drop is determined. More specifically, the processing logic determines whether the output signal (Det_drop) of the second comparator 725 (value "1") has been triggered, for example, indicating that a newly set voltage threshold (Vt) has been met. Upon meeting this new Vt, the mixed mode can immediately end because no further contribution from Vccq is needed, and the memory device can enter amplifier mode. If this value is not met (value "0"), then method 800 can loop back to operation 810 and effectively restart.

[0077] At operation 860, the memory device transitions to amplifier mode. More specifically, the processing logic deactivates the second transistor 425 (JOIN=0), thus cutting off the decrementing ramp of the JOIN signal, and keeps the first transistor 421 active (OEN=1). Additionally, the processing logic now focuses on the output signal (hi_curr) of the first comparator 721 to detect the trigger threshold.

[0078] At operation 870, a current drop is detected. More specifically, the processing logic determines whether a current draw drop in I / O circuitry 312 is detected. As long as the current remains sufficiently high, the output signal (hi_curr) will remain at a value of one (“1”) and continue looping through operation 860. However, in response to a sufficient drop in current draw (e.g., satisfying a second threshold criterion), the threshold voltage (Vt) of the first comparator 721 will trigger to a zero value (“0”) output signal (hi_curr). In response to the output zero, the method loops back to operation 810 and effectively restarts, placing the memory device back into short-circuit mode.

[0079] Figure 9 This is a flowchart of an example method 900 for selectively switching power from one or both of two voltage sources to an I / O circuit system according to an embodiment. The method 900 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 900 is performed by… Figure 1The control logic 113 and / or 713 and / or logic execution of the local media controller 135.

[0080] Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. Furthermore, in some embodiments, one or more operations may be omitted. Therefore, not all operations described are required in every embodiment, and other processing flows are possible.

[0081] At operation 910, a first voltage source is used. More specifically, the memory device causes the first voltage source (Vcc) to power the core memory circuitry of the memory device.

[0082] At operation 920, a second voltage source is used. More specifically, the memory device causes the second voltage source (Vccq) to power the input / output (I / O) buffer set of the memory device.

[0083] At operation 930, the short-circuit operation mode is entered. More specifically, the processing logic of the memory device causes the first transistor to be activated immediately after the memory device is started. The first transistor is coupled between the second voltage source and the I / O circuit system of the memory device.

[0084] At operation 940, the memory device transitions to a mixed mode. More specifically, the processing logic causes a second transistor to be activated in response to detecting that current draw from the I / O circuitry meets a first threshold criterion. The second transistor is coupled between the voltage regulator of the first voltage source and the I / O circuitry.

[0085] At operation 950, the memory device operates in a mixed mode. More specifically, the processing logic causes the first transistor to be deactivated during the time interval during which the I / O circuitry is powered by the first and second voltage sources.

[0086] Figure 10 This describes an instance machine of computer system 1000, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 1000 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1(The operation of control logic 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0087] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0088] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1018, which communicate with each other via a bus 1030.

[0089] Processing device 1002 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1002 is configured to execute instructions 1026 for performing the operations and steps discussed herein. Computer system 1000 may additionally include a network interface device 1008 for communication on network 1020.

[0090] Data storage system 1018 may include machine-readable storage medium 1024 (also referred to as computer-readable medium) on which one or more instruction sets 1026 or software embodying any or more of the methods or functions described herein are stored. Instructions 1026 may also reside wholly or at least partially within main memory 1004 and / or processing device 1002 during execution by computer system 1000, both of which also constitute machine-readable storage media. Machine-readable storage medium 1024, data storage system 1018, and / or main memory 1004 may correspond to... Figure 1 The memory subsystem 110.

[0091] In one embodiment, instruction 1026 includes instructions for implementing different power supplies (e.g., Figure 1 The control logic 113) contains functional instructions. Although the machine-readable storage medium 1024 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" or similarly "non-transitory computer-readable medium" should also be considered to include any medium capable of storing a set of instructions for machine execution or encoding said set of instructions and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0092] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0093] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0094] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0095] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0096] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0097] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. An apparatus comprising: A voltage regulator coupled to a first voltage source, which supplies power to the core memory circuitry of the memory device. A first transistor is coupled between the output of the voltage regulator and the input / output I / O circuitry of the memory device; A second transistor is coupled between a second voltage source and the I / O circuit system, the second voltage source supplying power to the I / O buffer set, wherein the first voltage source supplies a higher voltage compared to the second voltage source; and Control logic, coupled to the gates of the first transistor and the second transistor, performs operations including the following: This activates the second transistor to allow current to flow from the second voltage source to the I / O circuit system; In response to detecting that the current draw from the I / O circuit system meets a first threshold criterion, the first transistor is activated; and This causes the second transistor to be deactivated during the time interval during which the I / O circuit system is powered by the first voltage source and the second voltage source.

2. The device of claim 1, further comprising a comparator having inputs from the drain and source of the second transistor, wherein the comparator provides an output signal indicating whether the first threshold criterion is satisfied to the control logic.

3. The device of claim 2, wherein, in order to deactivate during the time interval, the second transistor linearly transitions from fully activated to fully deactivated, and wherein the operation further comprises: In response to deactivating the second transistor during the time interval, the threshold voltage used to turn off the comparator is changed to a value less than zero; and In response to the comparator detecting that the value is less than zero, the second transistor is completely deactivated.

4. The device of claim 1, wherein after completely deactivating the second transistor, the operation further comprises: The decrease in the current draw of the I / O circuit system is detected to meet the second threshold criterion; This completely deactivates the first transistor; and This causes the second transistor to be fully activated.

5. The device of claim 4, further comprising a comparator having inputs from the drain and source of the first transistor, wherein the comparator provides an output signal indicating whether the second threshold criterion is satisfied to the control logic.

6. The device of claim 1, wherein the first transistor and the second transistor are each n-type complementary metal-oxide-semiconductor (NMOS) transistors.

7. A system comprising: The first voltage source supplies power to the core memory circuitry of the memory device; A voltage regulator coupled to the first voltage source; The first transistor is coupled between the output and input / output I / O circuitry of the voltage regulator; A second voltage source supplies power to the I / O buffer set of the memory device, and the first voltage source provides a voltage higher than that of the second voltage source; The second transistor is coupled between the second voltage source and the I / O circuit system; and Control logic, coupled to the gates of the first transistor and the second transistor, performs operations including the following: This activates the second transistor to allow current to flow from the second voltage source to the I / O circuit system; In response to detecting that the current draw from the I / O circuit system meets a first threshold criterion, the first transistor is activated; and This causes the second transistor to be deactivated during the time interval during which the I / O circuit system is powered by the first voltage source and the second voltage source.

8. The system of claim 7, wherein the voltage regulator includes an operational amplifier and further includes a voltage divider coupled between the second voltage source and the positive input terminal of the operational amplifier, wherein the top resistor of the voltage divider can be adjusted by a trim value to eliminate offset of the operational amplifier within at least one percent of the voltage of the second voltage source.

9. The system of claim 7, further comprising a comparator having inputs from the drain and source of the second transistor, wherein the comparator provides an output signal indicating whether the first threshold criterion is satisfied to the control logic.

10. The system of claim 9, wherein, in order to deactivate during the time interval, the second transistor linearly transitions from fully activated to fully deactivated, and wherein the operation further comprises: In response to deactivating the second transistor during the time interval, the threshold voltage used to turn off the comparator is changed to a value less than zero; and In response to the comparator detecting that the value is less than zero, the second transistor is completely deactivated.

11. The system of claim 7, wherein after the second transistor is completely deactivated, the operation further comprises: The decrease in the current draw of the I / O circuit system is detected to meet the second threshold criterion; This completely deactivates the first transistor; and This causes the second transistor to be fully activated.

12. The system of claim 11, further comprising a comparator having inputs from the drain and source of the first transistor, wherein the comparator provides an output signal indicating whether the second threshold criterion is satisfied to the control logic.

13. The system of claim 7, wherein the first transistor and the second transistor are each n-type complementary metal-oxide-semiconductor (NMOS) transistors.

14. A method comprising: This causes the core memory circuitry of the memory device to be powered by a first voltage source; This causes the input / output I / O buffer set of the memory device to be powered by a second voltage source, wherein the first voltage source supplies a higher voltage compared to the second voltage source; The control logic of the memory device causes the first transistor to be activated immediately after the memory device is started. The first transistor is coupled between the second voltage source and the I / O circuit system of the memory device. The control logic activates a second transistor in response to detecting that the current draw from the I / O circuit system meets a first threshold criterion. The second transistor is coupled between the voltage regulator of the first voltage source and the I / O circuit system. and The control logic causes the first transistor to be deactivated during the time interval during which the I / O circuit system is powered by the first voltage source and the second voltage source.

15. The method of claim 14, further comprising setting a threshold voltage of a comparator to the first threshold criterion via the control logic after the startup of the memory device, the comparator having inputs from the drain and source of the first transistor.

16. The method of claim 14, further comprising receiving, via the control logic, a comparator state indicating that the first threshold criterion is satisfied, the comparator having inputs from the drain and source of the first transistor.

17. The method of claim 16, wherein causing the first transistor to deactivate during the time interval comprises causing the first transistor to transition linearly from fully activated to fully deactivated, further comprising: The control logic, in response to causing the first transistor to deactivate during the time interval, changes the threshold voltage used to cut off the comparator to a value less than zero; and In response to the comparator detecting that the value is less than zero, the first transistor is completely deactivated.

18. The method of claim 14, further comprising: After the first transistor is completely deactivated, the control logic detects whether the decrease in the current draw of the I / O circuit system satisfies the second threshold criterion. This completely deactivates the second transistor; and This causes the first transistor to be fully activated.

19. The method of claim 18, further comprising receiving, via the control logic, a comparator state indicating whether the second threshold criterion is satisfied, the comparator having inputs from the drain and source of the second transistor.

Images