III-V semiconductor device with lanthanum aluminate dielectric layer and method for manufacturing the same

Abstract

The present invention discloses a manufacturing method of a III-V semiconductor element having a lanthanum aluminate dielectric layer. The manufacturing method includes the following steps: forming a III-V semiconductor channel layer on a substrate; forming a barrier layer on the above-mentioned channel layer; and forming a mixed layer of La 2‑x Al x O3 lanthanum aluminate layer, where X is less than 1 and greater than or equal to 0.1, and the above-mentioned source and the above-mentioned drain are exposed to the above-mentioned barrier layer and the above-mentioned lanthanum aluminate layer; and forming a source, a drain, and a gate between the aforementioned source and the aforementioned drain on the above-mentioned lanthanum aluminate layer. In addition, the present invention also relates to a III-V semiconductor element having a lanthanum aluminate dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor electronic device manufacturing technology, and particularly to a III-V semiconductor device with a lanthanum aluminate dielectric layer and a manufacturing method thereof, which increases the capacitance value corresponding to the capacitance effect between the gate and the substrate by increasing the dielectric value of the metal oxide layer formed between the gate and the substrate, and reduces the leakage voltage value. Background Art

[0002] A metal oxide semiconductor field effect transistor (MOSFET) is an electronic component commonly used as a switching device in a circuit. Taking a silicon semiconductor MOSFET as an example, it has a channel layer formed of silicon element, source and drain electrodes are formed on the channel layer, an insulating layer of metal oxide (MOS) is provided on the upper surface of the channel layer, and a metal or polysilicon electrode of the gate is provided on the insulating layer. When a positive voltage is applied to the gate electrode, a capacitance effect will occur between the gate electrode and the substrate below the channel layer, causing carriers (electrons) to accumulate in the channel layer near the gate and forming an electron channel between the source and the drain. At this time, a potential difference is formed between the source and the drain, and electrons can flow from the source to the drain.

[0003] Most of the conventional MOSFETs have a silicon-based channel layer material. III-V semiconductor materials (such as gallium arsenide, GaAs) have better operating performance than traditional silicon-based MOSFETs due to their direct bandgap and high carrier mobility. Therefore, various electronic semiconductor devices currently use III-V semiconductor materials for manufacturing, and some current MOSFETs also have a channel layer made of III-V semiconductor materials.

[0004] Since a MOSFET operates based on the capacitance effect between the gate and the substrate, the capacitance value between the gate and the substrate will affect the operating performance of the MOSFET. The dielectric layer provided between the gate electrode and the channel layer will affect the value of the capacitance.

[0005] In the traditional silicon transistor structure, silicon dioxide is mainly used as the gate dielectric layer. Because silicon dioxide can be obtained by oxidizing silicon, and it has advantages such as lattice matching and excellent interface quality with respect to silicon, enabling a silicon field effect transistor (MOSFET) to obtain a higher capacitance value and excellent control characteristics. However, III-V semiconductors lack a native oxide like silicon dioxide with respect to silicon that can be used as the gate dielectric layer. Therefore, with the increasing demand for unit capacitance in integrated circuit devices, it is necessary to develop dielectric materials with a higher dielectric constant as the gate dielectric layer for III-V semiconductor transistors.

[0006] Currently, some manufacturers have also proposed using lanthanum oxide / silicon dioxide (La 2 O 3 / SiO 2)A dielectric layer is fabricated. However, once tetravalent silicon penetrates into the III-V semiconductor substrate, it will increase the N-type carrier concentration on the surface of the channel layer and thus increase the conductivity, making it difficult to close the carrier channel generated by the gate potential and affecting the operating performance of the MOSFET. SUMMARY OF THE INVENTION

[0007] In view of the above deficiencies of the prior art, according to an embodiment of the present invention, it is desired to provide a III-V semiconductor device with a lanthanum aluminate dielectric layer, and a manufacturing method of the foregoing III-V semiconductor device with a lanthanum aluminate dielectric layer, aiming to achieve the following invention objectives: (1) Since its dielectric material does not contain silicon elements, the reliability of closing the carrier channel is effectively improved; (2) By increasing the dielectric constant of the lanthanum aluminate dielectric layer, at the same physical thickness, the thickness equivalent to SiO 2 can be reduced, the unit capacitance value can be increased, and the miniaturization of electronic devices becomes feasible. (3) By selectively determining the ratio of the lanthanum aluminate dielectric layer, the dielectric coefficient of the dielectric layer can be changed, giving the transistor device better flexibility in electrical performance selection.

[0008] According to an embodiment, a manufacturing method of a III-V semiconductor device with a lanthanum aluminate dielectric layer provided by the present invention includes the following steps: forming a III-V semiconductor channel layer on a substrate; forming a source electrode and a drain electrode spaced apart from each other on the above channel layer; forming a blocking layer on the above channel layer; and forming a La 2-x Al x O 3 lanthanum aluminate layer by co-deposition on the above blocking layer, where X is less than 1 and greater than or equal to 0.1; wherein the above source electrode and the above drain electrode are exposed to the above blocking layer and the above lanthanum aluminate layer; and forming a gate electrode between the above source electrode and the above drain electrode on the above lanthanum aluminate layer.

[0009] According to an embodiment, by the above method of the present invention, a III-V semiconductor device with a lanthanum aluminate dielectric layer provided by the present invention can be fabricated, including a substrate, a III-V semiconductor channel layer formed on the above substrate, a blocking layer formed on the above channel layer, a La 2-x Al x O 3 lanthanum aluminate layer formed by co-deposition on the above blocking layer, where X is less than 1 and greater than or equal to 0.1, and a source electrode, a drain electrode, and a gate electrode between the foregoing source electrode and the foregoing drain electrode formed on the above lanthanum aluminate layer.

[0010] Compared with the prior art, the III-V semiconductor device with a lanthanum aluminate dielectric layer and its manufacturing method of the present invention deposit La 2 O 3With Al 2 O 3 The La 2-x Al x O 3 Lanthanum aluminate layer. Or it can be deposited on the channel layer by controlling its molecular flux by evaporation, and finally forming La 2-x Al x O 3 Lanthanum aluminate layer. La formed by lanthanum oxide and aluminum oxide 2-x Al x O 3 The lanthanum aluminate layer is used as the dielectric layer of the gate, which can avoid the problem that the carrier channel is difficult to close when the silicon-based metal oxide layer is used for the III-V semiconductor channel layer, and can improve the dielectric constant of the metal oxide layer, increase the operating performance of the gate and have a higher breakdown voltage, which can further improve the operating performance of semiconductor devices using III-V elements as the channel layer; in particular, according to the present invention, the component ratio can be accurately selected according to the user's needs, thereby providing a variable range between a higher dielectric constant or a higher breakdown voltage, allowing users to have higher selection flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 1 is a flow chart of a first preferred embodiment of a method for manufacturing a III-V semiconductor device having a lanthanum aluminate dielectric layer according to the present invention.

[0012] Figures 2 to 8 for Figure 1 Schematic side view of each step of the embodiment.

[0013] Figure 9 FIG. 1 is a flow chart of a second preferred embodiment of a method for manufacturing a III-V semiconductor device having a lanthanum aluminate dielectric layer according to the present invention.

[0014] Figures 10 to 15 for Figure 9 Schematic side view of each step of the embodiment.

[0015] Among them: 10, 10' are substrates; 20, 20' are channel layers; 30, 30' are barrier layers; 32' are recessed portions; 41, 41' are source electrodes; 42, 42 are drain electrodes; 50, 50' are lanthanum aluminate dielectric layers; 51 is a lanthanum oxide layer; 52 is an aluminum oxide layer; 53, 53' are sacrificial portions; 60, 60' are gates; S1~S6, S1'~S6' are steps. DETAILED DESCRIPTION

[0016] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. These embodiments should be understood as being only for illustrative purposes of the present invention and not for limiting the protection scope of the present invention. After reading the content recorded in the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

[0017] The First Preferred Embodiment

[0018] The method for manufacturing a III-V semiconductor device with a lanthanum aluminate dielectric layer in the first preferred embodiment of the present invention is as shown in the flowchart of Figure 1 As shown first in Figure 2 In step S1, a channel layer 20 made of III-V elements is formed on a substrate 10. In this example, gallium nitride (GaN) is taken as an example. Of course, those skilled in the art can easily understand that the substrate can be a silicon substrate, a sapphire substrate, an aluminum nitride substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium phosphide substrate, etc., and the channel layer material can be gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), gallium arsenide (GaAs), indium gallium arsenide (In 1-x Ga x As, X≤1), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc., or Al 1-x Ga x N / GaN (X<0.5), In 1-x Al x N / GaN (X = 0 to 0.5), AlN / GaN, AlN / Al 1-x Ga x N (x<0.5) or other similar III-V compounds; Subsequently, as shown in Figure 3 In step S2, a blocking layer 30 with a height of about 5 to 30 nanometers is formed on the channel layer 20 with aluminum gallium nitride (AlGaN, AlxGa 1 -xN, 0<=x<=0.40) or aluminum nitride (AlN) to prevent the diffusion of substances in the metal oxide layer in the subsequent manufacturing process to the channel layer 20; Subsequently, in step S3 as shown in Figure 4As shown, at the left and right near-edge positions of the blocking layer 30, a similar metal material stack is formed by, for example, titanium / aluminum / nickel / gold through atomic layer deposition or other conductive materials such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, and other materials with appropriate work functions, or any combination of the above, using deposition techniques such as chemical vapor deposition, physical vapor deposition, or other appropriate deposition techniques. The source electrode 41 and the drain electrode 42 with a thickness of 0.2 to 2 μm are respectively formed. The distance between the source electrode 41 and the drain electrode 42 is generally 2 to 20 μm. When electrical energy is applied to the source electrode 41 and the drain electrode 42, a two-dimensional electron gas (2DEG) is formed at the interface between the channel layer 20 and the blocking layer 30, thereby forming a conductive channel.

[0019] As Figure 5 shown, when in step S4, on the above-mentioned source electrode 41, drain electrode 42, and blocking layer 30, a metal oxide layer of lanthanum aluminate formed by lanthanum oxide and aluminum oxide is formed. In this example, taking the pulsed laser deposition (PLD) method as an example, multiple layers of lanthanum oxide layer 51 and multiple layers of aluminum oxide layer 52 are alternately formed on the blocking layer 30 as Figure 6 shown. The thickness of each layer of lanthanum oxide layer 51 or aluminum oxide layer 52 is 0.2 to 2 nanometers. Since laser coating is achieved by hitting the lanthanum oxide and aluminum oxide targets with a laser beam, the number of laser pulses and the length of time of hitting can be controlled to determine the thickness of each lanthanum oxide layer 51 or aluminum oxide layer 52, thereby controlling the ratio of the two, and thus adjusting the X value in the future lanthanum aluminate dielectric layer (La 2-x Al x O 3 )50, where X is greater than 0.1 and less than 1.0.

[0020] In step S5, as Figure 7 shown, the sacrificial area 53 of the lanthanum aluminate dielectric layer located above the source electrode 41 and the drain electrode 42 is removed (as Figure 5 shown), and the whole is heated to 400 to 800 degrees Celsius for rapid annealing, so that multiple layers of lanthanum oxide layer 51 and multiple layers of aluminum oxide layer 52 are uniformly mixed to form a mixed lanthanum aluminate dielectric layer 50. The thickness of the lanthanum aluminate dielectric layer 50 is 1 nanometer to 50 nanometers. Thereby improving the operating characteristics of the electronic device using group III-V elements as the channel layer.

[0021] Of course, as can be easily inferred by those with ordinary knowledge in the technical field, the laser coating method here is not limited. Whether it is evaporation coating, atomic layer deposition (ALD), or molecular beam epitaxy (MBE), they all belong to the available forming methods for forming the lanthanum aluminate dielectric layer of the present invention. Finally, as Figure 8 shown in step S6, a metal stack of nickel / gold with a thickness of, for example, 0.1 to 2 μm is formed on the uniformly mixed lanthanum aluminate dielectric layer 50, and then a photoresist is applied, exposed, developed, and etched to form a gate 60 between the source 41 and the drain 42.

[0022] The following is the comparison of the dielectric constant and breakdown voltage results when the thickness of the lanthanum aluminate coating layer is 2 - 50 nm and the composition of La 2-x AL x O 3 is different (the x value is different), as shown in Table 1:

[0023] Table 1

[0024]

[0025] Due to the high dielectric value and high breakdown voltage at the same time, it fully meets the requirements of III-V MOSFETs. When a voltage is applied to the gate, it can smoothly block the electron channel. Especially in the case of a high dielectric constant, the gate voltage that needs to be applied can be lower while still maintaining a sufficient electric field for open-circuit control of the electron channel, which not only effectively improves the electron signal conversion rate, but also the capacitance value of the transistor is higher, and for the same capacitance, the thickness of the dielectric layer can effectively reduce the leakage current caused by direct tunneling and avoid the deterioration of the electrical properties of the transistor. In addition, as can be easily understood by those with ordinary knowledge in the technical field, the gate can also be made of conductive materials such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, and other conductive materials whose work functions are compatible with the substrate material, or any combination of the above. The electrode layer of the gate 60 can be formed by, for example, atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, or any combination of the above. And the width of the gate is between about 30 nm and 60 nm.

[0026] Second preferred embodiment

[0027] The steps of the second preferred embodiment of the present invention are as Figure 9 shown, where the same steps S1’ and S2’ as in the previous embodiment and the corresponding Figure 10 and Figure 11, similarly, a channel layer 20' is formed on the substrate 10', and a blocking layer 30' is formed on the channel layer 20', which will not be elaborated here. Subsequently, in step S3', in addition to forming a source electrode 41' and a drain electrode 42' on the blocking layer 30' in the same way, and as Figure 12 shown, a recessed portion 32' with a thickness greater than 0 but less than 10 nanometers is formed on the blocking layer 30' by etching.

[0028] In this embodiment, Figure 13 step S4' of

[0029] is carried out by the electron gun evaporation (E-gun evaporator) method. While evaporating lanthanum oxide and aluminum oxide materials with an electron beam, the lanthanum oxide and aluminum oxide become gaseous and then are deposited. By providing different electron beam currents, different evaporation speeds are selected, so that the lanthanum oxide and aluminum oxide molecules are mixed with different molecular flow rates and then deposited approximately uniformly on the blocking layer 30'. Since the operating environment itself has an operating temperature of, for example, 400 - 800 °C, the deposited precursors can be directly and uniformly mixed to form the lanthanum aluminate-based dielectric layer 50' of the present invention and the sacrificial portion 53' located on the source electrode 41' and the drain electrode 42'. Figure 14 and Figure 15 In steps S5' and S6', which are the same as those in the previous embodiment, by removing the sacrificial portion 53' and forming a gate electrode 60' at the position of the lanthanum aluminate-based dielectric layer 50' corresponding to the recessed portion 32', the III-V semiconductor device with a lanthanum aluminate-based dielectric layer disclosed in the present invention can be completed.

[0030] As shown in Table 1 above, as long as the selection ratio is changed during the manufacturing process, the dielectric layer of the transistor manufactured according to the present invention can have a better dielectric constant or a better breakdown voltage, with a wide range of electrical performance variation, so it can be changed according to the user's needs, providing the flexibility of product use and meeting the market demand.

[0031] The above manufacturing method forms a lanthanum aluminate dielectric layer on the channel layer (or blocking layer) of group III-V elements, which provides a high dielectric constant with a dielectric constant K of 24 to 28, and its breakdown voltage is between 9.6 and 10.0 MV / cm. For existing semiconductor devices using group III-V elements as channel layer materials, an appropriate metal oxide layer corresponding to the channel layer material can be obtained. Moreover, since silicon is an N-type dopant for group III-V materials, the lanthanum aluminate dielectric layer used in the present invention avoids the doping effect generated when a silicon-based oxide dielectric layer is used for a group III-V channel layer, which in turn affects the problem that the channel is not easily turned off. Moreover, the high dielectric constant can obtain better gate operation performance, effectively reducing the leakage current caused by direct tunneling, thus making it feasible to miniaturize the overall electronic device.

Claims

1. A manufacturing method of a III-V semiconductor device with a lanthanum aluminate dielectric layer, characterized in that, it includes the following steps: a) Forming a III-V semiconductor channel layer on a substrate; b) Forming a barrier layer on the above-mentioned channel layer; c) Forming a source electrode and a drain electrode which are away from each other on the above-mentioned barrier layer; d) Form a La 2-x Al x O 3 lanthanum aluminate layer on the above-mentioned barrier layer, where X is less than 1 and greater than or equal to 0.1, and the above-mentioned source and the above-mentioned drain are exposed to the above-mentioned barrier layer and the above-mentioned lanthanum aluminate layer; and e) Forming a gate electrode between the above-mentioned source electrode and the above-mentioned drain electrode on the above-mentioned lanthanum aluminate layer; wherein, the above-mentioned step d) further includes a sub-step d1) of alternately growing a plurality of lanthanum oxide layers and a plurality of aluminum oxide layers; and a sub-step d2) of subsequently performing annealing at 400 to 800 degrees Celsius to uniformly mix the above-mentioned lanthanum oxide layers and aluminum oxide layers.

2. The manufacturing method of a III-V semiconductor device with a lanthanum aluminate dielectric layer according to claim 1, characterized in that, the above-mentioned sub-step d1) uses laser coating to alternately grow a plurality of lanthanum oxide layers and a plurality of aluminum oxide layers.

3. The manufacturing method of a III-V semiconductor device with a lanthanum aluminate dielectric layer according to claim 1, characterized in that, the above-mentioned sub-step d1) uses atomic layer deposition to alternately grow a plurality of lanthanum oxide layers and a plurality of aluminum oxide layers.

4. The manufacturing method of a III-V semiconductor device with a lanthanum aluminate dielectric layer according to any one of claims 1-3, characterized in that, it further includes an etching step e) between the above-mentioned step b) and the above-mentioned step c), so as to form at least one recess corresponding to the position of the above-mentioned gate electrode in the above-mentioned barrier layer, thereby at least partially reducing the thickness of the barrier layer corresponding to the position of the above-mentioned gate electrode.

5. A III-V semiconductor device with a lanthanum aluminate dielectric layer manufactured by the manufacturing method according to any one of claims 1-3, characterized in that, the above-mentioned III-V semiconductor device with a lanthanum aluminate dielectric layer includes: a substrate; a III-V semiconductor channel layer formed on the above-mentioned substrate; a barrier layer formed on the above-mentioned channel layer; a source electrode and a drain electrode formed on the above-mentioned barrier layer; A lanthanum aluminum oxide layer formed on the above-mentioned barrier layer, where X is less than 1 and greater than or equal to 0.1; and 2-x Al x O 3 ​ a gate electrode formed on the above-mentioned lanthanum aluminate layer and between the above-mentioned source electrode and the above-mentioned drain electrode.

6. The III-V semiconductor device with a lanthanum aluminate dielectric layer according to claim 5, characterized in that, The above-mentioned La 2-x Al x O 3 The thickness of the lanthanum aluminate layer is between 1 nm and 50 nm.

7. The III-V semiconductor device with a lanthanum aluminate dielectric layer according to claim 5, characterized in that, at least one recess corresponding to the position of the above-mentioned gate electrode is formed in the above-mentioned barrier layer, thereby at least partially reducing the thickness of the barrier layer corresponding to the position of the above-mentioned gate electrode.

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