Base Station Interface Module and Base Station

Abstract

An embodiment of the present application provides a base station interface module and a base station. The base station interface module includes: a general public radio interface, a high-speed serial interface, a first scrambling module, and a forward error correction coding module; a first output end of the general public radio interface is connected to an input end of the first scrambling module; an output end of the first scrambling module is connected to an input end of the forward error correction coding module; an output end of the forward error correction coding module is connected to an input end of the high-speed serial interface; wherein, the first scrambling module is used for scrambling S codes, T codes, and scrambled data. The base station interface module and the base station provided by the embodiments of the present application add a forward error correction coding module between the scrambling module and the high-speed serial interface, reduce the bit error rate in application scenarios with a relatively high line rate, and improve the stability of data interaction between the AAU and the BBU.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a base station interface module and a base station. Background Art

[0002] An Active Antenna Unit (AAU) is connected to an indoor baseband unit (BBU) through optical fibers. Uplink data is sent from the AAU to the BBU, and downlink data is sent from the BBU to the AAU.

[0003] In existing base station interface solutions, data is generally packetized according to the Common Public Radio Interface (CPRI) protocol.

[0004] However, in existing base station interface solutions, for application scenarios with relatively high line rates, the base station will have bit errors, affecting the long-term stable operation of the base station. Summary of the Invention

[0005] Embodiments of this application provide a base station interface module and a base station to solve the technical problem of poor stability of base stations in the prior art.

[0006] In a first aspect, embodiments of this application provide a base station interface module, including:

[0007] A Common Public Radio Interface, a high-speed serial interface, a first scrambling module, and a forward error correction coding module;

[0008] A first output end of the Common Public Radio Interface is connected to an input end of the first scrambling module;

[0009] An output end of the first scrambling module is connected to an input end of the forward error correction coding module;

[0010] An output end of the forward error correction coding module is connected to an input end of the high-speed serial interface;

[0011] Wherein, the first scrambling module is used to scramble S codes, T codes, and scrambled data.

[0012] Optionally, it further includes a second scrambling module and a first selector;

[0013] A second output end of the Common Public Radio Interface is connected to an input end of the second scrambling module;

[0014] An output end of the forward error correction coding module is connected to an input end of the high-speed serial interface through the first selector;

[0015] The output end of the forward error correction coding module is connected to the first input end of the first selector;

[0016] The output end of the second scrambling module is connected to the second input end of the first selector;

[0017] The output end of the first selector is connected to the input end of the high-speed serial interface;

[0018] When the enable end of the first selector is in the first state, the output end of the forward error correction coding module is conducted to the input end of the high-speed serial interface;

[0019] When the enable end of the first selector is in the second state, the output end of the second scrambling module is conducted to the input end of the high-speed serial interface;

[0020] Wherein, the second scrambling module is used for scrambling the scrambled data.

[0021] Optionally, a first descrambling module and a forward error correction decoding module are further included;

[0022] The first output end of the high-speed serial interface is connected to the input end of the forward error correction decoding module;

[0023] The output end of the forward error correction decoding module is connected to the input end of the first descrambling module;

[0024] The output end of the first descrambling module is connected to the input end of the general public radio interface;

[0025] Wherein, the first descrambling module is used for descrambling the S code, the T code and the descrambled data.

[0026] Optionally, a second descrambling module and a second selector are further included;

[0027] The second output end of the high-speed serial interface is connected to the input end of the second descrambling module;

[0028] The output end of the first descrambling module is connected to the input end of the general public radio interface through the second selector;

[0029] The output end of the second selector is connected to the input end of the general public radio interface;

[0030] When the enable end of the second selector is in the first state, the output end of the first descrambling module is conducted to the input end of the general public radio interface;

[0031] When the enable end of the second selector is in the second state, the output end of the second descrambling module is conducted to the input end of the general public radio interface;

[0032] Among them, the second descrambling module is used to descramble the descrambled data.

[0033] Optionally, the forward error correction encoding module is a Reed-Solomon code encoding module.

[0034] Optionally, the forward error correction decoding module is a Reed-Solomon code decoding module.

[0035] Optionally, the forward error correction encoding module is implemented by a soft core.

[0036] Optionally, the forward error correction decoding module is implemented by a hard core.

[0037] Optionally, the forward error correction decoding module includes a frequency conversion sub-module;

[0038] The frequency conversion sub-module is used to perform frequency conversion processing on the differential input clock to generate the clock of the forward error correction decoding module.

[0039] In a second aspect, an embodiment of the present application provides a base station, including the base station interface module described in the first aspect above.

[0040] The base station interface module and the base station provided by the embodiments of the present application add a forward error correction encoding module between the scrambling module and the high-speed serial interface, reducing the bit error rate in application scenarios with a relatively high line rate and improving the stability of data interaction between the AAU and the BBU. Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 It is a schematic diagram of the connection between the AAU and the BBU;

[0043] Figure 2 It is a schematic diagram of the CPRI frame structure;

[0044] Figure 3 It is a schematic diagram of the BBU interface framework;

[0045] Figure 4 It is a schematic diagram of the overall framework of the base station interface module provided by the embodiment of the present application;

[0046] Figure 5 It is a schematic diagram of the clock module provided by the embodiment of the present application;

[0047] Figure 6 It is the bit error rate comparison diagram provided by the embodiments of the present application. Detailed implementation manners

[0048] Figure 1 It is the schematic connection diagram of the AAU and the BBU. As Figure 1 shown, the AAU and the BBU are connected by optical fibers. The uplink data is sent from the AAU to the BBU, and the downlink data is sent from the BBU to the AAU. The stability of the optical port is extremely important for the operation of the base station. Existing solutions have also taken a series of measures to improve the stability of the optical port and monitor the optical port status.

[0049] Figure 2 It is the schematic diagram of the CPRI frame structure. As Figure 2 shown, in the existing base station interface solutions, data is generally packetized according to the Common Public Radio Interface (CPRI) protocol.

[0050] The optical port rate is relatively high. At the same time, in order to improve the utilization rate of the line rate, 64 / 66B coding is generally adopted. The AAU and the BBU use the same scrambling and descrambling polynomials and scrambling and descrambling initial values.

[0051] The optical port status is monitored by detecting the control word in the data. Figure 3 It is the schematic diagram of the BBU interface framework. As Figure 3 shown, it is the general framework of the BBU interface. The AAU interface framework is mirror-symmetrical to the BBU interface framework. The transceiver IP core is the transceiver intellectual property core; Asy_gearbox is the asynchronous transmission, which is a module in the transceiver IP that implements the coding function.

[0052] In the existing interface solutions, in the application scenarios with low line rate, the base station interface is very stable and reliable, such as the 10G optical port line rate; however, for the application scenarios with relatively high line rate, the base station will have bit errors, affecting the long-term stable operation of the base station, such as the 25G optical port commonly used in existing base stations.

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0054] Figure 4It is a schematic diagram of the overall framework of the base station interface module provided by an embodiment of the present application. As Figure 4 shown, the base station interface module provided by an embodiment of the present application includes:

[0055] a General Public Radio Interface 401, a High-Speed Serial Interface 402, a First Scrambling Module 403, and a Forward Error Correction Coding Module 404;

[0056] A first output end of the General Public Radio Interface 401 is connected to an input end of the First Scrambling Module 403;

[0057] An output end of the First Scrambling Module 403 is connected to an input end of the Forward Error Correction Coding Module 404;

[0058] An output end of the Forward Error Correction Coding Module 404 is connected to an input end of the High-Speed Serial Interface 402;

[0059] Wherein, the First Scrambling Module 403 is used for scrambling S code, T code, and the data to be scrambled.

[0060] Specifically, the First Scrambling Module 403 performs scrambling using a standard protocol. The Forward Error Correction Coding Module 404 can be a Reed-Solomon (RS) code coding module. The Forward Error Correction Coding Module 404 is implemented through a soft core.

[0061] The scrambling and descrambling module of the existing base station interface uses a scrambling polynomial consistent with the standard protocol. The scrambling and descrambling module of the existing base station interface does not adopt self-synchronous scrambling of the standard protocol.

[0062] In the embodiment of the present application, not only the data to be scrambled is scrambled, but also the S code and T code are scrambled. It is a self-synchronous scrambling structure, that is, the scrambler is jointly generated by the data to be scrambled and the polynomial. In this structure, the descrambler does not need to establish synchronization, that is, it does not perform comma (comma is a specific character used for CPRI protocol synchronization) synchronization. Even for different scrambler initial values, as long as the same polynomial and the corresponding scrambled data are used, self-synchronous descrambling can be achieved.

[0063] Optionally, it further includes a Second Scrambling Module 405 and a First Selector 406;

[0064] A second output end of the General Public Radio Interface 401 is connected to an input end of the Second Scrambling Module 405;

[0065] An output end of the Forward Error Correction Coding Module 404 is connected to an input end of the High-Speed Serial Interface 402 through the First Selector 406;

[0066] The output end of the forward error correction coding module 404 is connected to the first input end of the first selector 406;

[0067] The output end of the second scrambling module 405 is connected to the second input end of the first selector 406;

[0068] The output end of the first selector 406 is connected to the input end of the high-speed serial interface 402;

[0069] When the enable end of the first selector 406 is in the first state, the output end of the forward error correction coding module 404 is turned on with the input end of the high-speed serial interface 402;

[0070] When the enable end of the first selector 406 is in the second state, the output end of the second scrambling module 405 is turned on with the input end of the high-speed serial interface 402;

[0071] Wherein, the second scrambling module 405 is used for scrambling the scrambled data.

[0072] Specifically, as Figure 4 shown, the base station interface module in the embodiment of the present application further includes a second scrambling module 405. The second scrambling module 405 performs scrambling in the original scrambling manner in the existing solution, that is, only scrambles the scrambled data.

[0073] When the enable end of the first selector 406 is in the first state, the output end of the forward error correction coding module 404 is turned on with the input end of the high-speed serial interface 402, and standard protocol scrambling is adopted.

[0074] When the enable end of the first selector 406 is in the second state, the output end of the second scrambling module 405 is turned on with the input end of the high-speed serial interface 402, and scrambling is performed in the original scrambling manner in the existing solution.

[0075] For example, a switching register is used as the first selector 406. A switching register is provided for optical splitter port control of forward error correction (FEC) (referring to adding RS coding, that is, introducing forward error correction) and non-forward error correction code (non-FEC) switching.

[0076] On the encoding side, both FEC-encoded and non-FEC-encoded data are output, and the GTY (High-Speed Serial Interface. In Xilinx's Field Programmable Gate Array (FPGA) for Gigabit applications, some high-speed serial interfaces are generally integrated, collectively referred to as Gigabit Transceiver (GTx), including GTP, GTR, GTX, GTH, GTZ, GTY, GTM (with increasing transmission rates), etc.) inlet switches the data source according to the configuration of the switching register.

[0077] Optionally, it further includes a first descrambling module 407 and a forward error correction decoding module 408;

[0078] The first output end of the high-speed serial interface 402 is connected to the input end of the forward error correction decoding module 408;

[0079] The output end of the forward error correction decoding module 408 is connected to the input end of the first descrambling module 407;

[0080] The output end of the first descrambling module 407 is connected to the input end of the general public radio interface 401;

[0081] Wherein, the first descrambling module 407 is used to descramble the S code, T code, and the descrambled data.

[0082] Specifically, as Figure 4 shown, in the embodiment of the present application, the first descrambling module 407 in the base station interface module uses a standard protocol for descrambling, and the forward error correction decoding module 408 can be a Reed-Solomon (RS) code decoding module. The forward error correction decoding module 408 is implemented through a hard core.

[0083] Optionally, it further includes a second descrambling module 409 and a second selector 410;

[0084] The second output end of the high-speed serial interface 402 is connected to the input end of the second descrambling module 409;

[0085] The output end of the first descrambling module 407 is connected to the input end of the general public radio interface 401 through the second selector 410;

[0086] The output end of the second selector 410 is connected to the input end of the general public radio interface 401;

[0087] When the enable end of the second selector 410 is in the first state, the output end of the first descrambling module 407 is conducted with the input end of the general public radio interface 401;

[0088] When the enable terminal of the second selector 410 is in the second state, the output terminal of the second descrambling module 409 is conducted with the input terminal of the general public radio interface 401;

[0089] Among them, the second descrambling module 409 is used to descramble the data to be descrambled.

[0090] Specifically, as Figure 4 shown, in the embodiment of the present application, the second descrambling module 409 in the base station interface module descrambles in the original descrambling manner of the existing solution, that is, only descrambles the data to be descrambled.

[0091] When the enable terminal of the second selector 410 is in the first state, the output terminal of the first descrambling module 407 is conducted with the input terminal of the general public radio interface 401, and descrambling is performed using the standard protocol.

[0092] When the enable terminal of the second selector 410 is in the second state, the output terminal of the second descrambling module 409 is conducted with the input terminal of the general public radio interface 401, and descrambling is performed using the original descrambling manner of the existing solution.

[0093] For example, a switching register is used as the second selector 410. A switching register is provided for optical splitter port control of FEC and non-FEC switching.

[0094] On the decoding side, the hardcore outputs FEC-encoded and non-FEC-encoded data in the same clock domain. After non-FEC descrambling, the data is the same as the FEC-encoded data. The data source is switched according to the register configuration type, and the gearbox slip code signal is switched (this is a signal fed back to the transceiver IP core to notify the transceiver of the slip code. When FEC is enabled, the used slip code signal is different and needs to be switched).

[0095] Optionally, the forward error correction decoding module 408 includes a frequency conversion sub-module;

[0096] The frequency conversion sub-module is used to perform frequency conversion processing on the differential input clock to generate the clock of the forward error correction decoding module 408.

[0097] Specifically, Figure 5 is a schematic diagram of the clock module provided by the embodiment of the present application. As Figure 5 shown, the existing base station interface has 2 clock domains, and the embodiment of the present application uses 3 clock domains for the data channel. On the encoding side, each channel has only one clock domain as before (gt_tx_clk refers to TX_CLK_OUT_CHX (clock domain name)); on the decoding side, a hardcore output is added as the rx_fast_clk clock domain (for the clock domain of the added forward feedback part).

[0098] Since the FEC / non-FEC switch requires the same clock domain, the hardcore output needs to be used to convert to the gt_tx_clk clock domain.

[0099] The decoding core in the FEC hardcore requires a clock of no less than 380M and is not related to the GTY reference clock. It can be obtained by using the clock multiplication in Figure 5 the following.

[0100] RX_FAST_CLK@368M (clock domain name, "@368M" indicates that the frequency of this clock domain is 368M) and RSFEC_CLK@294M (clock domain name, "@294M" indicates that the frequency of this clock domain is 294M) are required to maintain clock phase correlation. They can be output by the same Phase Locked Loop (PLL). These two clocks cannot add FalsePath constraints (the timing requirements are not met after adding, and this requirement belongs to the content related to FPGA constraints).

[0101] Figure 5 In the following figure, the differential input clocks (named GTREFCLKP and GTREFCLKN respectively) are input to the clock multiplication module (named MMCM(ddr) and MMCM(sys) respectively, where MMCM is the IP core name) through the high-speed serial interface input buffer (IBUF_GTE4, differential input primitive module name) for multiplication processing. The clock after multiplication processing is input to the IP hardcore (decoding) through the input buffer. The clock after multiplication processing (FEC_FAST_CLK@368.64M) and the protocol-side clocks (TX_CLK_OUT_CH0, TX_CLK_OUT_CH1, TX_CLK_OUT_CH2, and TX_CLK_OUT_CH4) are input to the asynchronous data conversion device (named FIFO). The protocol-side receiving module (named IR(RX)) decodes the data according to the protocol, and the protocol-side sending module (named IR(TX)) packets according to the protocol. The triangles in the figure represent the input buffers.

[0102] Figure 5 In the following figure, CLK represents the clock domain. For example, RX_CLK_OUT_CH0@368.64M represents that the name of the clock domain is RX_CLK_OUT_CH0 and the frequency is 368.64M.

[0103] The following further illustrates the base station interface module in the above embodiments with a specific example:

[0104] The RS-FEC function is implemented by an Xilinx IP core with a coding rate of 0.97. The IP core supports a maximum line speed processing of 28.05 Gbps per channel. There are two implementation schemes for the IP core. The soft core achieves the optimal resources for a single optical port, and the hard core achieves the optimal resources for two or more optical ports.

[0105] 1) The functions of both the transmitting and receiving sides of the RS-FEC function are implemented by the soft core. Each 32GFC RS-FEC (IP core name) soft core can implement single-channel transmission coding, scrambling processing; and single-channel receiving codeword synchronization, descrambling, and decoding processing.

[0106] 2) The receiving side of the RS-FEC function is implemented by the hard core, but the transmitting side still needs to be implemented by the soft core. Each 100G FECRX (IP core name) hard core can implement 4-channel IR receiving processing. For the 100G FEC RX IP hard core resources, only the decoder is a hard core, and other synchronization / descrambling / de-rate matching / decoding block merging are not implemented by the hard core and still require logic resources.

[0107] The increased resources of the RS-FEC function for the BBU with a maximum of 6 optical ports are as follows. The RS-FEC hard core scheme has half fewer Look Up Table (LUT) resources than the soft core scheme, that is, it is implemented by 2 100G FEC RX hard cores + 6 32GFC RS-FEC TX soft cores, as shown in Table 1 specifically.

[0108] Table 1 Scheme comparison table

[0109]

[0110] Figure 6 is the bit error rate comparison diagram provided by the embodiments of the present application. As Figure 6 shown, it is the bit error rate comparison diagram in two modes of FEC and non-FEC. It can be seen from the figure that after adding FEC in the project and re-encoding the base station interface, the system bit error rate can be significantly reduced.

[0111] Table 2 shows the Signal to Noise Ratio (SNR) of various types of test points of the base station. Combining Table 2 and Figure 6 it can be seen that for the two modes of poor points and midpoints, the difference in bit error rate is not significant, but for good points and excellent points, FEC can greatly reduce the base station bit error rate.

[0112] Table 2 SNR of each test point of the base station

[0113] Base station test point SNR Excellent point >22dB Good point 15 - 20dB Midpoint 5dB - 10dB Poor point -5dB - 0dB

[0114] Embodiments of this application improve the stability of data interaction between the AAU and the BBU through RS coding; embodiments of this application are also compatible with the non-FEC mode, and the base station can be switched and selected through registers according to the actual situation, making the base station more flexible; embodiments of this application demonstrate a more resource-saving solution on the chip while meeting the functions, saving costs.

[0115] Optionally, embodiments of this application also provide a base station, including the base station interface module described in the above embodiments.

[0116] The base station provided by embodiments of this application improves the stability of data interaction between the AAU and the BBU through the base station interface module, and is also compatible with the non-FEC mode. The base station can be switched and selected through registers according to the actual situation, making the base station more flexible; embodiments of this application demonstrate a more resource-saving solution on the chip while meeting the functions, saving costs.

[0117] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.

Claims

1. A base station interface module, characterized in that, Comprising: A general public radio interface, a high-speed serial interface, a first scrambling module, and a forward error correction coding module; A first output end of the general public radio interface is connected to an input end of the first scrambling module; An output end of the first scrambling module is connected to an input end of the forward error correction coding module; An output end of the forward error correction coding module is connected to an input end of the high-speed serial interface; Wherein, the general public radio interface adopts 64 / 66B coding; the first scrambling module is used for scrambling S code, T code, and scrambled data.

2. The base station interface module according to claim 1, characterized in that Further comprising a second scrambling module and a first selector; A second output end of the general public radio interface is connected to an input end of the second scrambling module; An output end of the forward error correction coding module is connected to an input end of the high-speed serial interface through the first selector; An output end of the forward error correction coding module is connected to a first input end of the first selector; An output end of the second scrambling module is connected to a second input end of the first selector; An output end of the first selector is connected to an input end of the high-speed serial interface; When an enabling end of the first selector is in a first state, an output end of the forward error correction coding module is conducted with an input end of the high-speed serial interface; When the enabling end of the first selector is in a second state, an output end of the second scrambling module is conducted with an input end of the high-speed serial interface; Wherein, the second scrambling module is used for scrambling the scrambled data.

3. The base station interface module according to claim 1, wherein Further comprising a first descrambling module and a forward error correction decoding module; A first output end of the high-speed serial interface is connected to an input end of the forward error correction decoding module; An output end of the forward error correction decoding module is connected to an input end of the first descrambling module; An output end of the first descrambling module is connected to an input end of the general public radio interface; Wherein, the first descrambling module is used for descrambling S code, T code, and descrambled data.

4. The base station interface module according to claim 3, characterized in that, Further comprising a second descrambling module and a second selector; A second output end of the high-speed serial interface is connected to an input end of the second descrambling module; An output end of the first descrambling module is connected to an input end of the general public radio interface through the second selector; An output end of the second selector is connected to an input end of the general public radio interface; When an enabling end of the second selector is in a first state, an output end of the first descrambling module is conducted with an input end of the general public radio interface; When the enabling end of the second selector is in a second state, an output end of the second descrambling module is conducted with an input end of the general public radio interface; Wherein, the second descrambling module is used for descrambling the descrambled data.

5. The base station interface module according to claim 1, characterized in that The forward error correction coding module is a Reed-Solomon code coding module.

6. The base station interface module according to claim 1, characterized in that, The forward error correction decoding module is a Reed-Solomon code decoding module.

7. The base station interface module according to claim 1, wherein The forward error correction coding module is implemented by a soft core.

8. The base station interface module according to claim 3, characterized in that, The forward error correction decoding module is implemented by a hard core.

9. The base station interface module according to claim 3, wherein The forward error correction decoding module includes a frequency conversion sub-module; The frequency conversion sub-module is used for performing frequency conversion processing on a differential input clock to generate a clock of the forward error correction decoding module.

10. A base station, characterized in that, Including the base station interface module according to any one of claims 1 to 9.

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